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1da177e4 LT |
1 | /* linux/drivers/i2c/busses/i2c-s3c2410.c |
2 | * | |
c564e6ae | 3 | * Copyright (C) 2004,2005,2009 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
6 | * S3C2410 I2C Controller | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | ||
26 | #include <linux/i2c.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/time.h> | |
29 | #include <linux/interrupt.h> | |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/errno.h> | |
32 | #include <linux/err.h> | |
d052d1be | 33 | #include <linux/platform_device.h> |
c62c3ca5 | 34 | #include <linux/pm_runtime.h> |
f8ce2547 | 35 | #include <linux/clk.h> |
61c7cff8 | 36 | #include <linux/cpufreq.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
21782180 | 38 | #include <linux/io.h> |
5a5f5080 TA |
39 | #include <linux/of_i2c.h> |
40 | #include <linux/of_gpio.h> | |
2693ac69 | 41 | #include <linux/pinctrl/consumer.h> |
1da177e4 | 42 | |
1da177e4 | 43 | #include <asm/irq.h> |
1da177e4 | 44 | |
436d42c6 | 45 | #include <linux/platform_data/i2c-s3c2410.h> |
1da177e4 | 46 | |
e636602a HS |
47 | /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ |
48 | ||
7a6674da HS |
49 | #define S3C2410_IICCON 0x00 |
50 | #define S3C2410_IICSTAT 0x04 | |
51 | #define S3C2410_IICADD 0x08 | |
52 | #define S3C2410_IICDS 0x0C | |
53 | #define S3C2440_IICLC 0x10 | |
e636602a | 54 | |
7a6674da HS |
55 | #define S3C2410_IICCON_ACKEN (1 << 7) |
56 | #define S3C2410_IICCON_TXDIV_16 (0 << 6) | |
57 | #define S3C2410_IICCON_TXDIV_512 (1 << 6) | |
58 | #define S3C2410_IICCON_IRQEN (1 << 5) | |
59 | #define S3C2410_IICCON_IRQPEND (1 << 4) | |
60 | #define S3C2410_IICCON_SCALE(x) ((x) & 0xf) | |
e636602a HS |
61 | #define S3C2410_IICCON_SCALEMASK (0xf) |
62 | ||
7a6674da HS |
63 | #define S3C2410_IICSTAT_MASTER_RX (2 << 6) |
64 | #define S3C2410_IICSTAT_MASTER_TX (3 << 6) | |
65 | #define S3C2410_IICSTAT_SLAVE_RX (0 << 6) | |
66 | #define S3C2410_IICSTAT_SLAVE_TX (1 << 6) | |
67 | #define S3C2410_IICSTAT_MODEMASK (3 << 6) | |
e636602a | 68 | |
7a6674da HS |
69 | #define S3C2410_IICSTAT_START (1 << 5) |
70 | #define S3C2410_IICSTAT_BUSBUSY (1 << 5) | |
71 | #define S3C2410_IICSTAT_TXRXEN (1 << 4) | |
72 | #define S3C2410_IICSTAT_ARBITR (1 << 3) | |
73 | #define S3C2410_IICSTAT_ASSLAVE (1 << 2) | |
74 | #define S3C2410_IICSTAT_ADDR0 (1 << 1) | |
75 | #define S3C2410_IICSTAT_LASTBIT (1 << 0) | |
e636602a HS |
76 | |
77 | #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) | |
78 | #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) | |
79 | #define S3C2410_IICLC_SDA_DELAY10 (2 << 0) | |
80 | #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) | |
81 | #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) | |
82 | ||
7a6674da | 83 | #define S3C2410_IICLC_FILTER_ON (1 << 2) |
e636602a | 84 | |
27452498 KL |
85 | /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ |
86 | #define QUIRK_S3C2440 (1 << 0) | |
ec39ef83 KL |
87 | #define QUIRK_HDMIPHY (1 << 1) |
88 | #define QUIRK_NO_GPIO (1 << 2) | |
1da177e4 | 89 | |
fe724bf9 DK |
90 | /* Max time to wait for bus to become idle after a xfer (in us) */ |
91 | #define S3C2410_IDLE_TIMEOUT 5000 | |
92 | ||
27452498 | 93 | /* i2c controller state */ |
1da177e4 LT |
94 | enum s3c24xx_i2c_state { |
95 | STATE_IDLE, | |
96 | STATE_START, | |
97 | STATE_READ, | |
98 | STATE_WRITE, | |
99 | STATE_STOP | |
100 | }; | |
101 | ||
102 | struct s3c24xx_i2c { | |
1da177e4 | 103 | wait_queue_head_t wait; |
27452498 | 104 | unsigned int quirks; |
be44f01e | 105 | unsigned int suspended:1; |
1da177e4 LT |
106 | |
107 | struct i2c_msg *msg; | |
108 | unsigned int msg_num; | |
109 | unsigned int msg_idx; | |
110 | unsigned int msg_ptr; | |
111 | ||
e00a8cdf | 112 | unsigned int tx_setup; |
e0d1ec97 | 113 | unsigned int irq; |
e00a8cdf | 114 | |
1da177e4 | 115 | enum s3c24xx_i2c_state state; |
61c7cff8 | 116 | unsigned long clkrate; |
1da177e4 LT |
117 | |
118 | void __iomem *regs; | |
119 | struct clk *clk; | |
120 | struct device *dev; | |
1da177e4 | 121 | struct i2c_adapter adap; |
61c7cff8 | 122 | |
4fd81eb2 | 123 | struct s3c2410_platform_i2c *pdata; |
5a5f5080 | 124 | int gpios[2]; |
2693ac69 | 125 | struct pinctrl *pctrl; |
61c7cff8 BD |
126 | #ifdef CONFIG_CPU_FREQ |
127 | struct notifier_block freq_transition; | |
128 | #endif | |
1da177e4 LT |
129 | }; |
130 | ||
27452498 KL |
131 | static struct platform_device_id s3c24xx_driver_ids[] = { |
132 | { | |
133 | .name = "s3c2410-i2c", | |
134 | .driver_data = 0, | |
135 | }, { | |
136 | .name = "s3c2440-i2c", | |
137 | .driver_data = QUIRK_S3C2440, | |
ec39ef83 KL |
138 | }, { |
139 | .name = "s3c2440-hdmiphy-i2c", | |
140 | .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, | |
27452498 KL |
141 | }, { }, |
142 | }; | |
143 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); | |
144 | ||
145 | #ifdef CONFIG_OF | |
146 | static const struct of_device_id s3c24xx_i2c_match[] = { | |
147 | { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, | |
148 | { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, | |
ec39ef83 KL |
149 | { .compatible = "samsung,s3c2440-hdmiphy-i2c", |
150 | .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, | |
faf93ff6 GM |
151 | { .compatible = "samsung,exynos5440-i2c", |
152 | .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) }, | |
27452498 KL |
153 | {}, |
154 | }; | |
155 | MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); | |
156 | #endif | |
1da177e4 | 157 | |
27452498 | 158 | /* s3c24xx_get_device_quirks |
1da177e4 | 159 | * |
27452498 | 160 | * Get controller type either from device tree or platform device variant. |
1da177e4 LT |
161 | */ |
162 | ||
27452498 | 163 | static inline unsigned int s3c24xx_get_device_quirks(struct platform_device *pdev) |
1da177e4 | 164 | { |
27452498 KL |
165 | if (pdev->dev.of_node) { |
166 | const struct of_device_id *match; | |
b900ba4c | 167 | match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); |
27452498 KL |
168 | return (unsigned int)match->data; |
169 | } | |
5a5f5080 | 170 | |
27452498 | 171 | return platform_get_device_id(pdev)->driver_data; |
1da177e4 LT |
172 | } |
173 | ||
1da177e4 LT |
174 | /* s3c24xx_i2c_master_complete |
175 | * | |
176 | * complete the message and wake up the caller, using the given return code, | |
177 | * or zero to mean ok. | |
178 | */ | |
179 | ||
180 | static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) | |
181 | { | |
182 | dev_dbg(i2c->dev, "master_complete %d\n", ret); | |
183 | ||
184 | i2c->msg_ptr = 0; | |
185 | i2c->msg = NULL; | |
3d0911bf | 186 | i2c->msg_idx++; |
1da177e4 LT |
187 | i2c->msg_num = 0; |
188 | if (ret) | |
189 | i2c->msg_idx = ret; | |
190 | ||
191 | wake_up(&i2c->wait); | |
192 | } | |
193 | ||
194 | static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) | |
195 | { | |
196 | unsigned long tmp; | |
3d0911bf | 197 | |
1da177e4 LT |
198 | tmp = readl(i2c->regs + S3C2410_IICCON); |
199 | writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
200 | } |
201 | ||
202 | static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) | |
203 | { | |
204 | unsigned long tmp; | |
3d0911bf | 205 | |
1da177e4 LT |
206 | tmp = readl(i2c->regs + S3C2410_IICCON); |
207 | writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
208 | } |
209 | ||
210 | /* irq enable/disable functions */ | |
211 | ||
212 | static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) | |
213 | { | |
214 | unsigned long tmp; | |
3d0911bf | 215 | |
1da177e4 LT |
216 | tmp = readl(i2c->regs + S3C2410_IICCON); |
217 | writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
218 | } | |
219 | ||
220 | static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) | |
221 | { | |
222 | unsigned long tmp; | |
3d0911bf | 223 | |
1da177e4 LT |
224 | tmp = readl(i2c->regs + S3C2410_IICCON); |
225 | writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); | |
226 | } | |
227 | ||
228 | ||
229 | /* s3c24xx_i2c_message_start | |
230 | * | |
3d0911bf | 231 | * put the start of a message onto the bus |
1da177e4 LT |
232 | */ |
233 | ||
3d0911bf | 234 | static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, |
1da177e4 LT |
235 | struct i2c_msg *msg) |
236 | { | |
237 | unsigned int addr = (msg->addr & 0x7f) << 1; | |
238 | unsigned long stat; | |
239 | unsigned long iiccon; | |
240 | ||
241 | stat = 0; | |
242 | stat |= S3C2410_IICSTAT_TXRXEN; | |
243 | ||
244 | if (msg->flags & I2C_M_RD) { | |
245 | stat |= S3C2410_IICSTAT_MASTER_RX; | |
246 | addr |= 1; | |
247 | } else | |
248 | stat |= S3C2410_IICSTAT_MASTER_TX; | |
249 | ||
250 | if (msg->flags & I2C_M_REV_DIR_ADDR) | |
251 | addr ^= 1; | |
252 | ||
48fc7f7e | 253 | /* todo - check for whether ack wanted or not */ |
1da177e4 LT |
254 | s3c24xx_i2c_enable_ack(i2c); |
255 | ||
256 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
257 | writel(stat, i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 258 | |
1da177e4 LT |
259 | dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); |
260 | writeb(addr, i2c->regs + S3C2410_IICDS); | |
3d0911bf | 261 | |
e00a8cdf BD |
262 | /* delay here to ensure the data byte has gotten onto the bus |
263 | * before the transaction is started */ | |
264 | ||
265 | ndelay(i2c->tx_setup); | |
266 | ||
1da177e4 LT |
267 | dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); |
268 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
3d0911bf BD |
269 | |
270 | stat |= S3C2410_IICSTAT_START; | |
1da177e4 LT |
271 | writel(stat, i2c->regs + S3C2410_IICSTAT); |
272 | } | |
273 | ||
274 | static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) | |
275 | { | |
276 | unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
277 | ||
278 | dev_dbg(i2c->dev, "STOP\n"); | |
279 | ||
0da2e776 DK |
280 | /* |
281 | * The datasheet says that the STOP sequence should be: | |
282 | * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') | |
283 | * 2) I2CCON.4 = 0 - Clear IRQPEND | |
284 | * 3) Wait until the stop condition takes effect. | |
285 | * 4*) I2CSTAT.4 = 0 - Clear TXRXEN | |
286 | * | |
287 | * Where, step "4*" is only for buses with the "HDMIPHY" quirk. | |
288 | * | |
289 | * However, after much experimentation, it appears that: | |
290 | * a) normal buses automatically clear BUSY and transition from | |
291 | * Master->Slave when they complete generating a STOP condition. | |
292 | * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 | |
293 | * after starting the STOP generation here. | |
294 | * b) HDMIPHY bus does neither, so there is no way to do step 3. | |
295 | * There is no indication when this bus has finished generating | |
296 | * STOP. | |
297 | * | |
298 | * In fact, we have found that as soon as the IRQPEND bit is cleared in | |
299 | * step 2, the HDMIPHY bus generates the STOP condition, and then | |
300 | * immediately starts transferring another data byte, even though the | |
301 | * bus is supposedly stopped. This is presumably because the bus is | |
302 | * still in "Master" mode, and its BUSY bit is still set. | |
303 | * | |
304 | * To avoid these extra post-STOP transactions on HDMI phy devices, we | |
305 | * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, | |
306 | * instead of first generating a proper STOP condition. This should | |
307 | * float SDA & SCK terminating the transfer. Subsequent transfers | |
308 | * start with a proper START condition, and proceed normally. | |
309 | * | |
310 | * The HDMIPHY bus is an internal bus that always has exactly two | |
311 | * devices, the host as Master and the HDMIPHY device as the slave. | |
312 | * Skipping the STOP condition has been tested on this bus and works. | |
313 | */ | |
314 | if (i2c->quirks & QUIRK_HDMIPHY) { | |
315 | /* Stop driving the I2C pins */ | |
316 | iicstat &= ~S3C2410_IICSTAT_TXRXEN; | |
317 | } else { | |
318 | /* stop the transfer */ | |
319 | iicstat &= ~S3C2410_IICSTAT_START; | |
320 | } | |
1da177e4 | 321 | writel(iicstat, i2c->regs + S3C2410_IICSTAT); |
3d0911bf | 322 | |
1da177e4 | 323 | i2c->state = STATE_STOP; |
3d0911bf | 324 | |
1da177e4 LT |
325 | s3c24xx_i2c_master_complete(i2c, ret); |
326 | s3c24xx_i2c_disable_irq(i2c); | |
327 | } | |
328 | ||
329 | /* helper functions to determine the current state in the set of | |
330 | * messages we are sending */ | |
331 | ||
332 | /* is_lastmsg() | |
333 | * | |
3d0911bf | 334 | * returns TRUE if the current message is the last in the set |
1da177e4 LT |
335 | */ |
336 | ||
337 | static inline int is_lastmsg(struct s3c24xx_i2c *i2c) | |
338 | { | |
339 | return i2c->msg_idx >= (i2c->msg_num - 1); | |
340 | } | |
341 | ||
342 | /* is_msglast | |
343 | * | |
344 | * returns TRUE if we this is the last byte in the current message | |
345 | */ | |
346 | ||
347 | static inline int is_msglast(struct s3c24xx_i2c *i2c) | |
348 | { | |
85747311 JY |
349 | /* msg->len is always 1 for the first byte of smbus block read. |
350 | * Actual length will be read from slave. More bytes will be | |
351 | * read according to the length then. */ | |
352 | if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) | |
353 | return 0; | |
354 | ||
1da177e4 LT |
355 | return i2c->msg_ptr == i2c->msg->len-1; |
356 | } | |
357 | ||
358 | /* is_msgend | |
359 | * | |
360 | * returns TRUE if we reached the end of the current message | |
361 | */ | |
362 | ||
363 | static inline int is_msgend(struct s3c24xx_i2c *i2c) | |
364 | { | |
365 | return i2c->msg_ptr >= i2c->msg->len; | |
366 | } | |
367 | ||
19820510 | 368 | /* i2c_s3c_irq_nextbyte |
1da177e4 LT |
369 | * |
370 | * process an interrupt and work out what to do | |
371 | */ | |
372 | ||
19820510 | 373 | static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) |
1da177e4 LT |
374 | { |
375 | unsigned long tmp; | |
376 | unsigned char byte; | |
377 | int ret = 0; | |
378 | ||
379 | switch (i2c->state) { | |
380 | ||
381 | case STATE_IDLE: | |
08882d20 | 382 | dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); |
1da177e4 | 383 | goto out; |
1da177e4 LT |
384 | |
385 | case STATE_STOP: | |
08882d20 | 386 | dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); |
3d0911bf | 387 | s3c24xx_i2c_disable_irq(i2c); |
1da177e4 LT |
388 | goto out_ack; |
389 | ||
390 | case STATE_START: | |
391 | /* last thing we did was send a start condition on the | |
392 | * bus, or started a new i2c message | |
393 | */ | |
3d0911bf | 394 | |
63f5c289 | 395 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
1da177e4 LT |
396 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
397 | /* ack was not received... */ | |
398 | ||
399 | dev_dbg(i2c->dev, "ack was not received\n"); | |
63f5c289 | 400 | s3c24xx_i2c_stop(i2c, -ENXIO); |
1da177e4 LT |
401 | goto out_ack; |
402 | } | |
403 | ||
404 | if (i2c->msg->flags & I2C_M_RD) | |
405 | i2c->state = STATE_READ; | |
406 | else | |
407 | i2c->state = STATE_WRITE; | |
408 | ||
409 | /* terminate the transfer if there is nothing to do | |
63f5c289 | 410 | * as this is used by the i2c probe to find devices. */ |
1da177e4 LT |
411 | |
412 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | |
413 | s3c24xx_i2c_stop(i2c, 0); | |
414 | goto out_ack; | |
415 | } | |
416 | ||
417 | if (i2c->state == STATE_READ) | |
418 | goto prepare_read; | |
419 | ||
3d0911bf | 420 | /* fall through to the write state, as we will need to |
1da177e4 LT |
421 | * send a byte as well */ |
422 | ||
423 | case STATE_WRITE: | |
424 | /* we are writing data to the device... check for the | |
425 | * end of the message, and if so, work out what to do | |
426 | */ | |
427 | ||
2709781b BD |
428 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
429 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | |
430 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | |
431 | ||
432 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | |
433 | goto out_ack; | |
434 | } | |
435 | } | |
436 | ||
3d0911bf | 437 | retry_write: |
2709781b | 438 | |
1da177e4 LT |
439 | if (!is_msgend(i2c)) { |
440 | byte = i2c->msg->buf[i2c->msg_ptr++]; | |
441 | writeb(byte, i2c->regs + S3C2410_IICDS); | |
e00a8cdf BD |
442 | |
443 | /* delay after writing the byte to allow the | |
444 | * data setup time on the bus, as writing the | |
445 | * data to the register causes the first bit | |
446 | * to appear on SDA, and SCL will change as | |
447 | * soon as the interrupt is acknowledged */ | |
448 | ||
449 | ndelay(i2c->tx_setup); | |
450 | ||
1da177e4 LT |
451 | } else if (!is_lastmsg(i2c)) { |
452 | /* we need to go to the next i2c message */ | |
453 | ||
454 | dev_dbg(i2c->dev, "WRITE: Next Message\n"); | |
455 | ||
456 | i2c->msg_ptr = 0; | |
3d0911bf | 457 | i2c->msg_idx++; |
1da177e4 | 458 | i2c->msg++; |
3d0911bf | 459 | |
1da177e4 LT |
460 | /* check to see if we need to do another message */ |
461 | if (i2c->msg->flags & I2C_M_NOSTART) { | |
462 | ||
463 | if (i2c->msg->flags & I2C_M_RD) { | |
464 | /* cannot do this, the controller | |
465 | * forces us to send a new START | |
466 | * when we change direction */ | |
467 | ||
468 | s3c24xx_i2c_stop(i2c, -EINVAL); | |
469 | } | |
470 | ||
471 | goto retry_write; | |
472 | } else { | |
1da177e4 LT |
473 | /* send the new start */ |
474 | s3c24xx_i2c_message_start(i2c, i2c->msg); | |
475 | i2c->state = STATE_START; | |
476 | } | |
477 | ||
478 | } else { | |
479 | /* send stop */ | |
480 | ||
481 | s3c24xx_i2c_stop(i2c, 0); | |
482 | } | |
483 | break; | |
484 | ||
485 | case STATE_READ: | |
3d0911bf | 486 | /* we have a byte of data in the data register, do |
48fc7f7e | 487 | * something with it, and then work out whether we are |
1da177e4 LT |
488 | * going to do any more read/write |
489 | */ | |
490 | ||
1da177e4 LT |
491 | byte = readb(i2c->regs + S3C2410_IICDS); |
492 | i2c->msg->buf[i2c->msg_ptr++] = byte; | |
493 | ||
85747311 JY |
494 | /* Add actual length to read for smbus block read */ |
495 | if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) | |
496 | i2c->msg->len += byte; | |
3d0911bf | 497 | prepare_read: |
1da177e4 LT |
498 | if (is_msglast(i2c)) { |
499 | /* last byte of buffer */ | |
500 | ||
501 | if (is_lastmsg(i2c)) | |
502 | s3c24xx_i2c_disable_ack(i2c); | |
3d0911bf | 503 | |
1da177e4 LT |
504 | } else if (is_msgend(i2c)) { |
505 | /* ok, we've read the entire buffer, see if there | |
506 | * is anything else we need to do */ | |
507 | ||
508 | if (is_lastmsg(i2c)) { | |
509 | /* last message, send stop and complete */ | |
510 | dev_dbg(i2c->dev, "READ: Send Stop\n"); | |
511 | ||
512 | s3c24xx_i2c_stop(i2c, 0); | |
513 | } else { | |
514 | /* go to the next transfer */ | |
515 | dev_dbg(i2c->dev, "READ: Next Transfer\n"); | |
516 | ||
517 | i2c->msg_ptr = 0; | |
518 | i2c->msg_idx++; | |
519 | i2c->msg++; | |
520 | } | |
521 | } | |
522 | ||
523 | break; | |
524 | } | |
525 | ||
526 | /* acknowlegde the IRQ and get back on with the work */ | |
527 | ||
528 | out_ack: | |
3d0911bf | 529 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
530 | tmp &= ~S3C2410_IICCON_IRQPEND; |
531 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
532 | out: | |
533 | return ret; | |
534 | } | |
535 | ||
536 | /* s3c24xx_i2c_irq | |
537 | * | |
538 | * top level IRQ servicing routine | |
539 | */ | |
540 | ||
7d12e780 | 541 | static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) |
1da177e4 LT |
542 | { |
543 | struct s3c24xx_i2c *i2c = dev_id; | |
544 | unsigned long status; | |
545 | unsigned long tmp; | |
546 | ||
547 | status = readl(i2c->regs + S3C2410_IICSTAT); | |
548 | ||
549 | if (status & S3C2410_IICSTAT_ARBITR) { | |
3d0911bf | 550 | /* deal with arbitration loss */ |
1da177e4 LT |
551 | dev_err(i2c->dev, "deal with arbitration loss\n"); |
552 | } | |
553 | ||
554 | if (i2c->state == STATE_IDLE) { | |
555 | dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); | |
556 | ||
3d0911bf | 557 | tmp = readl(i2c->regs + S3C2410_IICCON); |
1da177e4 LT |
558 | tmp &= ~S3C2410_IICCON_IRQPEND; |
559 | writel(tmp, i2c->regs + S3C2410_IICCON); | |
560 | goto out; | |
561 | } | |
3d0911bf | 562 | |
1da177e4 LT |
563 | /* pretty much this leaves us with the fact that we've |
564 | * transmitted or received whatever byte we last sent */ | |
565 | ||
19820510 | 566 | i2c_s3c_irq_nextbyte(i2c, status); |
1da177e4 LT |
567 | |
568 | out: | |
569 | return IRQ_HANDLED; | |
570 | } | |
571 | ||
572 | ||
573 | /* s3c24xx_i2c_set_master | |
574 | * | |
575 | * get the i2c bus for a master transaction | |
576 | */ | |
577 | ||
578 | static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) | |
579 | { | |
580 | unsigned long iicstat; | |
581 | int timeout = 400; | |
582 | ||
583 | while (timeout-- > 0) { | |
584 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
3d0911bf | 585 | |
1da177e4 LT |
586 | if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) |
587 | return 0; | |
588 | ||
589 | msleep(1); | |
590 | } | |
591 | ||
1da177e4 LT |
592 | return -ETIMEDOUT; |
593 | } | |
ec39ef83 | 594 | |
fe724bf9 DK |
595 | /* s3c24xx_i2c_wait_idle |
596 | * | |
597 | * wait for the i2c bus to become idle. | |
598 | */ | |
599 | ||
600 | static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) | |
601 | { | |
602 | unsigned long iicstat; | |
603 | ktime_t start, now; | |
604 | unsigned long delay; | |
31f313d9 | 605 | int spins; |
fe724bf9 DK |
606 | |
607 | /* ensure the stop has been through the bus */ | |
608 | ||
609 | dev_dbg(i2c->dev, "waiting for bus idle\n"); | |
610 | ||
611 | start = now = ktime_get(); | |
612 | ||
613 | /* | |
614 | * Most of the time, the bus is already idle within a few usec of the | |
615 | * end of a transaction. However, really slow i2c devices can stretch | |
616 | * the clock, delaying STOP generation. | |
617 | * | |
31f313d9 MB |
618 | * On slower SoCs this typically happens within a very small number of |
619 | * instructions so busy wait briefly to avoid scheduling overhead. | |
fe724bf9 | 620 | */ |
31f313d9 | 621 | spins = 3; |
fe724bf9 | 622 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); |
31f313d9 MB |
623 | while ((iicstat & S3C2410_IICSTAT_START) && --spins) { |
624 | cpu_relax(); | |
625 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
ec39ef83 KL |
626 | } |
627 | ||
31f313d9 MB |
628 | /* |
629 | * If we do get an appreciable delay as a compromise between idle | |
630 | * detection latency for the normal, fast case, and system load in the | |
631 | * slow device case, use an exponential back off in the polling loop, | |
632 | * up to 1/10th of the total timeout, then continue to poll at a | |
633 | * constant rate up to the timeout. | |
634 | */ | |
fe724bf9 DK |
635 | delay = 1; |
636 | while ((iicstat & S3C2410_IICSTAT_START) && | |
637 | ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { | |
638 | usleep_range(delay, 2 * delay); | |
639 | if (delay < S3C2410_IDLE_TIMEOUT / 10) | |
640 | delay <<= 1; | |
641 | now = ktime_get(); | |
642 | iicstat = readl(i2c->regs + S3C2410_IICSTAT); | |
643 | } | |
644 | ||
645 | if (iicstat & S3C2410_IICSTAT_START) | |
646 | dev_warn(i2c->dev, "timeout waiting for bus idle\n"); | |
1da177e4 LT |
647 | } |
648 | ||
649 | /* s3c24xx_i2c_doxfer | |
650 | * | |
651 | * this starts an i2c transfer | |
652 | */ | |
653 | ||
3d0911bf BD |
654 | static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, |
655 | struct i2c_msg *msgs, int num) | |
1da177e4 | 656 | { |
fe724bf9 | 657 | unsigned long timeout; |
1da177e4 LT |
658 | int ret; |
659 | ||
be44f01e | 660 | if (i2c->suspended) |
61c7cff8 BD |
661 | return -EIO; |
662 | ||
1da177e4 LT |
663 | ret = s3c24xx_i2c_set_master(i2c); |
664 | if (ret != 0) { | |
665 | dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); | |
666 | ret = -EAGAIN; | |
667 | goto out; | |
668 | } | |
669 | ||
1da177e4 LT |
670 | i2c->msg = msgs; |
671 | i2c->msg_num = num; | |
672 | i2c->msg_ptr = 0; | |
673 | i2c->msg_idx = 0; | |
674 | i2c->state = STATE_START; | |
675 | ||
676 | s3c24xx_i2c_enable_irq(i2c); | |
677 | s3c24xx_i2c_message_start(i2c, msgs); | |
3d0911bf | 678 | |
1da177e4 LT |
679 | timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); |
680 | ||
681 | ret = i2c->msg_idx; | |
682 | ||
3d0911bf | 683 | /* having these next two as dev_err() makes life very |
1da177e4 LT |
684 | * noisy when doing an i2cdetect */ |
685 | ||
686 | if (timeout == 0) | |
687 | dev_dbg(i2c->dev, "timeout\n"); | |
688 | else if (ret != num) | |
689 | dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); | |
690 | ||
0da2e776 DK |
691 | /* For QUIRK_HDMIPHY, bus is already disabled */ |
692 | if (i2c->quirks & QUIRK_HDMIPHY) | |
693 | goto out; | |
1bc2962e | 694 | |
fe724bf9 | 695 | s3c24xx_i2c_wait_idle(i2c); |
1da177e4 LT |
696 | |
697 | out: | |
698 | return ret; | |
699 | } | |
700 | ||
701 | /* s3c24xx_i2c_xfer | |
702 | * | |
703 | * first port of call from the i2c bus code when an message needs | |
44bbe87e | 704 | * transferring across the i2c bus. |
1da177e4 LT |
705 | */ |
706 | ||
707 | static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, | |
708 | struct i2c_msg *msgs, int num) | |
709 | { | |
710 | struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; | |
711 | int retry; | |
712 | int ret; | |
713 | ||
c62c3ca5 | 714 | pm_runtime_get_sync(&adap->dev); |
d3b64c59 | 715 | clk_prepare_enable(i2c->clk); |
d2360b8e | 716 | |
1da177e4 LT |
717 | for (retry = 0; retry < adap->retries; retry++) { |
718 | ||
719 | ret = s3c24xx_i2c_doxfer(i2c, msgs, num); | |
720 | ||
d2360b8e | 721 | if (ret != -EAGAIN) { |
d3b64c59 | 722 | clk_disable_unprepare(i2c->clk); |
a86ae9ff | 723 | pm_runtime_put(&adap->dev); |
1da177e4 | 724 | return ret; |
d2360b8e | 725 | } |
1da177e4 LT |
726 | |
727 | dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); | |
728 | ||
729 | udelay(100); | |
730 | } | |
731 | ||
d3b64c59 | 732 | clk_disable_unprepare(i2c->clk); |
a86ae9ff | 733 | pm_runtime_put(&adap->dev); |
1da177e4 LT |
734 | return -EREMOTEIO; |
735 | } | |
736 | ||
737 | /* declare our i2c functionality */ | |
738 | static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) | |
739 | { | |
14674e70 MB |
740 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART | |
741 | I2C_FUNC_PROTOCOL_MANGLING; | |
1da177e4 LT |
742 | } |
743 | ||
744 | /* i2c bus registration info */ | |
745 | ||
8f9082c5 | 746 | static const struct i2c_algorithm s3c24xx_i2c_algorithm = { |
1da177e4 LT |
747 | .master_xfer = s3c24xx_i2c_xfer, |
748 | .functionality = s3c24xx_i2c_func, | |
749 | }; | |
750 | ||
1da177e4 LT |
751 | /* s3c24xx_i2c_calcdivisor |
752 | * | |
753 | * return the divisor settings for a given frequency | |
754 | */ | |
755 | ||
756 | static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, | |
757 | unsigned int *div1, unsigned int *divs) | |
758 | { | |
759 | unsigned int calc_divs = clkin / wanted; | |
760 | unsigned int calc_div1; | |
761 | ||
762 | if (calc_divs > (16*16)) | |
763 | calc_div1 = 512; | |
764 | else | |
765 | calc_div1 = 16; | |
766 | ||
767 | calc_divs += calc_div1-1; | |
768 | calc_divs /= calc_div1; | |
769 | ||
770 | if (calc_divs == 0) | |
771 | calc_divs = 1; | |
772 | if (calc_divs > 17) | |
773 | calc_divs = 17; | |
774 | ||
775 | *divs = calc_divs; | |
776 | *div1 = calc_div1; | |
777 | ||
778 | return clkin / (calc_divs * calc_div1); | |
779 | } | |
780 | ||
61c7cff8 | 781 | /* s3c24xx_i2c_clockrate |
1da177e4 LT |
782 | * |
783 | * work out a divisor for the user requested frequency setting, | |
784 | * either by the requested frequency, or scanning the acceptable | |
785 | * range of frequencies until something is found | |
786 | */ | |
787 | ||
61c7cff8 | 788 | static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) |
1da177e4 | 789 | { |
4fd81eb2 | 790 | struct s3c2410_platform_i2c *pdata = i2c->pdata; |
1da177e4 | 791 | unsigned long clkin = clk_get_rate(i2c->clk); |
1da177e4 | 792 | unsigned int divs, div1; |
c564e6ae | 793 | unsigned long target_frequency; |
61c7cff8 | 794 | u32 iiccon; |
1da177e4 | 795 | int freq; |
1da177e4 | 796 | |
61c7cff8 | 797 | i2c->clkrate = clkin; |
1da177e4 | 798 | clkin /= 1000; /* clkin now in KHz */ |
3d0911bf | 799 | |
c564e6ae | 800 | dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); |
1da177e4 | 801 | |
c564e6ae | 802 | target_frequency = pdata->frequency ? pdata->frequency : 100000; |
1da177e4 | 803 | |
c564e6ae | 804 | target_frequency /= 1000; /* Target frequency now in KHz */ |
1da177e4 | 805 | |
c564e6ae | 806 | freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); |
1da177e4 | 807 | |
c564e6ae DS |
808 | if (freq > target_frequency) { |
809 | dev_err(i2c->dev, | |
810 | "Unable to achieve desired frequency %luKHz." \ | |
811 | " Lowest achievable %dKHz\n", target_frequency, freq); | |
812 | return -EINVAL; | |
1da177e4 LT |
813 | } |
814 | ||
1da177e4 | 815 | *got = freq; |
61c7cff8 BD |
816 | |
817 | iiccon = readl(i2c->regs + S3C2410_IICCON); | |
818 | iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); | |
819 | iiccon |= (divs-1); | |
820 | ||
821 | if (div1 == 512) | |
822 | iiccon |= S3C2410_IICCON_TXDIV_512; | |
823 | ||
824 | writel(iiccon, i2c->regs + S3C2410_IICCON); | |
825 | ||
27452498 | 826 | if (i2c->quirks & QUIRK_S3C2440) { |
a192f715 BD |
827 | unsigned long sda_delay; |
828 | ||
829 | if (pdata->sda_delay) { | |
7031307a MH |
830 | sda_delay = clkin * pdata->sda_delay; |
831 | sda_delay = DIV_ROUND_UP(sda_delay, 1000000); | |
a192f715 BD |
832 | sda_delay = DIV_ROUND_UP(sda_delay, 5); |
833 | if (sda_delay > 3) | |
834 | sda_delay = 3; | |
835 | sda_delay |= S3C2410_IICLC_FILTER_ON; | |
836 | } else | |
837 | sda_delay = 0; | |
838 | ||
839 | dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); | |
840 | writel(sda_delay, i2c->regs + S3C2440_IICLC); | |
841 | } | |
842 | ||
61c7cff8 BD |
843 | return 0; |
844 | } | |
845 | ||
846 | #ifdef CONFIG_CPU_FREQ | |
847 | ||
848 | #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) | |
849 | ||
850 | static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, | |
851 | unsigned long val, void *data) | |
852 | { | |
853 | struct s3c24xx_i2c *i2c = freq_to_i2c(nb); | |
61c7cff8 BD |
854 | unsigned int got; |
855 | int delta_f; | |
856 | int ret; | |
857 | ||
858 | delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; | |
859 | ||
860 | /* if we're post-change and the input clock has slowed down | |
861 | * or at pre-change and the clock is about to speed up, then | |
862 | * adjust our clock rate. <0 is slow, >0 speedup. | |
863 | */ | |
864 | ||
865 | if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || | |
866 | (val == CPUFREQ_PRECHANGE && delta_f > 0)) { | |
9bcd04bf | 867 | i2c_lock_adapter(&i2c->adap); |
61c7cff8 | 868 | ret = s3c24xx_i2c_clockrate(i2c, &got); |
9bcd04bf | 869 | i2c_unlock_adapter(&i2c->adap); |
61c7cff8 BD |
870 | |
871 | if (ret < 0) | |
872 | dev_err(i2c->dev, "cannot find frequency\n"); | |
873 | else | |
874 | dev_info(i2c->dev, "setting freq %d\n", got); | |
875 | } | |
876 | ||
1da177e4 LT |
877 | return 0; |
878 | } | |
879 | ||
61c7cff8 BD |
880 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) |
881 | { | |
882 | i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; | |
883 | ||
884 | return cpufreq_register_notifier(&i2c->freq_transition, | |
885 | CPUFREQ_TRANSITION_NOTIFIER); | |
886 | } | |
887 | ||
888 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) | |
889 | { | |
890 | cpufreq_unregister_notifier(&i2c->freq_transition, | |
891 | CPUFREQ_TRANSITION_NOTIFIER); | |
892 | } | |
893 | ||
894 | #else | |
895 | static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) | |
896 | { | |
1da177e4 LT |
897 | return 0; |
898 | } | |
899 | ||
61c7cff8 BD |
900 | static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) |
901 | { | |
902 | } | |
903 | #endif | |
904 | ||
5a5f5080 TA |
905 | #ifdef CONFIG_OF |
906 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
907 | { | |
908 | int idx, gpio, ret; | |
909 | ||
ec39ef83 KL |
910 | if (i2c->quirks & QUIRK_NO_GPIO) |
911 | return 0; | |
912 | ||
5a5f5080 TA |
913 | for (idx = 0; idx < 2; idx++) { |
914 | gpio = of_get_gpio(i2c->dev->of_node, idx); | |
915 | if (!gpio_is_valid(gpio)) { | |
916 | dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); | |
917 | goto free_gpio; | |
918 | } | |
963f2076 | 919 | i2c->gpios[idx] = gpio; |
5a5f5080 TA |
920 | |
921 | ret = gpio_request(gpio, "i2c-bus"); | |
922 | if (ret) { | |
923 | dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); | |
924 | goto free_gpio; | |
925 | } | |
926 | } | |
927 | return 0; | |
928 | ||
929 | free_gpio: | |
930 | while (--idx >= 0) | |
931 | gpio_free(i2c->gpios[idx]); | |
932 | return -EINVAL; | |
933 | } | |
934 | ||
935 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
936 | { | |
937 | unsigned int idx; | |
ec39ef83 KL |
938 | |
939 | if (i2c->quirks & QUIRK_NO_GPIO) | |
940 | return; | |
941 | ||
5a5f5080 TA |
942 | for (idx = 0; idx < 2; idx++) |
943 | gpio_free(i2c->gpios[idx]); | |
944 | } | |
945 | #else | |
946 | static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) | |
947 | { | |
8ebe661d | 948 | return 0; |
5a5f5080 TA |
949 | } |
950 | ||
951 | static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) | |
952 | { | |
953 | } | |
954 | #endif | |
955 | ||
1da177e4 LT |
956 | /* s3c24xx_i2c_init |
957 | * | |
3d0911bf | 958 | * initialise the controller, set the IO lines and frequency |
1da177e4 LT |
959 | */ |
960 | ||
961 | static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) | |
962 | { | |
963 | unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN; | |
964 | struct s3c2410_platform_i2c *pdata; | |
965 | unsigned int freq; | |
966 | ||
967 | /* get the plafrom data */ | |
968 | ||
4fd81eb2 | 969 | pdata = i2c->pdata; |
1da177e4 | 970 | |
1da177e4 | 971 | /* write slave address */ |
3d0911bf | 972 | |
1da177e4 LT |
973 | writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); |
974 | ||
975 | dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); | |
976 | ||
61c7cff8 BD |
977 | writel(iicon, i2c->regs + S3C2410_IICCON); |
978 | ||
1da177e4 LT |
979 | /* we need to work out the divisors for the clock... */ |
980 | ||
61c7cff8 BD |
981 | if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { |
982 | writel(0, i2c->regs + S3C2410_IICCON); | |
1da177e4 LT |
983 | dev_err(i2c->dev, "cannot meet bus frequency required\n"); |
984 | return -EINVAL; | |
985 | } | |
986 | ||
987 | /* todo - check that the i2c lines aren't being dragged anywhere */ | |
988 | ||
989 | dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); | |
990 | dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon); | |
1da177e4 | 991 | |
1da177e4 LT |
992 | return 0; |
993 | } | |
994 | ||
5a5f5080 TA |
995 | #ifdef CONFIG_OF |
996 | /* s3c24xx_i2c_parse_dt | |
997 | * | |
998 | * Parse the device tree node and retreive the platform data. | |
999 | */ | |
1000 | ||
1001 | static void | |
1002 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
1003 | { | |
1004 | struct s3c2410_platform_i2c *pdata = i2c->pdata; | |
1005 | ||
1006 | if (!np) | |
1007 | return; | |
1008 | ||
1009 | pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ | |
1010 | of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); | |
1011 | of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); | |
1012 | of_property_read_u32(np, "samsung,i2c-max-bus-freq", | |
1013 | (u32 *)&pdata->frequency); | |
1014 | } | |
1015 | #else | |
1016 | static void | |
1017 | s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) | |
1018 | { | |
1019 | return; | |
1020 | } | |
1021 | #endif | |
1022 | ||
1da177e4 LT |
1023 | /* s3c24xx_i2c_probe |
1024 | * | |
1025 | * called by the bus driver when a suitable device is found | |
1026 | */ | |
1027 | ||
3ae5eaec | 1028 | static int s3c24xx_i2c_probe(struct platform_device *pdev) |
1da177e4 | 1029 | { |
692acbd3 | 1030 | struct s3c24xx_i2c *i2c; |
4fd81eb2 | 1031 | struct s3c2410_platform_i2c *pdata = NULL; |
1da177e4 LT |
1032 | struct resource *res; |
1033 | int ret; | |
1034 | ||
5a5f5080 TA |
1035 | if (!pdev->dev.of_node) { |
1036 | pdata = pdev->dev.platform_data; | |
1037 | if (!pdata) { | |
1038 | dev_err(&pdev->dev, "no platform data\n"); | |
1039 | return -EINVAL; | |
1040 | } | |
6a039cab | 1041 | } |
399dee23 | 1042 | |
4ea1557f | 1043 | i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); |
692acbd3 BD |
1044 | if (!i2c) { |
1045 | dev_err(&pdev->dev, "no memory for state\n"); | |
1046 | return -ENOMEM; | |
1047 | } | |
1048 | ||
4fd81eb2 TA |
1049 | i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
1050 | if (!i2c->pdata) { | |
669da30d TB |
1051 | dev_err(&pdev->dev, "no memory for platform data\n"); |
1052 | return -ENOMEM; | |
4fd81eb2 TA |
1053 | } |
1054 | ||
27452498 | 1055 | i2c->quirks = s3c24xx_get_device_quirks(pdev); |
4fd81eb2 TA |
1056 | if (pdata) |
1057 | memcpy(i2c->pdata, pdata, sizeof(*pdata)); | |
5a5f5080 TA |
1058 | else |
1059 | s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); | |
4fd81eb2 | 1060 | |
692acbd3 BD |
1061 | strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); |
1062 | i2c->adap.owner = THIS_MODULE; | |
1063 | i2c->adap.algo = &s3c24xx_i2c_algorithm; | |
1064 | i2c->adap.retries = 2; | |
1065 | i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1066 | i2c->tx_setup = 50; | |
1067 | ||
692acbd3 | 1068 | init_waitqueue_head(&i2c->wait); |
399dee23 | 1069 | |
1da177e4 LT |
1070 | /* find the clock and enable it */ |
1071 | ||
3ae5eaec | 1072 | i2c->dev = &pdev->dev; |
2b255b94 | 1073 | i2c->clk = devm_clk_get(&pdev->dev, "i2c"); |
1da177e4 | 1074 | if (IS_ERR(i2c->clk)) { |
3ae5eaec | 1075 | dev_err(&pdev->dev, "cannot get clock\n"); |
669da30d | 1076 | return -ENOENT; |
1da177e4 LT |
1077 | } |
1078 | ||
3ae5eaec | 1079 | dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); |
1da177e4 | 1080 | |
1da177e4 LT |
1081 | |
1082 | /* map the registers */ | |
1083 | ||
1084 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
84dbf809 | 1085 | i2c->regs = devm_ioremap_resource(&pdev->dev, res); |
1da177e4 | 1086 | |
52caa59e LT |
1087 | if (IS_ERR(i2c->regs)) |
1088 | return PTR_ERR(i2c->regs); | |
1da177e4 | 1089 | |
a72ad456 MB |
1090 | dev_dbg(&pdev->dev, "registers %p (%p)\n", |
1091 | i2c->regs, res); | |
1da177e4 LT |
1092 | |
1093 | /* setup info block for the i2c core */ | |
1094 | ||
1095 | i2c->adap.algo_data = i2c; | |
3ae5eaec | 1096 | i2c->adap.dev.parent = &pdev->dev; |
1da177e4 | 1097 | |
2693ac69 TF |
1098 | i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); |
1099 | ||
658122fe AK |
1100 | /* inititalise the i2c gpio lines */ |
1101 | ||
1102 | if (i2c->pdata->cfg_gpio) { | |
1103 | i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); | |
1104 | } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) { | |
d16933b3 | 1105 | return -EINVAL; |
658122fe AK |
1106 | } |
1107 | ||
1da177e4 LT |
1108 | /* initialise the i2c controller */ |
1109 | ||
d16933b3 | 1110 | clk_prepare_enable(i2c->clk); |
1da177e4 | 1111 | ret = s3c24xx_i2c_init(i2c); |
d16933b3 TB |
1112 | clk_disable_unprepare(i2c->clk); |
1113 | if (ret != 0) { | |
1114 | dev_err(&pdev->dev, "I2C controller init failed\n"); | |
1115 | return ret; | |
1116 | } | |
1da177e4 | 1117 | /* find the IRQ for this unit (note, this relies on the init call to |
3d0911bf | 1118 | * ensure no current IRQs pending |
1da177e4 LT |
1119 | */ |
1120 | ||
e0d1ec97 BD |
1121 | i2c->irq = ret = platform_get_irq(pdev, 0); |
1122 | if (ret <= 0) { | |
3ae5eaec | 1123 | dev_err(&pdev->dev, "cannot find IRQ\n"); |
d16933b3 | 1124 | return ret; |
1da177e4 LT |
1125 | } |
1126 | ||
2b255b94 TB |
1127 | ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0, |
1128 | dev_name(&pdev->dev), i2c); | |
1da177e4 LT |
1129 | |
1130 | if (ret != 0) { | |
e0d1ec97 | 1131 | dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); |
d16933b3 | 1132 | return ret; |
1da177e4 LT |
1133 | } |
1134 | ||
61c7cff8 | 1135 | ret = s3c24xx_i2c_register_cpufreq(i2c); |
1da177e4 | 1136 | if (ret < 0) { |
61c7cff8 | 1137 | dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); |
d16933b3 | 1138 | return ret; |
1da177e4 LT |
1139 | } |
1140 | ||
399dee23 BD |
1141 | /* Note, previous versions of the driver used i2c_add_adapter() |
1142 | * to add the bus at any number. We now pass the bus number via | |
1143 | * the platform data, so if unset it will now default to always | |
1144 | * being bus 0. | |
1145 | */ | |
1146 | ||
4fd81eb2 | 1147 | i2c->adap.nr = i2c->pdata->bus_num; |
5a5f5080 | 1148 | i2c->adap.dev.of_node = pdev->dev.of_node; |
399dee23 BD |
1149 | |
1150 | ret = i2c_add_numbered_adapter(&i2c->adap); | |
1da177e4 | 1151 | if (ret < 0) { |
3ae5eaec | 1152 | dev_err(&pdev->dev, "failed to add bus to i2c core\n"); |
dc6fea44 TB |
1153 | s3c24xx_i2c_deregister_cpufreq(i2c); |
1154 | return ret; | |
1da177e4 LT |
1155 | } |
1156 | ||
5a5f5080 | 1157 | of_i2c_register_devices(&i2c->adap); |
3ae5eaec | 1158 | platform_set_drvdata(pdev, i2c); |
1da177e4 | 1159 | |
c62c3ca5 MB |
1160 | pm_runtime_enable(&pdev->dev); |
1161 | pm_runtime_enable(&i2c->adap.dev); | |
1162 | ||
22e965c2 | 1163 | dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); |
5b68790c | 1164 | return 0; |
1da177e4 LT |
1165 | } |
1166 | ||
1167 | /* s3c24xx_i2c_remove | |
1168 | * | |
1169 | * called when device is removed from the bus | |
1170 | */ | |
1171 | ||
3ae5eaec | 1172 | static int s3c24xx_i2c_remove(struct platform_device *pdev) |
1da177e4 | 1173 | { |
3ae5eaec | 1174 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); |
5b68790c | 1175 | |
c62c3ca5 MB |
1176 | pm_runtime_disable(&i2c->adap.dev); |
1177 | pm_runtime_disable(&pdev->dev); | |
1178 | ||
61c7cff8 BD |
1179 | s3c24xx_i2c_deregister_cpufreq(i2c); |
1180 | ||
5b68790c | 1181 | i2c_del_adapter(&i2c->adap); |
5b68790c | 1182 | |
d3b64c59 | 1183 | clk_disable_unprepare(i2c->clk); |
5b68790c | 1184 | |
2693ac69 TF |
1185 | if (pdev->dev.of_node && IS_ERR(i2c->pctrl)) |
1186 | s3c24xx_i2c_dt_gpio_free(i2c); | |
1da177e4 LT |
1187 | |
1188 | return 0; | |
1189 | } | |
1190 | ||
2935e0e0 | 1191 | #ifdef CONFIG_PM_SLEEP |
6a6c6189 | 1192 | static int s3c24xx_i2c_suspend_noirq(struct device *dev) |
be44f01e | 1193 | { |
6a6c6189 MD |
1194 | struct platform_device *pdev = to_platform_device(dev); |
1195 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
1196 | ||
be44f01e | 1197 | i2c->suspended = 1; |
6a6c6189 | 1198 | |
be44f01e BD |
1199 | return 0; |
1200 | } | |
1201 | ||
6a6c6189 | 1202 | static int s3c24xx_i2c_resume(struct device *dev) |
1da177e4 | 1203 | { |
6a6c6189 MD |
1204 | struct platform_device *pdev = to_platform_device(dev); |
1205 | struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); | |
9480e307 | 1206 | |
d3b64c59 | 1207 | clk_prepare_enable(i2c->clk); |
be44f01e | 1208 | s3c24xx_i2c_init(i2c); |
d3b64c59 | 1209 | clk_disable_unprepare(i2c->clk); |
a0d31021 | 1210 | i2c->suspended = 0; |
1da177e4 LT |
1211 | |
1212 | return 0; | |
1213 | } | |
2935e0e0 | 1214 | #endif |
1da177e4 | 1215 | |
2935e0e0 | 1216 | #ifdef CONFIG_PM |
47145210 | 1217 | static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { |
2935e0e0 | 1218 | #ifdef CONFIG_PM_SLEEP |
6a6c6189 MD |
1219 | .suspend_noirq = s3c24xx_i2c_suspend_noirq, |
1220 | .resume = s3c24xx_i2c_resume, | |
2935e0e0 | 1221 | #endif |
6a6c6189 MD |
1222 | }; |
1223 | ||
1224 | #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) | |
1da177e4 | 1225 | #else |
6a6c6189 | 1226 | #define S3C24XX_DEV_PM_OPS NULL |
1da177e4 LT |
1227 | #endif |
1228 | ||
1229 | /* device driver for platform bus bits */ | |
1230 | ||
7d85ccd8 | 1231 | static struct platform_driver s3c24xx_i2c_driver = { |
1da177e4 LT |
1232 | .probe = s3c24xx_i2c_probe, |
1233 | .remove = s3c24xx_i2c_remove, | |
7d85ccd8 | 1234 | .id_table = s3c24xx_driver_ids, |
3ae5eaec RK |
1235 | .driver = { |
1236 | .owner = THIS_MODULE, | |
7d85ccd8 | 1237 | .name = "s3c-i2c", |
6a6c6189 | 1238 | .pm = S3C24XX_DEV_PM_OPS, |
9df7eadf | 1239 | .of_match_table = of_match_ptr(s3c24xx_i2c_match), |
3ae5eaec | 1240 | }, |
1da177e4 LT |
1241 | }; |
1242 | ||
1243 | static int __init i2c_adap_s3c_init(void) | |
1244 | { | |
7d85ccd8 | 1245 | return platform_driver_register(&s3c24xx_i2c_driver); |
1da177e4 | 1246 | } |
18dc83a6 | 1247 | subsys_initcall(i2c_adap_s3c_init); |
1da177e4 LT |
1248 | |
1249 | static void __exit i2c_adap_s3c_exit(void) | |
1250 | { | |
7d85ccd8 | 1251 | platform_driver_unregister(&s3c24xx_i2c_driver); |
1da177e4 | 1252 | } |
1da177e4 LT |
1253 | module_exit(i2c_adap_s3c_exit); |
1254 | ||
1255 | MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |
1256 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
1257 | MODULE_LICENSE("GPL"); |