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Linux-2.6.12-rc2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / i2c / busses / i2c-s3c2410.c
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1da177e4
LT		 1/* linux/drivers/i2c/busses/i2c-s3c2410.c
2 *
3 * Copyright (C) 2004,2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 I2C Controller
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21*/
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25
26#include <linux/i2c.h>
27#include <linux/i2c-id.h>
28#include <linux/init.h>
29#include <linux/time.h>
30#include <linux/interrupt.h>
31#include <linux/sched.h>
32#include <linux/delay.h>
33#include <linux/errno.h>
34#include <linux/err.h>
35#include <linux/device.h>
36
37#include <asm/hardware.h>
38#include <asm/irq.h>
39#include <asm/io.h>
40
41#include <asm/hardware/clock.h>
42#include <asm/arch/regs-gpio.h>
43#include <asm/arch/regs-iic.h>
44#include <asm/arch/iic.h>
45
46/* i2c controller state */
47
48enum s3c24xx_i2c_state {
49 STATE_IDLE,
50 STATE_START,
51 STATE_READ,
52 STATE_WRITE,
53 STATE_STOP
54};
55
56struct s3c24xx_i2c {
57 spinlock_t lock;
58 wait_queue_head_t wait;
59
60 struct i2c_msg *msg;
61 unsigned int msg_num;
62 unsigned int msg_idx;
63 unsigned int msg_ptr;
64
65 enum s3c24xx_i2c_state state;
66
67 void __iomem *regs;
68 struct clk *clk;
69 struct device *dev;
70 struct resource *irq;
71 struct resource *ioarea;
72 struct i2c_adapter adap;
73};
74
75/* default platform data to use if not supplied in the platform_device
76*/
77
78static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
79 .flags = 0,
80 .slave_addr = 0x10,
81 .bus_freq = 100*1000,
82 .max_freq = 400*1000,
83 .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
84};
85
86/* s3c24xx_i2c_is2440()
87 *
88 * return true is this is an s3c2440
89*/
90
91static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
92{
93 struct platform_device *pdev = to_platform_device(i2c->dev);
94
95 return !strcmp(pdev->name, "s3c2440-i2c");
96}
97
98
99/* s3c24xx_i2c_get_platformdata
100 *
101 * get the platform data associated with the given device, or return
102 * the default if there is none
103*/
104
105static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
106{
107 if (dev->platform_data != NULL)
108 return (struct s3c2410_platform_i2c *)dev->platform_data;
109
110 return &s3c24xx_i2c_default_platform;
111}
112
113/* s3c24xx_i2c_master_complete
114 *
115 * complete the message and wake up the caller, using the given return code,
116 * or zero to mean ok.
117*/
118
119static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
120{
121 dev_dbg(i2c->dev, "master_complete %d\n", ret);
122
123 i2c->msg_ptr = 0;
124 i2c->msg = NULL;
125 i2c->msg_idx ++;
126 i2c->msg_num = 0;
127 if (ret)
128 i2c->msg_idx = ret;
129
130 wake_up(&i2c->wait);
131}
132
133static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
134{
135 unsigned long tmp;
136
137 tmp = readl(i2c->regs + S3C2410_IICCON);
138 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
139
140}
141
142static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
143{
144 unsigned long tmp;
145
146 tmp = readl(i2c->regs + S3C2410_IICCON);
147 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
148
149}
150
151/* irq enable/disable functions */
152
153static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
154{
155 unsigned long tmp;
156
157 tmp = readl(i2c->regs + S3C2410_IICCON);
158 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
159}
160
161static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
162{
163 unsigned long tmp;
164
165 tmp = readl(i2c->regs + S3C2410_IICCON);
166 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
167}
168
169
170/* s3c24xx_i2c_message_start
171 *
172 * put the start of a message onto the bus
173*/
174
175static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
176 struct i2c_msg *msg)
177{
178 unsigned int addr = (msg->addr & 0x7f) << 1;
179 unsigned long stat;
180 unsigned long iiccon;
181
182 stat = 0;
183 stat |= S3C2410_IICSTAT_TXRXEN;
184
185 if (msg->flags & I2C_M_RD) {
186 stat |= S3C2410_IICSTAT_MASTER_RX;
187 addr |= 1;
188 } else
189 stat |= S3C2410_IICSTAT_MASTER_TX;
190
191 if (msg->flags & I2C_M_REV_DIR_ADDR)
192 addr ^= 1;
193
194 // todo - check for wether ack wanted or not
195 s3c24xx_i2c_enable_ack(i2c);
196
197 iiccon = readl(i2c->regs + S3C2410_IICCON);
198 writel(stat, i2c->regs + S3C2410_IICSTAT);
199
200 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
201 writeb(addr, i2c->regs + S3C2410_IICDS);
202
203 // delay a bit and reset iiccon before setting start (per samsung)
204 udelay(1);
205 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
206 writel(iiccon, i2c->regs + S3C2410_IICCON);
207
208 stat |= S3C2410_IICSTAT_START;
209 writel(stat, i2c->regs + S3C2410_IICSTAT);
210}
211
212static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
213{
214 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
215
216 dev_dbg(i2c->dev, "STOP\n");
217
218 /* stop the transfer */
219 iicstat &= ~ S3C2410_IICSTAT_START;
220 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
221
222 i2c->state = STATE_STOP;
223
224 s3c24xx_i2c_master_complete(i2c, ret);
225 s3c24xx_i2c_disable_irq(i2c);
226}
227
228/* helper functions to determine the current state in the set of
229 * messages we are sending */
230
231/* is_lastmsg()
232 *
233 * returns TRUE if the current message is the last in the set
234*/
235
236static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
237{
238 return i2c->msg_idx >= (i2c->msg_num - 1);
239}
240
241/* is_msglast
242 *
243 * returns TRUE if we this is the last byte in the current message
244*/
245
246static inline int is_msglast(struct s3c24xx_i2c *i2c)
247{
248 return i2c->msg_ptr == i2c->msg->len-1;
249}
250
251/* is_msgend
252 *
253 * returns TRUE if we reached the end of the current message
254*/
255
256static inline int is_msgend(struct s3c24xx_i2c *i2c)
257{
258 return i2c->msg_ptr >= i2c->msg->len;
259}
260
261/* i2s_s3c_irq_nextbyte
262 *
263 * process an interrupt and work out what to do
264 */
265
266static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
267{
268 unsigned long tmp;
269 unsigned char byte;
270 int ret = 0;
271
272 switch (i2c->state) {
273
274 case STATE_IDLE:
275 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __FUNCTION__);
276 goto out;
277 break;
278
279 case STATE_STOP:
280 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __FUNCTION__);
281 s3c24xx_i2c_disable_irq(i2c);
282 goto out_ack;
283
284 case STATE_START:
285 /* last thing we did was send a start condition on the
286 * bus, or started a new i2c message
287 */
288
289 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
290 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
291 /* ack was not received... */
292
293 dev_dbg(i2c->dev, "ack was not received\n");
294 s3c24xx_i2c_stop(i2c, -EREMOTEIO);
295 goto out_ack;
296 }
297
298 if (i2c->msg->flags & I2C_M_RD)
299 i2c->state = STATE_READ;
300 else
301 i2c->state = STATE_WRITE;
302
303 /* terminate the transfer if there is nothing to do
304 * (used by the i2c probe to find devices */
305
306 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
307 s3c24xx_i2c_stop(i2c, 0);
308 goto out_ack;
309 }
310
311 if (i2c->state == STATE_READ)
312 goto prepare_read;
313
314 /* fall through to the write state, as we will need to
315 * send a byte as well */
316
317 case STATE_WRITE:
318 /* we are writing data to the device... check for the
319 * end of the message, and if so, work out what to do
320 */
321
322 retry_write:
323 if (!is_msgend(i2c)) {
324 byte = i2c->msg->buf[i2c->msg_ptr++];
325 writeb(byte, i2c->regs + S3C2410_IICDS);
326
327 } else if (!is_lastmsg(i2c)) {
328 /* we need to go to the next i2c message */
329
330 dev_dbg(i2c->dev, "WRITE: Next Message\n");
331
332 i2c->msg_ptr = 0;
333 i2c->msg_idx ++;
334 i2c->msg++;
335
336 /* check to see if we need to do another message */
337 if (i2c->msg->flags & I2C_M_NOSTART) {
338
339 if (i2c->msg->flags & I2C_M_RD) {
340 /* cannot do this, the controller
341 * forces us to send a new START
342 * when we change direction */
343
344 s3c24xx_i2c_stop(i2c, -EINVAL);
345 }
346
347 goto retry_write;
348 } else {
349
350 /* send the new start */
351 s3c24xx_i2c_message_start(i2c, i2c->msg);
352 i2c->state = STATE_START;
353 }
354
355 } else {
356 /* send stop */
357
358 s3c24xx_i2c_stop(i2c, 0);
359 }
360 break;
361
362 case STATE_READ:
363 /* we have a byte of data in the data register, do
364 * something with it, and then work out wether we are
365 * going to do any more read/write
366 */
367
368 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK) &&
369 !(is_msglast(i2c) && is_lastmsg(i2c))) {
370
371 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
372 dev_dbg(i2c->dev, "READ: No Ack\n");
373
374 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
375 goto out_ack;
376 }
377 }
378
379 byte = readb(i2c->regs + S3C2410_IICDS);
380 i2c->msg->buf[i2c->msg_ptr++] = byte;
381
382 prepare_read:
383 if (is_msglast(i2c)) {
384 /* last byte of buffer */
385
386 if (is_lastmsg(i2c))
387 s3c24xx_i2c_disable_ack(i2c);
388
389 } else if (is_msgend(i2c)) {
390 /* ok, we've read the entire buffer, see if there
391 * is anything else we need to do */
392
393 if (is_lastmsg(i2c)) {
394 /* last message, send stop and complete */
395 dev_dbg(i2c->dev, "READ: Send Stop\n");
396
397 s3c24xx_i2c_stop(i2c, 0);
398 } else {
399 /* go to the next transfer */
400 dev_dbg(i2c->dev, "READ: Next Transfer\n");
401
402 i2c->msg_ptr = 0;
403 i2c->msg_idx++;
404 i2c->msg++;
405 }
406 }
407
408 break;
409 }
410
411 /* acknowlegde the IRQ and get back on with the work */
412
413 out_ack:
414 tmp = readl(i2c->regs + S3C2410_IICCON);
415 tmp &= ~S3C2410_IICCON_IRQPEND;
416 writel(tmp, i2c->regs + S3C2410_IICCON);
417 out:
418 return ret;
419}
420
421/* s3c24xx_i2c_irq
422 *
423 * top level IRQ servicing routine
424*/
425
426static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id,
427 struct pt_regs *regs)
428{
429 struct s3c24xx_i2c *i2c = dev_id;
430 unsigned long status;
431 unsigned long tmp;
432
433 status = readl(i2c->regs + S3C2410_IICSTAT);
434
435 if (status & S3C2410_IICSTAT_ARBITR) {
436 // deal with arbitration loss
437 dev_err(i2c->dev, "deal with arbitration loss\n");
438 }
439
440 if (i2c->state == STATE_IDLE) {
441 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
442
443 tmp = readl(i2c->regs + S3C2410_IICCON);
444 tmp &= ~S3C2410_IICCON_IRQPEND;
445 writel(tmp, i2c->regs + S3C2410_IICCON);
446 goto out;
447 }
448
449 /* pretty much this leaves us with the fact that we've
450 * transmitted or received whatever byte we last sent */
451
452 i2s_s3c_irq_nextbyte(i2c, status);
453
454 out:
455 return IRQ_HANDLED;
456}
457
458
459/* s3c24xx_i2c_set_master
460 *
461 * get the i2c bus for a master transaction
462*/
463
464static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
465{
466 unsigned long iicstat;
467 int timeout = 400;
468
469 while (timeout-- > 0) {
470 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
471
472 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
473 return 0;
474
475 msleep(1);
476 }
477
478 dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
479 __raw_readl(S3C2410_GPEDAT));
480
481 return -ETIMEDOUT;
482}
483
484/* s3c24xx_i2c_doxfer
485 *
486 * this starts an i2c transfer
487*/
488
489static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
490{
491 unsigned long timeout;
492 int ret;
493
494 ret = s3c24xx_i2c_set_master(i2c);
495 if (ret != 0) {
496 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
497 ret = -EAGAIN;
498 goto out;
499 }
500
501 spin_lock_irq(&i2c->lock);
502
503 i2c->msg = msgs;
504 i2c->msg_num = num;
505 i2c->msg_ptr = 0;
506 i2c->msg_idx = 0;
507 i2c->state = STATE_START;
508
509 s3c24xx_i2c_enable_irq(i2c);
510 s3c24xx_i2c_message_start(i2c, msgs);
511 spin_unlock_irq(&i2c->lock);
512
513 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
514
515 ret = i2c->msg_idx;
516
517 /* having these next two as dev_err() makes life very
518 * noisy when doing an i2cdetect */
519
520 if (timeout == 0)
521 dev_dbg(i2c->dev, "timeout\n");
522 else if (ret != num)
523 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
524
525 /* ensure the stop has been through the bus */
526
527 msleep(1);
528
529 out:
530 return ret;
531}
532
533/* s3c24xx_i2c_xfer
534 *
535 * first port of call from the i2c bus code when an message needs
536 * transfering across the i2c bus.
537*/
538
539static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
540 struct i2c_msg *msgs, int num)
541{
542 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
543 int retry;
544 int ret;
545
546 for (retry = 0; retry < adap->retries; retry++) {
547
548 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
549
550 if (ret != -EAGAIN)
551 return ret;
552
553 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
554
555 udelay(100);
556 }
557
558 return -EREMOTEIO;
559}
560
561/* declare our i2c functionality */
562static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
563{
564 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
565}
566
567/* i2c bus registration info */
568
569static struct i2c_algorithm s3c24xx_i2c_algorithm = {
570 .name = "S3C2410-I2C-Algorithm",
571 .master_xfer = s3c24xx_i2c_xfer,
572 .functionality = s3c24xx_i2c_func,
573};
574
575static struct s3c24xx_i2c s3c24xx_i2c = {
576 .lock = SPIN_LOCK_UNLOCKED,
577 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
578 .adap = {
579 .name = "s3c2410-i2c",
580 .owner = THIS_MODULE,
581 .algo = &s3c24xx_i2c_algorithm,
582 .retries = 2,
583 .class = I2C_CLASS_HWMON,
584 },
585};
586
587/* s3c24xx_i2c_calcdivisor
588 *
589 * return the divisor settings for a given frequency
590*/
591
592static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
593 unsigned int *div1, unsigned int *divs)
594{
595 unsigned int calc_divs = clkin / wanted;
596 unsigned int calc_div1;
597
598 if (calc_divs > (16*16))
599 calc_div1 = 512;
600 else
601 calc_div1 = 16;
602
603 calc_divs += calc_div1-1;
604 calc_divs /= calc_div1;
605
606 if (calc_divs == 0)
607 calc_divs = 1;
608 if (calc_divs > 17)
609 calc_divs = 17;
610
611 *divs = calc_divs;
612 *div1 = calc_div1;
613
614 return clkin / (calc_divs * calc_div1);
615}
616
617/* freq_acceptable
618 *
619 * test wether a frequency is within the acceptable range of error
620*/
621
622static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
623{
624 int diff = freq - wanted;
625
626 return (diff >= -2 && diff <= 2);
627}
628
629/* s3c24xx_i2c_getdivisor
630 *
631 * work out a divisor for the user requested frequency setting,
632 * either by the requested frequency, or scanning the acceptable
633 * range of frequencies until something is found
634*/
635
636static int s3c24xx_i2c_getdivisor(struct s3c24xx_i2c *i2c,
637 struct s3c2410_platform_i2c *pdata,
638 unsigned long *iicon,
639 unsigned int *got)
640{
641 unsigned long clkin = clk_get_rate(i2c->clk);
642
643 unsigned int divs, div1;
644 int freq;
645 int start, end;
646
647 clkin /= 1000; /* clkin now in KHz */
648
649 dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
650 pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
651
652 if (pdata->bus_freq != 0) {
653 freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
654 &div1, &divs);
655 if (freq_acceptable(freq, pdata->bus_freq/1000))
656 goto found;
657 }
658
659 /* ok, we may have to search for something suitable... */
660
661 start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
662 end = pdata->min_freq;
663
664 start /= 1000;
665 end /= 1000;
666
667 /* search loop... */
668
669 for (; start > end; start--) {
670 freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
671 if (freq_acceptable(freq, start))
672 goto found;
673 }
674
675 /* cannot find frequency spec */
676
677 return -EINVAL;
678
679 found:
680 *got = freq;
681 *iicon |= (divs-1);
682 *iicon |= (div1 == 512) ? S3C2410_IICCON_TXDIV_512 : 0;
683 return 0;
684}
685
686/* s3c24xx_i2c_init
687 *
688 * initialise the controller, set the IO lines and frequency
689*/
690
691static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
692{
693 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
694 struct s3c2410_platform_i2c *pdata;
695 unsigned int freq;
696
697 /* get the plafrom data */
698
699 pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
700
701 /* inititalise the gpio */
702
703 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
704 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
705
706 /* write slave address */
707
708 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
709
710 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
711
712 /* we need to work out the divisors for the clock... */
713
714 if (s3c24xx_i2c_getdivisor(i2c, pdata, &iicon, &freq) != 0) {
715 dev_err(i2c->dev, "cannot meet bus frequency required\n");
716 return -EINVAL;
717 }
718
719 /* todo - check that the i2c lines aren't being dragged anywhere */
720
721 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
722 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
723
724 writel(iicon, i2c->regs + S3C2410_IICCON);
725
726 /* check for s3c2440 i2c controller */
727
728 if (s3c24xx_i2c_is2440(i2c)) {
729 dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
730
731 writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
732 }
733
734 return 0;
735}
736
737static void s3c24xx_i2c_free(struct s3c24xx_i2c *i2c)
738{
739 if (i2c->clk != NULL && !IS_ERR(i2c->clk)) {
740 clk_disable(i2c->clk);
741 clk_unuse(i2c->clk);
742 clk_put(i2c->clk);
743 i2c->clk = NULL;
744 }
745
746 if (i2c->regs != NULL) {
747 iounmap(i2c->regs);
748 i2c->regs = NULL;
749 }
750
751 if (i2c->ioarea != NULL) {
752 release_resource(i2c->ioarea);
753 kfree(i2c->ioarea);
754 i2c->ioarea = NULL;
755 }
756}
757
758/* s3c24xx_i2c_probe
759 *
760 * called by the bus driver when a suitable device is found
761*/
762
763static int s3c24xx_i2c_probe(struct device *dev)
764{
765 struct platform_device *pdev = to_platform_device(dev);
766 struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
767 struct resource *res;
768 int ret;
769
770 /* find the clock and enable it */
771
772 i2c->dev = dev;
773 i2c->clk = clk_get(dev, "i2c");
774 if (IS_ERR(i2c->clk)) {
775 dev_err(dev, "cannot get clock\n");
776 ret = -ENOENT;
777 goto out;
778 }
779
780 dev_dbg(dev, "clock source %p\n", i2c->clk);
781
782 clk_use(i2c->clk);
783 clk_enable(i2c->clk);
784
785 /* map the registers */
786
787 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
788 if (res == NULL) {
789 dev_err(dev, "cannot find IO resource\n");
790 ret = -ENOENT;
791 goto out;
792 }
793
794 i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
795 pdev->name);
796
797 if (i2c->ioarea == NULL) {
798 dev_err(dev, "cannot request IO\n");
799 ret = -ENXIO;
800 goto out;
801 }
802
803 i2c->regs = ioremap(res->start, (res->end-res->start)+1);
804
805 if (i2c->regs == NULL) {
806 dev_err(dev, "cannot map IO\n");
807 ret = -ENXIO;
808 goto out;
809 }
810
811 dev_dbg(dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
812
813 /* setup info block for the i2c core */
814
815 i2c->adap.algo_data = i2c;
816 i2c->adap.dev.parent = dev;
817
818 /* initialise the i2c controller */
819
820 ret = s3c24xx_i2c_init(i2c);
821 if (ret != 0)
822 goto out;
823
824 /* find the IRQ for this unit (note, this relies on the init call to
825 * ensure no current IRQs pending
826 */
827
828 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
829 if (res == NULL) {
830 dev_err(dev, "cannot find IRQ\n");
831 ret = -ENOENT;
832 goto out;
833 }
834
835 ret = request_irq(res->start, s3c24xx_i2c_irq, SA_INTERRUPT,
836 pdev->name, i2c);
837
838 if (ret != 0) {
839 dev_err(dev, "cannot claim IRQ\n");
840 goto out;
841 }
842
843 i2c->irq = res;
844
845 dev_dbg(dev, "irq resource %p (%ld)\n", res, res->start);
846
847 ret = i2c_add_adapter(&i2c->adap);
848 if (ret < 0) {
849 dev_err(dev, "failed to add bus to i2c core\n");
850 goto out;
851 }
852
853 dev_set_drvdata(dev, i2c);
854
855 dev_info(dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
856
857 out:
858 if (ret < 0)
859 s3c24xx_i2c_free(i2c);
860
861 return ret;
862}
863
864/* s3c24xx_i2c_remove
865 *
866 * called when device is removed from the bus
867*/
868
869static int s3c24xx_i2c_remove(struct device *dev)
870{
871 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
872
873 if (i2c != NULL) {
874 s3c24xx_i2c_free(i2c);
875 dev_set_drvdata(dev, NULL);
876 }
877
878 return 0;
879}
880
881#ifdef CONFIG_PM
882static int s3c24xx_i2c_resume(struct device *dev, u32 level)
883{
884 struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
885
886 if (i2c != NULL && level == RESUME_ENABLE) {
887 dev_dbg(dev, "resume: level %d\n", level);
888 s3c24xx_i2c_init(i2c);
889 }
890
891 return 0;
892}
893
894#else
895#define s3c24xx_i2c_resume NULL
896#endif
897
898/* device driver for platform bus bits */
899
900static struct device_driver s3c2410_i2c_driver = {
901 .name = "s3c2410-i2c",
902 .bus = &platform_bus_type,
903 .probe = s3c24xx_i2c_probe,
904 .remove = s3c24xx_i2c_remove,
905 .resume = s3c24xx_i2c_resume,
906};
907
908static struct device_driver s3c2440_i2c_driver = {
909 .name = "s3c2440-i2c",
910 .bus = &platform_bus_type,
911 .probe = s3c24xx_i2c_probe,
912 .remove = s3c24xx_i2c_remove,
913 .resume = s3c24xx_i2c_resume,
914};
915
916static int __init i2c_adap_s3c_init(void)
917{
918 int ret;
919
920 ret = driver_register(&s3c2410_i2c_driver);
921 if (ret == 0)
922 ret = driver_register(&s3c2440_i2c_driver);
923
924 return ret;
925}
926
927static void __exit i2c_adap_s3c_exit(void)
928{
929 driver_unregister(&s3c2410_i2c_driver);
930 driver_unregister(&s3c2440_i2c_driver);
931}
932
933module_init(i2c_adap_s3c_init);
934module_exit(i2c_adap_s3c_exit);
935
936MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
937MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
938MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)