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41561f28 VW |
1 | /* |
2 | * Provides I2C support for Philips PNX010x/PNX4008 boards. | |
3 | * | |
4 | * Authors: Dennis Kovalev <dkovalev@ru.mvista.com> | |
5 | * Vitaly Wool <vwool@ru.mvista.com> | |
6 | * | |
7 | * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/timer.h> | |
19 | #include <linux/completion.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/i2c-pnx.h> | |
a7d73d8c | 22 | #include <linux/io.h> |
0321cb83 RK |
23 | #include <linux/err.h> |
24 | #include <linux/clk.h> | |
25 | ||
a09e64fb | 26 | #include <mach/hardware.h> |
a7d73d8c | 27 | #include <mach/i2c.h> |
41561f28 VW |
28 | #include <asm/irq.h> |
29 | #include <asm/uaccess.h> | |
30 | ||
31 | #define I2C_PNX_TIMEOUT 10 /* msec */ | |
32 | #define I2C_PNX_SPEED_KHZ 100 | |
33 | #define I2C_PNX_REGION_SIZE 0x100 | |
34 | #define PNX_DEFAULT_FREQ 13 /* MHz */ | |
35 | ||
36 | static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data) | |
37 | { | |
38 | while (timeout > 0 && | |
39 | (ioread32(I2C_REG_STS(data)) & mstatus_active)) { | |
40 | mdelay(1); | |
41 | timeout--; | |
42 | } | |
43 | return (timeout <= 0); | |
44 | } | |
45 | ||
46 | static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data) | |
47 | { | |
48 | while (timeout > 0 && | |
49 | (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) { | |
50 | mdelay(1); | |
51 | timeout--; | |
52 | } | |
53 | return (timeout <= 0); | |
54 | } | |
55 | ||
56 | static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap) | |
57 | { | |
58 | struct i2c_pnx_algo_data *data = adap->algo_data; | |
59 | struct timer_list *timer = &data->mif.timer; | |
60 | int expires = I2C_PNX_TIMEOUT / (1000 / HZ); | |
61 | ||
b2f125bc KW |
62 | if (expires <= 1) |
63 | expires = 2; | |
64 | ||
41561f28 VW |
65 | del_timer_sync(timer); |
66 | ||
67 | dev_dbg(&adap->dev, "Timer armed at %lu plus %u jiffies.\n", | |
68 | jiffies, expires); | |
69 | ||
70 | timer->expires = jiffies + expires; | |
71 | timer->data = (unsigned long)adap; | |
72 | ||
73 | add_timer(timer); | |
74 | } | |
75 | ||
76 | /** | |
77 | * i2c_pnx_start - start a device | |
78 | * @slave_addr: slave address | |
79 | * @adap: pointer to adapter structure | |
80 | * | |
81 | * Generate a START signal in the desired mode. | |
82 | */ | |
83 | static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap) | |
84 | { | |
85 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
86 | ||
08882d20 | 87 | dev_dbg(&adap->dev, "%s(): addr 0x%x mode %d\n", __func__, |
41561f28 VW |
88 | slave_addr, alg_data->mif.mode); |
89 | ||
90 | /* Check for 7 bit slave addresses only */ | |
91 | if (slave_addr & ~0x7f) { | |
92 | dev_err(&adap->dev, "%s: Invalid slave address %x. " | |
93 | "Only 7-bit addresses are supported\n", | |
94 | adap->name, slave_addr); | |
95 | return -EINVAL; | |
96 | } | |
97 | ||
98 | /* First, make sure bus is idle */ | |
99 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) { | |
100 | /* Somebody else is monopolizing the bus */ | |
101 | dev_err(&adap->dev, "%s: Bus busy. Slave addr = %02x, " | |
102 | "cntrl = %x, stat = %x\n", | |
103 | adap->name, slave_addr, | |
104 | ioread32(I2C_REG_CTL(alg_data)), | |
105 | ioread32(I2C_REG_STS(alg_data))); | |
106 | return -EBUSY; | |
107 | } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { | |
108 | /* Sorry, we lost the bus */ | |
109 | dev_err(&adap->dev, "%s: Arbitration failure. " | |
110 | "Slave addr = %02x\n", adap->name, slave_addr); | |
111 | return -EIO; | |
112 | } | |
113 | ||
114 | /* | |
115 | * OK, I2C is enabled and we have the bus. | |
116 | * Clear the current TDI and AFI status flags. | |
117 | */ | |
118 | iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, | |
119 | I2C_REG_STS(alg_data)); | |
120 | ||
08882d20 | 121 | dev_dbg(&adap->dev, "%s(): sending %#x\n", __func__, |
41561f28 VW |
122 | (slave_addr << 1) | start_bit | alg_data->mif.mode); |
123 | ||
124 | /* Write the slave address, START bit and R/W bit */ | |
125 | iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode, | |
126 | I2C_REG_TX(alg_data)); | |
127 | ||
08882d20 | 128 | dev_dbg(&adap->dev, "%s(): exit\n", __func__); |
41561f28 VW |
129 | |
130 | return 0; | |
131 | } | |
132 | ||
133 | /** | |
134 | * i2c_pnx_stop - stop a device | |
135 | * @adap: pointer to I2C adapter structure | |
136 | * | |
137 | * Generate a STOP signal to terminate the master transaction. | |
138 | */ | |
139 | static void i2c_pnx_stop(struct i2c_adapter *adap) | |
140 | { | |
141 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
142 | /* Only 1 msec max timeout due to interrupt context */ | |
143 | long timeout = 1000; | |
144 | ||
145 | dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", | |
08882d20 | 146 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
147 | |
148 | /* Write a STOP bit to TX FIFO */ | |
149 | iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data)); | |
150 | ||
151 | /* Wait until the STOP is seen. */ | |
152 | while (timeout > 0 && | |
153 | (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) { | |
154 | /* may be called from interrupt context */ | |
155 | udelay(1); | |
156 | timeout--; | |
157 | } | |
158 | ||
159 | dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", | |
08882d20 | 160 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
161 | } |
162 | ||
163 | /** | |
164 | * i2c_pnx_master_xmit - transmit data to slave | |
165 | * @adap: pointer to I2C adapter structure | |
166 | * | |
167 | * Sends one byte of data to the slave | |
168 | */ | |
169 | static int i2c_pnx_master_xmit(struct i2c_adapter *adap) | |
170 | { | |
171 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
172 | u32 val; | |
173 | ||
174 | dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", | |
08882d20 | 175 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
176 | |
177 | if (alg_data->mif.len > 0) { | |
178 | /* We still have something to talk about... */ | |
179 | val = *alg_data->mif.buf++; | |
180 | ||
181 | if (alg_data->mif.len == 1) { | |
182 | val |= stop_bit; | |
183 | if (!alg_data->last) | |
184 | val |= start_bit; | |
185 | } | |
186 | ||
187 | alg_data->mif.len--; | |
188 | iowrite32(val, I2C_REG_TX(alg_data)); | |
189 | ||
08882d20 | 190 | dev_dbg(&adap->dev, "%s(): xmit %#x [%d]\n", __func__, |
41561f28 VW |
191 | val, alg_data->mif.len + 1); |
192 | ||
193 | if (alg_data->mif.len == 0) { | |
194 | if (alg_data->last) { | |
195 | /* Wait until the STOP is seen. */ | |
196 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | |
197 | dev_err(&adap->dev, "The bus is still " | |
198 | "active after timeout\n"); | |
199 | } | |
200 | /* Disable master interrupts */ | |
201 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | |
202 | ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), | |
203 | I2C_REG_CTL(alg_data)); | |
204 | ||
205 | del_timer_sync(&alg_data->mif.timer); | |
206 | ||
207 | dev_dbg(&adap->dev, "%s(): Waking up xfer routine.\n", | |
08882d20 | 208 | __func__); |
41561f28 VW |
209 | |
210 | complete(&alg_data->mif.complete); | |
211 | } | |
212 | } else if (alg_data->mif.len == 0) { | |
213 | /* zero-sized transfer */ | |
214 | i2c_pnx_stop(adap); | |
215 | ||
216 | /* Disable master interrupts. */ | |
217 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | |
218 | ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), | |
219 | I2C_REG_CTL(alg_data)); | |
220 | ||
221 | /* Stop timer. */ | |
222 | del_timer_sync(&alg_data->mif.timer); | |
223 | dev_dbg(&adap->dev, "%s(): Waking up xfer routine after " | |
08882d20 | 224 | "zero-xfer.\n", __func__); |
41561f28 VW |
225 | |
226 | complete(&alg_data->mif.complete); | |
227 | } | |
228 | ||
229 | dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", | |
08882d20 | 230 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
231 | |
232 | return 0; | |
233 | } | |
234 | ||
235 | /** | |
236 | * i2c_pnx_master_rcv - receive data from slave | |
237 | * @adap: pointer to I2C adapter structure | |
238 | * | |
239 | * Reads one byte data from the slave | |
240 | */ | |
241 | static int i2c_pnx_master_rcv(struct i2c_adapter *adap) | |
242 | { | |
243 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
244 | unsigned int val = 0; | |
245 | u32 ctl = 0; | |
246 | ||
247 | dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", | |
08882d20 | 248 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
249 | |
250 | /* Check, whether there is already data, | |
251 | * or we didn't 'ask' for it yet. | |
252 | */ | |
253 | if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) { | |
254 | dev_dbg(&adap->dev, "%s(): Write dummy data to fill " | |
08882d20 | 255 | "Rx-fifo...\n", __func__); |
41561f28 VW |
256 | |
257 | if (alg_data->mif.len == 1) { | |
258 | /* Last byte, do not acknowledge next rcv. */ | |
259 | val |= stop_bit; | |
260 | if (!alg_data->last) | |
261 | val |= start_bit; | |
262 | ||
263 | /* | |
264 | * Enable interrupt RFDAIE (data in Rx fifo), | |
265 | * and disable DRMIE (need data for Tx) | |
266 | */ | |
267 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
268 | ctl |= mcntrl_rffie | mcntrl_daie; | |
269 | ctl &= ~mcntrl_drmie; | |
270 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
271 | } | |
272 | ||
273 | /* | |
274 | * Now we'll 'ask' for data: | |
275 | * For each byte we want to receive, we must | |
276 | * write a (dummy) byte to the Tx-FIFO. | |
277 | */ | |
278 | iowrite32(val, I2C_REG_TX(alg_data)); | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
283 | /* Handle data. */ | |
284 | if (alg_data->mif.len > 0) { | |
285 | val = ioread32(I2C_REG_RX(alg_data)); | |
286 | *alg_data->mif.buf++ = (u8) (val & 0xff); | |
08882d20 | 287 | dev_dbg(&adap->dev, "%s(): rcv 0x%x [%d]\n", __func__, val, |
41561f28 VW |
288 | alg_data->mif.len); |
289 | ||
290 | alg_data->mif.len--; | |
291 | if (alg_data->mif.len == 0) { | |
292 | if (alg_data->last) | |
293 | /* Wait until the STOP is seen. */ | |
294 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | |
295 | dev_err(&adap->dev, "The bus is still " | |
296 | "active after timeout\n"); | |
297 | ||
298 | /* Disable master interrupts */ | |
299 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
300 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
301 | mcntrl_drmie | mcntrl_daie); | |
302 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
303 | ||
304 | /* Kill timer. */ | |
305 | del_timer_sync(&alg_data->mif.timer); | |
306 | complete(&alg_data->mif.complete); | |
307 | } | |
308 | } | |
309 | ||
310 | dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", | |
08882d20 | 311 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
312 | |
313 | return 0; | |
314 | } | |
315 | ||
6c566fb7 | 316 | static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) |
41561f28 VW |
317 | { |
318 | u32 stat, ctl; | |
319 | struct i2c_adapter *adap = dev_id; | |
320 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
321 | ||
322 | dev_dbg(&adap->dev, "%s(): mstat = %x mctrl = %x, mode = %d\n", | |
08882d20 | 323 | __func__, |
41561f28 VW |
324 | ioread32(I2C_REG_STS(alg_data)), |
325 | ioread32(I2C_REG_CTL(alg_data)), | |
326 | alg_data->mif.mode); | |
327 | stat = ioread32(I2C_REG_STS(alg_data)); | |
328 | ||
329 | /* let's see what kind of event this is */ | |
330 | if (stat & mstatus_afi) { | |
331 | /* We lost arbitration in the midst of a transfer */ | |
332 | alg_data->mif.ret = -EIO; | |
333 | ||
334 | /* Disable master interrupts. */ | |
335 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
336 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
337 | mcntrl_drmie); | |
338 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
339 | ||
340 | /* Stop timer, to prevent timeout. */ | |
341 | del_timer_sync(&alg_data->mif.timer); | |
342 | complete(&alg_data->mif.complete); | |
343 | } else if (stat & mstatus_nai) { | |
344 | /* Slave did not acknowledge, generate a STOP */ | |
345 | dev_dbg(&adap->dev, "%s(): " | |
346 | "Slave did not acknowledge, generating a STOP.\n", | |
08882d20 | 347 | __func__); |
41561f28 VW |
348 | i2c_pnx_stop(adap); |
349 | ||
350 | /* Disable master interrupts. */ | |
351 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
352 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | | |
353 | mcntrl_drmie); | |
354 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
355 | ||
356 | /* Our return value. */ | |
357 | alg_data->mif.ret = -EIO; | |
358 | ||
359 | /* Stop timer, to prevent timeout. */ | |
360 | del_timer_sync(&alg_data->mif.timer); | |
361 | complete(&alg_data->mif.complete); | |
362 | } else { | |
363 | /* | |
364 | * Two options: | |
365 | * - Master Tx needs data. | |
366 | * - There is data in the Rx-fifo | |
367 | * The latter is only the case if we have requested for data, | |
368 | * via a dummy write. (See 'i2c_pnx_master_rcv'.) | |
369 | * We therefore check, as a sanity check, whether that interrupt | |
370 | * has been enabled. | |
371 | */ | |
372 | if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) { | |
373 | if (alg_data->mif.mode == I2C_SMBUS_WRITE) { | |
374 | i2c_pnx_master_xmit(adap); | |
375 | } else if (alg_data->mif.mode == I2C_SMBUS_READ) { | |
376 | i2c_pnx_master_rcv(adap); | |
377 | } | |
378 | } | |
379 | } | |
380 | ||
381 | /* Clear TDI and AFI bits */ | |
382 | stat = ioread32(I2C_REG_STS(alg_data)); | |
383 | iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data)); | |
384 | ||
385 | dev_dbg(&adap->dev, "%s(): exiting, stat = %x ctrl = %x.\n", | |
08882d20 | 386 | __func__, ioread32(I2C_REG_STS(alg_data)), |
41561f28 VW |
387 | ioread32(I2C_REG_CTL(alg_data))); |
388 | ||
389 | return IRQ_HANDLED; | |
390 | } | |
391 | ||
392 | static void i2c_pnx_timeout(unsigned long data) | |
393 | { | |
394 | struct i2c_adapter *adap = (struct i2c_adapter *)data; | |
395 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
396 | u32 ctl; | |
397 | ||
398 | dev_err(&adap->dev, "Master timed out. stat = %04x, cntrl = %04x. " | |
399 | "Resetting master...\n", | |
400 | ioread32(I2C_REG_STS(alg_data)), | |
401 | ioread32(I2C_REG_CTL(alg_data))); | |
402 | ||
403 | /* Reset master and disable interrupts */ | |
404 | ctl = ioread32(I2C_REG_CTL(alg_data)); | |
405 | ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie); | |
406 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
407 | ||
408 | ctl |= mcntrl_reset; | |
409 | iowrite32(ctl, I2C_REG_CTL(alg_data)); | |
410 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
411 | alg_data->mif.ret = -EIO; | |
412 | complete(&alg_data->mif.complete); | |
413 | } | |
414 | ||
415 | static inline void bus_reset_if_active(struct i2c_adapter *adap) | |
416 | { | |
417 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
418 | u32 stat; | |
419 | ||
420 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) { | |
421 | dev_err(&adap->dev, | |
422 | "%s: Bus is still active after xfer. Reset it...\n", | |
423 | adap->name); | |
424 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
425 | I2C_REG_CTL(alg_data)); | |
426 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
427 | } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) { | |
428 | /* If there is data in the fifo's after transfer, | |
429 | * flush fifo's by reset. | |
430 | */ | |
431 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
432 | I2C_REG_CTL(alg_data)); | |
433 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
434 | } else if (stat & mstatus_nai) { | |
435 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | |
436 | I2C_REG_CTL(alg_data)); | |
437 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | |
438 | } | |
439 | } | |
440 | ||
441 | /** | |
442 | * i2c_pnx_xfer - generic transfer entry point | |
443 | * @adap: pointer to I2C adapter structure | |
444 | * @msgs: array of messages | |
445 | * @num: number of messages | |
446 | * | |
447 | * Initiates the transfer | |
448 | */ | |
449 | static int | |
450 | i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
451 | { | |
452 | struct i2c_msg *pmsg; | |
453 | int rc = 0, completed = 0, i; | |
454 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
455 | u32 stat = ioread32(I2C_REG_STS(alg_data)); | |
456 | ||
457 | dev_dbg(&adap->dev, "%s(): entering: %d messages, stat = %04x.\n", | |
08882d20 | 458 | __func__, num, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
459 | |
460 | bus_reset_if_active(adap); | |
461 | ||
462 | /* Process transactions in a loop. */ | |
463 | for (i = 0; rc >= 0 && i < num; i++) { | |
464 | u8 addr; | |
465 | ||
466 | pmsg = &msgs[i]; | |
467 | addr = pmsg->addr; | |
468 | ||
469 | if (pmsg->flags & I2C_M_TEN) { | |
470 | dev_err(&adap->dev, | |
471 | "%s: 10 bits addr not supported!\n", | |
472 | adap->name); | |
473 | rc = -EINVAL; | |
474 | break; | |
475 | } | |
476 | ||
477 | alg_data->mif.buf = pmsg->buf; | |
478 | alg_data->mif.len = pmsg->len; | |
479 | alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ? | |
480 | I2C_SMBUS_READ : I2C_SMBUS_WRITE; | |
481 | alg_data->mif.ret = 0; | |
482 | alg_data->last = (i == num - 1); | |
483 | ||
08882d20 | 484 | dev_dbg(&adap->dev, "%s(): mode %d, %d bytes\n", __func__, |
41561f28 VW |
485 | alg_data->mif.mode, |
486 | alg_data->mif.len); | |
487 | ||
488 | i2c_pnx_arm_timer(adap); | |
489 | ||
490 | /* initialize the completion var */ | |
491 | init_completion(&alg_data->mif.complete); | |
492 | ||
493 | /* Enable master interrupt */ | |
494 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie | | |
495 | mcntrl_naie | mcntrl_drmie, | |
496 | I2C_REG_CTL(alg_data)); | |
497 | ||
498 | /* Put start-code and slave-address on the bus. */ | |
499 | rc = i2c_pnx_start(addr, adap); | |
500 | if (rc < 0) | |
501 | break; | |
502 | ||
503 | /* Wait for completion */ | |
504 | wait_for_completion(&alg_data->mif.complete); | |
505 | ||
506 | if (!(rc = alg_data->mif.ret)) | |
507 | completed++; | |
508 | dev_dbg(&adap->dev, "%s(): Complete, return code = %d.\n", | |
08882d20 | 509 | __func__, rc); |
41561f28 VW |
510 | |
511 | /* Clear TDI and AFI bits in case they are set. */ | |
512 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) { | |
513 | dev_dbg(&adap->dev, | |
514 | "%s: TDI still set... clearing now.\n", | |
515 | adap->name); | |
516 | iowrite32(stat, I2C_REG_STS(alg_data)); | |
517 | } | |
518 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) { | |
519 | dev_dbg(&adap->dev, | |
520 | "%s: AFI still set... clearing now.\n", | |
521 | adap->name); | |
522 | iowrite32(stat, I2C_REG_STS(alg_data)); | |
523 | } | |
524 | } | |
525 | ||
526 | bus_reset_if_active(adap); | |
527 | ||
528 | /* Cleanup to be sure... */ | |
529 | alg_data->mif.buf = NULL; | |
530 | alg_data->mif.len = 0; | |
531 | ||
532 | dev_dbg(&adap->dev, "%s(): exiting, stat = %x\n", | |
08882d20 | 533 | __func__, ioread32(I2C_REG_STS(alg_data))); |
41561f28 VW |
534 | |
535 | if (completed != num) | |
536 | return ((rc < 0) ? rc : -EREMOTEIO); | |
537 | ||
538 | return num; | |
539 | } | |
540 | ||
541 | static u32 i2c_pnx_func(struct i2c_adapter *adapter) | |
542 | { | |
543 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; | |
544 | } | |
545 | ||
546 | static struct i2c_algorithm pnx_algorithm = { | |
547 | .master_xfer = i2c_pnx_xfer, | |
548 | .functionality = i2c_pnx_func, | |
549 | }; | |
550 | ||
a0dcf19f | 551 | #ifdef CONFIG_PM |
41561f28 VW |
552 | static int i2c_pnx_controller_suspend(struct platform_device *pdev, |
553 | pm_message_t state) | |
554 | { | |
555 | struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); | |
0321cb83 RK |
556 | struct i2c_pnx_algo_data *alg_data = i2c_pnx->adapter->algo_data; |
557 | ||
558 | /* FIXME: disable clock? */ | |
559 | clk_set_rate(alg_data->clk, 1); | |
560 | ||
561 | return 0; | |
41561f28 VW |
562 | } |
563 | ||
564 | static int i2c_pnx_controller_resume(struct platform_device *pdev) | |
565 | { | |
566 | struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); | |
0321cb83 RK |
567 | struct i2c_pnx_algo_data *alg_data = i2c_pnx->adapter->algo_data; |
568 | ||
569 | clk_set_rate(alg_data->clk, 1); | |
570 | ||
571 | return 0; | |
41561f28 | 572 | } |
a0dcf19f RK |
573 | #else |
574 | #define i2c_pnx_controller_suspend NULL | |
575 | #define i2c_pnx_controller_resume NULL | |
576 | #endif | |
41561f28 VW |
577 | |
578 | static int __devinit i2c_pnx_probe(struct platform_device *pdev) | |
579 | { | |
580 | unsigned long tmp; | |
581 | int ret = 0; | |
582 | struct i2c_pnx_algo_data *alg_data; | |
583 | int freq_mhz; | |
584 | struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data; | |
585 | ||
586 | if (!i2c_pnx || !i2c_pnx->adapter) { | |
587 | dev_err(&pdev->dev, "%s: no platform data supplied\n", | |
08882d20 | 588 | __func__); |
41561f28 VW |
589 | ret = -EINVAL; |
590 | goto out; | |
591 | } | |
592 | ||
593 | platform_set_drvdata(pdev, i2c_pnx); | |
594 | ||
0321cb83 RK |
595 | i2c_pnx->adapter->algo = &pnx_algorithm; |
596 | alg_data = i2c_pnx->adapter->algo_data; | |
597 | ||
598 | alg_data->clk = clk_get(&pdev->dev, NULL); | |
599 | if (IS_ERR(alg_data->clk)) { | |
600 | ret = PTR_ERR(alg_data->clk); | |
601 | goto out_drvdata; | |
602 | } | |
603 | ||
41561f28 VW |
604 | if (i2c_pnx->calculate_input_freq) |
605 | freq_mhz = i2c_pnx->calculate_input_freq(pdev); | |
606 | else { | |
607 | freq_mhz = PNX_DEFAULT_FREQ; | |
608 | dev_info(&pdev->dev, "Setting bus frequency to default value: " | |
898eb71c | 609 | "%d MHz\n", freq_mhz); |
41561f28 VW |
610 | } |
611 | ||
41561f28 VW |
612 | init_timer(&alg_data->mif.timer); |
613 | alg_data->mif.timer.function = i2c_pnx_timeout; | |
614 | alg_data->mif.timer.data = (unsigned long)i2c_pnx->adapter; | |
615 | ||
616 | /* Register I/O resource */ | |
449d2c75 JL |
617 | if (!request_mem_region(alg_data->base, I2C_PNX_REGION_SIZE, |
618 | pdev->name)) { | |
41561f28 VW |
619 | dev_err(&pdev->dev, |
620 | "I/O region 0x%08x for I2C already in use.\n", | |
621 | alg_data->base); | |
622 | ret = -ENODEV; | |
0321cb83 | 623 | goto out_clkget; |
41561f28 VW |
624 | } |
625 | ||
626 | if (!(alg_data->ioaddr = | |
627 | (u32)ioremap(alg_data->base, I2C_PNX_REGION_SIZE))) { | |
628 | dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n"); | |
629 | ret = -ENOMEM; | |
630 | goto out_release; | |
631 | } | |
632 | ||
0321cb83 | 633 | clk_set_rate(alg_data->clk, 1); |
41561f28 VW |
634 | |
635 | /* | |
636 | * Clock Divisor High This value is the number of system clocks | |
637 | * the serial clock (SCL) will be high. | |
638 | * For example, if the system clock period is 50 ns and the maximum | |
639 | * desired serial period is 10000 ns (100 kHz), then CLKHI would be | |
640 | * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value | |
641 | * programmed into CLKHI will vary from this slightly due to | |
642 | * variations in the output pad's rise and fall times as well as | |
643 | * the deglitching filter length. | |
644 | */ | |
645 | ||
646 | tmp = ((freq_mhz * 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2; | |
647 | iowrite32(tmp, I2C_REG_CKH(alg_data)); | |
648 | iowrite32(tmp, I2C_REG_CKL(alg_data)); | |
649 | ||
650 | iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data)); | |
651 | if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) { | |
652 | ret = -ENODEV; | |
653 | goto out_unmap; | |
654 | } | |
655 | init_completion(&alg_data->mif.complete); | |
656 | ||
657 | ret = request_irq(alg_data->irq, i2c_pnx_interrupt, | |
658 | 0, pdev->name, i2c_pnx->adapter); | |
659 | if (ret) | |
660 | goto out_clock; | |
661 | ||
662 | /* Register this adapter with the I2C subsystem */ | |
663 | i2c_pnx->adapter->dev.parent = &pdev->dev; | |
155a4931 KW |
664 | i2c_pnx->adapter->nr = pdev->id; |
665 | ret = i2c_add_numbered_adapter(i2c_pnx->adapter); | |
41561f28 VW |
666 | if (ret < 0) { |
667 | dev_err(&pdev->dev, "I2C: Failed to add bus\n"); | |
668 | goto out_irq; | |
669 | } | |
670 | ||
671 | dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n", | |
672 | i2c_pnx->adapter->name, alg_data->base, alg_data->irq); | |
673 | ||
674 | return 0; | |
675 | ||
676 | out_irq: | |
f8d5e5a8 | 677 | free_irq(alg_data->irq, i2c_pnx->adapter); |
41561f28 | 678 | out_clock: |
0321cb83 | 679 | clk_set_rate(alg_data->clk, 0); |
41561f28 VW |
680 | out_unmap: |
681 | iounmap((void *)alg_data->ioaddr); | |
682 | out_release: | |
449d2c75 | 683 | release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE); |
0321cb83 RK |
684 | out_clkget: |
685 | clk_put(alg_data->clk); | |
41561f28 VW |
686 | out_drvdata: |
687 | platform_set_drvdata(pdev, NULL); | |
688 | out: | |
689 | return ret; | |
690 | } | |
691 | ||
692 | static int __devexit i2c_pnx_remove(struct platform_device *pdev) | |
693 | { | |
694 | struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); | |
695 | struct i2c_adapter *adap = i2c_pnx->adapter; | |
696 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | |
697 | ||
f8d5e5a8 | 698 | free_irq(alg_data->irq, i2c_pnx->adapter); |
41561f28 | 699 | i2c_del_adapter(adap); |
0321cb83 | 700 | clk_set_rate(alg_data->clk, 0); |
41561f28 | 701 | iounmap((void *)alg_data->ioaddr); |
449d2c75 | 702 | release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE); |
0321cb83 | 703 | clk_put(alg_data->clk); |
41561f28 VW |
704 | platform_set_drvdata(pdev, NULL); |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static struct platform_driver i2c_pnx_driver = { | |
710 | .driver = { | |
711 | .name = "pnx-i2c", | |
712 | .owner = THIS_MODULE, | |
713 | }, | |
714 | .probe = i2c_pnx_probe, | |
715 | .remove = __devexit_p(i2c_pnx_remove), | |
716 | .suspend = i2c_pnx_controller_suspend, | |
717 | .resume = i2c_pnx_controller_resume, | |
718 | }; | |
719 | ||
720 | static int __init i2c_adap_pnx_init(void) | |
721 | { | |
722 | return platform_driver_register(&i2c_pnx_driver); | |
723 | } | |
724 | ||
725 | static void __exit i2c_adap_pnx_exit(void) | |
726 | { | |
727 | platform_driver_unregister(&i2c_pnx_driver); | |
728 | } | |
729 | ||
730 | MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>"); | |
731 | MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses"); | |
732 | MODULE_LICENSE("GPL"); | |
add8eda7 | 733 | MODULE_ALIAS("platform:pnx-i2c"); |
41561f28 | 734 | |
41561f28 VW |
735 | /* We need to make sure I2C is initialized before USB */ |
736 | subsys_initcall(i2c_adap_pnx_init); | |
41561f28 | 737 | module_exit(i2c_adap_pnx_exit); |