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a8da7fec WS |
1 | /* |
2 | * Freescale MXS I2C bus driver | |
3 | * | |
82fa63bd | 4 | * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K. |
a8da7fec WS |
5 | * |
6 | * based on a (non-working) driver which was: | |
7 | * | |
8 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
9 | * | |
a8da7fec WS |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/slab.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/i2c.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/completion.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/jiffies.h> | |
26 | #include <linux/io.h> | |
6b866c15 | 27 | #include <linux/stmp_device.h> |
b2378668 SG |
28 | #include <linux/of.h> |
29 | #include <linux/of_device.h> | |
62885f59 MV |
30 | #include <linux/dma-mapping.h> |
31 | #include <linux/dmaengine.h> | |
a8da7fec WS |
32 | |
33 | #define DRIVER_NAME "mxs-i2c" | |
34 | ||
35 | #define MXS_I2C_CTRL0 (0x00) | |
36 | #define MXS_I2C_CTRL0_SET (0x04) | |
37 | ||
38 | #define MXS_I2C_CTRL0_SFTRST 0x80000000 | |
fc91e401 | 39 | #define MXS_I2C_CTRL0_RUN 0x20000000 |
a8da7fec WS |
40 | #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 |
41 | #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000 | |
42 | #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000 | |
43 | #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000 | |
44 | #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000 | |
45 | #define MXS_I2C_CTRL0_DIRECTION 0x00010000 | |
46 | #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF) | |
47 | ||
cd4f2d4a MV |
48 | #define MXS_I2C_TIMING0 (0x10) |
49 | #define MXS_I2C_TIMING1 (0x20) | |
50 | #define MXS_I2C_TIMING2 (0x30) | |
51 | ||
a8da7fec WS |
52 | #define MXS_I2C_CTRL1 (0x40) |
53 | #define MXS_I2C_CTRL1_SET (0x44) | |
54 | #define MXS_I2C_CTRL1_CLR (0x48) | |
55 | ||
92b775c2 | 56 | #define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 |
a8da7fec WS |
57 | #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80 |
58 | #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40 | |
59 | #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20 | |
60 | #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10 | |
61 | #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08 | |
62 | #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04 | |
63 | #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02 | |
64 | #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01 | |
65 | ||
535ebd21 LS |
66 | #define MXS_I2C_STAT (0x50) |
67 | #define MXS_I2C_STAT_BUS_BUSY 0x00000800 | |
68 | #define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400 | |
69 | ||
fc91e401 MV |
70 | #define MXS_I2C_DATA (0xa0) |
71 | ||
72 | #define MXS_I2C_DEBUG0 (0xb0) | |
73 | #define MXS_I2C_DEBUG0_CLR (0xb8) | |
74 | ||
75 | #define MXS_I2C_DEBUG0_DMAREQ 0x80000000 | |
76 | ||
a8da7fec WS |
77 | #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \ |
78 | MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \ | |
79 | MXS_I2C_CTRL1_EARLY_TERM_IRQ | \ | |
80 | MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \ | |
81 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \ | |
82 | MXS_I2C_CTRL1_SLAVE_IRQ) | |
83 | ||
a8da7fec WS |
84 | |
85 | #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \ | |
86 | MXS_I2C_CTRL0_PRE_SEND_START | \ | |
87 | MXS_I2C_CTRL0_MASTER_MODE | \ | |
88 | MXS_I2C_CTRL0_DIRECTION | \ | |
89 | MXS_I2C_CTRL0_XFER_COUNT(1)) | |
90 | ||
91 | #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \ | |
92 | MXS_I2C_CTRL0_MASTER_MODE | \ | |
93 | MXS_I2C_CTRL0_DIRECTION) | |
94 | ||
95 | #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ | |
96 | MXS_I2C_CTRL0_MASTER_MODE) | |
97 | ||
98 | /** | |
99 | * struct mxs_i2c_dev - per device, private MXS-I2C data | |
100 | * | |
101 | * @dev: driver model device node | |
102 | * @regs: IO registers pointer | |
103 | * @cmd_complete: completion object for transaction wait | |
104 | * @cmd_err: error code for last transaction | |
105 | * @adapter: i2c subsystem adapter node | |
106 | */ | |
107 | struct mxs_i2c_dev { | |
108 | struct device *dev; | |
109 | void __iomem *regs; | |
110 | struct completion cmd_complete; | |
0f40cbc4 | 111 | int cmd_err; |
a8da7fec | 112 | struct i2c_adapter adapter; |
626f0a2f MV |
113 | |
114 | uint32_t timing0; | |
115 | uint32_t timing1; | |
869c6a3e | 116 | uint32_t timing2; |
62885f59 MV |
117 | |
118 | /* DMA support components */ | |
869c6a3e | 119 | struct dma_chan *dmach; |
62885f59 MV |
120 | uint32_t pio_data[2]; |
121 | uint32_t addr_data; | |
122 | struct scatterlist sg_io[2]; | |
123 | bool dma_read; | |
a8da7fec WS |
124 | }; |
125 | ||
63151c53 | 126 | static int mxs_i2c_reset(struct mxs_i2c_dev *i2c) |
a8da7fec | 127 | { |
63151c53 FE |
128 | int ret = stmp_reset_block(i2c->regs); |
129 | if (ret) | |
130 | return ret; | |
cd4f2d4a | 131 | |
626f0a2f MV |
132 | /* |
133 | * Configure timing for the I2C block. The I2C TIMING2 register has to | |
134 | * be programmed with this particular magic number. The rest is derived | |
135 | * from the XTAL speed and requested I2C speed. | |
136 | * | |
137 | * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4]. | |
138 | */ | |
139 | writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0); | |
140 | writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1); | |
869c6a3e | 141 | writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2); |
cd4f2d4a | 142 | |
a8da7fec | 143 | writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); |
63151c53 FE |
144 | |
145 | return 0; | |
a8da7fec WS |
146 | } |
147 | ||
62885f59 MV |
148 | static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c) |
149 | { | |
150 | if (i2c->dma_read) { | |
151 | dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); | |
152 | dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); | |
153 | } else { | |
154 | dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); | |
155 | } | |
156 | } | |
157 | ||
158 | static void mxs_i2c_dma_irq_callback(void *param) | |
159 | { | |
160 | struct mxs_i2c_dev *i2c = param; | |
161 | ||
162 | complete(&i2c->cmd_complete); | |
163 | mxs_i2c_dma_finish(i2c); | |
164 | } | |
165 | ||
166 | static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap, | |
167 | struct i2c_msg *msg, uint32_t flags) | |
168 | { | |
169 | struct dma_async_tx_descriptor *desc; | |
170 | struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); | |
171 | ||
172 | if (msg->flags & I2C_M_RD) { | |
173 | i2c->dma_read = 1; | |
174 | i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_READ; | |
175 | ||
176 | /* | |
177 | * SELECT command. | |
178 | */ | |
179 | ||
180 | /* Queue the PIO register write transfer. */ | |
181 | i2c->pio_data[0] = MXS_CMD_I2C_SELECT; | |
182 | desc = dmaengine_prep_slave_sg(i2c->dmach, | |
183 | (struct scatterlist *)&i2c->pio_data[0], | |
184 | 1, DMA_TRANS_NONE, 0); | |
185 | if (!desc) { | |
186 | dev_err(i2c->dev, | |
187 | "Failed to get PIO reg. write descriptor.\n"); | |
188 | goto select_init_pio_fail; | |
189 | } | |
190 | ||
191 | /* Queue the DMA data transfer. */ | |
192 | sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1); | |
193 | dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); | |
194 | desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1, | |
195 | DMA_MEM_TO_DEV, | |
196 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
197 | if (!desc) { | |
198 | dev_err(i2c->dev, | |
199 | "Failed to get DMA data write descriptor.\n"); | |
200 | goto select_init_dma_fail; | |
201 | } | |
202 | ||
203 | /* | |
204 | * READ command. | |
205 | */ | |
206 | ||
207 | /* Queue the PIO register write transfer. */ | |
208 | i2c->pio_data[1] = flags | MXS_CMD_I2C_READ | | |
209 | MXS_I2C_CTRL0_XFER_COUNT(msg->len); | |
210 | desc = dmaengine_prep_slave_sg(i2c->dmach, | |
211 | (struct scatterlist *)&i2c->pio_data[1], | |
212 | 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT); | |
213 | if (!desc) { | |
214 | dev_err(i2c->dev, | |
215 | "Failed to get PIO reg. write descriptor.\n"); | |
216 | goto select_init_dma_fail; | |
217 | } | |
218 | ||
219 | /* Queue the DMA data transfer. */ | |
220 | sg_init_one(&i2c->sg_io[1], msg->buf, msg->len); | |
221 | dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); | |
222 | desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1, | |
223 | DMA_DEV_TO_MEM, | |
224 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
225 | if (!desc) { | |
226 | dev_err(i2c->dev, | |
227 | "Failed to get DMA data write descriptor.\n"); | |
228 | goto read_init_dma_fail; | |
229 | } | |
230 | } else { | |
231 | i2c->dma_read = 0; | |
232 | i2c->addr_data = (msg->addr << 1) | I2C_SMBUS_WRITE; | |
233 | ||
234 | /* | |
235 | * WRITE command. | |
236 | */ | |
237 | ||
238 | /* Queue the PIO register write transfer. */ | |
239 | i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE | | |
240 | MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1); | |
241 | desc = dmaengine_prep_slave_sg(i2c->dmach, | |
242 | (struct scatterlist *)&i2c->pio_data[0], | |
243 | 1, DMA_TRANS_NONE, 0); | |
244 | if (!desc) { | |
245 | dev_err(i2c->dev, | |
246 | "Failed to get PIO reg. write descriptor.\n"); | |
247 | goto write_init_pio_fail; | |
248 | } | |
249 | ||
250 | /* Queue the DMA data transfer. */ | |
251 | sg_init_table(i2c->sg_io, 2); | |
252 | sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1); | |
253 | sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len); | |
254 | dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); | |
255 | desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2, | |
256 | DMA_MEM_TO_DEV, | |
257 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
258 | if (!desc) { | |
259 | dev_err(i2c->dev, | |
260 | "Failed to get DMA data write descriptor.\n"); | |
261 | goto write_init_dma_fail; | |
262 | } | |
263 | } | |
264 | ||
265 | /* | |
266 | * The last descriptor must have this callback, | |
267 | * to finish the DMA transaction. | |
268 | */ | |
269 | desc->callback = mxs_i2c_dma_irq_callback; | |
270 | desc->callback_param = i2c; | |
271 | ||
272 | /* Start the transfer. */ | |
273 | dmaengine_submit(desc); | |
274 | dma_async_issue_pending(i2c->dmach); | |
275 | return 0; | |
276 | ||
277 | /* Read failpath. */ | |
278 | read_init_dma_fail: | |
279 | dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE); | |
280 | select_init_dma_fail: | |
281 | dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE); | |
282 | select_init_pio_fail: | |
c35d3cfd | 283 | dmaengine_terminate_all(i2c->dmach); |
62885f59 MV |
284 | return -EINVAL; |
285 | ||
286 | /* Write failpath. */ | |
287 | write_init_dma_fail: | |
288 | dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE); | |
289 | write_init_pio_fail: | |
c35d3cfd | 290 | dmaengine_terminate_all(i2c->dmach); |
62885f59 MV |
291 | return -EINVAL; |
292 | } | |
293 | ||
fc91e401 MV |
294 | static int mxs_i2c_pio_wait_dmareq(struct mxs_i2c_dev *i2c) |
295 | { | |
296 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); | |
297 | ||
298 | while (!(readl(i2c->regs + MXS_I2C_DEBUG0) & | |
299 | MXS_I2C_DEBUG0_DMAREQ)) { | |
300 | if (time_after(jiffies, timeout)) | |
301 | return -ETIMEDOUT; | |
302 | cond_resched(); | |
303 | } | |
304 | ||
fc91e401 MV |
305 | return 0; |
306 | } | |
307 | ||
535ebd21 | 308 | static int mxs_i2c_pio_wait_cplt(struct mxs_i2c_dev *i2c, int last) |
fc91e401 MV |
309 | { |
310 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); | |
311 | ||
312 | /* | |
313 | * We do not use interrupts in the PIO mode. Due to the | |
314 | * maximum transfer length being 8 bytes in PIO mode, the | |
315 | * overhead of interrupt would be too large and this would | |
316 | * neglect the gain from using the PIO mode. | |
317 | */ | |
318 | ||
319 | while (!(readl(i2c->regs + MXS_I2C_CTRL1) & | |
320 | MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)) { | |
321 | if (time_after(jiffies, timeout)) | |
322 | return -ETIMEDOUT; | |
323 | cond_resched(); | |
324 | } | |
325 | ||
326 | writel(MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ, | |
327 | i2c->regs + MXS_I2C_CTRL1_CLR); | |
328 | ||
535ebd21 LS |
329 | /* |
330 | * When ending a transfer with a stop, we have to wait for the bus to | |
331 | * go idle before we report the transfer as completed. Otherwise the | |
332 | * start of the next transfer may race with the end of the current one. | |
333 | */ | |
334 | while (last && (readl(i2c->regs + MXS_I2C_STAT) & | |
335 | (MXS_I2C_STAT_BUS_BUSY | MXS_I2C_STAT_CLK_GEN_BUSY))) { | |
336 | if (time_after(jiffies, timeout)) | |
337 | return -ETIMEDOUT; | |
338 | cond_resched(); | |
339 | } | |
340 | ||
fc91e401 MV |
341 | return 0; |
342 | } | |
343 | ||
92b775c2 LS |
344 | static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c) |
345 | { | |
346 | u32 state; | |
347 | ||
348 | state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK; | |
349 | ||
350 | if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ) | |
351 | i2c->cmd_err = -ENXIO; | |
352 | else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ | | |
353 | MXS_I2C_CTRL1_MASTER_LOSS_IRQ | | |
354 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | | |
355 | MXS_I2C_CTRL1_SLAVE_IRQ)) | |
356 | i2c->cmd_err = -EIO; | |
357 | ||
358 | return i2c->cmd_err; | |
359 | } | |
360 | ||
535ebd21 LS |
361 | static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd) |
362 | { | |
363 | u32 reg; | |
364 | ||
365 | writel(cmd, i2c->regs + MXS_I2C_CTRL0); | |
366 | ||
367 | /* readback makes sure the write is latched into hardware */ | |
368 | reg = readl(i2c->regs + MXS_I2C_CTRL0); | |
369 | reg |= MXS_I2C_CTRL0_RUN; | |
370 | writel(reg, i2c->regs + MXS_I2C_CTRL0); | |
371 | } | |
372 | ||
fc91e401 MV |
373 | static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap, |
374 | struct i2c_msg *msg, uint32_t flags) | |
375 | { | |
376 | struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); | |
377 | uint32_t addr_data = msg->addr << 1; | |
378 | uint32_t data = 0; | |
379 | int i, shifts_left, ret; | |
380 | ||
381 | /* Mute IRQs coming from this block. */ | |
382 | writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR); | |
383 | ||
384 | if (msg->flags & I2C_M_RD) { | |
385 | addr_data |= I2C_SMBUS_READ; | |
386 | ||
387 | /* SELECT command. */ | |
535ebd21 | 388 | mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_SELECT); |
fc91e401 MV |
389 | |
390 | ret = mxs_i2c_pio_wait_dmareq(i2c); | |
391 | if (ret) | |
392 | return ret; | |
393 | ||
394 | writel(addr_data, i2c->regs + MXS_I2C_DATA); | |
535ebd21 | 395 | writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR); |
fc91e401 | 396 | |
535ebd21 | 397 | ret = mxs_i2c_pio_wait_cplt(i2c, 0); |
fc91e401 MV |
398 | if (ret) |
399 | return ret; | |
400 | ||
92b775c2 LS |
401 | if (mxs_i2c_pio_check_error_state(i2c)) |
402 | goto cleanup; | |
403 | ||
fc91e401 | 404 | /* READ command. */ |
535ebd21 LS |
405 | mxs_i2c_pio_trigger_cmd(i2c, |
406 | MXS_CMD_I2C_READ | flags | | |
407 | MXS_I2C_CTRL0_XFER_COUNT(msg->len)); | |
fc91e401 MV |
408 | |
409 | for (i = 0; i < msg->len; i++) { | |
410 | if ((i & 3) == 0) { | |
411 | ret = mxs_i2c_pio_wait_dmareq(i2c); | |
412 | if (ret) | |
413 | return ret; | |
414 | data = readl(i2c->regs + MXS_I2C_DATA); | |
535ebd21 LS |
415 | writel(MXS_I2C_DEBUG0_DMAREQ, |
416 | i2c->regs + MXS_I2C_DEBUG0_CLR); | |
fc91e401 MV |
417 | } |
418 | msg->buf[i] = data & 0xff; | |
419 | data >>= 8; | |
420 | } | |
421 | } else { | |
422 | addr_data |= I2C_SMBUS_WRITE; | |
423 | ||
424 | /* WRITE command. */ | |
535ebd21 LS |
425 | mxs_i2c_pio_trigger_cmd(i2c, |
426 | MXS_CMD_I2C_WRITE | flags | | |
427 | MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1)); | |
fc91e401 MV |
428 | |
429 | /* | |
430 | * The LSB of data buffer is the first byte blasted across | |
431 | * the bus. Higher order bytes follow. Thus the following | |
432 | * filling schematic. | |
433 | */ | |
434 | data = addr_data << 24; | |
435 | for (i = 0; i < msg->len; i++) { | |
436 | data >>= 8; | |
437 | data |= (msg->buf[i] << 24); | |
438 | if ((i & 3) == 2) { | |
439 | ret = mxs_i2c_pio_wait_dmareq(i2c); | |
440 | if (ret) | |
441 | return ret; | |
442 | writel(data, i2c->regs + MXS_I2C_DATA); | |
535ebd21 LS |
443 | writel(MXS_I2C_DEBUG0_DMAREQ, |
444 | i2c->regs + MXS_I2C_DEBUG0_CLR); | |
fc91e401 MV |
445 | } |
446 | } | |
447 | ||
448 | shifts_left = 24 - (i & 3) * 8; | |
449 | if (shifts_left) { | |
450 | data >>= shifts_left; | |
451 | ret = mxs_i2c_pio_wait_dmareq(i2c); | |
452 | if (ret) | |
453 | return ret; | |
454 | writel(data, i2c->regs + MXS_I2C_DATA); | |
535ebd21 LS |
455 | writel(MXS_I2C_DEBUG0_DMAREQ, |
456 | i2c->regs + MXS_I2C_DEBUG0_CLR); | |
fc91e401 MV |
457 | } |
458 | } | |
459 | ||
535ebd21 | 460 | ret = mxs_i2c_pio_wait_cplt(i2c, flags & MXS_I2C_CTRL0_POST_SEND_STOP); |
fc91e401 MV |
461 | if (ret) |
462 | return ret; | |
463 | ||
92b775c2 LS |
464 | /* make sure we capture any occurred error into cmd_err */ |
465 | mxs_i2c_pio_check_error_state(i2c); | |
466 | ||
467 | cleanup: | |
fc91e401 MV |
468 | /* Clear any dangling IRQs and re-enable interrupts. */ |
469 | writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR); | |
470 | writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
a8da7fec WS |
475 | /* |
476 | * Low level master read/write transaction. | |
477 | */ | |
478 | static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, | |
479 | int stop) | |
480 | { | |
481 | struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap); | |
63151c53 | 482 | int ret, err; |
a8da7fec WS |
483 | int flags; |
484 | ||
62885f59 MV |
485 | flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0; |
486 | ||
a8da7fec WS |
487 | dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n", |
488 | msg->addr, msg->len, msg->flags, stop); | |
489 | ||
490 | if (msg->len == 0) | |
491 | return -EINVAL; | |
492 | ||
fc91e401 MV |
493 | /* |
494 | * The current boundary to select between PIO/DMA transfer method | |
495 | * is set to 8 bytes, transfers shorter than 8 bytes are transfered | |
496 | * using PIO mode while longer transfers use DMA. The 8 byte border is | |
497 | * based on this empirical measurement and a lot of previous frobbing. | |
498 | */ | |
92b775c2 | 499 | i2c->cmd_err = 0; |
d6e102f4 | 500 | if (0) { /* disable PIO mode until a proper fix is made */ |
fc91e401 | 501 | ret = mxs_i2c_pio_setup_xfer(adap, msg, flags); |
63151c53 FE |
502 | if (ret) { |
503 | err = mxs_i2c_reset(i2c); | |
504 | if (err) | |
505 | return err; | |
506 | } | |
fc91e401 | 507 | } else { |
16735d02 | 508 | reinit_completion(&i2c->cmd_complete); |
fc91e401 MV |
509 | ret = mxs_i2c_dma_setup_xfer(adap, msg, flags); |
510 | if (ret) | |
511 | return ret; | |
a8da7fec | 512 | |
fc91e401 | 513 | ret = wait_for_completion_timeout(&i2c->cmd_complete, |
a8da7fec | 514 | msecs_to_jiffies(1000)); |
fc91e401 MV |
515 | if (ret == 0) |
516 | goto timeout; | |
92b775c2 | 517 | } |
fc91e401 | 518 | |
92b775c2 LS |
519 | if (i2c->cmd_err == -ENXIO) { |
520 | /* | |
521 | * If the transfer fails with a NAK from the slave the | |
522 | * controller halts until it gets told to return to idle state. | |
523 | */ | |
524 | writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK, | |
525 | i2c->regs + MXS_I2C_CTRL1_SET); | |
fc91e401 | 526 | } |
a8da7fec | 527 | |
92b775c2 LS |
528 | ret = i2c->cmd_err; |
529 | ||
fc91e401 | 530 | dev_dbg(i2c->dev, "Done with err=%d\n", ret); |
a8da7fec | 531 | |
fc91e401 | 532 | return ret; |
a8da7fec WS |
533 | |
534 | timeout: | |
535 | dev_dbg(i2c->dev, "Timeout!\n"); | |
82fa63bd | 536 | mxs_i2c_dma_finish(i2c); |
63151c53 FE |
537 | ret = mxs_i2c_reset(i2c); |
538 | if (ret) | |
539 | return ret; | |
540 | ||
a8da7fec WS |
541 | return -ETIMEDOUT; |
542 | } | |
543 | ||
544 | static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], | |
545 | int num) | |
546 | { | |
547 | int i; | |
548 | int err; | |
549 | ||
550 | for (i = 0; i < num; i++) { | |
551 | err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1)); | |
552 | if (err) | |
553 | return err; | |
554 | } | |
555 | ||
556 | return num; | |
557 | } | |
558 | ||
559 | static u32 mxs_i2c_func(struct i2c_adapter *adap) | |
560 | { | |
8f414059 | 561 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
a8da7fec WS |
562 | } |
563 | ||
564 | static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) | |
565 | { | |
566 | struct mxs_i2c_dev *i2c = dev_id; | |
567 | u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK; | |
568 | ||
569 | if (!stat) | |
570 | return IRQ_NONE; | |
571 | ||
572 | if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ) | |
573 | i2c->cmd_err = -ENXIO; | |
574 | else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ | | |
575 | MXS_I2C_CTRL1_MASTER_LOSS_IRQ | | |
576 | MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ)) | |
577 | /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */ | |
578 | i2c->cmd_err = -EIO; | |
a8da7fec | 579 | |
a8da7fec | 580 | writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR); |
844990da | 581 | |
a8da7fec WS |
582 | return IRQ_HANDLED; |
583 | } | |
584 | ||
585 | static const struct i2c_algorithm mxs_i2c_algo = { | |
586 | .master_xfer = mxs_i2c_xfer, | |
587 | .functionality = mxs_i2c_func, | |
588 | }; | |
589 | ||
869c6a3e | 590 | static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed) |
626f0a2f | 591 | { |
869c6a3e | 592 | /* The I2C block clock runs at 24MHz */ |
626f0a2f | 593 | const uint32_t clk = 24000000; |
869c6a3e | 594 | uint32_t divider; |
626f0a2f | 595 | uint16_t high_count, low_count, rcv_count, xmit_count; |
869c6a3e | 596 | uint32_t bus_free, leadin; |
626f0a2f MV |
597 | struct device *dev = i2c->dev; |
598 | ||
869c6a3e LW |
599 | divider = DIV_ROUND_UP(clk, speed); |
600 | ||
601 | if (divider < 25) { | |
602 | /* | |
603 | * limit the divider, so that min(low_count, high_count) | |
604 | * is >= 1 | |
605 | */ | |
606 | divider = 25; | |
607 | dev_warn(dev, | |
608 | "Speed too high (%u.%03u kHz), using %u.%03u kHz\n", | |
609 | speed / 1000, speed % 1000, | |
610 | clk / divider / 1000, clk / divider % 1000); | |
611 | } else if (divider > 1897) { | |
612 | /* | |
613 | * limit the divider, so that max(low_count, high_count) | |
614 | * cannot exceed 1023 | |
615 | */ | |
616 | divider = 1897; | |
617 | dev_warn(dev, | |
618 | "Speed too low (%u.%03u kHz), using %u.%03u kHz\n", | |
619 | speed / 1000, speed % 1000, | |
620 | clk / divider / 1000, clk / divider % 1000); | |
626f0a2f MV |
621 | } |
622 | ||
623 | /* | |
869c6a3e LW |
624 | * The I2C spec specifies the following timing data: |
625 | * standard mode fast mode Bitfield name | |
626 | * tLOW (SCL LOW period) 4700 ns 1300 ns | |
627 | * tHIGH (SCL HIGH period) 4000 ns 600 ns | |
628 | * tSU;DAT (data setup time) 250 ns 100 ns | |
629 | * tHD;STA (START hold time) 4000 ns 600 ns | |
630 | * tBUF (bus free time) 4700 ns 1300 ns | |
626f0a2f | 631 | * |
869c6a3e LW |
632 | * The hardware (of the i.MX28 at least) seems to add 2 additional |
633 | * clock cycles to the low_count and 7 cycles to the high_count. | |
634 | * This is compensated for by subtracting the respective constants | |
635 | * from the values written to the timing registers. | |
626f0a2f | 636 | */ |
869c6a3e LW |
637 | if (speed > 100000) { |
638 | /* fast mode */ | |
639 | low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6)); | |
640 | high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6)); | |
641 | leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000); | |
642 | bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000); | |
643 | } else { | |
644 | /* normal mode */ | |
645 | low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40)); | |
646 | high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40)); | |
647 | leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000); | |
648 | bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000); | |
649 | } | |
650 | rcv_count = high_count * 3 / 8; | |
651 | xmit_count = low_count * 3 / 8; | |
652 | ||
653 | dev_dbg(dev, | |
654 | "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n", | |
655 | speed, clk / divider, divider, low_count, high_count, | |
656 | xmit_count, rcv_count, leadin, bus_free); | |
626f0a2f | 657 | |
869c6a3e LW |
658 | low_count -= 2; |
659 | high_count -= 7; | |
626f0a2f MV |
660 | i2c->timing0 = (high_count << 16) | rcv_count; |
661 | i2c->timing1 = (low_count << 16) | xmit_count; | |
869c6a3e | 662 | i2c->timing2 = (bus_free << 16 | leadin); |
626f0a2f MV |
663 | } |
664 | ||
cd4f2d4a MV |
665 | static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c) |
666 | { | |
667 | uint32_t speed; | |
668 | struct device *dev = i2c->dev; | |
669 | struct device_node *node = dev->of_node; | |
670 | int ret; | |
671 | ||
cd4f2d4a | 672 | ret = of_property_read_u32(node, "clock-frequency", &speed); |
626f0a2f | 673 | if (ret) { |
cd4f2d4a | 674 | dev_warn(dev, "No I2C speed selected, using 100kHz\n"); |
626f0a2f MV |
675 | speed = 100000; |
676 | } | |
677 | ||
678 | mxs_i2c_derive_timing(i2c, speed); | |
cd4f2d4a MV |
679 | |
680 | return 0; | |
681 | } | |
682 | ||
0b255e92 | 683 | static int mxs_i2c_probe(struct platform_device *pdev) |
a8da7fec WS |
684 | { |
685 | struct device *dev = &pdev->dev; | |
686 | struct mxs_i2c_dev *i2c; | |
687 | struct i2c_adapter *adap; | |
688 | struct resource *res; | |
689 | resource_size_t res_size; | |
e5aba13d | 690 | int err, irq; |
a8da7fec WS |
691 | |
692 | i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); | |
693 | if (!i2c) | |
694 | return -ENOMEM; | |
695 | ||
696 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
62885f59 | 697 | irq = platform_get_irq(pdev, 0); |
62885f59 | 698 | |
e5aba13d | 699 | if (!res || irq < 0) |
a8da7fec WS |
700 | return -ENOENT; |
701 | ||
702 | res_size = resource_size(res); | |
703 | if (!devm_request_mem_region(dev, res->start, res_size, res->name)) | |
704 | return -EBUSY; | |
705 | ||
706 | i2c->regs = devm_ioremap_nocache(dev, res->start, res_size); | |
707 | if (!i2c->regs) | |
708 | return -EBUSY; | |
709 | ||
a8da7fec WS |
710 | err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c); |
711 | if (err) | |
712 | return err; | |
713 | ||
714 | i2c->dev = dev; | |
cd4f2d4a | 715 | |
85de7fac MV |
716 | init_completion(&i2c->cmd_complete); |
717 | ||
72ee734a WS |
718 | if (dev->of_node) { |
719 | err = mxs_i2c_get_ofdata(i2c); | |
720 | if (err) | |
721 | return err; | |
722 | } | |
cd4f2d4a | 723 | |
62885f59 | 724 | /* Setup the DMA */ |
e5aba13d | 725 | i2c->dmach = dma_request_slave_channel(dev, "rx-tx"); |
82fa63bd WS |
726 | if (!i2c->dmach) { |
727 | dev_err(dev, "Failed to request dma\n"); | |
728 | return -ENODEV; | |
62885f59 MV |
729 | } |
730 | ||
a8da7fec WS |
731 | platform_set_drvdata(pdev, i2c); |
732 | ||
733 | /* Do reset to enforce correct startup after pinmuxing */ | |
63151c53 FE |
734 | err = mxs_i2c_reset(i2c); |
735 | if (err) | |
736 | return err; | |
a8da7fec WS |
737 | |
738 | adap = &i2c->adapter; | |
739 | strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name)); | |
740 | adap->owner = THIS_MODULE; | |
741 | adap->algo = &mxs_i2c_algo; | |
742 | adap->dev.parent = dev; | |
743 | adap->nr = pdev->id; | |
b2378668 | 744 | adap->dev.of_node = pdev->dev.of_node; |
a8da7fec WS |
745 | i2c_set_adapdata(adap, i2c); |
746 | err = i2c_add_numbered_adapter(adap); | |
747 | if (err) { | |
748 | dev_err(dev, "Failed to add adapter (%d)\n", err); | |
749 | writel(MXS_I2C_CTRL0_SFTRST, | |
750 | i2c->regs + MXS_I2C_CTRL0_SET); | |
751 | return err; | |
752 | } | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
0b255e92 | 757 | static int mxs_i2c_remove(struct platform_device *pdev) |
a8da7fec WS |
758 | { |
759 | struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev); | |
a8da7fec | 760 | |
bf51a8c5 | 761 | i2c_del_adapter(&i2c->adapter); |
a8da7fec | 762 | |
62885f59 MV |
763 | if (i2c->dmach) |
764 | dma_release_channel(i2c->dmach); | |
765 | ||
a8da7fec WS |
766 | writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET); |
767 | ||
a8da7fec WS |
768 | return 0; |
769 | } | |
770 | ||
b2378668 SG |
771 | static const struct of_device_id mxs_i2c_dt_ids[] = { |
772 | { .compatible = "fsl,imx28-i2c", }, | |
773 | { /* sentinel */ } | |
774 | }; | |
775 | MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids); | |
776 | ||
a8da7fec WS |
777 | static struct platform_driver mxs_i2c_driver = { |
778 | .driver = { | |
779 | .name = DRIVER_NAME, | |
780 | .owner = THIS_MODULE, | |
b2378668 | 781 | .of_match_table = mxs_i2c_dt_ids, |
a8da7fec | 782 | }, |
cc40bf9a | 783 | .probe = mxs_i2c_probe, |
0b255e92 | 784 | .remove = mxs_i2c_remove, |
a8da7fec WS |
785 | }; |
786 | ||
787 | static int __init mxs_i2c_init(void) | |
788 | { | |
cc40bf9a | 789 | return platform_driver_register(&mxs_i2c_driver); |
a8da7fec WS |
790 | } |
791 | subsys_initcall(mxs_i2c_init); | |
792 | ||
793 | static void __exit mxs_i2c_exit(void) | |
794 | { | |
795 | platform_driver_unregister(&mxs_i2c_driver); | |
796 | } | |
797 | module_exit(mxs_i2c_exit); | |
798 | ||
799 | MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); | |
800 | MODULE_DESCRIPTION("MXS I2C Bus Driver"); | |
801 | MODULE_LICENSE("GPL"); | |
802 | MODULE_ALIAS("platform:" DRIVER_NAME); |