Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, |
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | |
4 | <mdsxyz123@yahoo.com> | |
84c1af4c | 5 | Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org> |
0cd96eb0 DW |
6 | Copyright (C) 2010 Intel Corporation, |
7 | David Woodhouse <dwmw2@infradead.org> | |
1da177e4 LT |
8 | |
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | /* | |
ae7b0497 JD |
25 | Supports the following Intel I/O Controller Hubs (ICH): |
26 | ||
27 | I/O Block I2C | |
28 | region SMBus Block proc. block | |
29 | Chip name PCI ID size PEC buffer call read | |
30 | ---------------------------------------------------------------------- | |
31 | 82801AA (ICH) 0x2413 16 no no no no | |
32 | 82801AB (ICH0) 0x2423 16 no no no no | |
33 | 82801BA (ICH2) 0x2443 16 no no no no | |
34 | 82801CA (ICH3) 0x2483 32 soft no no no | |
35 | 82801DB (ICH4) 0x24c3 32 hard yes no no | |
36 | 82801E (ICH5) 0x24d3 32 hard yes yes yes | |
37 | 6300ESB 0x25a4 32 hard yes yes yes | |
38 | 82801F (ICH6) 0x266a 32 hard yes yes yes | |
39 | 6310ESB/6320ESB 0x269b 32 hard yes yes yes | |
40 | 82801G (ICH7) 0x27da 32 hard yes yes yes | |
41 | 82801H (ICH8) 0x283e 32 hard yes yes yes | |
42 | 82801I (ICH9) 0x2930 32 hard yes yes yes | |
cb04e95b | 43 | EP80579 (Tolapai) 0x5032 32 hard yes yes yes |
d28dc711 GJ |
44 | ICH10 0x3a30 32 hard yes yes yes |
45 | ICH10 0x3a60 32 hard yes yes yes | |
cb04e95b | 46 | 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes |
662cda8a | 47 | 6 Series (PCH) 0x1c22 32 hard yes yes yes |
e30d9859 | 48 | Patsburg (PCH) 0x1d22 32 hard yes yes yes |
55fee8d7 DW |
49 | Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes |
50 | Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | |
51 | Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | |
662cda8a | 52 | DH89xxCC (PCH) 0x2330 32 hard yes yes yes |
6e2a851e | 53 | Panther Point (PCH) 0x1e22 32 hard yes yes yes |
062737fb | 54 | Lynx Point (PCH) 0x8c22 32 hard yes yes yes |
4a8f1ddd | 55 | Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes |
ae7b0497 JD |
56 | |
57 | Features supported by this driver: | |
58 | Software PEC no | |
59 | Hardware PEC yes | |
60 | Block buffer yes | |
61 | Block process call transaction no | |
6342064c | 62 | I2C block read transaction yes (doesn't use the block buffer) |
55fee8d7 | 63 | Slave mode no |
636752bc | 64 | Interrupt processing yes |
ae7b0497 JD |
65 | |
66 | See the file Documentation/i2c/busses/i2c-i801 for details. | |
1da177e4 LT |
67 | */ |
68 | ||
636752bc | 69 | #include <linux/interrupt.h> |
1da177e4 LT |
70 | #include <linux/module.h> |
71 | #include <linux/pci.h> | |
72 | #include <linux/kernel.h> | |
73 | #include <linux/stddef.h> | |
74 | #include <linux/delay.h> | |
1da177e4 LT |
75 | #include <linux/ioport.h> |
76 | #include <linux/init.h> | |
77 | #include <linux/i2c.h> | |
54fb4a05 | 78 | #include <linux/acpi.h> |
1561bfe5 | 79 | #include <linux/io.h> |
fa5bfab7 | 80 | #include <linux/dmi.h> |
665a96b7 | 81 | #include <linux/slab.h> |
636752bc | 82 | #include <linux/wait.h> |
3ad7ea18 | 83 | #include <linux/err.h> |
f6afc8b1 | 84 | #include <linux/of_i2c.h> |
3ad7ea18 | 85 | |
79e3e5b8 JD |
86 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
87 | defined CONFIG_DMI | |
3ad7ea18 JD |
88 | #include <linux/gpio.h> |
89 | #include <linux/i2c-mux-gpio.h> | |
90 | #include <linux/platform_device.h> | |
91 | #endif | |
1da177e4 | 92 | |
1da177e4 | 93 | /* I801 SMBus address offsets */ |
0cd96eb0 DW |
94 | #define SMBHSTSTS(p) (0 + (p)->smba) |
95 | #define SMBHSTCNT(p) (2 + (p)->smba) | |
96 | #define SMBHSTCMD(p) (3 + (p)->smba) | |
97 | #define SMBHSTADD(p) (4 + (p)->smba) | |
98 | #define SMBHSTDAT0(p) (5 + (p)->smba) | |
99 | #define SMBHSTDAT1(p) (6 + (p)->smba) | |
100 | #define SMBBLKDAT(p) (7 + (p)->smba) | |
101 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ | |
102 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ | |
103 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ | |
1da177e4 LT |
104 | |
105 | /* PCI Address Constants */ | |
6dcc19df | 106 | #define SMBBAR 4 |
636752bc | 107 | #define SMBPCISTS 0x006 |
1da177e4 | 108 | #define SMBHSTCFG 0x040 |
1da177e4 | 109 | |
636752bc DK |
110 | /* Host status bits for SMBPCISTS */ |
111 | #define SMBPCISTS_INTS 0x08 | |
112 | ||
1da177e4 LT |
113 | /* Host configuration bits for SMBHSTCFG */ |
114 | #define SMBHSTCFG_HST_EN 1 | |
115 | #define SMBHSTCFG_SMB_SMI_EN 2 | |
116 | #define SMBHSTCFG_I2C_EN 4 | |
117 | ||
25985edc | 118 | /* Auxiliary control register bits, ICH4+ only */ |
ca8b9e32 OR |
119 | #define SMBAUXCTL_CRC 1 |
120 | #define SMBAUXCTL_E32B 2 | |
121 | ||
1da177e4 | 122 | /* Other settings */ |
84c1af4c | 123 | #define MAX_RETRIES 400 |
1da177e4 LT |
124 | |
125 | /* I801 command constants */ | |
126 | #define I801_QUICK 0x00 | |
127 | #define I801_BYTE 0x04 | |
128 | #define I801_BYTE_DATA 0x08 | |
129 | #define I801_WORD_DATA 0x0C | |
ae7b0497 | 130 | #define I801_PROC_CALL 0x10 /* unimplemented */ |
1da177e4 | 131 | #define I801_BLOCK_DATA 0x14 |
6342064c | 132 | #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ |
edbeea63 DK |
133 | |
134 | /* I801 Host Control register bits */ | |
135 | #define SMBHSTCNT_INTREN 0x01 | |
136 | #define SMBHSTCNT_KILL 0x02 | |
137 | #define SMBHSTCNT_LAST_BYTE 0x20 | |
138 | #define SMBHSTCNT_START 0x40 | |
139 | #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ | |
1da177e4 | 140 | |
ca8b9e32 OR |
141 | /* I801 Hosts Status register bits */ |
142 | #define SMBHSTSTS_BYTE_DONE 0x80 | |
143 | #define SMBHSTSTS_INUSE_STS 0x40 | |
144 | #define SMBHSTSTS_SMBALERT_STS 0x20 | |
145 | #define SMBHSTSTS_FAILED 0x10 | |
146 | #define SMBHSTSTS_BUS_ERR 0x08 | |
147 | #define SMBHSTSTS_DEV_ERR 0x04 | |
148 | #define SMBHSTSTS_INTR 0x02 | |
149 | #define SMBHSTSTS_HOST_BUSY 0x01 | |
1da177e4 | 150 | |
70a1cc19 DK |
151 | #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ |
152 | SMBHSTSTS_DEV_ERR) | |
153 | ||
154 | #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ | |
155 | STATUS_ERROR_FLAGS) | |
cf898dc5 | 156 | |
a6e5e2be JD |
157 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
158 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 | |
159 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | |
55fee8d7 DW |
160 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ |
161 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 | |
162 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | |
163 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | |
6e2a851e | 164 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 |
a6e5e2be JD |
165 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 |
166 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | |
062737fb | 167 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 |
4a8f1ddd | 168 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 |
55fee8d7 | 169 | |
3ad7ea18 JD |
170 | struct i801_mux_config { |
171 | char *gpio_chip; | |
172 | unsigned values[3]; | |
173 | int n_values; | |
174 | unsigned classes[3]; | |
175 | unsigned gpios[2]; /* Relative to gpio_chip->base */ | |
176 | int n_gpios; | |
177 | }; | |
178 | ||
0cd96eb0 DW |
179 | struct i801_priv { |
180 | struct i2c_adapter adapter; | |
181 | unsigned long smba; | |
182 | unsigned char original_hstcfg; | |
183 | struct pci_dev *pci_dev; | |
184 | unsigned int features; | |
636752bc DK |
185 | |
186 | /* isr processing */ | |
187 | wait_queue_head_t waitq; | |
188 | u8 status; | |
d3ff6ce4 DK |
189 | |
190 | /* Command state used by isr for byte-by-byte block transactions */ | |
191 | u8 cmd; | |
192 | bool is_read; | |
193 | int count; | |
194 | int len; | |
195 | u8 *data; | |
3ad7ea18 | 196 | |
79e3e5b8 JD |
197 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
198 | defined CONFIG_DMI | |
3ad7ea18 | 199 | const struct i801_mux_config *mux_drvdata; |
3ad7ea18 JD |
200 | struct platform_device *mux_pdev; |
201 | #endif | |
0cd96eb0 DW |
202 | }; |
203 | ||
d6072f84 | 204 | static struct pci_driver i801_driver; |
369f6f4a JD |
205 | |
206 | #define FEATURE_SMBUS_PEC (1 << 0) | |
207 | #define FEATURE_BLOCK_BUFFER (1 << 1) | |
208 | #define FEATURE_BLOCK_PROC (1 << 2) | |
209 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | |
636752bc | 210 | #define FEATURE_IRQ (1 << 4) |
e7198fbf JD |
211 | /* Not really a feature, but it's convenient to handle it as such */ |
212 | #define FEATURE_IDF (1 << 15) | |
1da177e4 | 213 | |
adff687d JD |
214 | static const char *i801_feature_names[] = { |
215 | "SMBus PEC", | |
216 | "Block buffer", | |
217 | "Block process call", | |
218 | "I2C block read", | |
636752bc | 219 | "Interrupt", |
adff687d JD |
220 | }; |
221 | ||
222 | static unsigned int disable_features; | |
223 | module_param(disable_features, uint, S_IRUGO | S_IWUSR); | |
224 | MODULE_PARM_DESC(disable_features, "Disable selected driver features"); | |
225 | ||
cf898dc5 JD |
226 | /* Make sure the SMBus host is ready to start transmitting. |
227 | Return 0 if it is, -EBUSY if it is not. */ | |
0cd96eb0 | 228 | static int i801_check_pre(struct i801_priv *priv) |
1da177e4 | 229 | { |
2b73809d | 230 | int status; |
1da177e4 | 231 | |
0cd96eb0 | 232 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 | 233 | if (status & SMBHSTSTS_HOST_BUSY) { |
0cd96eb0 | 234 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
cf898dc5 JD |
235 | return -EBUSY; |
236 | } | |
237 | ||
238 | status &= STATUS_FLAGS; | |
239 | if (status) { | |
0cd96eb0 | 240 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
2b73809d | 241 | status); |
0cd96eb0 DW |
242 | outb_p(status, SMBHSTSTS(priv)); |
243 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; | |
cf898dc5 | 244 | if (status) { |
0cd96eb0 | 245 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
246 | "Failed clearing status flags (%02x)\n", |
247 | status); | |
97140342 | 248 | return -EBUSY; |
1da177e4 LT |
249 | } |
250 | } | |
251 | ||
cf898dc5 JD |
252 | return 0; |
253 | } | |
1da177e4 | 254 | |
6cad93c4 JD |
255 | /* |
256 | * Convert the status register to an error code, and clear it. | |
257 | * Note that status only contains the bits we want to clear, not the | |
258 | * actual register value. | |
259 | */ | |
260 | static int i801_check_post(struct i801_priv *priv, int status) | |
cf898dc5 JD |
261 | { |
262 | int result = 0; | |
1da177e4 | 263 | |
636752bc DK |
264 | /* |
265 | * If the SMBus is still busy, we give up | |
266 | * Note: This timeout condition only happens when using polling | |
267 | * transactions. For interrupt operation, NAK/timeout is indicated by | |
268 | * DEV_ERR. | |
269 | */ | |
6cad93c4 | 270 | if (unlikely(status < 0)) { |
0cd96eb0 | 271 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
ca8b9e32 | 272 | /* try to stop the current command */ |
0cd96eb0 DW |
273 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
274 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, | |
275 | SMBHSTCNT(priv)); | |
84c1af4c | 276 | usleep_range(1000, 2000); |
0cd96eb0 DW |
277 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
278 | SMBHSTCNT(priv)); | |
cf898dc5 JD |
279 | |
280 | /* Check if it worked */ | |
0cd96eb0 | 281 | status = inb_p(SMBHSTSTS(priv)); |
cf898dc5 JD |
282 | if ((status & SMBHSTSTS_HOST_BUSY) || |
283 | !(status & SMBHSTSTS_FAILED)) | |
0cd96eb0 | 284 | dev_err(&priv->pci_dev->dev, |
cf898dc5 | 285 | "Failed terminating the transaction\n"); |
0cd96eb0 | 286 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
cf898dc5 | 287 | return -ETIMEDOUT; |
1da177e4 LT |
288 | } |
289 | ||
2b73809d | 290 | if (status & SMBHSTSTS_FAILED) { |
97140342 | 291 | result = -EIO; |
0cd96eb0 | 292 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
cf898dc5 JD |
293 | } |
294 | if (status & SMBHSTSTS_DEV_ERR) { | |
295 | result = -ENXIO; | |
0cd96eb0 | 296 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
1da177e4 | 297 | } |
2b73809d | 298 | if (status & SMBHSTSTS_BUS_ERR) { |
dcb5c923 | 299 | result = -EAGAIN; |
0cd96eb0 | 300 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
1da177e4 LT |
301 | } |
302 | ||
6cad93c4 JD |
303 | /* Clear status flags except BYTE_DONE, to be cleared by caller */ |
304 | outb_p(status, SMBHSTSTS(priv)); | |
1da177e4 | 305 | |
1da177e4 LT |
306 | return result; |
307 | } | |
308 | ||
6cad93c4 JD |
309 | /* Wait for BUSY being cleared and either INTR or an error flag being set */ |
310 | static int i801_wait_intr(struct i801_priv *priv) | |
cf898dc5 | 311 | { |
cf898dc5 | 312 | int timeout = 0; |
6cad93c4 | 313 | int status; |
cf898dc5 JD |
314 | |
315 | /* We will always wait for a fraction of a second! */ | |
316 | do { | |
84c1af4c | 317 | usleep_range(250, 500); |
0cd96eb0 | 318 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
319 | } while (((status & SMBHSTSTS_HOST_BUSY) || |
320 | !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && | |
321 | (timeout++ < MAX_RETRIES)); | |
cf898dc5 | 322 | |
6cad93c4 JD |
323 | if (timeout > MAX_RETRIES) { |
324 | dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); | |
325 | return -ETIMEDOUT; | |
326 | } | |
327 | return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); | |
cf898dc5 JD |
328 | } |
329 | ||
6cad93c4 JD |
330 | /* Wait for either BYTE_DONE or an error flag being set */ |
331 | static int i801_wait_byte_done(struct i801_priv *priv) | |
ca8b9e32 OR |
332 | { |
333 | int timeout = 0; | |
2b73809d | 334 | int status; |
ca8b9e32 | 335 | |
6cad93c4 | 336 | /* We will always wait for a fraction of a second! */ |
ca8b9e32 | 337 | do { |
84c1af4c | 338 | usleep_range(250, 500); |
0cd96eb0 | 339 | status = inb_p(SMBHSTSTS(priv)); |
6cad93c4 JD |
340 | } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && |
341 | (timeout++ < MAX_RETRIES)); | |
342 | ||
343 | if (timeout > MAX_RETRIES) { | |
344 | dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); | |
345 | return -ETIMEDOUT; | |
346 | } | |
347 | return status & STATUS_ERROR_FLAGS; | |
348 | } | |
349 | ||
350 | static int i801_transaction(struct i801_priv *priv, int xact) | |
351 | { | |
352 | int status; | |
353 | int result; | |
ca8b9e32 | 354 | |
6cad93c4 JD |
355 | result = i801_check_pre(priv); |
356 | if (result < 0) | |
357 | return result; | |
4ccc28f7 | 358 | |
636752bc DK |
359 | if (priv->features & FEATURE_IRQ) { |
360 | outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, | |
361 | SMBHSTCNT(priv)); | |
362 | wait_event(priv->waitq, (status = priv->status)); | |
363 | priv->status = 0; | |
364 | return i801_check_post(priv, status); | |
365 | } | |
366 | ||
6cad93c4 JD |
367 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
368 | * SMBSCMD are passed in xact */ | |
369 | outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
370 | ||
371 | status = i801_wait_intr(priv); | |
372 | return i801_check_post(priv, status); | |
ca8b9e32 OR |
373 | } |
374 | ||
0cd96eb0 DW |
375 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
376 | union i2c_smbus_data *data, | |
7edcb9ab OR |
377 | char read_write, int hwpec) |
378 | { | |
379 | int i, len; | |
97140342 | 380 | int status; |
7edcb9ab | 381 | |
0cd96eb0 | 382 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
7edcb9ab OR |
383 | |
384 | /* Use 32-byte buffer to process this transaction */ | |
385 | if (read_write == I2C_SMBUS_WRITE) { | |
386 | len = data->block[0]; | |
0cd96eb0 | 387 | outb_p(len, SMBHSTDAT0(priv)); |
7edcb9ab | 388 | for (i = 0; i < len; i++) |
0cd96eb0 | 389 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
7edcb9ab OR |
390 | } |
391 | ||
37af8711 | 392 | status = i801_transaction(priv, I801_BLOCK_DATA | |
edbeea63 | 393 | (hwpec ? SMBHSTCNT_PEC_EN : 0)); |
97140342 DB |
394 | if (status) |
395 | return status; | |
7edcb9ab OR |
396 | |
397 | if (read_write == I2C_SMBUS_READ) { | |
0cd96eb0 | 398 | len = inb_p(SMBHSTDAT0(priv)); |
7edcb9ab | 399 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
97140342 | 400 | return -EPROTO; |
7edcb9ab OR |
401 | |
402 | data->block[0] = len; | |
403 | for (i = 0; i < len; i++) | |
0cd96eb0 | 404 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
7edcb9ab OR |
405 | } |
406 | return 0; | |
407 | } | |
408 | ||
d3ff6ce4 DK |
409 | static void i801_isr_byte_done(struct i801_priv *priv) |
410 | { | |
411 | if (priv->is_read) { | |
412 | /* For SMBus block reads, length is received with first byte */ | |
413 | if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && | |
414 | (priv->count == 0)) { | |
415 | priv->len = inb_p(SMBHSTDAT0(priv)); | |
416 | if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { | |
417 | dev_err(&priv->pci_dev->dev, | |
418 | "Illegal SMBus block read size %d\n", | |
419 | priv->len); | |
420 | /* FIXME: Recover */ | |
421 | priv->len = I2C_SMBUS_BLOCK_MAX; | |
422 | } else { | |
423 | dev_dbg(&priv->pci_dev->dev, | |
424 | "SMBus block read size is %d\n", | |
425 | priv->len); | |
426 | } | |
427 | priv->data[-1] = priv->len; | |
428 | } | |
429 | ||
430 | /* Read next byte */ | |
431 | if (priv->count < priv->len) | |
432 | priv->data[priv->count++] = inb(SMBBLKDAT(priv)); | |
433 | else | |
434 | dev_dbg(&priv->pci_dev->dev, | |
435 | "Discarding extra byte on block read\n"); | |
436 | ||
437 | /* Set LAST_BYTE for last byte of read transaction */ | |
438 | if (priv->count == priv->len - 1) | |
439 | outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, | |
440 | SMBHSTCNT(priv)); | |
441 | } else if (priv->count < priv->len - 1) { | |
442 | /* Write next byte, except for IRQ after last byte */ | |
443 | outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); | |
444 | } | |
445 | ||
446 | /* Clear BYTE_DONE to continue with next byte */ | |
447 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); | |
448 | } | |
449 | ||
636752bc | 450 | /* |
d3ff6ce4 DK |
451 | * There are two kinds of interrupts: |
452 | * | |
453 | * 1) i801 signals transaction completion with one of these interrupts: | |
454 | * INTR - Success | |
455 | * DEV_ERR - Invalid command, NAK or communication timeout | |
456 | * BUS_ERR - SMI# transaction collision | |
457 | * FAILED - transaction was canceled due to a KILL request | |
458 | * When any of these occur, update ->status and wake up the waitq. | |
459 | * ->status must be cleared before kicking off the next transaction. | |
460 | * | |
461 | * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt | |
462 | * occurs for each byte of a byte-by-byte to prepare the next byte. | |
636752bc DK |
463 | */ |
464 | static irqreturn_t i801_isr(int irq, void *dev_id) | |
465 | { | |
466 | struct i801_priv *priv = dev_id; | |
467 | u16 pcists; | |
468 | u8 status; | |
469 | ||
470 | /* Confirm this is our interrupt */ | |
471 | pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); | |
472 | if (!(pcists & SMBPCISTS_INTS)) | |
473 | return IRQ_NONE; | |
474 | ||
475 | status = inb_p(SMBHSTSTS(priv)); | |
476 | if (status != 0x42) | |
477 | dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status); | |
478 | ||
d3ff6ce4 DK |
479 | if (status & SMBHSTSTS_BYTE_DONE) |
480 | i801_isr_byte_done(priv); | |
481 | ||
636752bc DK |
482 | /* |
483 | * Clear irq sources and report transaction result. | |
484 | * ->status must be cleared before the next transaction is started. | |
485 | */ | |
486 | status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; | |
487 | if (status) { | |
488 | outb_p(status, SMBHSTSTS(priv)); | |
489 | priv->status |= status; | |
490 | wake_up(&priv->waitq); | |
491 | } | |
492 | ||
493 | return IRQ_HANDLED; | |
494 | } | |
495 | ||
efa3cb15 DK |
496 | /* |
497 | * For "byte-by-byte" block transactions: | |
498 | * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 | |
499 | * I2C read uses cmd=I801_I2C_BLOCK_DATA | |
500 | */ | |
0cd96eb0 DW |
501 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
502 | union i2c_smbus_data *data, | |
6342064c JD |
503 | char read_write, int command, |
504 | int hwpec) | |
1da177e4 LT |
505 | { |
506 | int i, len; | |
507 | int smbcmd; | |
2b73809d | 508 | int status; |
cf898dc5 | 509 | int result; |
cf898dc5 | 510 | |
0cd96eb0 | 511 | result = i801_check_pre(priv); |
cf898dc5 JD |
512 | if (result < 0) |
513 | return result; | |
1da177e4 | 514 | |
7edcb9ab | 515 | len = data->block[0]; |
1da177e4 LT |
516 | |
517 | if (read_write == I2C_SMBUS_WRITE) { | |
0cd96eb0 DW |
518 | outb_p(len, SMBHSTDAT0(priv)); |
519 | outb_p(data->block[1], SMBBLKDAT(priv)); | |
1da177e4 LT |
520 | } |
521 | ||
efa3cb15 DK |
522 | if (command == I2C_SMBUS_I2C_BLOCK_DATA && |
523 | read_write == I2C_SMBUS_READ) | |
524 | smbcmd = I801_I2C_BLOCK_DATA; | |
525 | else | |
526 | smbcmd = I801_BLOCK_DATA; | |
527 | ||
d3ff6ce4 DK |
528 | if (priv->features & FEATURE_IRQ) { |
529 | priv->is_read = (read_write == I2C_SMBUS_READ); | |
530 | if (len == 1 && priv->is_read) | |
531 | smbcmd |= SMBHSTCNT_LAST_BYTE; | |
532 | priv->cmd = smbcmd | SMBHSTCNT_INTREN; | |
533 | priv->len = len; | |
534 | priv->count = 0; | |
535 | priv->data = &data->block[1]; | |
536 | ||
537 | outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); | |
538 | wait_event(priv->waitq, (status = priv->status)); | |
539 | priv->status = 0; | |
540 | return i801_check_post(priv, status); | |
541 | } | |
542 | ||
1da177e4 | 543 | for (i = 1; i <= len; i++) { |
efa3cb15 | 544 | if (i == len && read_write == I2C_SMBUS_READ) |
edbeea63 | 545 | smbcmd |= SMBHSTCNT_LAST_BYTE; |
37af8711 | 546 | outb_p(smbcmd, SMBHSTCNT(priv)); |
1da177e4 | 547 | |
1da177e4 | 548 | if (i == 1) |
edbeea63 | 549 | outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, |
0cd96eb0 | 550 | SMBHSTCNT(priv)); |
1da177e4 | 551 | |
6cad93c4 JD |
552 | status = i801_wait_byte_done(priv); |
553 | if (status) | |
554 | goto exit; | |
1da177e4 | 555 | |
6342064c JD |
556 | if (i == 1 && read_write == I2C_SMBUS_READ |
557 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | |
0cd96eb0 | 558 | len = inb_p(SMBHSTDAT0(priv)); |
cf898dc5 | 559 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
0cd96eb0 | 560 | dev_err(&priv->pci_dev->dev, |
cf898dc5 JD |
561 | "Illegal SMBus block read size %d\n", |
562 | len); | |
563 | /* Recover */ | |
0cd96eb0 DW |
564 | while (inb_p(SMBHSTSTS(priv)) & |
565 | SMBHSTSTS_HOST_BUSY) | |
566 | outb_p(SMBHSTSTS_BYTE_DONE, | |
567 | SMBHSTSTS(priv)); | |
568 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | |
97140342 | 569 | return -EPROTO; |
cf898dc5 | 570 | } |
1da177e4 LT |
571 | data->block[0] = len; |
572 | } | |
573 | ||
574 | /* Retrieve/store value in SMBBLKDAT */ | |
575 | if (read_write == I2C_SMBUS_READ) | |
0cd96eb0 | 576 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
1da177e4 | 577 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
0cd96eb0 | 578 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
1da177e4 | 579 | |
cf898dc5 | 580 | /* signals SMBBLKDAT ready */ |
6cad93c4 | 581 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); |
1da177e4 | 582 | } |
cf898dc5 | 583 | |
6cad93c4 JD |
584 | status = i801_wait_intr(priv); |
585 | exit: | |
586 | return i801_check_post(priv, status); | |
7edcb9ab | 587 | } |
1da177e4 | 588 | |
0cd96eb0 | 589 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
7edcb9ab | 590 | { |
0cd96eb0 DW |
591 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
592 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) | |
97140342 | 593 | return -EIO; |
7edcb9ab OR |
594 | return 0; |
595 | } | |
596 | ||
597 | /* Block transaction function */ | |
0cd96eb0 DW |
598 | static int i801_block_transaction(struct i801_priv *priv, |
599 | union i2c_smbus_data *data, char read_write, | |
7edcb9ab OR |
600 | int command, int hwpec) |
601 | { | |
602 | int result = 0; | |
603 | unsigned char hostc; | |
604 | ||
605 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
606 | if (read_write == I2C_SMBUS_WRITE) { | |
607 | /* set I2C_EN bit in configuration register */ | |
0cd96eb0 DW |
608 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
609 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, | |
7edcb9ab | 610 | hostc | SMBHSTCFG_I2C_EN); |
0cd96eb0 DW |
611 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
612 | dev_err(&priv->pci_dev->dev, | |
6342064c | 613 | "I2C block read is unsupported!\n"); |
97140342 | 614 | return -EOPNOTSUPP; |
7edcb9ab OR |
615 | } |
616 | } | |
617 | ||
6342064c JD |
618 | if (read_write == I2C_SMBUS_WRITE |
619 | || command == I2C_SMBUS_I2C_BLOCK_DATA) { | |
7edcb9ab OR |
620 | if (data->block[0] < 1) |
621 | data->block[0] = 1; | |
622 | if (data->block[0] > I2C_SMBUS_BLOCK_MAX) | |
623 | data->block[0] = I2C_SMBUS_BLOCK_MAX; | |
624 | } else { | |
6342064c | 625 | data->block[0] = 32; /* max for SMBus block reads */ |
7edcb9ab OR |
626 | } |
627 | ||
c074c39d JD |
628 | /* Experience has shown that the block buffer can only be used for |
629 | SMBus (not I2C) block transactions, even though the datasheet | |
630 | doesn't mention this limitation. */ | |
0cd96eb0 | 631 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
c074c39d | 632 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
0cd96eb0 DW |
633 | && i801_set_block_buffer_mode(priv) == 0) |
634 | result = i801_block_transaction_by_block(priv, data, | |
635 | read_write, hwpec); | |
7edcb9ab | 636 | else |
0cd96eb0 DW |
637 | result = i801_block_transaction_byte_by_byte(priv, data, |
638 | read_write, | |
6342064c | 639 | command, hwpec); |
7edcb9ab | 640 | |
6342064c JD |
641 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
642 | && read_write == I2C_SMBUS_WRITE) { | |
1da177e4 | 643 | /* restore saved configuration register value */ |
0cd96eb0 | 644 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
1da177e4 LT |
645 | } |
646 | return result; | |
647 | } | |
648 | ||
97140342 | 649 | /* Return negative errno on error. */ |
3fb21c64 | 650 | static s32 i801_access(struct i2c_adapter *adap, u16 addr, |
1da177e4 | 651 | unsigned short flags, char read_write, u8 command, |
3fb21c64 | 652 | int size, union i2c_smbus_data *data) |
1da177e4 | 653 | { |
e8aac4a9 | 654 | int hwpec; |
1da177e4 LT |
655 | int block = 0; |
656 | int ret, xact = 0; | |
0cd96eb0 | 657 | struct i801_priv *priv = i2c_get_adapdata(adap); |
1da177e4 | 658 | |
0cd96eb0 | 659 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
e8aac4a9 JD |
660 | && size != I2C_SMBUS_QUICK |
661 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | |
1da177e4 LT |
662 | |
663 | switch (size) { | |
664 | case I2C_SMBUS_QUICK: | |
665 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 666 | SMBHSTADD(priv)); |
1da177e4 LT |
667 | xact = I801_QUICK; |
668 | break; | |
669 | case I2C_SMBUS_BYTE: | |
670 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 | 671 | SMBHSTADD(priv)); |
1da177e4 | 672 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 673 | outb_p(command, SMBHSTCMD(priv)); |
1da177e4 LT |
674 | xact = I801_BYTE; |
675 | break; | |
676 | case I2C_SMBUS_BYTE_DATA: | |
677 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
678 | SMBHSTADD(priv)); |
679 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 680 | if (read_write == I2C_SMBUS_WRITE) |
0cd96eb0 | 681 | outb_p(data->byte, SMBHSTDAT0(priv)); |
1da177e4 LT |
682 | xact = I801_BYTE_DATA; |
683 | break; | |
684 | case I2C_SMBUS_WORD_DATA: | |
685 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | |
0cd96eb0 DW |
686 | SMBHSTADD(priv)); |
687 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 | 688 | if (read_write == I2C_SMBUS_WRITE) { |
0cd96eb0 DW |
689 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
690 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); | |
1da177e4 LT |
691 | } |
692 | xact = I801_WORD_DATA; | |
693 | break; | |
694 | case I2C_SMBUS_BLOCK_DATA: | |
1da177e4 | 695 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
0cd96eb0 DW |
696 | SMBHSTADD(priv)); |
697 | outb_p(command, SMBHSTCMD(priv)); | |
1da177e4 LT |
698 | block = 1; |
699 | break; | |
6342064c JD |
700 | case I2C_SMBUS_I2C_BLOCK_DATA: |
701 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | |
702 | * bit should be cleared here, even when reading */ | |
0cd96eb0 | 703 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
6342064c JD |
704 | if (read_write == I2C_SMBUS_READ) { |
705 | /* NB: page 240 of ICH5 datasheet also shows | |
706 | * that DATA1 is the cmd field when reading */ | |
0cd96eb0 | 707 | outb_p(command, SMBHSTDAT1(priv)); |
6342064c | 708 | } else |
0cd96eb0 | 709 | outb_p(command, SMBHSTCMD(priv)); |
6342064c JD |
710 | block = 1; |
711 | break; | |
1da177e4 | 712 | default: |
0cd96eb0 DW |
713 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
714 | size); | |
97140342 | 715 | return -EOPNOTSUPP; |
1da177e4 LT |
716 | } |
717 | ||
ca8b9e32 | 718 | if (hwpec) /* enable/disable hardware PEC */ |
0cd96eb0 | 719 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
ca8b9e32 | 720 | else |
0cd96eb0 DW |
721 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
722 | SMBAUXCTL(priv)); | |
e8aac4a9 | 723 | |
3fb21c64 | 724 | if (block) |
0cd96eb0 DW |
725 | ret = i801_block_transaction(priv, data, read_write, size, |
726 | hwpec); | |
7edcb9ab | 727 | else |
37af8711 | 728 | ret = i801_transaction(priv, xact); |
1da177e4 | 729 | |
c79cfbac | 730 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
7edcb9ab OR |
731 | time, so we forcibly disable it after every transaction. Turn off |
732 | E32B for the same reason. */ | |
a0921b6c | 733 | if (hwpec || block) |
0cd96eb0 DW |
734 | outb_p(inb_p(SMBAUXCTL(priv)) & |
735 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
c79cfbac | 736 | |
3fb21c64 | 737 | if (block) |
1da177e4 | 738 | return ret; |
3fb21c64 | 739 | if (ret) |
97140342 | 740 | return ret; |
1da177e4 LT |
741 | if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) |
742 | return 0; | |
743 | ||
744 | switch (xact & 0x7f) { | |
745 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | |
746 | case I801_BYTE_DATA: | |
0cd96eb0 | 747 | data->byte = inb_p(SMBHSTDAT0(priv)); |
1da177e4 LT |
748 | break; |
749 | case I801_WORD_DATA: | |
0cd96eb0 DW |
750 | data->word = inb_p(SMBHSTDAT0(priv)) + |
751 | (inb_p(SMBHSTDAT1(priv)) << 8); | |
1da177e4 LT |
752 | break; |
753 | } | |
754 | return 0; | |
755 | } | |
756 | ||
757 | ||
758 | static u32 i801_func(struct i2c_adapter *adapter) | |
759 | { | |
0cd96eb0 DW |
760 | struct i801_priv *priv = i2c_get_adapdata(adapter); |
761 | ||
1da177e4 | 762 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
369f6f4a JD |
763 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
764 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | |
0cd96eb0 DW |
765 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
766 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? | |
6342064c | 767 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
1da177e4 LT |
768 | } |
769 | ||
8f9082c5 | 770 | static const struct i2c_algorithm smbus_algorithm = { |
1da177e4 LT |
771 | .smbus_xfer = i801_access, |
772 | .functionality = i801_func, | |
773 | }; | |
774 | ||
3527bd50 | 775 | static DEFINE_PCI_DEVICE_TABLE(i801_ids) = { |
1da177e4 LT |
776 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
777 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | |
778 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, | |
779 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, | |
780 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, | |
781 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, | |
782 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, | |
783 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, | |
784 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, | |
b0a70b57 | 785 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
8254fc4a | 786 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
adbc2a10 | 787 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
cb04e95b | 788 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
d28dc711 GJ |
789 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
790 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | |
cb04e95b SH |
791 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
792 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, | |
e30d9859 | 793 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, |
55fee8d7 DW |
794 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, |
795 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | |
796 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | |
662cda8a | 797 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, |
6e2a851e | 798 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, |
062737fb | 799 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, |
4a8f1ddd | 800 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, |
1da177e4 LT |
801 | { 0, } |
802 | }; | |
803 | ||
3fb21c64 | 804 | MODULE_DEVICE_TABLE(pci, i801_ids); |
1da177e4 | 805 | |
8eacfceb | 806 | #if defined CONFIG_X86 && defined CONFIG_DMI |
1561bfe5 JD |
807 | static unsigned char apanel_addr; |
808 | ||
809 | /* Scan the system ROM for the signature "FJKEYINF" */ | |
810 | static __init const void __iomem *bios_signature(const void __iomem *bios) | |
811 | { | |
812 | ssize_t offset; | |
813 | const unsigned char signature[] = "FJKEYINF"; | |
814 | ||
815 | for (offset = 0; offset < 0x10000; offset += 0x10) { | |
816 | if (check_signature(bios + offset, signature, | |
817 | sizeof(signature)-1)) | |
818 | return bios + offset; | |
819 | } | |
820 | return NULL; | |
821 | } | |
822 | ||
823 | static void __init input_apanel_init(void) | |
824 | { | |
825 | void __iomem *bios; | |
826 | const void __iomem *p; | |
827 | ||
828 | bios = ioremap(0xF0000, 0x10000); /* Can't fail */ | |
829 | p = bios_signature(bios); | |
830 | if (p) { | |
831 | /* just use the first address */ | |
832 | apanel_addr = readb(p + 8 + 3) >> 1; | |
833 | } | |
834 | iounmap(bios); | |
835 | } | |
1561bfe5 | 836 | |
fa5bfab7 HG |
837 | struct dmi_onboard_device_info { |
838 | const char *name; | |
839 | u8 type; | |
840 | unsigned short i2c_addr; | |
841 | const char *i2c_type; | |
842 | }; | |
843 | ||
0b255e92 | 844 | static const struct dmi_onboard_device_info dmi_devices[] = { |
fa5bfab7 HG |
845 | { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, |
846 | { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, | |
847 | { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, | |
848 | }; | |
849 | ||
0b255e92 BP |
850 | static void dmi_check_onboard_device(u8 type, const char *name, |
851 | struct i2c_adapter *adap) | |
fa5bfab7 HG |
852 | { |
853 | int i; | |
854 | struct i2c_board_info info; | |
855 | ||
856 | for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { | |
857 | /* & ~0x80, ignore enabled/disabled bit */ | |
858 | if ((type & ~0x80) != dmi_devices[i].type) | |
859 | continue; | |
faabd47f | 860 | if (strcasecmp(name, dmi_devices[i].name)) |
fa5bfab7 HG |
861 | continue; |
862 | ||
863 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
864 | info.addr = dmi_devices[i].i2c_addr; | |
865 | strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); | |
866 | i2c_new_device(adap, &info); | |
867 | break; | |
868 | } | |
869 | } | |
870 | ||
871 | /* We use our own function to check for onboard devices instead of | |
872 | dmi_find_device() as some buggy BIOS's have the devices we are interested | |
873 | in marked as disabled */ | |
0b255e92 | 874 | static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) |
fa5bfab7 HG |
875 | { |
876 | int i, count; | |
877 | ||
878 | if (dm->type != 10) | |
879 | return; | |
880 | ||
881 | count = (dm->length - sizeof(struct dmi_header)) / 2; | |
882 | for (i = 0; i < count; i++) { | |
883 | const u8 *d = (char *)(dm + 1) + (i * 2); | |
884 | const char *name = ((char *) dm) + dm->length; | |
885 | u8 type = d[0]; | |
886 | u8 s = d[1]; | |
887 | ||
888 | if (!s) | |
889 | continue; | |
890 | s--; | |
891 | while (s > 0 && name[0]) { | |
892 | name += strlen(name) + 1; | |
893 | s--; | |
894 | } | |
895 | if (name[0] == 0) /* Bogus string reference */ | |
896 | continue; | |
897 | ||
898 | dmi_check_onboard_device(type, name, adap); | |
899 | } | |
900 | } | |
fa5bfab7 | 901 | |
e7198fbf | 902 | /* Register optional slaves */ |
0b255e92 | 903 | static void i801_probe_optional_slaves(struct i801_priv *priv) |
e7198fbf JD |
904 | { |
905 | /* Only register slaves on main SMBus channel */ | |
906 | if (priv->features & FEATURE_IDF) | |
907 | return; | |
908 | ||
e7198fbf JD |
909 | if (apanel_addr) { |
910 | struct i2c_board_info info; | |
911 | ||
912 | memset(&info, 0, sizeof(struct i2c_board_info)); | |
913 | info.addr = apanel_addr; | |
914 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | |
915 | i2c_new_device(&priv->adapter, &info); | |
916 | } | |
8eacfceb | 917 | |
e7198fbf JD |
918 | if (dmi_name_in_vendors("FUJITSU")) |
919 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | |
e7198fbf | 920 | } |
8eacfceb JD |
921 | #else |
922 | static void __init input_apanel_init(void) {} | |
0b255e92 | 923 | static void i801_probe_optional_slaves(struct i801_priv *priv) {} |
8eacfceb | 924 | #endif /* CONFIG_X86 && CONFIG_DMI */ |
e7198fbf | 925 | |
79e3e5b8 JD |
926 | #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \ |
927 | defined CONFIG_DMI | |
3ad7ea18 JD |
928 | static struct i801_mux_config i801_mux_config_asus_z8_d12 = { |
929 | .gpio_chip = "gpio_ich", | |
930 | .values = { 0x02, 0x03 }, | |
931 | .n_values = 2, | |
932 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
933 | .gpios = { 52, 53 }, | |
934 | .n_gpios = 2, | |
935 | }; | |
936 | ||
937 | static struct i801_mux_config i801_mux_config_asus_z8_d18 = { | |
938 | .gpio_chip = "gpio_ich", | |
939 | .values = { 0x02, 0x03, 0x01 }, | |
940 | .n_values = 3, | |
941 | .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, | |
942 | .gpios = { 52, 53 }, | |
943 | .n_gpios = 2, | |
944 | }; | |
945 | ||
0b255e92 | 946 | static const struct dmi_system_id mux_dmi_table[] = { |
3ad7ea18 JD |
947 | { |
948 | .matches = { | |
949 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
950 | DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), | |
951 | }, | |
952 | .driver_data = &i801_mux_config_asus_z8_d12, | |
953 | }, | |
954 | { | |
955 | .matches = { | |
956 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
957 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), | |
958 | }, | |
959 | .driver_data = &i801_mux_config_asus_z8_d12, | |
960 | }, | |
961 | { | |
962 | .matches = { | |
963 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
964 | DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), | |
965 | }, | |
966 | .driver_data = &i801_mux_config_asus_z8_d12, | |
967 | }, | |
968 | { | |
969 | .matches = { | |
970 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
971 | DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), | |
972 | }, | |
973 | .driver_data = &i801_mux_config_asus_z8_d12, | |
974 | }, | |
975 | { | |
976 | .matches = { | |
977 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
978 | DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), | |
979 | }, | |
980 | .driver_data = &i801_mux_config_asus_z8_d12, | |
981 | }, | |
982 | { | |
983 | .matches = { | |
984 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
985 | DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), | |
986 | }, | |
987 | .driver_data = &i801_mux_config_asus_z8_d12, | |
988 | }, | |
989 | { | |
990 | .matches = { | |
991 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
992 | DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), | |
993 | }, | |
994 | .driver_data = &i801_mux_config_asus_z8_d18, | |
995 | }, | |
996 | { | |
997 | .matches = { | |
998 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
999 | DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), | |
1000 | }, | |
1001 | .driver_data = &i801_mux_config_asus_z8_d18, | |
1002 | }, | |
1003 | { | |
1004 | .matches = { | |
1005 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
1006 | DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), | |
1007 | }, | |
1008 | .driver_data = &i801_mux_config_asus_z8_d12, | |
1009 | }, | |
1010 | { } | |
1011 | }; | |
1012 | ||
3ad7ea18 | 1013 | /* Setup multiplexing if needed */ |
0b255e92 | 1014 | static int i801_add_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1015 | { |
1016 | struct device *dev = &priv->adapter.dev; | |
1017 | const struct i801_mux_config *mux_config; | |
3ad7ea18 | 1018 | struct i2c_mux_gpio_platform_data gpio_data; |
f82b8626 | 1019 | int err; |
3ad7ea18 JD |
1020 | |
1021 | if (!priv->mux_drvdata) | |
1022 | return 0; | |
1023 | mux_config = priv->mux_drvdata; | |
1024 | ||
3ad7ea18 JD |
1025 | /* Prepare the platform data */ |
1026 | memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); | |
1027 | gpio_data.parent = priv->adapter.nr; | |
1028 | gpio_data.values = mux_config->values; | |
1029 | gpio_data.n_values = mux_config->n_values; | |
1030 | gpio_data.classes = mux_config->classes; | |
f82b8626 JD |
1031 | gpio_data.gpio_chip = mux_config->gpio_chip; |
1032 | gpio_data.gpios = mux_config->gpios; | |
3ad7ea18 JD |
1033 | gpio_data.n_gpios = mux_config->n_gpios; |
1034 | gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; | |
1035 | ||
1036 | /* Register the mux device */ | |
1037 | priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", | |
f82b8626 | 1038 | PLATFORM_DEVID_AUTO, &gpio_data, |
3ad7ea18 JD |
1039 | sizeof(struct i2c_mux_gpio_platform_data)); |
1040 | if (IS_ERR(priv->mux_pdev)) { | |
1041 | err = PTR_ERR(priv->mux_pdev); | |
1042 | priv->mux_pdev = NULL; | |
1043 | dev_err(dev, "Failed to register i2c-mux-gpio device\n"); | |
1044 | return err; | |
1045 | } | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
0b255e92 | 1050 | static void i801_del_mux(struct i801_priv *priv) |
3ad7ea18 JD |
1051 | { |
1052 | if (priv->mux_pdev) | |
1053 | platform_device_unregister(priv->mux_pdev); | |
1054 | } | |
1055 | ||
0b255e92 | 1056 | static unsigned int i801_get_adapter_class(struct i801_priv *priv) |
3ad7ea18 JD |
1057 | { |
1058 | const struct dmi_system_id *id; | |
1059 | const struct i801_mux_config *mux_config; | |
1060 | unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1061 | int i; | |
1062 | ||
1063 | id = dmi_first_match(mux_dmi_table); | |
1064 | if (id) { | |
28901f57 | 1065 | /* Remove branch classes from trunk */ |
3ad7ea18 JD |
1066 | mux_config = id->driver_data; |
1067 | for (i = 0; i < mux_config->n_values; i++) | |
1068 | class &= ~mux_config->classes[i]; | |
1069 | ||
1070 | /* Remember for later */ | |
1071 | priv->mux_drvdata = mux_config; | |
1072 | } | |
1073 | ||
1074 | return class; | |
1075 | } | |
1076 | #else | |
1077 | static inline int i801_add_mux(struct i801_priv *priv) { return 0; } | |
1078 | static inline void i801_del_mux(struct i801_priv *priv) { } | |
1079 | ||
1080 | static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) | |
1081 | { | |
1082 | return I2C_CLASS_HWMON | I2C_CLASS_SPD; | |
1083 | } | |
1084 | #endif | |
1085 | ||
0b255e92 | 1086 | static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1da177e4 | 1087 | { |
02dd7ae2 | 1088 | unsigned char temp; |
adff687d | 1089 | int err, i; |
0cd96eb0 DW |
1090 | struct i801_priv *priv; |
1091 | ||
1092 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1093 | if (!priv) | |
1094 | return -ENOMEM; | |
1095 | ||
1096 | i2c_set_adapdata(&priv->adapter, priv); | |
1097 | priv->adapter.owner = THIS_MODULE; | |
3ad7ea18 | 1098 | priv->adapter.class = i801_get_adapter_class(priv); |
0cd96eb0 | 1099 | priv->adapter.algo = &smbus_algorithm; |
1da177e4 | 1100 | |
0cd96eb0 | 1101 | priv->pci_dev = dev; |
250d1bd3 | 1102 | switch (dev->device) { |
e7198fbf JD |
1103 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: |
1104 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | |
1105 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | |
1106 | priv->features |= FEATURE_IDF; | |
1107 | /* fall through */ | |
e0e8398c | 1108 | default: |
0cd96eb0 | 1109 | priv->features |= FEATURE_I2C_BLOCK_READ; |
6676a847 | 1110 | priv->features |= FEATURE_IRQ; |
6342064c JD |
1111 | /* fall through */ |
1112 | case PCI_DEVICE_ID_INTEL_82801DB_3: | |
0cd96eb0 DW |
1113 | priv->features |= FEATURE_SMBUS_PEC; |
1114 | priv->features |= FEATURE_BLOCK_BUFFER; | |
e0e8398c JD |
1115 | /* fall through */ |
1116 | case PCI_DEVICE_ID_INTEL_82801CA_3: | |
1117 | case PCI_DEVICE_ID_INTEL_82801BA_2: | |
1118 | case PCI_DEVICE_ID_INTEL_82801AB_3: | |
1119 | case PCI_DEVICE_ID_INTEL_82801AA_3: | |
250d1bd3 | 1120 | break; |
250d1bd3 | 1121 | } |
02dd7ae2 | 1122 | |
adff687d JD |
1123 | /* Disable features on user request */ |
1124 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | |
0cd96eb0 | 1125 | if (priv->features & disable_features & (1 << i)) |
adff687d JD |
1126 | dev_notice(&dev->dev, "%s disabled by user\n", |
1127 | i801_feature_names[i]); | |
1128 | } | |
0cd96eb0 | 1129 | priv->features &= ~disable_features; |
adff687d | 1130 | |
02dd7ae2 JD |
1131 | err = pci_enable_device(dev); |
1132 | if (err) { | |
1133 | dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", | |
1134 | err); | |
1135 | goto exit; | |
1136 | } | |
1137 | ||
1138 | /* Determine the address of the SMBus area */ | |
0cd96eb0 DW |
1139 | priv->smba = pci_resource_start(dev, SMBBAR); |
1140 | if (!priv->smba) { | |
02dd7ae2 JD |
1141 | dev_err(&dev->dev, "SMBus base address uninitialized, " |
1142 | "upgrade BIOS\n"); | |
1143 | err = -ENODEV; | |
d6fcb3b9 | 1144 | goto exit; |
02dd7ae2 JD |
1145 | } |
1146 | ||
54fb4a05 | 1147 | err = acpi_check_resource_conflict(&dev->resource[SMBBAR]); |
18669eab JD |
1148 | if (err) { |
1149 | err = -ENODEV; | |
54fb4a05 | 1150 | goto exit; |
18669eab | 1151 | } |
54fb4a05 | 1152 | |
02dd7ae2 JD |
1153 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
1154 | if (err) { | |
1155 | dev_err(&dev->dev, "Failed to request SMBus region " | |
0cd96eb0 | 1156 | "0x%lx-0x%Lx\n", priv->smba, |
598736c5 | 1157 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
d6fcb3b9 | 1158 | goto exit; |
02dd7ae2 JD |
1159 | } |
1160 | ||
0cd96eb0 DW |
1161 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
1162 | priv->original_hstcfg = temp; | |
02dd7ae2 JD |
1163 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
1164 | if (!(temp & SMBHSTCFG_HST_EN)) { | |
1165 | dev_info(&dev->dev, "Enabling SMBus device\n"); | |
1166 | temp |= SMBHSTCFG_HST_EN; | |
1167 | } | |
0cd96eb0 | 1168 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
02dd7ae2 | 1169 | |
636752bc | 1170 | if (temp & SMBHSTCFG_SMB_SMI_EN) { |
02dd7ae2 | 1171 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
636752bc DK |
1172 | /* Disable SMBus interrupt feature if SMBus using SMI# */ |
1173 | priv->features &= ~FEATURE_IRQ; | |
636752bc | 1174 | } |
1da177e4 | 1175 | |
a0921b6c | 1176 | /* Clear special mode bits */ |
0cd96eb0 DW |
1177 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
1178 | outb_p(inb_p(SMBAUXCTL(priv)) & | |
1179 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); | |
a0921b6c | 1180 | |
636752bc DK |
1181 | if (priv->features & FEATURE_IRQ) { |
1182 | init_waitqueue_head(&priv->waitq); | |
1183 | ||
1184 | err = request_irq(dev->irq, i801_isr, IRQF_SHARED, | |
1185 | i801_driver.name, priv); | |
1186 | if (err) { | |
1187 | dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", | |
1188 | dev->irq, err); | |
1189 | goto exit_release; | |
1190 | } | |
29b60854 | 1191 | dev_info(&dev->dev, "SMBus using PCI Interrupt\n"); |
636752bc DK |
1192 | } |
1193 | ||
405ae7d3 | 1194 | /* set up the sysfs linkage to our parent device */ |
0cd96eb0 | 1195 | priv->adapter.dev.parent = &dev->dev; |
1da177e4 | 1196 | |
7e2193a8 | 1197 | /* Retry up to 3 times on lost arbitration */ |
0cd96eb0 | 1198 | priv->adapter.retries = 3; |
7e2193a8 | 1199 | |
0cd96eb0 DW |
1200 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
1201 | "SMBus I801 adapter at %04lx", priv->smba); | |
1202 | err = i2c_add_adapter(&priv->adapter); | |
02dd7ae2 JD |
1203 | if (err) { |
1204 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | |
636752bc | 1205 | goto exit_free_irq; |
02dd7ae2 | 1206 | } |
1561bfe5 | 1207 | |
f6afc8b1 | 1208 | of_i2c_register_devices(&priv->adapter); |
e7198fbf | 1209 | i801_probe_optional_slaves(priv); |
3ad7ea18 JD |
1210 | /* We ignore errors - multiplexing is optional */ |
1211 | i801_add_mux(priv); | |
1561bfe5 | 1212 | |
0cd96eb0 | 1213 | pci_set_drvdata(dev, priv); |
636752bc | 1214 | |
d6fcb3b9 | 1215 | return 0; |
02dd7ae2 | 1216 | |
636752bc DK |
1217 | exit_free_irq: |
1218 | if (priv->features & FEATURE_IRQ) | |
1219 | free_irq(dev->irq, priv); | |
d6fcb3b9 DR |
1220 | exit_release: |
1221 | pci_release_region(dev, SMBBAR); | |
02dd7ae2 | 1222 | exit: |
0cd96eb0 | 1223 | kfree(priv); |
02dd7ae2 | 1224 | return err; |
1da177e4 LT |
1225 | } |
1226 | ||
0b255e92 | 1227 | static void i801_remove(struct pci_dev *dev) |
1da177e4 | 1228 | { |
0cd96eb0 DW |
1229 | struct i801_priv *priv = pci_get_drvdata(dev); |
1230 | ||
3ad7ea18 | 1231 | i801_del_mux(priv); |
0cd96eb0 DW |
1232 | i2c_del_adapter(&priv->adapter); |
1233 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | |
636752bc DK |
1234 | |
1235 | if (priv->features & FEATURE_IRQ) | |
1236 | free_irq(dev->irq, priv); | |
6dcc19df | 1237 | pci_release_region(dev, SMBBAR); |
636752bc | 1238 | |
0cd96eb0 DW |
1239 | pci_set_drvdata(dev, NULL); |
1240 | kfree(priv); | |
d6fcb3b9 DR |
1241 | /* |
1242 | * do not call pci_disable_device(dev) since it can cause hard hangs on | |
1243 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | |
1244 | */ | |
1da177e4 LT |
1245 | } |
1246 | ||
a5aaea37 JD |
1247 | #ifdef CONFIG_PM |
1248 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | |
1249 | { | |
0cd96eb0 DW |
1250 | struct i801_priv *priv = pci_get_drvdata(dev); |
1251 | ||
a5aaea37 | 1252 | pci_save_state(dev); |
0cd96eb0 | 1253 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
a5aaea37 JD |
1254 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
1255 | return 0; | |
1256 | } | |
1257 | ||
1258 | static int i801_resume(struct pci_dev *dev) | |
1259 | { | |
1260 | pci_set_power_state(dev, PCI_D0); | |
1261 | pci_restore_state(dev); | |
1262 | return pci_enable_device(dev); | |
1263 | } | |
1264 | #else | |
1265 | #define i801_suspend NULL | |
1266 | #define i801_resume NULL | |
1267 | #endif | |
1268 | ||
1da177e4 LT |
1269 | static struct pci_driver i801_driver = { |
1270 | .name = "i801_smbus", | |
1271 | .id_table = i801_ids, | |
1272 | .probe = i801_probe, | |
0b255e92 | 1273 | .remove = i801_remove, |
a5aaea37 JD |
1274 | .suspend = i801_suspend, |
1275 | .resume = i801_resume, | |
1da177e4 LT |
1276 | }; |
1277 | ||
1278 | static int __init i2c_i801_init(void) | |
1279 | { | |
6aa1464d JD |
1280 | if (dmi_name_in_vendors("FUJITSU")) |
1281 | input_apanel_init(); | |
1da177e4 LT |
1282 | return pci_register_driver(&i801_driver); |
1283 | } | |
1284 | ||
1285 | static void __exit i2c_i801_exit(void) | |
1286 | { | |
1287 | pci_unregister_driver(&i801_driver); | |
1288 | } | |
1289 | ||
6342064c JD |
1290 | MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, " |
1291 | "Jean Delvare <khali@linux-fr.org>"); | |
1da177e4 LT |
1292 | MODULE_DESCRIPTION("I801 SMBus driver"); |
1293 | MODULE_LICENSE("GPL"); | |
1294 | ||
1295 | module_init(i2c_i801_init); | |
1296 | module_exit(i2c_i801_exit); |