Commit | Line | Data |
---|---|---|
1ab52cf9 | 1 | /* |
a0e06ea6 | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
1ab52cf9 BS |
3 | * |
4 | * Based on the TI DAVINCI I2C adapter driver. | |
5 | * | |
6 | * Copyright (C) 2006 Texas Instruments. | |
7 | * Copyright (C) 2007 MontaVista Software Inc. | |
8 | * Copyright (C) 2009 Provigent Ltd. | |
9 | * | |
10 | * ---------------------------------------------------------------------------- | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * ---------------------------------------------------------------------------- | |
26 | * | |
27 | */ | |
e68bb91b | 28 | #include <linux/export.h> |
1ab52cf9 BS |
29 | #include <linux/clk.h> |
30 | #include <linux/errno.h> | |
1ab52cf9 | 31 | #include <linux/err.h> |
2373f6b9 | 32 | #include <linux/i2c.h> |
1ab52cf9 | 33 | #include <linux/interrupt.h> |
1ab52cf9 | 34 | #include <linux/io.h> |
18dbdda8 | 35 | #include <linux/pm_runtime.h> |
2373f6b9 | 36 | #include <linux/delay.h> |
9dd3162d | 37 | #include <linux/module.h> |
2373f6b9 | 38 | #include "i2c-designware-core.h" |
ce6eb574 | 39 | |
f3fa9f3d DB |
40 | /* |
41 | * Registers offset | |
42 | */ | |
43 | #define DW_IC_CON 0x0 | |
44 | #define DW_IC_TAR 0x4 | |
45 | #define DW_IC_DATA_CMD 0x10 | |
46 | #define DW_IC_SS_SCL_HCNT 0x14 | |
47 | #define DW_IC_SS_SCL_LCNT 0x18 | |
48 | #define DW_IC_FS_SCL_HCNT 0x1c | |
49 | #define DW_IC_FS_SCL_LCNT 0x20 | |
50 | #define DW_IC_INTR_STAT 0x2c | |
51 | #define DW_IC_INTR_MASK 0x30 | |
52 | #define DW_IC_RAW_INTR_STAT 0x34 | |
53 | #define DW_IC_RX_TL 0x38 | |
54 | #define DW_IC_TX_TL 0x3c | |
55 | #define DW_IC_CLR_INTR 0x40 | |
56 | #define DW_IC_CLR_RX_UNDER 0x44 | |
57 | #define DW_IC_CLR_RX_OVER 0x48 | |
58 | #define DW_IC_CLR_TX_OVER 0x4c | |
59 | #define DW_IC_CLR_RD_REQ 0x50 | |
60 | #define DW_IC_CLR_TX_ABRT 0x54 | |
61 | #define DW_IC_CLR_RX_DONE 0x58 | |
62 | #define DW_IC_CLR_ACTIVITY 0x5c | |
63 | #define DW_IC_CLR_STOP_DET 0x60 | |
64 | #define DW_IC_CLR_START_DET 0x64 | |
65 | #define DW_IC_CLR_GEN_CALL 0x68 | |
66 | #define DW_IC_ENABLE 0x6c | |
67 | #define DW_IC_STATUS 0x70 | |
68 | #define DW_IC_TXFLR 0x74 | |
69 | #define DW_IC_RXFLR 0x78 | |
70 | #define DW_IC_TX_ABRT_SOURCE 0x80 | |
3ca4ed87 | 71 | #define DW_IC_ENABLE_STATUS 0x9c |
f3fa9f3d DB |
72 | #define DW_IC_COMP_PARAM_1 0xf4 |
73 | #define DW_IC_COMP_TYPE 0xfc | |
74 | #define DW_IC_COMP_TYPE_VALUE 0x44570140 | |
75 | ||
76 | #define DW_IC_INTR_RX_UNDER 0x001 | |
77 | #define DW_IC_INTR_RX_OVER 0x002 | |
78 | #define DW_IC_INTR_RX_FULL 0x004 | |
79 | #define DW_IC_INTR_TX_OVER 0x008 | |
80 | #define DW_IC_INTR_TX_EMPTY 0x010 | |
81 | #define DW_IC_INTR_RD_REQ 0x020 | |
82 | #define DW_IC_INTR_TX_ABRT 0x040 | |
83 | #define DW_IC_INTR_RX_DONE 0x080 | |
84 | #define DW_IC_INTR_ACTIVITY 0x100 | |
85 | #define DW_IC_INTR_STOP_DET 0x200 | |
86 | #define DW_IC_INTR_START_DET 0x400 | |
87 | #define DW_IC_INTR_GEN_CALL 0x800 | |
88 | ||
89 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ | |
90 | DW_IC_INTR_TX_EMPTY | \ | |
91 | DW_IC_INTR_TX_ABRT | \ | |
92 | DW_IC_INTR_STOP_DET) | |
93 | ||
94 | #define DW_IC_STATUS_ACTIVITY 0x1 | |
95 | ||
96 | #define DW_IC_ERR_TX_ABRT 0x1 | |
97 | ||
98 | /* | |
99 | * status codes | |
100 | */ | |
101 | #define STATUS_IDLE 0x0 | |
102 | #define STATUS_WRITE_IN_PROGRESS 0x1 | |
103 | #define STATUS_READ_IN_PROGRESS 0x2 | |
104 | ||
105 | #define TIMEOUT 20 /* ms */ | |
106 | ||
107 | /* | |
108 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register | |
109 | * | |
110 | * only expected abort codes are listed here | |
111 | * refer to the datasheet for the full list | |
112 | */ | |
113 | #define ABRT_7B_ADDR_NOACK 0 | |
114 | #define ABRT_10ADDR1_NOACK 1 | |
115 | #define ABRT_10ADDR2_NOACK 2 | |
116 | #define ABRT_TXDATA_NOACK 3 | |
117 | #define ABRT_GCALL_NOACK 4 | |
118 | #define ABRT_GCALL_READ 5 | |
119 | #define ABRT_SBYTE_ACKDET 7 | |
120 | #define ABRT_SBYTE_NORSTRT 9 | |
121 | #define ABRT_10B_RD_NORSTRT 10 | |
122 | #define ABRT_MASTER_DIS 11 | |
123 | #define ARB_LOST 12 | |
124 | ||
125 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) | |
126 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) | |
127 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) | |
128 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) | |
129 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) | |
130 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) | |
131 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) | |
132 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) | |
133 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) | |
134 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) | |
135 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) | |
136 | ||
137 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ | |
138 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ | |
139 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ | |
140 | DW_IC_TX_ABRT_TXDATA_NOACK | \ | |
141 | DW_IC_TX_ABRT_GCALL_NOACK) | |
142 | ||
1ab52cf9 | 143 | static char *abort_sources[] = { |
a0e06ea6 | 144 | [ABRT_7B_ADDR_NOACK] = |
1ab52cf9 | 145 | "slave address not acknowledged (7bit mode)", |
a0e06ea6 | 146 | [ABRT_10ADDR1_NOACK] = |
1ab52cf9 | 147 | "first address byte not acknowledged (10bit mode)", |
a0e06ea6 | 148 | [ABRT_10ADDR2_NOACK] = |
1ab52cf9 | 149 | "second address byte not acknowledged (10bit mode)", |
a0e06ea6 | 150 | [ABRT_TXDATA_NOACK] = |
1ab52cf9 | 151 | "data not acknowledged", |
a0e06ea6 | 152 | [ABRT_GCALL_NOACK] = |
1ab52cf9 | 153 | "no acknowledgement for a general call", |
a0e06ea6 | 154 | [ABRT_GCALL_READ] = |
1ab52cf9 | 155 | "read after general call", |
a0e06ea6 | 156 | [ABRT_SBYTE_ACKDET] = |
1ab52cf9 | 157 | "start byte acknowledged", |
a0e06ea6 | 158 | [ABRT_SBYTE_NORSTRT] = |
1ab52cf9 | 159 | "trying to send start byte when restart is disabled", |
a0e06ea6 | 160 | [ABRT_10B_RD_NORSTRT] = |
1ab52cf9 | 161 | "trying to read when restart is disabled (10bit mode)", |
a0e06ea6 | 162 | [ABRT_MASTER_DIS] = |
1ab52cf9 | 163 | "trying to use disabled adapter", |
a0e06ea6 | 164 | [ARB_LOST] = |
1ab52cf9 BS |
165 | "lost arbitration", |
166 | }; | |
167 | ||
2373f6b9 | 168 | u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
7f279601 | 169 | { |
a8a9f3fe | 170 | u32 value; |
18c4089e | 171 | |
a8a9f3fe SR |
172 | if (dev->accessor_flags & ACCESS_16BIT) |
173 | value = readw(dev->base + offset) | | |
174 | (readw(dev->base + offset + 2) << 16); | |
175 | else | |
176 | value = readl(dev->base + offset); | |
177 | ||
178 | if (dev->accessor_flags & ACCESS_SWAP) | |
18c4089e JHD |
179 | return swab32(value); |
180 | else | |
181 | return value; | |
7f279601 JHD |
182 | } |
183 | ||
2373f6b9 | 184 | void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
7f279601 | 185 | { |
a8a9f3fe | 186 | if (dev->accessor_flags & ACCESS_SWAP) |
18c4089e JHD |
187 | b = swab32(b); |
188 | ||
a8a9f3fe SR |
189 | if (dev->accessor_flags & ACCESS_16BIT) { |
190 | writew((u16)b, dev->base + offset); | |
191 | writew((u16)(b >> 16), dev->base + offset + 2); | |
192 | } else { | |
193 | writel(b, dev->base + offset); | |
194 | } | |
7f279601 JHD |
195 | } |
196 | ||
d60c7e81 SK |
197 | static u32 |
198 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | |
199 | { | |
200 | /* | |
201 | * DesignWare I2C core doesn't seem to have solid strategy to meet | |
202 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec | |
203 | * will result in violation of the tHD;STA spec. | |
204 | */ | |
205 | if (cond) | |
206 | /* | |
207 | * Conditional expression: | |
208 | * | |
209 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH | |
210 | * | |
211 | * This is based on the DW manuals, and represents an ideal | |
212 | * configuration. The resulting I2C bus speed will be | |
213 | * faster than any of the others. | |
214 | * | |
215 | * If your hardware is free from tHD;STA issue, try this one. | |
216 | */ | |
217 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; | |
218 | else | |
219 | /* | |
220 | * Conditional expression: | |
221 | * | |
222 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) | |
223 | * | |
224 | * This is just experimental rule; the tHD;STA period turned | |
225 | * out to be proportinal to (_HCNT + 3). With this setting, | |
226 | * we could meet both tHIGH and tHD;STA timing specs. | |
227 | * | |
228 | * If unsure, you'd better to take this alternative. | |
229 | * | |
230 | * The reason why we need to take into account "tf" here, | |
231 | * is the same as described in i2c_dw_scl_lcnt(). | |
232 | */ | |
233 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; | |
234 | } | |
235 | ||
236 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) | |
237 | { | |
238 | /* | |
239 | * Conditional expression: | |
240 | * | |
241 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) | |
242 | * | |
243 | * DW I2C core starts counting the SCL CNTs for the LOW period | |
244 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. | |
245 | * In order to meet the tLOW timing spec, we need to take into | |
246 | * account the fall time of SCL signal (tf). Default tf value | |
247 | * should be 0.3 us, for safety. | |
248 | */ | |
249 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; | |
250 | } | |
251 | ||
3ca4ed87 MW |
252 | static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable) |
253 | { | |
254 | int timeout = 100; | |
255 | ||
256 | do { | |
257 | dw_writel(dev, enable, DW_IC_ENABLE); | |
258 | if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable) | |
259 | return; | |
260 | ||
261 | /* | |
262 | * Wait 10 times the signaling period of the highest I2C | |
263 | * transfer supported by the driver (for 400KHz this is | |
264 | * 25us) as described in the DesignWare I2C databook. | |
265 | */ | |
266 | usleep_range(25, 250); | |
267 | } while (timeout--); | |
268 | ||
269 | dev_warn(dev->dev, "timeout in %sabling adapter\n", | |
270 | enable ? "en" : "dis"); | |
271 | } | |
272 | ||
1ab52cf9 BS |
273 | /** |
274 | * i2c_dw_init() - initialize the designware i2c master hardware | |
275 | * @dev: device private data | |
276 | * | |
277 | * This functions configures and enables the I2C master. | |
278 | * This function is called during I2C init function, and in case of timeout at | |
279 | * run time. | |
280 | */ | |
2373f6b9 | 281 | int i2c_dw_init(struct dw_i2c_dev *dev) |
1ab52cf9 | 282 | { |
1d31b58f | 283 | u32 input_clock_khz; |
e18563fc | 284 | u32 hcnt, lcnt; |
4a423a8c DB |
285 | u32 reg; |
286 | ||
1d31b58f DB |
287 | input_clock_khz = dev->get_clk_rate_khz(dev); |
288 | ||
4a423a8c DB |
289 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
290 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { | |
a8a9f3fe SR |
291 | /* Configure register endianess access */ |
292 | dev->accessor_flags |= ACCESS_SWAP; | |
293 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { | |
294 | /* Configure register access mode 16bit */ | |
295 | dev->accessor_flags |= ACCESS_16BIT; | |
296 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { | |
4a423a8c DB |
297 | dev_err(dev->dev, "Unknown Synopsys component type: " |
298 | "0x%08x\n", reg); | |
299 | return -ENODEV; | |
300 | } | |
1ab52cf9 BS |
301 | |
302 | /* Disable the adapter */ | |
3ca4ed87 | 303 | __i2c_dw_enable(dev, false); |
1ab52cf9 BS |
304 | |
305 | /* set standard and fast speed deviders for high/low periods */ | |
d60c7e81 SK |
306 | |
307 | /* Standard-mode */ | |
308 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
309 | 40, /* tHD;STA = tHIGH = 4.0 us */ | |
310 | 3, /* tf = 0.3 us */ | |
311 | 0, /* 0: DW default, 1: Ideal */ | |
312 | 0); /* No offset */ | |
313 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
314 | 47, /* tLOW = 4.7 us */ | |
315 | 3, /* tf = 0.3 us */ | |
316 | 0); /* No offset */ | |
7f279601 JHD |
317 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
318 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); | |
d60c7e81 SK |
319 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
320 | ||
321 | /* Fast-mode */ | |
322 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, | |
323 | 6, /* tHD;STA = tHIGH = 0.6 us */ | |
324 | 3, /* tf = 0.3 us */ | |
325 | 0, /* 0: DW default, 1: Ideal */ | |
326 | 0); /* No offset */ | |
327 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, | |
328 | 13, /* tLOW = 1.3 us */ | |
329 | 3, /* tf = 0.3 us */ | |
330 | 0); /* No offset */ | |
7f279601 JHD |
331 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
332 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); | |
d60c7e81 | 333 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
1ab52cf9 | 334 | |
4cb6d1d6 | 335 | /* Configure Tx/Rx FIFO threshold levels */ |
7f279601 JHD |
336 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
337 | dw_writel(dev, 0, DW_IC_RX_TL); | |
4cb6d1d6 | 338 | |
1ab52cf9 | 339 | /* configure the i2c master */ |
e18563fc | 340 | dw_writel(dev, dev->master_cfg , DW_IC_CON); |
4a423a8c | 341 | return 0; |
1ab52cf9 | 342 | } |
e68bb91b | 343 | EXPORT_SYMBOL_GPL(i2c_dw_init); |
1ab52cf9 BS |
344 | |
345 | /* | |
346 | * Waiting for bus not busy | |
347 | */ | |
348 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |
349 | { | |
350 | int timeout = TIMEOUT; | |
351 | ||
7f279601 | 352 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
1ab52cf9 BS |
353 | if (timeout <= 0) { |
354 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | |
355 | return -ETIMEDOUT; | |
356 | } | |
357 | timeout--; | |
1451b91f | 358 | usleep_range(1000, 1100); |
1ab52cf9 BS |
359 | } |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
81e798b7 SK |
364 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
365 | { | |
366 | struct i2c_msg *msgs = dev->msgs; | |
367 | u32 ic_con; | |
368 | ||
369 | /* Disable the adapter */ | |
3ca4ed87 | 370 | __i2c_dw_enable(dev, false); |
81e798b7 SK |
371 | |
372 | /* set the slave (target) address */ | |
7f279601 | 373 | dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); |
81e798b7 SK |
374 | |
375 | /* if the slave address is ten bit address, enable 10BITADDR */ | |
7f279601 | 376 | ic_con = dw_readl(dev, DW_IC_CON); |
81e798b7 SK |
377 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
378 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | |
379 | else | |
380 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | |
7f279601 | 381 | dw_writel(dev, ic_con, DW_IC_CON); |
81e798b7 | 382 | |
a6b6cde1 DW |
383 | /* enforce disabled interrupts (due to HW issues) */ |
384 | i2c_dw_disable_int(dev); | |
385 | ||
81e798b7 | 386 | /* Enable the adapter */ |
3ca4ed87 | 387 | __i2c_dw_enable(dev, true); |
201d6a70 | 388 | |
2a2d95e9 MW |
389 | /* Clear and enable interrupts */ |
390 | i2c_dw_clear_int(dev); | |
7f279601 | 391 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
81e798b7 SK |
392 | } |
393 | ||
1ab52cf9 | 394 | /* |
201d6a70 SK |
395 | * Initiate (and continue) low level master read/write transaction. |
396 | * This function is only called from i2c_dw_isr, and pumping i2c_msg | |
397 | * messages into the tx buffer. Even if the size of i2c_msg data is | |
398 | * longer than the size of the tx buffer, it handles everything. | |
1ab52cf9 | 399 | */ |
bccd780f | 400 | static void |
e77cf232 | 401 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
1ab52cf9 | 402 | { |
1ab52cf9 | 403 | struct i2c_msg *msgs = dev->msgs; |
81e798b7 | 404 | u32 intr_mask; |
ae72222d | 405 | int tx_limit, rx_limit; |
ed5e1dd5 SK |
406 | u32 addr = msgs[dev->msg_write_idx].addr; |
407 | u32 buf_len = dev->tx_buf_len; | |
69932487 | 408 | u8 *buf = dev->tx_buf; |
1ab52cf9 | 409 | |
201d6a70 | 410 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
c70c5cd3 | 411 | |
6d2ea487 | 412 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
a0e06ea6 SK |
413 | /* |
414 | * if target address has changed, we need to | |
1ab52cf9 BS |
415 | * reprogram the target address in the i2c |
416 | * adapter when we are done with this transfer | |
417 | */ | |
8f588e40 SK |
418 | if (msgs[dev->msg_write_idx].addr != addr) { |
419 | dev_err(dev->dev, | |
420 | "%s: invalid target address\n", __func__); | |
421 | dev->msg_err = -EINVAL; | |
422 | break; | |
423 | } | |
1ab52cf9 BS |
424 | |
425 | if (msgs[dev->msg_write_idx].len == 0) { | |
426 | dev_err(dev->dev, | |
427 | "%s: invalid message length\n", __func__); | |
428 | dev->msg_err = -EINVAL; | |
8f588e40 | 429 | break; |
1ab52cf9 BS |
430 | } |
431 | ||
432 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { | |
433 | /* new i2c_msg */ | |
26ea15b1 | 434 | buf = msgs[dev->msg_write_idx].buf; |
1ab52cf9 BS |
435 | buf_len = msgs[dev->msg_write_idx].len; |
436 | } | |
437 | ||
7f279601 JHD |
438 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
439 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); | |
ae72222d | 440 | |
1ab52cf9 | 441 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
17a76b4b MW |
442 | u32 cmd = 0; |
443 | ||
444 | /* | |
445 | * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must | |
446 | * manually set the stop bit. However, it cannot be | |
447 | * detected from the registers so we set it always | |
448 | * when writing/reading the last byte. | |
449 | */ | |
450 | if (dev->msg_write_idx == dev->msgs_num - 1 && | |
451 | buf_len == 1) | |
452 | cmd |= BIT(9); | |
453 | ||
1ab52cf9 | 454 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
e6f34cea JA |
455 | |
456 | /* avoid rx buffer overrun */ | |
457 | if (rx_limit - dev->rx_outstanding <= 0) | |
458 | break; | |
459 | ||
17a76b4b | 460 | dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); |
1ab52cf9 | 461 | rx_limit--; |
e6f34cea | 462 | dev->rx_outstanding++; |
1ab52cf9 | 463 | } else |
17a76b4b | 464 | dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); |
1ab52cf9 BS |
465 | tx_limit--; buf_len--; |
466 | } | |
c70c5cd3 | 467 | |
26ea15b1 | 468 | dev->tx_buf = buf; |
c70c5cd3 SK |
469 | dev->tx_buf_len = buf_len; |
470 | ||
471 | if (buf_len > 0) { | |
472 | /* more bytes to be written */ | |
c70c5cd3 SK |
473 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
474 | break; | |
69151e53 | 475 | } else |
c70c5cd3 | 476 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
1ab52cf9 BS |
477 | } |
478 | ||
69151e53 SK |
479 | /* |
480 | * If i2c_msg index search is completed, we don't need TX_EMPTY | |
481 | * interrupt any more. | |
482 | */ | |
483 | if (dev->msg_write_idx == dev->msgs_num) | |
484 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; | |
485 | ||
8f588e40 SK |
486 | if (dev->msg_err) |
487 | intr_mask = 0; | |
488 | ||
2373f6b9 | 489 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
1ab52cf9 BS |
490 | } |
491 | ||
492 | static void | |
78839bd0 | 493 | i2c_dw_read(struct dw_i2c_dev *dev) |
1ab52cf9 | 494 | { |
1ab52cf9 | 495 | struct i2c_msg *msgs = dev->msgs; |
ae72222d | 496 | int rx_valid; |
1ab52cf9 | 497 | |
6d2ea487 | 498 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
ed5e1dd5 | 499 | u32 len; |
1ab52cf9 BS |
500 | u8 *buf; |
501 | ||
502 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) | |
503 | continue; | |
504 | ||
1ab52cf9 BS |
505 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
506 | len = msgs[dev->msg_read_idx].len; | |
507 | buf = msgs[dev->msg_read_idx].buf; | |
508 | } else { | |
509 | len = dev->rx_buf_len; | |
510 | buf = dev->rx_buf; | |
511 | } | |
512 | ||
7f279601 | 513 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
ae72222d | 514 | |
e6f34cea | 515 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) { |
7f279601 | 516 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
e6f34cea JA |
517 | dev->rx_outstanding--; |
518 | } | |
1ab52cf9 BS |
519 | |
520 | if (len > 0) { | |
521 | dev->status |= STATUS_READ_IN_PROGRESS; | |
522 | dev->rx_buf_len = len; | |
523 | dev->rx_buf = buf; | |
524 | return; | |
525 | } else | |
526 | dev->status &= ~STATUS_READ_IN_PROGRESS; | |
527 | } | |
528 | } | |
529 | ||
ce6eb574 SK |
530 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
531 | { | |
532 | unsigned long abort_source = dev->abort_source; | |
533 | int i; | |
534 | ||
6d1ea0f6 | 535 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
984b3f57 | 536 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
6d1ea0f6 SK |
537 | dev_dbg(dev->dev, |
538 | "%s: %s\n", __func__, abort_sources[i]); | |
539 | return -EREMOTEIO; | |
540 | } | |
541 | ||
984b3f57 | 542 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
ce6eb574 SK |
543 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
544 | ||
545 | if (abort_source & DW_IC_TX_ARB_LOST) | |
546 | return -EAGAIN; | |
ce6eb574 SK |
547 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
548 | return -EINVAL; /* wrong msgs[] data */ | |
549 | else | |
550 | return -EIO; | |
551 | } | |
552 | ||
1ab52cf9 BS |
553 | /* |
554 | * Prepare controller for a transaction and call i2c_dw_xfer_msg | |
555 | */ | |
2373f6b9 | 556 | int |
1ab52cf9 BS |
557 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
558 | { | |
559 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); | |
560 | int ret; | |
561 | ||
562 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); | |
563 | ||
564 | mutex_lock(&dev->lock); | |
18dbdda8 | 565 | pm_runtime_get_sync(dev->dev); |
1ab52cf9 BS |
566 | |
567 | INIT_COMPLETION(dev->cmd_complete); | |
568 | dev->msgs = msgs; | |
569 | dev->msgs_num = num; | |
570 | dev->cmd_err = 0; | |
571 | dev->msg_write_idx = 0; | |
572 | dev->msg_read_idx = 0; | |
573 | dev->msg_err = 0; | |
574 | dev->status = STATUS_IDLE; | |
ce6eb574 | 575 | dev->abort_source = 0; |
e6f34cea | 576 | dev->rx_outstanding = 0; |
1ab52cf9 BS |
577 | |
578 | ret = i2c_dw_wait_bus_not_busy(dev); | |
579 | if (ret < 0) | |
580 | goto done; | |
581 | ||
582 | /* start the transfers */ | |
81e798b7 | 583 | i2c_dw_xfer_init(dev); |
1ab52cf9 BS |
584 | |
585 | /* wait for tx to complete */ | |
586 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); | |
587 | if (ret == 0) { | |
588 | dev_err(dev->dev, "controller timed out\n"); | |
589 | i2c_dw_init(dev); | |
590 | ret = -ETIMEDOUT; | |
591 | goto done; | |
592 | } else if (ret < 0) | |
593 | goto done; | |
594 | ||
595 | if (dev->msg_err) { | |
596 | ret = dev->msg_err; | |
597 | goto done; | |
598 | } | |
599 | ||
600 | /* no error */ | |
601 | if (likely(!dev->cmd_err)) { | |
07745399 | 602 | /* Disable the adapter */ |
3ca4ed87 | 603 | __i2c_dw_enable(dev, false); |
1ab52cf9 BS |
604 | ret = num; |
605 | goto done; | |
606 | } | |
607 | ||
608 | /* We have an error */ | |
609 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { | |
ce6eb574 SK |
610 | ret = i2c_dw_handle_tx_abort(dev); |
611 | goto done; | |
1ab52cf9 BS |
612 | } |
613 | ret = -EIO; | |
614 | ||
615 | done: | |
43452335 MW |
616 | pm_runtime_mark_last_busy(dev->dev); |
617 | pm_runtime_put_autosuspend(dev->dev); | |
1ab52cf9 BS |
618 | mutex_unlock(&dev->lock); |
619 | ||
620 | return ret; | |
621 | } | |
e68bb91b | 622 | EXPORT_SYMBOL_GPL(i2c_dw_xfer); |
1ab52cf9 | 623 | |
2373f6b9 | 624 | u32 i2c_dw_func(struct i2c_adapter *adap) |
1ab52cf9 | 625 | { |
2fa8326b DB |
626 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
627 | return dev->functionality; | |
1ab52cf9 | 628 | } |
e68bb91b | 629 | EXPORT_SYMBOL_GPL(i2c_dw_func); |
1ab52cf9 | 630 | |
e28000a3 SK |
631 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
632 | { | |
633 | u32 stat; | |
634 | ||
635 | /* | |
636 | * The IC_INTR_STAT register just indicates "enabled" interrupts. | |
637 | * Ths unmasked raw version of interrupt status bits are available | |
638 | * in the IC_RAW_INTR_STAT register. | |
639 | * | |
640 | * That is, | |
2373f6b9 | 641 | * stat = dw_readl(IC_INTR_STAT); |
e28000a3 | 642 | * equals to, |
2373f6b9 | 643 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
e28000a3 SK |
644 | * |
645 | * The raw version might be useful for debugging purposes. | |
646 | */ | |
7f279601 | 647 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
e28000a3 SK |
648 | |
649 | /* | |
650 | * Do not use the IC_CLR_INTR register to clear interrupts, or | |
651 | * you'll miss some interrupts, triggered during the period from | |
2373f6b9 | 652 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
e28000a3 SK |
653 | * |
654 | * Instead, use the separately-prepared IC_CLR_* registers. | |
655 | */ | |
656 | if (stat & DW_IC_INTR_RX_UNDER) | |
7f279601 | 657 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
e28000a3 | 658 | if (stat & DW_IC_INTR_RX_OVER) |
7f279601 | 659 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
e28000a3 | 660 | if (stat & DW_IC_INTR_TX_OVER) |
7f279601 | 661 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
e28000a3 | 662 | if (stat & DW_IC_INTR_RD_REQ) |
7f279601 | 663 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
e28000a3 SK |
664 | if (stat & DW_IC_INTR_TX_ABRT) { |
665 | /* | |
666 | * The IC_TX_ABRT_SOURCE register is cleared whenever | |
667 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | |
668 | */ | |
7f279601 JHD |
669 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
670 | dw_readl(dev, DW_IC_CLR_TX_ABRT); | |
e28000a3 SK |
671 | } |
672 | if (stat & DW_IC_INTR_RX_DONE) | |
7f279601 | 673 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
e28000a3 | 674 | if (stat & DW_IC_INTR_ACTIVITY) |
7f279601 | 675 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
e28000a3 | 676 | if (stat & DW_IC_INTR_STOP_DET) |
7f279601 | 677 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
e28000a3 | 678 | if (stat & DW_IC_INTR_START_DET) |
7f279601 | 679 | dw_readl(dev, DW_IC_CLR_START_DET); |
e28000a3 | 680 | if (stat & DW_IC_INTR_GEN_CALL) |
7f279601 | 681 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
e28000a3 SK |
682 | |
683 | return stat; | |
684 | } | |
685 | ||
1ab52cf9 BS |
686 | /* |
687 | * Interrupt service routine. This gets called whenever an I2C interrupt | |
688 | * occurs. | |
689 | */ | |
2373f6b9 | 690 | irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
1ab52cf9 BS |
691 | { |
692 | struct dw_i2c_dev *dev = dev_id; | |
af06cf6c DB |
693 | u32 stat, enabled; |
694 | ||
695 | enabled = dw_readl(dev, DW_IC_ENABLE); | |
696 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); | |
697 | dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__, | |
698 | dev->adapter.name, enabled, stat); | |
699 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) | |
700 | return IRQ_NONE; | |
1ab52cf9 | 701 | |
e28000a3 | 702 | stat = i2c_dw_read_clear_intrbits(dev); |
e28000a3 | 703 | |
1ab52cf9 | 704 | if (stat & DW_IC_INTR_TX_ABRT) { |
1ab52cf9 BS |
705 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
706 | dev->status = STATUS_IDLE; | |
597fe310 SK |
707 | |
708 | /* | |
709 | * Anytime TX_ABRT is set, the contents of the tx/rx | |
710 | * buffers are flushed. Make sure to skip them. | |
711 | */ | |
7f279601 | 712 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
597fe310 | 713 | goto tx_aborted; |
07745399 SK |
714 | } |
715 | ||
21a89d41 | 716 | if (stat & DW_IC_INTR_RX_FULL) |
07745399 | 717 | i2c_dw_read(dev); |
21a89d41 SK |
718 | |
719 | if (stat & DW_IC_INTR_TX_EMPTY) | |
07745399 | 720 | i2c_dw_xfer_msg(dev); |
07745399 SK |
721 | |
722 | /* | |
723 | * No need to modify or disable the interrupt mask here. | |
724 | * i2c_dw_xfer_msg() will take care of it according to | |
725 | * the current transmit status. | |
726 | */ | |
1ab52cf9 | 727 | |
597fe310 | 728 | tx_aborted: |
8f588e40 | 729 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
1ab52cf9 BS |
730 | complete(&dev->cmd_complete); |
731 | ||
732 | return IRQ_HANDLED; | |
733 | } | |
e68bb91b | 734 | EXPORT_SYMBOL_GPL(i2c_dw_isr); |
f3fa9f3d DB |
735 | |
736 | void i2c_dw_enable(struct dw_i2c_dev *dev) | |
737 | { | |
738 | /* Enable the adapter */ | |
3ca4ed87 | 739 | __i2c_dw_enable(dev, true); |
f3fa9f3d | 740 | } |
e68bb91b | 741 | EXPORT_SYMBOL_GPL(i2c_dw_enable); |
f3fa9f3d | 742 | |
18dbdda8 | 743 | u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev) |
f3fa9f3d | 744 | { |
18dbdda8 DB |
745 | return dw_readl(dev, DW_IC_ENABLE); |
746 | } | |
e68bb91b | 747 | EXPORT_SYMBOL_GPL(i2c_dw_is_enabled); |
f3fa9f3d | 748 | |
18dbdda8 DB |
749 | void i2c_dw_disable(struct dw_i2c_dev *dev) |
750 | { | |
f3fa9f3d | 751 | /* Disable controller */ |
3ca4ed87 | 752 | __i2c_dw_enable(dev, false); |
f3fa9f3d DB |
753 | |
754 | /* Disable all interupts */ | |
755 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
756 | dw_readl(dev, DW_IC_CLR_INTR); | |
757 | } | |
e68bb91b | 758 | EXPORT_SYMBOL_GPL(i2c_dw_disable); |
f3fa9f3d DB |
759 | |
760 | void i2c_dw_clear_int(struct dw_i2c_dev *dev) | |
761 | { | |
762 | dw_readl(dev, DW_IC_CLR_INTR); | |
763 | } | |
e68bb91b | 764 | EXPORT_SYMBOL_GPL(i2c_dw_clear_int); |
f3fa9f3d DB |
765 | |
766 | void i2c_dw_disable_int(struct dw_i2c_dev *dev) | |
767 | { | |
768 | dw_writel(dev, 0, DW_IC_INTR_MASK); | |
769 | } | |
e68bb91b | 770 | EXPORT_SYMBOL_GPL(i2c_dw_disable_int); |
f3fa9f3d DB |
771 | |
772 | u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) | |
773 | { | |
774 | return dw_readl(dev, DW_IC_COMP_PARAM_1); | |
775 | } | |
e68bb91b | 776 | EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); |
9dd3162d MW |
777 | |
778 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); | |
779 | MODULE_LICENSE("GPL"); |