[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / gpu / host1x / dev.c

/*
 * Tegra host1x driver
 *
 * Copyright (c) 2010-2013, NVIDIA Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/slab.h>

#define CREATE_TRACE_POINTS
#include <trace/events/host1x.h>
#undef CREATE_TRACE_POINTS

#include "bus.h"
#include "channel.h"
#include "debug.h"
#include "dev.h"
#include "intr.h"

#include "hw/host1x01.h"
#include "hw/host1x02.h"
#include "hw/host1x04.h"
#include "hw/host1x05.h"

void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
{
	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;

	writel(v, sync_regs + r);
}

u32 host1x_sync_readl(struct host1x *host1x, u32 r)
{
	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;

	return readl(sync_regs + r);
}

void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
{
	writel(v, ch->regs + r);
}

u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
{
	return readl(ch->regs + r);
}

static const struct host1x_info host1x01_info = {
	.nb_channels = 8,
	.nb_pts = 32,
	.nb_mlocks = 16,
	.nb_bases = 8,
	.init = host1x01_init,
	.sync_offset = 0x3000,
	.dma_mask = DMA_BIT_MASK(32),
};

static const struct host1x_info host1x02_info = {
	.nb_channels = 9,
	.nb_pts = 32,
	.nb_mlocks = 16,
	.nb_bases = 12,
	.init = host1x02_init,
	.sync_offset = 0x3000,
	.dma_mask = DMA_BIT_MASK(32),
};

static const struct host1x_info host1x04_info = {
	.nb_channels = 12,
	.nb_pts = 192,
	.nb_mlocks = 16,
	.nb_bases = 64,
	.init = host1x04_init,
	.sync_offset = 0x2100,
	.dma_mask = DMA_BIT_MASK(34),
};

static const struct host1x_info host1x05_info = {
	.nb_channels = 14,
	.nb_pts = 192,
	.nb_mlocks = 16,
	.nb_bases = 64,
	.init = host1x05_init,
	.sync_offset = 0x2100,
	.dma_mask = DMA_BIT_MASK(34),
};

static const struct of_device_id host1x_of_match[] = {
	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
	{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
	{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
	{ },
};
MODULE_DEVICE_TABLE(of, host1x_of_match);

static int host1x_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	struct host1x *host;
	struct resource *regs;
	int syncpt_irq;
	int err;

	id = of_match_device(host1x_of_match, &pdev->dev);
	if (!id)
		return -EINVAL;

	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!regs) {
		dev_err(&pdev->dev, "failed to get registers\n");
		return -ENXIO;
	}

	syncpt_irq = platform_get_irq(pdev, 0);
	if (syncpt_irq < 0) {
		dev_err(&pdev->dev, "failed to get IRQ\n");
		return -ENXIO;
	}

	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
	if (!host)
		return -ENOMEM;

	mutex_init(&host->devices_lock);
	INIT_LIST_HEAD(&host->devices);
	INIT_LIST_HEAD(&host->list);
	host->dev = &pdev->dev;
	host->info = id->data;

	/* set common host1x device data */
	platform_set_drvdata(pdev, host);

	host->regs = devm_ioremap_resource(&pdev->dev, regs);
	if (IS_ERR(host->regs))
		return PTR_ERR(host->regs);

	dma_set_mask_and_coherent(host->dev, host->info->dma_mask);

	if (host->info->init) {
		err = host->info->init(host);
		if (err)
			return err;
	}

	host->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(host->clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		err = PTR_ERR(host->clk);
		return err;
	}

	host->rst = devm_reset_control_get(&pdev->dev, "host1x");
	if (IS_ERR(host->rst)) {
		err = PTR_ERR(host->rst);
		dev_err(&pdev->dev, "failed to get reset: %d\n", err);
		return err;
	}

	if (iommu_present(&platform_bus_type)) {
		struct iommu_domain_geometry *geometry;
		unsigned long order;

		host->domain = iommu_domain_alloc(&platform_bus_type);
		if (!host->domain)
			return -ENOMEM;

		err = iommu_attach_device(host->domain, &pdev->dev);
		if (err)
			goto fail_free_domain;

		geometry = &host->domain->geometry;

		order = __ffs(host->domain->pgsize_bitmap);
		init_iova_domain(&host->iova, 1UL << order,
				 geometry->aperture_start >> order,
				 geometry->aperture_end >> order);
		host->iova_end = geometry->aperture_end;
	}

	err = host1x_channel_list_init(host);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize channel list\n");
		goto fail_detach_device;
	}

	err = clk_prepare_enable(host->clk);
	if (err < 0) {
		dev_err(&pdev->dev, "failed to enable clock\n");
		goto fail_detach_device;
	}

	err = reset_control_deassert(host->rst);
	if (err < 0) {
		dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
		goto fail_unprepare_disable;
	}

	err = host1x_syncpt_init(host);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize syncpts\n");
		goto fail_reset_assert;
	}

	err = host1x_intr_init(host, syncpt_irq);
	if (err) {
		dev_err(&pdev->dev, "failed to initialize interrupts\n");
		goto fail_deinit_syncpt;
	}

	host1x_debug_init(host);

	err = host1x_register(host);
	if (err < 0)
		goto fail_deinit_intr;

	return 0;

fail_deinit_intr:
	host1x_intr_deinit(host);
fail_deinit_syncpt:
	host1x_syncpt_deinit(host);
fail_reset_assert:
	reset_control_assert(host->rst);
fail_unprepare_disable:
	clk_disable_unprepare(host->clk);
fail_detach_device:
	if (host->domain) {
		put_iova_domain(&host->iova);
		iommu_detach_device(host->domain, &pdev->dev);
	}
fail_free_domain:
	if (host->domain)
		iommu_domain_free(host->domain);

	return err;
}

static int host1x_remove(struct platform_device *pdev)
{
	struct host1x *host = platform_get_drvdata(pdev);

	host1x_unregister(host);
	host1x_intr_deinit(host);
	host1x_syncpt_deinit(host);
	reset_control_assert(host->rst);
	clk_disable_unprepare(host->clk);

	if (host->domain) {
		put_iova_domain(&host->iova);
		iommu_detach_device(host->domain, &pdev->dev);
		iommu_domain_free(host->domain);
	}

	return 0;
}

static struct platform_driver tegra_host1x_driver = {
	.driver = {
		.name = "tegra-host1x",
		.of_match_table = host1x_of_match,
	},
	.probe = host1x_probe,
	.remove = host1x_remove,
};

static struct platform_driver * const drivers[] = {
	&tegra_host1x_driver,
	&tegra_mipi_driver,
};

static int __init tegra_host1x_init(void)
{
	int err;

	err = bus_register(&host1x_bus_type);
	if (err < 0)
		return err;

	err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
	if (err < 0)
		bus_unregister(&host1x_bus_type);

	return err;
}
module_init(tegra_host1x_init);

static void __exit tegra_host1x_exit(void)
{
	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
	bus_unregister(&host1x_bus_type);
}
module_exit(tegra_host1x_exit);

MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
MODULE_DESCRIPTION("Host1x driver for Tegra products");
MODULE_LICENSE("GPL");
Commit	Line	Data
75471687 TB	1	/*
	2	* Tegra host1x driver
	3	*
	4	* Copyright (c) 2010-2013, NVIDIA Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
75471687	19	#include <linux/clk.h>
097452e6	20	#include <linux/dma-mapping.h>
7e7d432c TR	21	#include <linux/io.h>
	22	#include <linux/list.h>
	23	#include <linux/module.h>
	24	#include <linux/of_device.h>
	25	#include <linux/of.h>
	26	#include <linux/slab.h>
75471687 TB	27
	28	#define CREATE_TRACE_POINTS
	29	#include <trace/events/host1x.h>
404bfb78	30	#undef CREATE_TRACE_POINTS
75471687	31
776dc384	32	#include "bus.h"
6579324a	33	#include "channel.h"
6236451d	34	#include "debug.h"
7e7d432c TR	35	#include "dev.h"
	36	#include "intr.h"
	37
75471687	38	#include "hw/host1x01.h"
5407f31b	39	#include "hw/host1x02.h"
e6fff4aa	40	#include "hw/host1x04.h"
a134789a	41	#include "hw/host1x05.h"
75471687 TB	42
	43	void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
	44	{
	45	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
	46
	47	writel(v, sync_regs + r);
	48	}
	49
	50	u32 host1x_sync_readl(struct host1x *host1x, u32 r)
	51	{
	52	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
	53
	54	return readl(sync_regs + r);
	55	}
	56
6579324a TB	57	void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
	58	{
	59	writel(v, ch->regs + r);
	60	}
	61
	62	u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
	63	{
	64	return readl(ch->regs + r);
	65	}
	66
75471687	67	static const struct host1x_info host1x01_info = {
0b8070d1 TR	68	.nb_channels = 8,
	69	.nb_pts = 32,
	70	.nb_mlocks = 16,
	71	.nb_bases = 8,
	72	.init = host1x01_init,
	73	.sync_offset = 0x3000,
	74	.dma_mask = DMA_BIT_MASK(32),
75471687 TB	75	};
75471687 TB	76
5407f31b TR	77	static const struct host1x_info host1x02_info = {
	78	.nb_channels = 9,
	79	.nb_pts = 32,
	80	.nb_mlocks = 16,
	81	.nb_bases = 12,
	82	.init = host1x02_init,
	83	.sync_offset = 0x3000,
097452e6	84	.dma_mask = DMA_BIT_MASK(32),
5407f31b TR	85	};
5407f31b TR	86
e6fff4aa TR	87	static const struct host1x_info host1x04_info = {
	88	.nb_channels = 12,
	89	.nb_pts = 192,
	90	.nb_mlocks = 16,
	91	.nb_bases = 64,
	92	.init = host1x04_init,
	93	.sync_offset = 0x2100,
097452e6	94	.dma_mask = DMA_BIT_MASK(34),
e6fff4aa TR	95	};
e6fff4aa TR	96
a134789a TR	97	static const struct host1x_info host1x05_info = {
	98	.nb_channels = 14,
	99	.nb_pts = 192,
	100	.nb_mlocks = 16,
	101	.nb_bases = 64,
	102	.init = host1x05_init,
	103	.sync_offset = 0x2100,
097452e6	104	.dma_mask = DMA_BIT_MASK(34),
a134789a TR	105	};
a134789a TR	106
6df633d0	107	static const struct of_device_id host1x_of_match[] = {
a134789a	108	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
e6fff4aa	109	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
5407f31b	110	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
75471687 TB	111	{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
	112	{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
	113	{ },
	114	};
	115	MODULE_DEVICE_TABLE(of, host1x_of_match);
	116
	117	static int host1x_probe(struct platform_device *pdev)
	118	{
	119	const struct of_device_id *id;
	120	struct host1x *host;
	121	struct resource *regs;
	122	int syncpt_irq;
	123	int err;
	124
	125	id = of_match_device(host1x_of_match, &pdev->dev);
	126	if (!id)
	127	return -EINVAL;
	128
	129	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	130	if (!regs) {
	131	dev_err(&pdev->dev, "failed to get registers\n");
	132	return -ENXIO;
	133	}
	134
	135	syncpt_irq = platform_get_irq(pdev, 0);
	136	if (syncpt_irq < 0) {
	137	dev_err(&pdev->dev, "failed to get IRQ\n");
	138	return -ENXIO;
	139	}
	140
	141	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
	142	if (!host)
	143	return -ENOMEM;
	144
776dc384 TR	145	mutex_init(&host->devices_lock);
	146	INIT_LIST_HEAD(&host->devices);
	147	INIT_LIST_HEAD(&host->list);
75471687 TB	148	host->dev = &pdev->dev;
	149	host->info = id->data;
	150
	151	/* set common host1x device data */
	152	platform_set_drvdata(pdev, host);
	153
	154	host->regs = devm_ioremap_resource(&pdev->dev, regs);
	155	if (IS_ERR(host->regs))
	156	return PTR_ERR(host->regs);
	157
097452e6 AC	158	dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
097452e6 AC	159
75471687 TB	160	if (host->info->init) {
	161	err = host->info->init(host);
	162	if (err)
	163	return err;
	164	}
	165
	166	host->clk = devm_clk_get(&pdev->dev, NULL);
	167	if (IS_ERR(host->clk)) {
	168	dev_err(&pdev->dev, "failed to get clock\n");
	169	err = PTR_ERR(host->clk);
	170	return err;
	171	}
	172
b386c6b7 TR	173	host->rst = devm_reset_control_get(&pdev->dev, "host1x");
b386c6b7 TR	174	if (IS_ERR(host->rst)) {
59e04bc2	175	err = PTR_ERR(host->rst);
b386c6b7 TR	176	dev_err(&pdev->dev, "failed to get reset: %d\n", err);
	177	return err;
	178	}
	179
404bfb78 MP	180	if (iommu_present(&platform_bus_type)) {
	181	struct iommu_domain_geometry *geometry;
	182	unsigned long order;
	183
	184	host->domain = iommu_domain_alloc(&platform_bus_type);
	185	if (!host->domain)
	186	return -ENOMEM;
	187
	188	err = iommu_attach_device(host->domain, &pdev->dev);
	189	if (err)
	190	goto fail_free_domain;
	191
	192	geometry = &host->domain->geometry;
	193
	194	order = __ffs(host->domain->pgsize_bitmap);
	195	init_iova_domain(&host->iova, 1UL << order,
	196	geometry->aperture_start >> order,
	197	geometry->aperture_end >> order);
	198	host->iova_end = geometry->aperture_end;
	199	}
	200
6579324a TB	201	err = host1x_channel_list_init(host);
	202	if (err) {
	203	dev_err(&pdev->dev, "failed to initialize channel list\n");
404bfb78	204	goto fail_detach_device;
6579324a TB	205	}
6579324a TB	206
75471687 TB	207	err = clk_prepare_enable(host->clk);
	208	if (err < 0) {
	209	dev_err(&pdev->dev, "failed to enable clock\n");
404bfb78	210	goto fail_detach_device;
75471687 TB	211	}
75471687 TB	212
b386c6b7 TR	213	err = reset_control_deassert(host->rst);
	214	if (err < 0) {
	215	dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
	216	goto fail_unprepare_disable;
	217	}
	218
75471687 TB	219	err = host1x_syncpt_init(host);
	220	if (err) {
	221	dev_err(&pdev->dev, "failed to initialize syncpts\n");
b386c6b7	222	goto fail_reset_assert;
75471687 TB	223	}
75471687 TB	224
7ede0b0b TB	225	err = host1x_intr_init(host, syncpt_irq);
	226	if (err) {
	227	dev_err(&pdev->dev, "failed to initialize interrupts\n");
	228	goto fail_deinit_syncpt;
	229	}
	230
6236451d TB	231	host1x_debug_init(host);
6236451d TB	232
776dc384 TR	233	err = host1x_register(host);
	234	if (err < 0)
	235	goto fail_deinit_intr;
692e6d7b	236
75471687	237	return 0;
7ede0b0b	238
776dc384 TR	239	fail_deinit_intr:
776dc384 TR	240	host1x_intr_deinit(host);
7ede0b0b TB	241	fail_deinit_syncpt:
7ede0b0b TB	242	host1x_syncpt_deinit(host);
b386c6b7 TR	243	fail_reset_assert:
b386c6b7 TR	244	reset_control_assert(host->rst);
9c78c4c3 WY	245	fail_unprepare_disable:
9c78c4c3 WY	246	clk_disable_unprepare(host->clk);
404bfb78 MP	247	fail_detach_device:
	248	if (host->domain) {
	249	put_iova_domain(&host->iova);
	250	iommu_detach_device(host->domain, &pdev->dev);
	251	}
	252	fail_free_domain:
	253	if (host->domain)
	254	iommu_domain_free(host->domain);
	255
7ede0b0b	256	return err;
75471687 TB	257	}
75471687 TB	258
452e7f0c	259	static int host1x_remove(struct platform_device *pdev)
75471687 TB	260	{
	261	struct host1x *host = platform_get_drvdata(pdev);
	262
776dc384	263	host1x_unregister(host);
7ede0b0b	264	host1x_intr_deinit(host);
75471687	265	host1x_syncpt_deinit(host);
b386c6b7	266	reset_control_assert(host->rst);
75471687 TB	267	clk_disable_unprepare(host->clk);
75471687 TB	268
404bfb78 MP	269	if (host->domain) {
	270	put_iova_domain(&host->iova);
	271	iommu_detach_device(host->domain, &pdev->dev);
	272	iommu_domain_free(host->domain);
	273	}
	274
75471687 TB	275	return 0;
	276	}
	277
692e6d7b	278	static struct platform_driver tegra_host1x_driver = {
75471687	279	.driver = {
75471687 TB	280	.name = "tegra-host1x",
	281	.of_match_table = host1x_of_match,
	282	},
452e7f0c TR	283	.probe = host1x_probe,
452e7f0c TR	284	.remove = host1x_remove,
75471687 TB	285	};
75471687 TB	286
28fae81f TR	287	static struct platform_driver * const drivers[] = {
	288	&tegra_host1x_driver,
	289	&tegra_mipi_driver,
	290	};
	291
692e6d7b TB	292	static int __init tegra_host1x_init(void)
	293	{
	294	int err;
	295
f4c5cf88	296	err = bus_register(&host1x_bus_type);
692e6d7b TB	297	if (err < 0)
	298	return err;
	299
28fae81f	300	err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
4de6a2d6	301	if (err < 0)
28fae81f	302	bus_unregister(&host1x_bus_type);
692e6d7b	303
4de6a2d6	304	return err;
692e6d7b TB	305	}
	306	module_init(tegra_host1x_init);
	307
	308	static void __exit tegra_host1x_exit(void)
	309	{
28fae81f	310	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
f4c5cf88	311	bus_unregister(&host1x_bus_type);
692e6d7b TB	312	}
692e6d7b TB	313	module_exit(tegra_host1x_exit);
75471687	314
692e6d7b	315	MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
75471687 TB	316	MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
	317	MODULE_DESCRIPTION("Host1x driver for Tegra products");
	318	MODULE_LICENSE("GPL");