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16ea975e RC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | /* LCDC DRM driver, based on da8xx-fb */ | |
19 | ||
103cd8bc JS |
20 | #include <linux/component.h> |
21 | ||
16ea975e RC |
22 | #include "tilcdc_drv.h" |
23 | #include "tilcdc_regs.h" | |
24 | #include "tilcdc_tfp410.h" | |
0d4bbaf9 | 25 | #include "tilcdc_panel.h" |
103cd8bc | 26 | #include "tilcdc_external.h" |
16ea975e RC |
27 | |
28 | #include "drm_fb_helper.h" | |
29 | ||
30 | static LIST_HEAD(module_list); | |
31 | ||
32 | void tilcdc_module_init(struct tilcdc_module *mod, const char *name, | |
33 | const struct tilcdc_module_ops *funcs) | |
34 | { | |
35 | mod->name = name; | |
36 | mod->funcs = funcs; | |
37 | INIT_LIST_HEAD(&mod->list); | |
38 | list_add(&mod->list, &module_list); | |
39 | } | |
40 | ||
41 | void tilcdc_module_cleanup(struct tilcdc_module *mod) | |
42 | { | |
43 | list_del(&mod->list); | |
44 | } | |
45 | ||
46 | static struct of_device_id tilcdc_of_match[]; | |
47 | ||
48 | static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev, | |
1eb83451 | 49 | struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) |
16ea975e RC |
50 | { |
51 | return drm_fb_cma_create(dev, file_priv, mode_cmd); | |
52 | } | |
53 | ||
54 | static void tilcdc_fb_output_poll_changed(struct drm_device *dev) | |
55 | { | |
56 | struct tilcdc_drm_private *priv = dev->dev_private; | |
c0844817 | 57 | drm_fbdev_cma_hotplug_event(priv->fbdev); |
16ea975e RC |
58 | } |
59 | ||
60 | static const struct drm_mode_config_funcs mode_config_funcs = { | |
61 | .fb_create = tilcdc_fb_create, | |
62 | .output_poll_changed = tilcdc_fb_output_poll_changed, | |
63 | }; | |
64 | ||
65 | static int modeset_init(struct drm_device *dev) | |
66 | { | |
67 | struct tilcdc_drm_private *priv = dev->dev_private; | |
68 | struct tilcdc_module *mod; | |
69 | ||
70 | drm_mode_config_init(dev); | |
71 | ||
72 | priv->crtc = tilcdc_crtc_create(dev); | |
73 | ||
74 | list_for_each_entry(mod, &module_list, list) { | |
75 | DBG("loading module: %s", mod->name); | |
76 | mod->funcs->modeset_init(mod, dev); | |
77 | } | |
78 | ||
16ea975e RC |
79 | dev->mode_config.min_width = 0; |
80 | dev->mode_config.min_height = 0; | |
81 | dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); | |
82 | dev->mode_config.max_height = 2048; | |
83 | dev->mode_config.funcs = &mode_config_funcs; | |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
88 | #ifdef CONFIG_CPU_FREQ | |
89 | static int cpufreq_transition(struct notifier_block *nb, | |
90 | unsigned long val, void *data) | |
91 | { | |
92 | struct tilcdc_drm_private *priv = container_of(nb, | |
93 | struct tilcdc_drm_private, freq_transition); | |
94 | if (val == CPUFREQ_POSTCHANGE) { | |
95 | if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) { | |
96 | priv->lcd_fck_rate = clk_get_rate(priv->clk); | |
97 | tilcdc_crtc_update_clk(priv->crtc); | |
98 | } | |
99 | } | |
100 | ||
101 | return 0; | |
102 | } | |
103 | #endif | |
104 | ||
105 | /* | |
106 | * DRM operations: | |
107 | */ | |
108 | ||
109 | static int tilcdc_unload(struct drm_device *dev) | |
110 | { | |
111 | struct tilcdc_drm_private *priv = dev->dev_private; | |
16ea975e | 112 | |
103cd8bc JS |
113 | tilcdc_remove_external_encoders(dev); |
114 | ||
3a490122 | 115 | drm_fbdev_cma_fini(priv->fbdev); |
16ea975e RC |
116 | drm_kms_helper_poll_fini(dev); |
117 | drm_mode_config_cleanup(dev); | |
118 | drm_vblank_cleanup(dev); | |
119 | ||
120 | pm_runtime_get_sync(dev->dev); | |
121 | drm_irq_uninstall(dev); | |
122 | pm_runtime_put_sync(dev->dev); | |
123 | ||
124 | #ifdef CONFIG_CPU_FREQ | |
125 | cpufreq_unregister_notifier(&priv->freq_transition, | |
126 | CPUFREQ_TRANSITION_NOTIFIER); | |
127 | #endif | |
128 | ||
129 | if (priv->clk) | |
130 | clk_put(priv->clk); | |
131 | ||
132 | if (priv->mmio) | |
133 | iounmap(priv->mmio); | |
134 | ||
135 | flush_workqueue(priv->wq); | |
136 | destroy_workqueue(priv->wq); | |
137 | ||
138 | dev->dev_private = NULL; | |
139 | ||
140 | pm_runtime_disable(dev->dev); | |
141 | ||
16ea975e RC |
142 | kfree(priv); |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | static int tilcdc_load(struct drm_device *dev, unsigned long flags) | |
148 | { | |
149 | struct platform_device *pdev = dev->platformdev; | |
150 | struct device_node *node = pdev->dev.of_node; | |
151 | struct tilcdc_drm_private *priv; | |
dc28aa07 | 152 | struct tilcdc_module *mod; |
16ea975e | 153 | struct resource *res; |
dc28aa07 | 154 | u32 bpp = 0; |
16ea975e RC |
155 | int ret; |
156 | ||
157 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
158 | if (!priv) { | |
159 | dev_err(dev->dev, "failed to allocate private data\n"); | |
160 | return -ENOMEM; | |
161 | } | |
162 | ||
163 | dev->dev_private = priv; | |
164 | ||
103cd8bc JS |
165 | priv->is_componentized = |
166 | tilcdc_get_external_components(dev->dev, NULL) > 0; | |
167 | ||
16ea975e | 168 | priv->wq = alloc_ordered_workqueue("tilcdc", 0); |
b478e336 EG |
169 | if (!priv->wq) { |
170 | ret = -ENOMEM; | |
171 | goto fail_free_priv; | |
172 | } | |
16ea975e RC |
173 | |
174 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
175 | if (!res) { | |
176 | dev_err(dev->dev, "failed to get memory resource\n"); | |
177 | ret = -EINVAL; | |
b478e336 | 178 | goto fail_free_wq; |
16ea975e RC |
179 | } |
180 | ||
181 | priv->mmio = ioremap_nocache(res->start, resource_size(res)); | |
182 | if (!priv->mmio) { | |
183 | dev_err(dev->dev, "failed to ioremap\n"); | |
184 | ret = -ENOMEM; | |
b478e336 | 185 | goto fail_free_wq; |
16ea975e RC |
186 | } |
187 | ||
188 | priv->clk = clk_get(dev->dev, "fck"); | |
189 | if (IS_ERR(priv->clk)) { | |
190 | dev_err(dev->dev, "failed to get functional clock\n"); | |
191 | ret = -ENODEV; | |
b478e336 | 192 | goto fail_iounmap; |
16ea975e RC |
193 | } |
194 | ||
195 | priv->disp_clk = clk_get(dev->dev, "dpll_disp_ck"); | |
196 | if (IS_ERR(priv->clk)) { | |
197 | dev_err(dev->dev, "failed to get display clock\n"); | |
198 | ret = -ENODEV; | |
b478e336 | 199 | goto fail_put_clk; |
16ea975e RC |
200 | } |
201 | ||
202 | #ifdef CONFIG_CPU_FREQ | |
203 | priv->lcd_fck_rate = clk_get_rate(priv->clk); | |
204 | priv->freq_transition.notifier_call = cpufreq_transition; | |
205 | ret = cpufreq_register_notifier(&priv->freq_transition, | |
206 | CPUFREQ_TRANSITION_NOTIFIER); | |
207 | if (ret) { | |
208 | dev_err(dev->dev, "failed to register cpufreq notifier\n"); | |
b478e336 | 209 | goto fail_put_disp_clk; |
16ea975e RC |
210 | } |
211 | #endif | |
212 | ||
213 | if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) | |
4e564346 DE |
214 | priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; |
215 | ||
216 | DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); | |
217 | ||
218 | if (of_property_read_u32(node, "ti,max-width", &priv->max_width)) | |
219 | priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; | |
220 | ||
221 | DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); | |
222 | ||
223 | if (of_property_read_u32(node, "ti,max-pixelclock", | |
224 | &priv->max_pixelclock)) | |
225 | priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; | |
226 | ||
227 | DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); | |
16ea975e RC |
228 | |
229 | pm_runtime_enable(dev->dev); | |
e3487e07 | 230 | pm_runtime_irq_safe(dev->dev); |
16ea975e RC |
231 | |
232 | /* Determine LCD IP Version */ | |
233 | pm_runtime_get_sync(dev->dev); | |
234 | switch (tilcdc_read(dev, LCDC_PID_REG)) { | |
235 | case 0x4c100102: | |
236 | priv->rev = 1; | |
237 | break; | |
238 | case 0x4f200800: | |
239 | case 0x4f201000: | |
240 | priv->rev = 2; | |
241 | break; | |
242 | default: | |
243 | dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, " | |
244 | "defaulting to LCD revision 1\n", | |
245 | tilcdc_read(dev, LCDC_PID_REG)); | |
246 | priv->rev = 1; | |
247 | break; | |
248 | } | |
249 | ||
250 | pm_runtime_put_sync(dev->dev); | |
251 | ||
252 | ret = modeset_init(dev); | |
253 | if (ret < 0) { | |
254 | dev_err(dev->dev, "failed to initialize mode setting\n"); | |
b478e336 | 255 | goto fail_cpufreq_unregister; |
16ea975e RC |
256 | } |
257 | ||
103cd8bc JS |
258 | platform_set_drvdata(pdev, dev); |
259 | ||
260 | if (priv->is_componentized) { | |
261 | ret = component_bind_all(dev->dev, dev); | |
262 | if (ret < 0) | |
263 | goto fail_mode_config_cleanup; | |
264 | ||
265 | ret = tilcdc_add_external_encoders(dev, &bpp); | |
266 | if (ret < 0) | |
267 | goto fail_component_cleanup; | |
268 | } | |
269 | ||
270 | if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) { | |
271 | dev_err(dev->dev, "no encoders/connectors found\n"); | |
272 | ret = -ENXIO; | |
273 | goto fail_external_cleanup; | |
274 | } | |
275 | ||
16ea975e RC |
276 | ret = drm_vblank_init(dev, 1); |
277 | if (ret < 0) { | |
278 | dev_err(dev->dev, "failed to initialize vblank\n"); | |
103cd8bc | 279 | goto fail_external_cleanup; |
16ea975e RC |
280 | } |
281 | ||
282 | pm_runtime_get_sync(dev->dev); | |
bb0f1b5c | 283 | ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); |
16ea975e RC |
284 | pm_runtime_put_sync(dev->dev); |
285 | if (ret < 0) { | |
286 | dev_err(dev->dev, "failed to install IRQ handler\n"); | |
b478e336 | 287 | goto fail_vblank_cleanup; |
16ea975e RC |
288 | } |
289 | ||
dc28aa07 BP |
290 | list_for_each_entry(mod, &module_list, list) { |
291 | DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp); | |
292 | bpp = mod->preferred_bpp; | |
293 | if (bpp > 0) | |
294 | break; | |
295 | } | |
296 | ||
4314e19e | 297 | drm_helper_disable_unused_functions(dev); |
dc28aa07 | 298 | priv->fbdev = drm_fbdev_cma_init(dev, bpp, |
16ea975e RC |
299 | dev->mode_config.num_crtc, |
300 | dev->mode_config.num_connector); | |
b478e336 EG |
301 | if (IS_ERR(priv->fbdev)) { |
302 | ret = PTR_ERR(priv->fbdev); | |
303 | goto fail_irq_uninstall; | |
304 | } | |
16ea975e RC |
305 | |
306 | drm_kms_helper_poll_init(dev); | |
307 | ||
308 | return 0; | |
309 | ||
b478e336 EG |
310 | fail_irq_uninstall: |
311 | pm_runtime_get_sync(dev->dev); | |
312 | drm_irq_uninstall(dev); | |
313 | pm_runtime_put_sync(dev->dev); | |
314 | ||
315 | fail_vblank_cleanup: | |
316 | drm_vblank_cleanup(dev); | |
317 | ||
318 | fail_mode_config_cleanup: | |
319 | drm_mode_config_cleanup(dev); | |
320 | ||
103cd8bc JS |
321 | fail_component_cleanup: |
322 | if (priv->is_componentized) | |
323 | component_unbind_all(dev->dev, dev); | |
324 | ||
325 | fail_external_cleanup: | |
326 | tilcdc_remove_external_encoders(dev); | |
327 | ||
b478e336 EG |
328 | fail_cpufreq_unregister: |
329 | pm_runtime_disable(dev->dev); | |
330 | #ifdef CONFIG_CPU_FREQ | |
331 | cpufreq_unregister_notifier(&priv->freq_transition, | |
332 | CPUFREQ_TRANSITION_NOTIFIER); | |
333 | fail_put_disp_clk: | |
334 | clk_put(priv->disp_clk); | |
335 | #endif | |
336 | ||
337 | fail_put_clk: | |
338 | clk_put(priv->clk); | |
339 | ||
340 | fail_iounmap: | |
341 | iounmap(priv->mmio); | |
342 | ||
343 | fail_free_wq: | |
344 | flush_workqueue(priv->wq); | |
345 | destroy_workqueue(priv->wq); | |
346 | ||
347 | fail_free_priv: | |
348 | dev->dev_private = NULL; | |
349 | kfree(priv); | |
16ea975e RC |
350 | return ret; |
351 | } | |
352 | ||
353 | static void tilcdc_preclose(struct drm_device *dev, struct drm_file *file) | |
354 | { | |
355 | struct tilcdc_drm_private *priv = dev->dev_private; | |
356 | ||
357 | tilcdc_crtc_cancel_page_flip(priv->crtc, file); | |
358 | } | |
359 | ||
360 | static void tilcdc_lastclose(struct drm_device *dev) | |
361 | { | |
362 | struct tilcdc_drm_private *priv = dev->dev_private; | |
363 | drm_fbdev_cma_restore_mode(priv->fbdev); | |
364 | } | |
365 | ||
e9f0d76f | 366 | static irqreturn_t tilcdc_irq(int irq, void *arg) |
16ea975e RC |
367 | { |
368 | struct drm_device *dev = arg; | |
369 | struct tilcdc_drm_private *priv = dev->dev_private; | |
370 | return tilcdc_crtc_irq(priv->crtc); | |
371 | } | |
372 | ||
373 | static void tilcdc_irq_preinstall(struct drm_device *dev) | |
374 | { | |
375 | tilcdc_clear_irqstatus(dev, 0xffffffff); | |
376 | } | |
377 | ||
378 | static int tilcdc_irq_postinstall(struct drm_device *dev) | |
379 | { | |
380 | struct tilcdc_drm_private *priv = dev->dev_private; | |
381 | ||
382 | /* enable FIFO underflow irq: */ | |
a50b24f4 | 383 | if (priv->rev == 1) |
16ea975e | 384 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA); |
a50b24f4 | 385 | else |
16ea975e | 386 | tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA); |
16ea975e RC |
387 | |
388 | return 0; | |
389 | } | |
390 | ||
391 | static void tilcdc_irq_uninstall(struct drm_device *dev) | |
392 | { | |
393 | struct tilcdc_drm_private *priv = dev->dev_private; | |
394 | ||
395 | /* disable irqs that we might have enabled: */ | |
396 | if (priv->rev == 1) { | |
397 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, | |
398 | LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); | |
399 | tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA); | |
400 | } else { | |
401 | tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG, | |
402 | LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | | |
403 | LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA | | |
404 | LCDC_FRAME_DONE); | |
405 | } | |
406 | ||
407 | } | |
408 | ||
409 | static void enable_vblank(struct drm_device *dev, bool enable) | |
410 | { | |
411 | struct tilcdc_drm_private *priv = dev->dev_private; | |
412 | u32 reg, mask; | |
413 | ||
414 | if (priv->rev == 1) { | |
415 | reg = LCDC_DMA_CTRL_REG; | |
416 | mask = LCDC_V1_END_OF_FRAME_INT_ENA; | |
417 | } else { | |
418 | reg = LCDC_INT_ENABLE_SET_REG; | |
419 | mask = LCDC_V2_END_OF_FRAME0_INT_ENA | | |
420 | LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE; | |
421 | } | |
422 | ||
423 | if (enable) | |
424 | tilcdc_set(dev, reg, mask); | |
425 | else | |
426 | tilcdc_clear(dev, reg, mask); | |
427 | } | |
428 | ||
88e72717 | 429 | static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe) |
16ea975e RC |
430 | { |
431 | enable_vblank(dev, true); | |
432 | return 0; | |
433 | } | |
434 | ||
88e72717 | 435 | static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe) |
16ea975e RC |
436 | { |
437 | enable_vblank(dev, false); | |
438 | } | |
439 | ||
440 | #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP) | |
441 | static const struct { | |
442 | const char *name; | |
443 | uint8_t rev; | |
444 | uint8_t save; | |
445 | uint32_t reg; | |
32501459 | 446 | } registers[] = { |
16ea975e RC |
447 | #define REG(rev, save, reg) { #reg, rev, save, reg } |
448 | /* exists in revision 1: */ | |
449 | REG(1, false, LCDC_PID_REG), | |
450 | REG(1, true, LCDC_CTRL_REG), | |
451 | REG(1, false, LCDC_STAT_REG), | |
452 | REG(1, true, LCDC_RASTER_CTRL_REG), | |
453 | REG(1, true, LCDC_RASTER_TIMING_0_REG), | |
454 | REG(1, true, LCDC_RASTER_TIMING_1_REG), | |
455 | REG(1, true, LCDC_RASTER_TIMING_2_REG), | |
456 | REG(1, true, LCDC_DMA_CTRL_REG), | |
457 | REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), | |
458 | REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), | |
459 | REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), | |
460 | REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), | |
461 | /* new in revision 2: */ | |
462 | REG(2, false, LCDC_RAW_STAT_REG), | |
463 | REG(2, false, LCDC_MASKED_STAT_REG), | |
464 | REG(2, false, LCDC_INT_ENABLE_SET_REG), | |
465 | REG(2, false, LCDC_INT_ENABLE_CLR_REG), | |
466 | REG(2, false, LCDC_END_OF_INT_IND_REG), | |
467 | REG(2, true, LCDC_CLK_ENABLE_REG), | |
468 | REG(2, true, LCDC_INT_ENABLE_SET_REG), | |
469 | #undef REG | |
470 | }; | |
471 | #endif | |
472 | ||
473 | #ifdef CONFIG_DEBUG_FS | |
474 | static int tilcdc_regs_show(struct seq_file *m, void *arg) | |
475 | { | |
476 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
477 | struct drm_device *dev = node->minor->dev; | |
478 | struct tilcdc_drm_private *priv = dev->dev_private; | |
479 | unsigned i; | |
480 | ||
481 | pm_runtime_get_sync(dev->dev); | |
482 | ||
483 | seq_printf(m, "revision: %d\n", priv->rev); | |
484 | ||
485 | for (i = 0; i < ARRAY_SIZE(registers); i++) | |
486 | if (priv->rev >= registers[i].rev) | |
487 | seq_printf(m, "%s:\t %08x\n", registers[i].name, | |
488 | tilcdc_read(dev, registers[i].reg)); | |
489 | ||
490 | pm_runtime_put_sync(dev->dev); | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | static int tilcdc_mm_show(struct seq_file *m, void *arg) | |
496 | { | |
497 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
498 | struct drm_device *dev = node->minor->dev; | |
b04a5906 | 499 | return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm); |
16ea975e RC |
500 | } |
501 | ||
502 | static struct drm_info_list tilcdc_debugfs_list[] = { | |
503 | { "regs", tilcdc_regs_show, 0 }, | |
504 | { "mm", tilcdc_mm_show, 0 }, | |
505 | { "fb", drm_fb_cma_debugfs_show, 0 }, | |
506 | }; | |
507 | ||
508 | static int tilcdc_debugfs_init(struct drm_minor *minor) | |
509 | { | |
510 | struct drm_device *dev = minor->dev; | |
511 | struct tilcdc_module *mod; | |
512 | int ret; | |
513 | ||
514 | ret = drm_debugfs_create_files(tilcdc_debugfs_list, | |
515 | ARRAY_SIZE(tilcdc_debugfs_list), | |
516 | minor->debugfs_root, minor); | |
517 | ||
518 | list_for_each_entry(mod, &module_list, list) | |
519 | if (mod->funcs->debugfs_init) | |
520 | mod->funcs->debugfs_init(mod, minor); | |
521 | ||
522 | if (ret) { | |
523 | dev_err(dev->dev, "could not install tilcdc_debugfs_list\n"); | |
524 | return ret; | |
525 | } | |
526 | ||
527 | return ret; | |
528 | } | |
529 | ||
530 | static void tilcdc_debugfs_cleanup(struct drm_minor *minor) | |
531 | { | |
532 | struct tilcdc_module *mod; | |
533 | drm_debugfs_remove_files(tilcdc_debugfs_list, | |
534 | ARRAY_SIZE(tilcdc_debugfs_list), minor); | |
535 | ||
536 | list_for_each_entry(mod, &module_list, list) | |
537 | if (mod->funcs->debugfs_cleanup) | |
538 | mod->funcs->debugfs_cleanup(mod, minor); | |
539 | } | |
540 | #endif | |
541 | ||
542 | static const struct file_operations fops = { | |
543 | .owner = THIS_MODULE, | |
544 | .open = drm_open, | |
545 | .release = drm_release, | |
546 | .unlocked_ioctl = drm_ioctl, | |
547 | #ifdef CONFIG_COMPAT | |
548 | .compat_ioctl = drm_compat_ioctl, | |
549 | #endif | |
550 | .poll = drm_poll, | |
551 | .read = drm_read, | |
16ea975e RC |
552 | .llseek = no_llseek, |
553 | .mmap = drm_gem_cma_mmap, | |
554 | }; | |
555 | ||
556 | static struct drm_driver tilcdc_driver = { | |
557 | .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET, | |
558 | .load = tilcdc_load, | |
559 | .unload = tilcdc_unload, | |
560 | .preclose = tilcdc_preclose, | |
561 | .lastclose = tilcdc_lastclose, | |
915b4d11 | 562 | .set_busid = drm_platform_set_busid, |
16ea975e RC |
563 | .irq_handler = tilcdc_irq, |
564 | .irq_preinstall = tilcdc_irq_preinstall, | |
565 | .irq_postinstall = tilcdc_irq_postinstall, | |
566 | .irq_uninstall = tilcdc_irq_uninstall, | |
b44f8408 | 567 | .get_vblank_counter = drm_vblank_no_hw_counter, |
16ea975e RC |
568 | .enable_vblank = tilcdc_enable_vblank, |
569 | .disable_vblank = tilcdc_disable_vblank, | |
570 | .gem_free_object = drm_gem_cma_free_object, | |
571 | .gem_vm_ops = &drm_gem_cma_vm_ops, | |
572 | .dumb_create = drm_gem_cma_dumb_create, | |
573 | .dumb_map_offset = drm_gem_cma_dumb_map_offset, | |
43387b37 | 574 | .dumb_destroy = drm_gem_dumb_destroy, |
16ea975e RC |
575 | #ifdef CONFIG_DEBUG_FS |
576 | .debugfs_init = tilcdc_debugfs_init, | |
577 | .debugfs_cleanup = tilcdc_debugfs_cleanup, | |
578 | #endif | |
579 | .fops = &fops, | |
580 | .name = "tilcdc", | |
581 | .desc = "TI LCD Controller DRM", | |
582 | .date = "20121205", | |
583 | .major = 1, | |
584 | .minor = 0, | |
585 | }; | |
586 | ||
587 | /* | |
588 | * Power management: | |
589 | */ | |
590 | ||
591 | #ifdef CONFIG_PM_SLEEP | |
592 | static int tilcdc_pm_suspend(struct device *dev) | |
593 | { | |
594 | struct drm_device *ddev = dev_get_drvdata(dev); | |
595 | struct tilcdc_drm_private *priv = ddev->dev_private; | |
596 | unsigned i, n = 0; | |
597 | ||
598 | drm_kms_helper_poll_disable(ddev); | |
599 | ||
600 | /* Save register state: */ | |
601 | for (i = 0; i < ARRAY_SIZE(registers); i++) | |
602 | if (registers[i].save && (priv->rev >= registers[i].rev)) | |
603 | priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg); | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
608 | static int tilcdc_pm_resume(struct device *dev) | |
609 | { | |
610 | struct drm_device *ddev = dev_get_drvdata(dev); | |
611 | struct tilcdc_drm_private *priv = ddev->dev_private; | |
612 | unsigned i, n = 0; | |
613 | ||
614 | /* Restore register state: */ | |
615 | for (i = 0; i < ARRAY_SIZE(registers); i++) | |
616 | if (registers[i].save && (priv->rev >= registers[i].rev)) | |
617 | tilcdc_write(ddev, registers[i].reg, priv->saved_register[n++]); | |
618 | ||
619 | drm_kms_helper_poll_enable(ddev); | |
620 | ||
621 | return 0; | |
622 | } | |
623 | #endif | |
624 | ||
625 | static const struct dev_pm_ops tilcdc_pm_ops = { | |
626 | SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume) | |
627 | }; | |
628 | ||
629 | /* | |
630 | * Platform driver: | |
631 | */ | |
632 | ||
103cd8bc JS |
633 | static int tilcdc_bind(struct device *dev) |
634 | { | |
635 | return drm_platform_init(&tilcdc_driver, to_platform_device(dev)); | |
636 | } | |
637 | ||
638 | static void tilcdc_unbind(struct device *dev) | |
639 | { | |
640 | drm_put_dev(dev_get_drvdata(dev)); | |
641 | } | |
642 | ||
643 | static const struct component_master_ops tilcdc_comp_ops = { | |
644 | .bind = tilcdc_bind, | |
645 | .unbind = tilcdc_unbind, | |
646 | }; | |
647 | ||
16ea975e RC |
648 | static int tilcdc_pdev_probe(struct platform_device *pdev) |
649 | { | |
103cd8bc JS |
650 | struct component_match *match = NULL; |
651 | int ret; | |
652 | ||
16ea975e RC |
653 | /* bail out early if no DT data: */ |
654 | if (!pdev->dev.of_node) { | |
655 | dev_err(&pdev->dev, "device-tree data is missing\n"); | |
656 | return -ENXIO; | |
657 | } | |
658 | ||
103cd8bc JS |
659 | ret = tilcdc_get_external_components(&pdev->dev, &match); |
660 | if (ret < 0) | |
661 | return ret; | |
662 | else if (ret == 0) | |
663 | return drm_platform_init(&tilcdc_driver, pdev); | |
664 | else | |
665 | return component_master_add_with_match(&pdev->dev, | |
666 | &tilcdc_comp_ops, | |
667 | match); | |
16ea975e RC |
668 | } |
669 | ||
670 | static int tilcdc_pdev_remove(struct platform_device *pdev) | |
671 | { | |
103cd8bc JS |
672 | struct drm_device *ddev = dev_get_drvdata(&pdev->dev); |
673 | struct tilcdc_drm_private *priv = ddev->dev_private; | |
674 | ||
675 | /* Check if a subcomponent has already triggered the unloading. */ | |
676 | if (!priv) | |
677 | return 0; | |
678 | ||
679 | if (priv->is_componentized) | |
680 | component_master_del(&pdev->dev, &tilcdc_comp_ops); | |
681 | else | |
682 | drm_put_dev(platform_get_drvdata(pdev)); | |
16ea975e RC |
683 | |
684 | return 0; | |
685 | } | |
686 | ||
687 | static struct of_device_id tilcdc_of_match[] = { | |
688 | { .compatible = "ti,am33xx-tilcdc", }, | |
689 | { }, | |
690 | }; | |
691 | MODULE_DEVICE_TABLE(of, tilcdc_of_match); | |
692 | ||
693 | static struct platform_driver tilcdc_platform_driver = { | |
694 | .probe = tilcdc_pdev_probe, | |
695 | .remove = tilcdc_pdev_remove, | |
696 | .driver = { | |
16ea975e RC |
697 | .name = "tilcdc", |
698 | .pm = &tilcdc_pm_ops, | |
699 | .of_match_table = tilcdc_of_match, | |
700 | }, | |
701 | }; | |
702 | ||
703 | static int __init tilcdc_drm_init(void) | |
704 | { | |
705 | DBG("init"); | |
706 | tilcdc_tfp410_init(); | |
0d4bbaf9 | 707 | tilcdc_panel_init(); |
16ea975e RC |
708 | return platform_driver_register(&tilcdc_platform_driver); |
709 | } | |
710 | ||
711 | static void __exit tilcdc_drm_fini(void) | |
712 | { | |
713 | DBG("fini"); | |
16ea975e | 714 | platform_driver_unregister(&tilcdc_platform_driver); |
eb565a2b | 715 | tilcdc_panel_fini(); |
eb565a2b | 716 | tilcdc_tfp410_fini(); |
16ea975e RC |
717 | } |
718 | ||
2023d84d | 719 | module_init(tilcdc_drm_init); |
16ea975e RC |
720 | module_exit(tilcdc_drm_fini); |
721 | ||
722 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
723 | MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); | |
724 | MODULE_LICENSE("GPL"); |