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43b3cd99 AD |
1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
0f0de06c AD |
24 | #include <linux/firmware.h> |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/module.h> | |
43b3cd99 AD |
28 | #include "drmP.h" |
29 | #include "radeon.h" | |
30 | #include "radeon_asic.h" | |
31 | #include "radeon_drm.h" | |
32 | #include "sid.h" | |
33 | #include "atom.h" | |
48c0c902 | 34 | #include "si_blit_shaders.h" |
43b3cd99 | 35 | |
0f0de06c AD |
36 | #define SI_PFP_UCODE_SIZE 2144 |
37 | #define SI_PM4_UCODE_SIZE 2144 | |
38 | #define SI_CE_UCODE_SIZE 2144 | |
39 | #define SI_RLC_UCODE_SIZE 2048 | |
40 | #define SI_MC_UCODE_SIZE 7769 | |
41 | ||
42 | MODULE_FIRMWARE("radeon/TAHITI_pfp.bin"); | |
43 | MODULE_FIRMWARE("radeon/TAHITI_me.bin"); | |
44 | MODULE_FIRMWARE("radeon/TAHITI_ce.bin"); | |
45 | MODULE_FIRMWARE("radeon/TAHITI_mc.bin"); | |
46 | MODULE_FIRMWARE("radeon/TAHITI_rlc.bin"); | |
47 | MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin"); | |
48 | MODULE_FIRMWARE("radeon/PITCAIRN_me.bin"); | |
49 | MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin"); | |
50 | MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin"); | |
51 | MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin"); | |
52 | MODULE_FIRMWARE("radeon/VERDE_pfp.bin"); | |
53 | MODULE_FIRMWARE("radeon/VERDE_me.bin"); | |
54 | MODULE_FIRMWARE("radeon/VERDE_ce.bin"); | |
55 | MODULE_FIRMWARE("radeon/VERDE_mc.bin"); | |
56 | MODULE_FIRMWARE("radeon/VERDE_rlc.bin"); | |
57 | ||
25a857fb AD |
58 | extern int r600_ih_ring_alloc(struct radeon_device *rdev); |
59 | extern void r600_ih_ring_fini(struct radeon_device *rdev); | |
0a96d72b | 60 | extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); |
c476dde2 AD |
61 | extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); |
62 | extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); | |
ca7db22b | 63 | extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); |
0a96d72b | 64 | |
1bd47d2e AD |
65 | /* get temperature in millidegrees */ |
66 | int si_get_temp(struct radeon_device *rdev) | |
67 | { | |
68 | u32 temp; | |
69 | int actual_temp = 0; | |
70 | ||
71 | temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> | |
72 | CTF_TEMP_SHIFT; | |
73 | ||
74 | if (temp & 0x200) | |
75 | actual_temp = 255; | |
76 | else | |
77 | actual_temp = temp & 0x1ff; | |
78 | ||
79 | actual_temp = (actual_temp * 1000); | |
80 | ||
81 | return actual_temp; | |
82 | } | |
83 | ||
8b074dd6 AD |
84 | #define TAHITI_IO_MC_REGS_SIZE 36 |
85 | ||
86 | static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { | |
87 | {0x0000006f, 0x03044000}, | |
88 | {0x00000070, 0x0480c018}, | |
89 | {0x00000071, 0x00000040}, | |
90 | {0x00000072, 0x01000000}, | |
91 | {0x00000074, 0x000000ff}, | |
92 | {0x00000075, 0x00143400}, | |
93 | {0x00000076, 0x08ec0800}, | |
94 | {0x00000077, 0x040000cc}, | |
95 | {0x00000079, 0x00000000}, | |
96 | {0x0000007a, 0x21000409}, | |
97 | {0x0000007c, 0x00000000}, | |
98 | {0x0000007d, 0xe8000000}, | |
99 | {0x0000007e, 0x044408a8}, | |
100 | {0x0000007f, 0x00000003}, | |
101 | {0x00000080, 0x00000000}, | |
102 | {0x00000081, 0x01000000}, | |
103 | {0x00000082, 0x02000000}, | |
104 | {0x00000083, 0x00000000}, | |
105 | {0x00000084, 0xe3f3e4f4}, | |
106 | {0x00000085, 0x00052024}, | |
107 | {0x00000087, 0x00000000}, | |
108 | {0x00000088, 0x66036603}, | |
109 | {0x00000089, 0x01000000}, | |
110 | {0x0000008b, 0x1c0a0000}, | |
111 | {0x0000008c, 0xff010000}, | |
112 | {0x0000008e, 0xffffefff}, | |
113 | {0x0000008f, 0xfff3efff}, | |
114 | {0x00000090, 0xfff3efbf}, | |
115 | {0x00000094, 0x00101101}, | |
116 | {0x00000095, 0x00000fff}, | |
117 | {0x00000096, 0x00116fff}, | |
118 | {0x00000097, 0x60010000}, | |
119 | {0x00000098, 0x10010000}, | |
120 | {0x00000099, 0x00006000}, | |
121 | {0x0000009a, 0x00001000}, | |
122 | {0x0000009f, 0x00a77400} | |
123 | }; | |
124 | ||
125 | static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { | |
126 | {0x0000006f, 0x03044000}, | |
127 | {0x00000070, 0x0480c018}, | |
128 | {0x00000071, 0x00000040}, | |
129 | {0x00000072, 0x01000000}, | |
130 | {0x00000074, 0x000000ff}, | |
131 | {0x00000075, 0x00143400}, | |
132 | {0x00000076, 0x08ec0800}, | |
133 | {0x00000077, 0x040000cc}, | |
134 | {0x00000079, 0x00000000}, | |
135 | {0x0000007a, 0x21000409}, | |
136 | {0x0000007c, 0x00000000}, | |
137 | {0x0000007d, 0xe8000000}, | |
138 | {0x0000007e, 0x044408a8}, | |
139 | {0x0000007f, 0x00000003}, | |
140 | {0x00000080, 0x00000000}, | |
141 | {0x00000081, 0x01000000}, | |
142 | {0x00000082, 0x02000000}, | |
143 | {0x00000083, 0x00000000}, | |
144 | {0x00000084, 0xe3f3e4f4}, | |
145 | {0x00000085, 0x00052024}, | |
146 | {0x00000087, 0x00000000}, | |
147 | {0x00000088, 0x66036603}, | |
148 | {0x00000089, 0x01000000}, | |
149 | {0x0000008b, 0x1c0a0000}, | |
150 | {0x0000008c, 0xff010000}, | |
151 | {0x0000008e, 0xffffefff}, | |
152 | {0x0000008f, 0xfff3efff}, | |
153 | {0x00000090, 0xfff3efbf}, | |
154 | {0x00000094, 0x00101101}, | |
155 | {0x00000095, 0x00000fff}, | |
156 | {0x00000096, 0x00116fff}, | |
157 | {0x00000097, 0x60010000}, | |
158 | {0x00000098, 0x10010000}, | |
159 | {0x00000099, 0x00006000}, | |
160 | {0x0000009a, 0x00001000}, | |
161 | {0x0000009f, 0x00a47400} | |
162 | }; | |
163 | ||
164 | static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { | |
165 | {0x0000006f, 0x03044000}, | |
166 | {0x00000070, 0x0480c018}, | |
167 | {0x00000071, 0x00000040}, | |
168 | {0x00000072, 0x01000000}, | |
169 | {0x00000074, 0x000000ff}, | |
170 | {0x00000075, 0x00143400}, | |
171 | {0x00000076, 0x08ec0800}, | |
172 | {0x00000077, 0x040000cc}, | |
173 | {0x00000079, 0x00000000}, | |
174 | {0x0000007a, 0x21000409}, | |
175 | {0x0000007c, 0x00000000}, | |
176 | {0x0000007d, 0xe8000000}, | |
177 | {0x0000007e, 0x044408a8}, | |
178 | {0x0000007f, 0x00000003}, | |
179 | {0x00000080, 0x00000000}, | |
180 | {0x00000081, 0x01000000}, | |
181 | {0x00000082, 0x02000000}, | |
182 | {0x00000083, 0x00000000}, | |
183 | {0x00000084, 0xe3f3e4f4}, | |
184 | {0x00000085, 0x00052024}, | |
185 | {0x00000087, 0x00000000}, | |
186 | {0x00000088, 0x66036603}, | |
187 | {0x00000089, 0x01000000}, | |
188 | {0x0000008b, 0x1c0a0000}, | |
189 | {0x0000008c, 0xff010000}, | |
190 | {0x0000008e, 0xffffefff}, | |
191 | {0x0000008f, 0xfff3efff}, | |
192 | {0x00000090, 0xfff3efbf}, | |
193 | {0x00000094, 0x00101101}, | |
194 | {0x00000095, 0x00000fff}, | |
195 | {0x00000096, 0x00116fff}, | |
196 | {0x00000097, 0x60010000}, | |
197 | {0x00000098, 0x10010000}, | |
198 | {0x00000099, 0x00006000}, | |
199 | {0x0000009a, 0x00001000}, | |
200 | {0x0000009f, 0x00a37400} | |
201 | }; | |
202 | ||
203 | /* ucode loading */ | |
204 | static int si_mc_load_microcode(struct radeon_device *rdev) | |
205 | { | |
206 | const __be32 *fw_data; | |
207 | u32 running, blackout = 0; | |
208 | u32 *io_mc_regs; | |
209 | int i, ucode_size, regs_size; | |
210 | ||
211 | if (!rdev->mc_fw) | |
212 | return -EINVAL; | |
213 | ||
214 | switch (rdev->family) { | |
215 | case CHIP_TAHITI: | |
216 | io_mc_regs = (u32 *)&tahiti_io_mc_regs; | |
217 | ucode_size = SI_MC_UCODE_SIZE; | |
218 | regs_size = TAHITI_IO_MC_REGS_SIZE; | |
219 | break; | |
220 | case CHIP_PITCAIRN: | |
221 | io_mc_regs = (u32 *)&pitcairn_io_mc_regs; | |
222 | ucode_size = SI_MC_UCODE_SIZE; | |
223 | regs_size = TAHITI_IO_MC_REGS_SIZE; | |
224 | break; | |
225 | case CHIP_VERDE: | |
226 | default: | |
227 | io_mc_regs = (u32 *)&verde_io_mc_regs; | |
228 | ucode_size = SI_MC_UCODE_SIZE; | |
229 | regs_size = TAHITI_IO_MC_REGS_SIZE; | |
230 | break; | |
231 | } | |
232 | ||
233 | running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; | |
234 | ||
235 | if (running == 0) { | |
236 | if (running) { | |
237 | blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); | |
238 | WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); | |
239 | } | |
240 | ||
241 | /* reset the engine and set to writable */ | |
242 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); | |
243 | WREG32(MC_SEQ_SUP_CNTL, 0x00000010); | |
244 | ||
245 | /* load mc io regs */ | |
246 | for (i = 0; i < regs_size; i++) { | |
247 | WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); | |
248 | WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); | |
249 | } | |
250 | /* load the MC ucode */ | |
251 | fw_data = (const __be32 *)rdev->mc_fw->data; | |
252 | for (i = 0; i < ucode_size; i++) | |
253 | WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); | |
254 | ||
255 | /* put the engine back into the active state */ | |
256 | WREG32(MC_SEQ_SUP_CNTL, 0x00000008); | |
257 | WREG32(MC_SEQ_SUP_CNTL, 0x00000004); | |
258 | WREG32(MC_SEQ_SUP_CNTL, 0x00000001); | |
259 | ||
260 | /* wait for training to complete */ | |
261 | for (i = 0; i < rdev->usec_timeout; i++) { | |
262 | if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) | |
263 | break; | |
264 | udelay(1); | |
265 | } | |
266 | for (i = 0; i < rdev->usec_timeout; i++) { | |
267 | if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) | |
268 | break; | |
269 | udelay(1); | |
270 | } | |
271 | ||
272 | if (running) | |
273 | WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); | |
274 | } | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
0f0de06c AD |
279 | static int si_init_microcode(struct radeon_device *rdev) |
280 | { | |
281 | struct platform_device *pdev; | |
282 | const char *chip_name; | |
283 | const char *rlc_chip_name; | |
284 | size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size; | |
285 | char fw_name[30]; | |
286 | int err; | |
287 | ||
288 | DRM_DEBUG("\n"); | |
289 | ||
290 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); | |
291 | err = IS_ERR(pdev); | |
292 | if (err) { | |
293 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | switch (rdev->family) { | |
298 | case CHIP_TAHITI: | |
299 | chip_name = "TAHITI"; | |
300 | rlc_chip_name = "TAHITI"; | |
301 | pfp_req_size = SI_PFP_UCODE_SIZE * 4; | |
302 | me_req_size = SI_PM4_UCODE_SIZE * 4; | |
303 | ce_req_size = SI_CE_UCODE_SIZE * 4; | |
304 | rlc_req_size = SI_RLC_UCODE_SIZE * 4; | |
305 | mc_req_size = SI_MC_UCODE_SIZE * 4; | |
306 | break; | |
307 | case CHIP_PITCAIRN: | |
308 | chip_name = "PITCAIRN"; | |
309 | rlc_chip_name = "PITCAIRN"; | |
310 | pfp_req_size = SI_PFP_UCODE_SIZE * 4; | |
311 | me_req_size = SI_PM4_UCODE_SIZE * 4; | |
312 | ce_req_size = SI_CE_UCODE_SIZE * 4; | |
313 | rlc_req_size = SI_RLC_UCODE_SIZE * 4; | |
314 | mc_req_size = SI_MC_UCODE_SIZE * 4; | |
315 | break; | |
316 | case CHIP_VERDE: | |
317 | chip_name = "VERDE"; | |
318 | rlc_chip_name = "VERDE"; | |
319 | pfp_req_size = SI_PFP_UCODE_SIZE * 4; | |
320 | me_req_size = SI_PM4_UCODE_SIZE * 4; | |
321 | ce_req_size = SI_CE_UCODE_SIZE * 4; | |
322 | rlc_req_size = SI_RLC_UCODE_SIZE * 4; | |
323 | mc_req_size = SI_MC_UCODE_SIZE * 4; | |
324 | break; | |
325 | default: BUG(); | |
326 | } | |
327 | ||
328 | DRM_INFO("Loading %s Microcode\n", chip_name); | |
329 | ||
330 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
331 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); | |
332 | if (err) | |
333 | goto out; | |
334 | if (rdev->pfp_fw->size != pfp_req_size) { | |
335 | printk(KERN_ERR | |
336 | "si_cp: Bogus length %zu in firmware \"%s\"\n", | |
337 | rdev->pfp_fw->size, fw_name); | |
338 | err = -EINVAL; | |
339 | goto out; | |
340 | } | |
341 | ||
342 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
343 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); | |
344 | if (err) | |
345 | goto out; | |
346 | if (rdev->me_fw->size != me_req_size) { | |
347 | printk(KERN_ERR | |
348 | "si_cp: Bogus length %zu in firmware \"%s\"\n", | |
349 | rdev->me_fw->size, fw_name); | |
350 | err = -EINVAL; | |
351 | } | |
352 | ||
353 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name); | |
354 | err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev); | |
355 | if (err) | |
356 | goto out; | |
357 | if (rdev->ce_fw->size != ce_req_size) { | |
358 | printk(KERN_ERR | |
359 | "si_cp: Bogus length %zu in firmware \"%s\"\n", | |
360 | rdev->ce_fw->size, fw_name); | |
361 | err = -EINVAL; | |
362 | } | |
363 | ||
364 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); | |
365 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); | |
366 | if (err) | |
367 | goto out; | |
368 | if (rdev->rlc_fw->size != rlc_req_size) { | |
369 | printk(KERN_ERR | |
370 | "si_rlc: Bogus length %zu in firmware \"%s\"\n", | |
371 | rdev->rlc_fw->size, fw_name); | |
372 | err = -EINVAL; | |
373 | } | |
374 | ||
375 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); | |
376 | err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev); | |
377 | if (err) | |
378 | goto out; | |
379 | if (rdev->mc_fw->size != mc_req_size) { | |
380 | printk(KERN_ERR | |
381 | "si_mc: Bogus length %zu in firmware \"%s\"\n", | |
382 | rdev->mc_fw->size, fw_name); | |
383 | err = -EINVAL; | |
384 | } | |
385 | ||
386 | out: | |
387 | platform_device_unregister(pdev); | |
388 | ||
389 | if (err) { | |
390 | if (err != -EINVAL) | |
391 | printk(KERN_ERR | |
392 | "si_cp: Failed to load firmware \"%s\"\n", | |
393 | fw_name); | |
394 | release_firmware(rdev->pfp_fw); | |
395 | rdev->pfp_fw = NULL; | |
396 | release_firmware(rdev->me_fw); | |
397 | rdev->me_fw = NULL; | |
398 | release_firmware(rdev->ce_fw); | |
399 | rdev->ce_fw = NULL; | |
400 | release_firmware(rdev->rlc_fw); | |
401 | rdev->rlc_fw = NULL; | |
402 | release_firmware(rdev->mc_fw); | |
403 | rdev->mc_fw = NULL; | |
404 | } | |
405 | return err; | |
406 | } | |
407 | ||
43b3cd99 AD |
408 | /* watermark setup */ |
409 | static u32 dce6_line_buffer_adjust(struct radeon_device *rdev, | |
410 | struct radeon_crtc *radeon_crtc, | |
411 | struct drm_display_mode *mode, | |
412 | struct drm_display_mode *other_mode) | |
413 | { | |
414 | u32 tmp; | |
415 | /* | |
416 | * Line Buffer Setup | |
417 | * There are 3 line buffers, each one shared by 2 display controllers. | |
418 | * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between | |
419 | * the display controllers. The paritioning is done via one of four | |
420 | * preset allocations specified in bits 21:20: | |
421 | * 0 - half lb | |
422 | * 2 - whole lb, other crtc must be disabled | |
423 | */ | |
424 | /* this can get tricky if we have two large displays on a paired group | |
425 | * of crtcs. Ideally for multiple large displays we'd assign them to | |
426 | * non-linked crtcs for maximum line buffer allocation. | |
427 | */ | |
428 | if (radeon_crtc->base.enabled && mode) { | |
429 | if (other_mode) | |
430 | tmp = 0; /* 1/2 */ | |
431 | else | |
432 | tmp = 2; /* whole */ | |
433 | } else | |
434 | tmp = 0; | |
435 | ||
436 | WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, | |
437 | DC_LB_MEMORY_CONFIG(tmp)); | |
438 | ||
439 | if (radeon_crtc->base.enabled && mode) { | |
440 | switch (tmp) { | |
441 | case 0: | |
442 | default: | |
443 | return 4096 * 2; | |
444 | case 2: | |
445 | return 8192 * 2; | |
446 | } | |
447 | } | |
448 | ||
449 | /* controller not enabled, so no lb used */ | |
450 | return 0; | |
451 | } | |
452 | ||
ca7db22b | 453 | static u32 si_get_number_of_dram_channels(struct radeon_device *rdev) |
43b3cd99 AD |
454 | { |
455 | u32 tmp = RREG32(MC_SHARED_CHMAP); | |
456 | ||
457 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
458 | case 0: | |
459 | default: | |
460 | return 1; | |
461 | case 1: | |
462 | return 2; | |
463 | case 2: | |
464 | return 4; | |
465 | case 3: | |
466 | return 8; | |
467 | case 4: | |
468 | return 3; | |
469 | case 5: | |
470 | return 6; | |
471 | case 6: | |
472 | return 10; | |
473 | case 7: | |
474 | return 12; | |
475 | case 8: | |
476 | return 16; | |
477 | } | |
478 | } | |
479 | ||
480 | struct dce6_wm_params { | |
481 | u32 dram_channels; /* number of dram channels */ | |
482 | u32 yclk; /* bandwidth per dram data pin in kHz */ | |
483 | u32 sclk; /* engine clock in kHz */ | |
484 | u32 disp_clk; /* display clock in kHz */ | |
485 | u32 src_width; /* viewport width */ | |
486 | u32 active_time; /* active display time in ns */ | |
487 | u32 blank_time; /* blank time in ns */ | |
488 | bool interlaced; /* mode is interlaced */ | |
489 | fixed20_12 vsc; /* vertical scale ratio */ | |
490 | u32 num_heads; /* number of active crtcs */ | |
491 | u32 bytes_per_pixel; /* bytes per pixel display + overlay */ | |
492 | u32 lb_size; /* line buffer allocated to pipe */ | |
493 | u32 vtaps; /* vertical scaler taps */ | |
494 | }; | |
495 | ||
496 | static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm) | |
497 | { | |
498 | /* Calculate raw DRAM Bandwidth */ | |
499 | fixed20_12 dram_efficiency; /* 0.7 */ | |
500 | fixed20_12 yclk, dram_channels, bandwidth; | |
501 | fixed20_12 a; | |
502 | ||
503 | a.full = dfixed_const(1000); | |
504 | yclk.full = dfixed_const(wm->yclk); | |
505 | yclk.full = dfixed_div(yclk, a); | |
506 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
507 | a.full = dfixed_const(10); | |
508 | dram_efficiency.full = dfixed_const(7); | |
509 | dram_efficiency.full = dfixed_div(dram_efficiency, a); | |
510 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
511 | bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); | |
512 | ||
513 | return dfixed_trunc(bandwidth); | |
514 | } | |
515 | ||
516 | static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm) | |
517 | { | |
518 | /* Calculate DRAM Bandwidth and the part allocated to display. */ | |
519 | fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ | |
520 | fixed20_12 yclk, dram_channels, bandwidth; | |
521 | fixed20_12 a; | |
522 | ||
523 | a.full = dfixed_const(1000); | |
524 | yclk.full = dfixed_const(wm->yclk); | |
525 | yclk.full = dfixed_div(yclk, a); | |
526 | dram_channels.full = dfixed_const(wm->dram_channels * 4); | |
527 | a.full = dfixed_const(10); | |
528 | disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ | |
529 | disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); | |
530 | bandwidth.full = dfixed_mul(dram_channels, yclk); | |
531 | bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); | |
532 | ||
533 | return dfixed_trunc(bandwidth); | |
534 | } | |
535 | ||
536 | static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm) | |
537 | { | |
538 | /* Calculate the display Data return Bandwidth */ | |
539 | fixed20_12 return_efficiency; /* 0.8 */ | |
540 | fixed20_12 sclk, bandwidth; | |
541 | fixed20_12 a; | |
542 | ||
543 | a.full = dfixed_const(1000); | |
544 | sclk.full = dfixed_const(wm->sclk); | |
545 | sclk.full = dfixed_div(sclk, a); | |
546 | a.full = dfixed_const(10); | |
547 | return_efficiency.full = dfixed_const(8); | |
548 | return_efficiency.full = dfixed_div(return_efficiency, a); | |
549 | a.full = dfixed_const(32); | |
550 | bandwidth.full = dfixed_mul(a, sclk); | |
551 | bandwidth.full = dfixed_mul(bandwidth, return_efficiency); | |
552 | ||
553 | return dfixed_trunc(bandwidth); | |
554 | } | |
555 | ||
556 | static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm) | |
557 | { | |
558 | return 32; | |
559 | } | |
560 | ||
561 | static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm) | |
562 | { | |
563 | /* Calculate the DMIF Request Bandwidth */ | |
564 | fixed20_12 disp_clk_request_efficiency; /* 0.8 */ | |
565 | fixed20_12 disp_clk, sclk, bandwidth; | |
566 | fixed20_12 a, b1, b2; | |
567 | u32 min_bandwidth; | |
568 | ||
569 | a.full = dfixed_const(1000); | |
570 | disp_clk.full = dfixed_const(wm->disp_clk); | |
571 | disp_clk.full = dfixed_div(disp_clk, a); | |
572 | a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2); | |
573 | b1.full = dfixed_mul(a, disp_clk); | |
574 | ||
575 | a.full = dfixed_const(1000); | |
576 | sclk.full = dfixed_const(wm->sclk); | |
577 | sclk.full = dfixed_div(sclk, a); | |
578 | a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm)); | |
579 | b2.full = dfixed_mul(a, sclk); | |
580 | ||
581 | a.full = dfixed_const(10); | |
582 | disp_clk_request_efficiency.full = dfixed_const(8); | |
583 | disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); | |
584 | ||
585 | min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2)); | |
586 | ||
587 | a.full = dfixed_const(min_bandwidth); | |
588 | bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency); | |
589 | ||
590 | return dfixed_trunc(bandwidth); | |
591 | } | |
592 | ||
593 | static u32 dce6_available_bandwidth(struct dce6_wm_params *wm) | |
594 | { | |
595 | /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ | |
596 | u32 dram_bandwidth = dce6_dram_bandwidth(wm); | |
597 | u32 data_return_bandwidth = dce6_data_return_bandwidth(wm); | |
598 | u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm); | |
599 | ||
600 | return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); | |
601 | } | |
602 | ||
603 | static u32 dce6_average_bandwidth(struct dce6_wm_params *wm) | |
604 | { | |
605 | /* Calculate the display mode Average Bandwidth | |
606 | * DisplayMode should contain the source and destination dimensions, | |
607 | * timing, etc. | |
608 | */ | |
609 | fixed20_12 bpp; | |
610 | fixed20_12 line_time; | |
611 | fixed20_12 src_width; | |
612 | fixed20_12 bandwidth; | |
613 | fixed20_12 a; | |
614 | ||
615 | a.full = dfixed_const(1000); | |
616 | line_time.full = dfixed_const(wm->active_time + wm->blank_time); | |
617 | line_time.full = dfixed_div(line_time, a); | |
618 | bpp.full = dfixed_const(wm->bytes_per_pixel); | |
619 | src_width.full = dfixed_const(wm->src_width); | |
620 | bandwidth.full = dfixed_mul(src_width, bpp); | |
621 | bandwidth.full = dfixed_mul(bandwidth, wm->vsc); | |
622 | bandwidth.full = dfixed_div(bandwidth, line_time); | |
623 | ||
624 | return dfixed_trunc(bandwidth); | |
625 | } | |
626 | ||
627 | static u32 dce6_latency_watermark(struct dce6_wm_params *wm) | |
628 | { | |
629 | /* First calcualte the latency in ns */ | |
630 | u32 mc_latency = 2000; /* 2000 ns. */ | |
631 | u32 available_bandwidth = dce6_available_bandwidth(wm); | |
632 | u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; | |
633 | u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; | |
634 | u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ | |
635 | u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + | |
636 | (wm->num_heads * cursor_line_pair_return_time); | |
637 | u32 latency = mc_latency + other_heads_data_return_time + dc_latency; | |
638 | u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; | |
639 | u32 tmp, dmif_size = 12288; | |
640 | fixed20_12 a, b, c; | |
641 | ||
642 | if (wm->num_heads == 0) | |
643 | return 0; | |
644 | ||
645 | a.full = dfixed_const(2); | |
646 | b.full = dfixed_const(1); | |
647 | if ((wm->vsc.full > a.full) || | |
648 | ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || | |
649 | (wm->vtaps >= 5) || | |
650 | ((wm->vsc.full >= a.full) && wm->interlaced)) | |
651 | max_src_lines_per_dst_line = 4; | |
652 | else | |
653 | max_src_lines_per_dst_line = 2; | |
654 | ||
655 | a.full = dfixed_const(available_bandwidth); | |
656 | b.full = dfixed_const(wm->num_heads); | |
657 | a.full = dfixed_div(a, b); | |
658 | ||
659 | b.full = dfixed_const(mc_latency + 512); | |
660 | c.full = dfixed_const(wm->disp_clk); | |
661 | b.full = dfixed_div(b, c); | |
662 | ||
663 | c.full = dfixed_const(dmif_size); | |
664 | b.full = dfixed_div(c, b); | |
665 | ||
666 | tmp = min(dfixed_trunc(a), dfixed_trunc(b)); | |
667 | ||
668 | b.full = dfixed_const(1000); | |
669 | c.full = dfixed_const(wm->disp_clk); | |
670 | b.full = dfixed_div(c, b); | |
671 | c.full = dfixed_const(wm->bytes_per_pixel); | |
672 | b.full = dfixed_mul(b, c); | |
673 | ||
674 | lb_fill_bw = min(tmp, dfixed_trunc(b)); | |
675 | ||
676 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); | |
677 | b.full = dfixed_const(1000); | |
678 | c.full = dfixed_const(lb_fill_bw); | |
679 | b.full = dfixed_div(c, b); | |
680 | a.full = dfixed_div(a, b); | |
681 | line_fill_time = dfixed_trunc(a); | |
682 | ||
683 | if (line_fill_time < wm->active_time) | |
684 | return latency; | |
685 | else | |
686 | return latency + (line_fill_time - wm->active_time); | |
687 | ||
688 | } | |
689 | ||
690 | static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) | |
691 | { | |
692 | if (dce6_average_bandwidth(wm) <= | |
693 | (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) | |
694 | return true; | |
695 | else | |
696 | return false; | |
697 | }; | |
698 | ||
699 | static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) | |
700 | { | |
701 | if (dce6_average_bandwidth(wm) <= | |
702 | (dce6_available_bandwidth(wm) / wm->num_heads)) | |
703 | return true; | |
704 | else | |
705 | return false; | |
706 | }; | |
707 | ||
708 | static bool dce6_check_latency_hiding(struct dce6_wm_params *wm) | |
709 | { | |
710 | u32 lb_partitions = wm->lb_size / wm->src_width; | |
711 | u32 line_time = wm->active_time + wm->blank_time; | |
712 | u32 latency_tolerant_lines; | |
713 | u32 latency_hiding; | |
714 | fixed20_12 a; | |
715 | ||
716 | a.full = dfixed_const(1); | |
717 | if (wm->vsc.full > a.full) | |
718 | latency_tolerant_lines = 1; | |
719 | else { | |
720 | if (lb_partitions <= (wm->vtaps + 1)) | |
721 | latency_tolerant_lines = 1; | |
722 | else | |
723 | latency_tolerant_lines = 2; | |
724 | } | |
725 | ||
726 | latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); | |
727 | ||
728 | if (dce6_latency_watermark(wm) <= latency_hiding) | |
729 | return true; | |
730 | else | |
731 | return false; | |
732 | } | |
733 | ||
734 | static void dce6_program_watermarks(struct radeon_device *rdev, | |
735 | struct radeon_crtc *radeon_crtc, | |
736 | u32 lb_size, u32 num_heads) | |
737 | { | |
738 | struct drm_display_mode *mode = &radeon_crtc->base.mode; | |
739 | struct dce6_wm_params wm; | |
740 | u32 pixel_period; | |
741 | u32 line_time = 0; | |
742 | u32 latency_watermark_a = 0, latency_watermark_b = 0; | |
743 | u32 priority_a_mark = 0, priority_b_mark = 0; | |
744 | u32 priority_a_cnt = PRIORITY_OFF; | |
745 | u32 priority_b_cnt = PRIORITY_OFF; | |
746 | u32 tmp, arb_control3; | |
747 | fixed20_12 a, b, c; | |
748 | ||
749 | if (radeon_crtc->base.enabled && num_heads && mode) { | |
750 | pixel_period = 1000000 / (u32)mode->clock; | |
751 | line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); | |
752 | priority_a_cnt = 0; | |
753 | priority_b_cnt = 0; | |
754 | ||
755 | wm.yclk = rdev->pm.current_mclk * 10; | |
756 | wm.sclk = rdev->pm.current_sclk * 10; | |
757 | wm.disp_clk = mode->clock; | |
758 | wm.src_width = mode->crtc_hdisplay; | |
759 | wm.active_time = mode->crtc_hdisplay * pixel_period; | |
760 | wm.blank_time = line_time - wm.active_time; | |
761 | wm.interlaced = false; | |
762 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
763 | wm.interlaced = true; | |
764 | wm.vsc = radeon_crtc->vsc; | |
765 | wm.vtaps = 1; | |
766 | if (radeon_crtc->rmx_type != RMX_OFF) | |
767 | wm.vtaps = 2; | |
768 | wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ | |
769 | wm.lb_size = lb_size; | |
ca7db22b AD |
770 | if (rdev->family == CHIP_ARUBA) |
771 | wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); | |
772 | else | |
773 | wm.dram_channels = si_get_number_of_dram_channels(rdev); | |
43b3cd99 AD |
774 | wm.num_heads = num_heads; |
775 | ||
776 | /* set for high clocks */ | |
777 | latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535); | |
778 | /* set for low clocks */ | |
779 | /* wm.yclk = low clk; wm.sclk = low clk */ | |
780 | latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535); | |
781 | ||
782 | /* possibly force display priority to high */ | |
783 | /* should really do this at mode validation time... */ | |
784 | if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || | |
785 | !dce6_average_bandwidth_vs_available_bandwidth(&wm) || | |
786 | !dce6_check_latency_hiding(&wm) || | |
787 | (rdev->disp_priority == 2)) { | |
788 | DRM_DEBUG_KMS("force priority to high\n"); | |
789 | priority_a_cnt |= PRIORITY_ALWAYS_ON; | |
790 | priority_b_cnt |= PRIORITY_ALWAYS_ON; | |
791 | } | |
792 | ||
793 | a.full = dfixed_const(1000); | |
794 | b.full = dfixed_const(mode->clock); | |
795 | b.full = dfixed_div(b, a); | |
796 | c.full = dfixed_const(latency_watermark_a); | |
797 | c.full = dfixed_mul(c, b); | |
798 | c.full = dfixed_mul(c, radeon_crtc->hsc); | |
799 | c.full = dfixed_div(c, a); | |
800 | a.full = dfixed_const(16); | |
801 | c.full = dfixed_div(c, a); | |
802 | priority_a_mark = dfixed_trunc(c); | |
803 | priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; | |
804 | ||
805 | a.full = dfixed_const(1000); | |
806 | b.full = dfixed_const(mode->clock); | |
807 | b.full = dfixed_div(b, a); | |
808 | c.full = dfixed_const(latency_watermark_b); | |
809 | c.full = dfixed_mul(c, b); | |
810 | c.full = dfixed_mul(c, radeon_crtc->hsc); | |
811 | c.full = dfixed_div(c, a); | |
812 | a.full = dfixed_const(16); | |
813 | c.full = dfixed_div(c, a); | |
814 | priority_b_mark = dfixed_trunc(c); | |
815 | priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; | |
816 | } | |
817 | ||
818 | /* select wm A */ | |
819 | arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); | |
820 | tmp = arb_control3; | |
821 | tmp &= ~LATENCY_WATERMARK_MASK(3); | |
822 | tmp |= LATENCY_WATERMARK_MASK(1); | |
823 | WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); | |
824 | WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, | |
825 | (LATENCY_LOW_WATERMARK(latency_watermark_a) | | |
826 | LATENCY_HIGH_WATERMARK(line_time))); | |
827 | /* select wm B */ | |
828 | tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); | |
829 | tmp &= ~LATENCY_WATERMARK_MASK(3); | |
830 | tmp |= LATENCY_WATERMARK_MASK(2); | |
831 | WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); | |
832 | WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, | |
833 | (LATENCY_LOW_WATERMARK(latency_watermark_b) | | |
834 | LATENCY_HIGH_WATERMARK(line_time))); | |
835 | /* restore original selection */ | |
836 | WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); | |
837 | ||
838 | /* write the priority marks */ | |
839 | WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); | |
840 | WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); | |
841 | ||
842 | } | |
843 | ||
844 | void dce6_bandwidth_update(struct radeon_device *rdev) | |
845 | { | |
846 | struct drm_display_mode *mode0 = NULL; | |
847 | struct drm_display_mode *mode1 = NULL; | |
848 | u32 num_heads = 0, lb_size; | |
849 | int i; | |
850 | ||
851 | radeon_update_display_priority(rdev); | |
852 | ||
853 | for (i = 0; i < rdev->num_crtc; i++) { | |
854 | if (rdev->mode_info.crtcs[i]->base.enabled) | |
855 | num_heads++; | |
856 | } | |
857 | for (i = 0; i < rdev->num_crtc; i += 2) { | |
858 | mode0 = &rdev->mode_info.crtcs[i]->base.mode; | |
859 | mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; | |
860 | lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); | |
861 | dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); | |
862 | lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); | |
863 | dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); | |
864 | } | |
865 | } | |
866 | ||
0a96d72b AD |
867 | /* |
868 | * Core functions | |
869 | */ | |
870 | static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev, | |
871 | u32 num_tile_pipes, | |
872 | u32 num_backends_per_asic, | |
873 | u32 *backend_disable_mask_per_asic, | |
874 | u32 num_shader_engines) | |
875 | { | |
876 | u32 backend_map = 0; | |
877 | u32 enabled_backends_mask = 0; | |
878 | u32 enabled_backends_count = 0; | |
879 | u32 num_backends_per_se; | |
880 | u32 cur_pipe; | |
881 | u32 swizzle_pipe[SI_MAX_PIPES]; | |
882 | u32 cur_backend = 0; | |
883 | u32 i; | |
884 | bool force_no_swizzle; | |
885 | ||
886 | /* force legal values */ | |
887 | if (num_tile_pipes < 1) | |
888 | num_tile_pipes = 1; | |
889 | if (num_tile_pipes > rdev->config.si.max_tile_pipes) | |
890 | num_tile_pipes = rdev->config.si.max_tile_pipes; | |
891 | if (num_shader_engines < 1) | |
892 | num_shader_engines = 1; | |
893 | if (num_shader_engines > rdev->config.si.max_shader_engines) | |
894 | num_shader_engines = rdev->config.si.max_shader_engines; | |
895 | if (num_backends_per_asic < num_shader_engines) | |
896 | num_backends_per_asic = num_shader_engines; | |
897 | if (num_backends_per_asic > (rdev->config.si.max_backends_per_se * num_shader_engines)) | |
898 | num_backends_per_asic = rdev->config.si.max_backends_per_se * num_shader_engines; | |
899 | ||
900 | /* make sure we have the same number of backends per se */ | |
901 | num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines); | |
902 | /* set up the number of backends per se */ | |
903 | num_backends_per_se = num_backends_per_asic / num_shader_engines; | |
904 | if (num_backends_per_se > rdev->config.si.max_backends_per_se) { | |
905 | num_backends_per_se = rdev->config.si.max_backends_per_se; | |
906 | num_backends_per_asic = num_backends_per_se * num_shader_engines; | |
907 | } | |
908 | ||
909 | /* create enable mask and count for enabled backends */ | |
910 | for (i = 0; i < SI_MAX_BACKENDS; ++i) { | |
911 | if (((*backend_disable_mask_per_asic >> i) & 1) == 0) { | |
912 | enabled_backends_mask |= (1 << i); | |
913 | ++enabled_backends_count; | |
914 | } | |
915 | if (enabled_backends_count == num_backends_per_asic) | |
916 | break; | |
917 | } | |
918 | ||
919 | /* force the backends mask to match the current number of backends */ | |
920 | if (enabled_backends_count != num_backends_per_asic) { | |
921 | u32 this_backend_enabled; | |
922 | u32 shader_engine; | |
923 | u32 backend_per_se; | |
924 | ||
925 | enabled_backends_mask = 0; | |
926 | enabled_backends_count = 0; | |
927 | *backend_disable_mask_per_asic = SI_MAX_BACKENDS_MASK; | |
928 | for (i = 0; i < SI_MAX_BACKENDS; ++i) { | |
929 | /* calc the current se */ | |
930 | shader_engine = i / rdev->config.si.max_backends_per_se; | |
931 | /* calc the backend per se */ | |
932 | backend_per_se = i % rdev->config.si.max_backends_per_se; | |
933 | /* default to not enabled */ | |
934 | this_backend_enabled = 0; | |
935 | if ((shader_engine < num_shader_engines) && | |
936 | (backend_per_se < num_backends_per_se)) | |
937 | this_backend_enabled = 1; | |
938 | if (this_backend_enabled) { | |
939 | enabled_backends_mask |= (1 << i); | |
940 | *backend_disable_mask_per_asic &= ~(1 << i); | |
941 | ++enabled_backends_count; | |
942 | } | |
943 | } | |
944 | } | |
945 | ||
946 | ||
947 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * SI_MAX_PIPES); | |
948 | switch (rdev->family) { | |
949 | case CHIP_TAHITI: | |
950 | case CHIP_PITCAIRN: | |
951 | case CHIP_VERDE: | |
952 | force_no_swizzle = true; | |
953 | break; | |
954 | default: | |
955 | force_no_swizzle = false; | |
956 | break; | |
957 | } | |
958 | if (force_no_swizzle) { | |
959 | bool last_backend_enabled = false; | |
960 | ||
961 | force_no_swizzle = false; | |
962 | for (i = 0; i < SI_MAX_BACKENDS; ++i) { | |
963 | if (((enabled_backends_mask >> i) & 1) == 1) { | |
964 | if (last_backend_enabled) | |
965 | force_no_swizzle = true; | |
966 | last_backend_enabled = true; | |
967 | } else | |
968 | last_backend_enabled = false; | |
969 | } | |
970 | } | |
971 | ||
972 | switch (num_tile_pipes) { | |
973 | case 1: | |
974 | case 3: | |
975 | case 5: | |
976 | case 7: | |
977 | DRM_ERROR("odd number of pipes!\n"); | |
978 | break; | |
979 | case 2: | |
980 | swizzle_pipe[0] = 0; | |
981 | swizzle_pipe[1] = 1; | |
982 | break; | |
983 | case 4: | |
984 | if (force_no_swizzle) { | |
985 | swizzle_pipe[0] = 0; | |
986 | swizzle_pipe[1] = 1; | |
987 | swizzle_pipe[2] = 2; | |
988 | swizzle_pipe[3] = 3; | |
989 | } else { | |
990 | swizzle_pipe[0] = 0; | |
991 | swizzle_pipe[1] = 2; | |
992 | swizzle_pipe[2] = 1; | |
993 | swizzle_pipe[3] = 3; | |
994 | } | |
995 | break; | |
996 | case 6: | |
997 | if (force_no_swizzle) { | |
998 | swizzle_pipe[0] = 0; | |
999 | swizzle_pipe[1] = 1; | |
1000 | swizzle_pipe[2] = 2; | |
1001 | swizzle_pipe[3] = 3; | |
1002 | swizzle_pipe[4] = 4; | |
1003 | swizzle_pipe[5] = 5; | |
1004 | } else { | |
1005 | swizzle_pipe[0] = 0; | |
1006 | swizzle_pipe[1] = 2; | |
1007 | swizzle_pipe[2] = 4; | |
1008 | swizzle_pipe[3] = 1; | |
1009 | swizzle_pipe[4] = 3; | |
1010 | swizzle_pipe[5] = 5; | |
1011 | } | |
1012 | break; | |
1013 | case 8: | |
1014 | if (force_no_swizzle) { | |
1015 | swizzle_pipe[0] = 0; | |
1016 | swizzle_pipe[1] = 1; | |
1017 | swizzle_pipe[2] = 2; | |
1018 | swizzle_pipe[3] = 3; | |
1019 | swizzle_pipe[4] = 4; | |
1020 | swizzle_pipe[5] = 5; | |
1021 | swizzle_pipe[6] = 6; | |
1022 | swizzle_pipe[7] = 7; | |
1023 | } else { | |
1024 | swizzle_pipe[0] = 0; | |
1025 | swizzle_pipe[1] = 2; | |
1026 | swizzle_pipe[2] = 4; | |
1027 | swizzle_pipe[3] = 6; | |
1028 | swizzle_pipe[4] = 1; | |
1029 | swizzle_pipe[5] = 3; | |
1030 | swizzle_pipe[6] = 5; | |
1031 | swizzle_pipe[7] = 7; | |
1032 | } | |
1033 | break; | |
1034 | } | |
1035 | ||
1036 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
1037 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
1038 | cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS; | |
1039 | ||
1040 | backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4))); | |
1041 | ||
1042 | cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS; | |
1043 | } | |
1044 | ||
1045 | return backend_map; | |
1046 | } | |
1047 | ||
1048 | static u32 si_get_disable_mask_per_asic(struct radeon_device *rdev, | |
1049 | u32 disable_mask_per_se, | |
1050 | u32 max_disable_mask_per_se, | |
1051 | u32 num_shader_engines) | |
1052 | { | |
1053 | u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se); | |
1054 | u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se; | |
1055 | ||
1056 | if (num_shader_engines == 1) | |
1057 | return disable_mask_per_asic; | |
1058 | else if (num_shader_engines == 2) | |
1059 | return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se); | |
1060 | else | |
1061 | return 0xffffffff; | |
1062 | } | |
1063 | ||
1064 | static void si_tiling_mode_table_init(struct radeon_device *rdev) | |
1065 | { | |
1066 | const u32 num_tile_mode_states = 32; | |
1067 | u32 reg_offset, gb_tile_moden, split_equal_to_row_size; | |
1068 | ||
1069 | switch (rdev->config.si.mem_row_size_in_kb) { | |
1070 | case 1: | |
1071 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; | |
1072 | break; | |
1073 | case 2: | |
1074 | default: | |
1075 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; | |
1076 | break; | |
1077 | case 4: | |
1078 | split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; | |
1079 | break; | |
1080 | } | |
1081 | ||
1082 | if ((rdev->family == CHIP_TAHITI) || | |
1083 | (rdev->family == CHIP_PITCAIRN)) { | |
1084 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { | |
1085 | switch (reg_offset) { | |
1086 | case 0: /* non-AA compressed depth or any compressed stencil */ | |
1087 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1088 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1089 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1090 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1091 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1092 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1093 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1094 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1095 | break; | |
1096 | case 1: /* 2xAA/4xAA compressed depth only */ | |
1097 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1098 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1099 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1100 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | | |
1101 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1102 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1103 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1104 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1105 | break; | |
1106 | case 2: /* 8xAA compressed depth only */ | |
1107 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1108 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1109 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1110 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1111 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1112 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1113 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1114 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1115 | break; | |
1116 | case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ | |
1117 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1118 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1119 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1120 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | | |
1121 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1122 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1123 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1124 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1125 | break; | |
1126 | case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ | |
1127 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1128 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1129 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1130 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1131 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1132 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1133 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1134 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1135 | break; | |
1136 | case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ | |
1137 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1138 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1139 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1140 | TILE_SPLIT(split_equal_to_row_size) | | |
1141 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1142 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1143 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1144 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1145 | break; | |
1146 | case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ | |
1147 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1148 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1149 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1150 | TILE_SPLIT(split_equal_to_row_size) | | |
1151 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1152 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1153 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1154 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | |
1155 | break; | |
1156 | case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ | |
1157 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1158 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1159 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1160 | TILE_SPLIT(split_equal_to_row_size) | | |
1161 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1162 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1163 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1164 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1165 | break; | |
1166 | case 8: /* 1D and 1D Array Surfaces */ | |
1167 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | | |
1168 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1169 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1170 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1171 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1172 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1173 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1174 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1175 | break; | |
1176 | case 9: /* Displayable maps. */ | |
1177 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1178 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1179 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1180 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1181 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1182 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1183 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1184 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1185 | break; | |
1186 | case 10: /* Display 8bpp. */ | |
1187 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1188 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1189 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1190 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1191 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1192 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1193 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1194 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1195 | break; | |
1196 | case 11: /* Display 16bpp. */ | |
1197 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1198 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1199 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1200 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1201 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1202 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1203 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1204 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1205 | break; | |
1206 | case 12: /* Display 32bpp. */ | |
1207 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1208 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1209 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1210 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | |
1211 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1212 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1213 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1214 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | |
1215 | break; | |
1216 | case 13: /* Thin. */ | |
1217 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1218 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1219 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1220 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1221 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1222 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1223 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1224 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1225 | break; | |
1226 | case 14: /* Thin 8 bpp. */ | |
1227 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1228 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1229 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1230 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1231 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1232 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1233 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1234 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | |
1235 | break; | |
1236 | case 15: /* Thin 16 bpp. */ | |
1237 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1238 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1239 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1240 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1241 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1242 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1243 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1244 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | |
1245 | break; | |
1246 | case 16: /* Thin 32 bpp. */ | |
1247 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1248 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1249 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1250 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | |
1251 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1252 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1253 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1254 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | |
1255 | break; | |
1256 | case 17: /* Thin 64 bpp. */ | |
1257 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1258 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1259 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1260 | TILE_SPLIT(split_equal_to_row_size) | | |
1261 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1262 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1263 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1264 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | |
1265 | break; | |
1266 | case 21: /* 8 bpp PRT. */ | |
1267 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1268 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1269 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1270 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1271 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1272 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | | |
1273 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1274 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1275 | break; | |
1276 | case 22: /* 16 bpp PRT */ | |
1277 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1278 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1279 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1280 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1281 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1282 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1283 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1284 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); | |
1285 | break; | |
1286 | case 23: /* 32 bpp PRT */ | |
1287 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1288 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1289 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1290 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1291 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1292 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1293 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1294 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1295 | break; | |
1296 | case 24: /* 64 bpp PRT */ | |
1297 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1298 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1299 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1300 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | |
1301 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1302 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1303 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1304 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1305 | break; | |
1306 | case 25: /* 128 bpp PRT */ | |
1307 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1308 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1309 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1310 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | | |
1311 | NUM_BANKS(ADDR_SURF_8_BANK) | | |
1312 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1313 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1314 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | |
1315 | break; | |
1316 | default: | |
1317 | gb_tile_moden = 0; | |
1318 | break; | |
1319 | } | |
1320 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); | |
1321 | } | |
1322 | } else if (rdev->family == CHIP_VERDE) { | |
1323 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { | |
1324 | switch (reg_offset) { | |
1325 | case 0: /* non-AA compressed depth or any compressed stencil */ | |
1326 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1327 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1328 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1329 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1330 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1331 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1332 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1333 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); | |
1334 | break; | |
1335 | case 1: /* 2xAA/4xAA compressed depth only */ | |
1336 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1337 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1338 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1339 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | | |
1340 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1341 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1342 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1343 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); | |
1344 | break; | |
1345 | case 2: /* 8xAA compressed depth only */ | |
1346 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1347 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1348 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1349 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1350 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1351 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1352 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1353 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); | |
1354 | break; | |
1355 | case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ | |
1356 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1357 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1358 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1359 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | | |
1360 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1361 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1362 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1363 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); | |
1364 | break; | |
1365 | case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ | |
1366 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1367 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1368 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1369 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1370 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1371 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1372 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1373 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1374 | break; | |
1375 | case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ | |
1376 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1377 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1378 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1379 | TILE_SPLIT(split_equal_to_row_size) | | |
1380 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1381 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1382 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1383 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1384 | break; | |
1385 | case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ | |
1386 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1387 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1388 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1389 | TILE_SPLIT(split_equal_to_row_size) | | |
1390 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1391 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1392 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1393 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1394 | break; | |
1395 | case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ | |
1396 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1397 | MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | | |
1398 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1399 | TILE_SPLIT(split_equal_to_row_size) | | |
1400 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1401 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1402 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1403 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); | |
1404 | break; | |
1405 | case 8: /* 1D and 1D Array Surfaces */ | |
1406 | gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | | |
1407 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1408 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1409 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1410 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1411 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1412 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1413 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1414 | break; | |
1415 | case 9: /* Displayable maps. */ | |
1416 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1417 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1418 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1419 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1420 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1421 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1422 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1423 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1424 | break; | |
1425 | case 10: /* Display 8bpp. */ | |
1426 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1427 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1428 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1429 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1430 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1431 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1432 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1433 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); | |
1434 | break; | |
1435 | case 11: /* Display 16bpp. */ | |
1436 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1437 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1438 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1439 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1440 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1441 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1442 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1443 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1444 | break; | |
1445 | case 12: /* Display 32bpp. */ | |
1446 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1447 | MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | | |
1448 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1449 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | |
1450 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1451 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1452 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1453 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1454 | break; | |
1455 | case 13: /* Thin. */ | |
1456 | gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | | |
1457 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1458 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1459 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | | |
1460 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1461 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1462 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1463 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1464 | break; | |
1465 | case 14: /* Thin 8 bpp. */ | |
1466 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1467 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1468 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1469 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1470 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1471 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1472 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1473 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1474 | break; | |
1475 | case 15: /* Thin 16 bpp. */ | |
1476 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1477 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1478 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1479 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1480 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1481 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1482 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1483 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1484 | break; | |
1485 | case 16: /* Thin 32 bpp. */ | |
1486 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1487 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1488 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1489 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | |
1490 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1491 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1492 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1493 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1494 | break; | |
1495 | case 17: /* Thin 64 bpp. */ | |
1496 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1497 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1498 | PIPE_CONFIG(ADDR_SURF_P4_8x16) | | |
1499 | TILE_SPLIT(split_equal_to_row_size) | | |
1500 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1501 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1502 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1503 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1504 | break; | |
1505 | case 21: /* 8 bpp PRT. */ | |
1506 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1507 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1508 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1509 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1510 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1511 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | | |
1512 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1513 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1514 | break; | |
1515 | case 22: /* 16 bpp PRT */ | |
1516 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1517 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1518 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1519 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1520 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1521 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1522 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | | |
1523 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); | |
1524 | break; | |
1525 | case 23: /* 32 bpp PRT */ | |
1526 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1527 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1528 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1529 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | | |
1530 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1531 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1532 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | | |
1533 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1534 | break; | |
1535 | case 24: /* 64 bpp PRT */ | |
1536 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1537 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1538 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1539 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | | |
1540 | NUM_BANKS(ADDR_SURF_16_BANK) | | |
1541 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1542 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1543 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); | |
1544 | break; | |
1545 | case 25: /* 128 bpp PRT */ | |
1546 | gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | | |
1547 | MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | | |
1548 | PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | | |
1549 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | | |
1550 | NUM_BANKS(ADDR_SURF_8_BANK) | | |
1551 | BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | | |
1552 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | | |
1553 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); | |
1554 | break; | |
1555 | default: | |
1556 | gb_tile_moden = 0; | |
1557 | break; | |
1558 | } | |
1559 | WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); | |
1560 | } | |
1561 | } else | |
1562 | DRM_ERROR("unknown asic: 0x%x\n", rdev->family); | |
1563 | } | |
1564 | ||
1565 | static void si_gpu_init(struct radeon_device *rdev) | |
1566 | { | |
1567 | u32 cc_rb_backend_disable = 0; | |
1568 | u32 cc_gc_shader_array_config; | |
1569 | u32 gb_addr_config = 0; | |
1570 | u32 mc_shared_chmap, mc_arb_ramcfg; | |
1571 | u32 gb_backend_map; | |
1572 | u32 cgts_tcc_disable; | |
1573 | u32 sx_debug_1; | |
1574 | u32 gc_user_shader_array_config; | |
1575 | u32 gc_user_rb_backend_disable; | |
1576 | u32 cgts_user_tcc_disable; | |
1577 | u32 hdp_host_path_cntl; | |
1578 | u32 tmp; | |
1579 | int i, j; | |
1580 | ||
1581 | switch (rdev->family) { | |
1582 | case CHIP_TAHITI: | |
1583 | rdev->config.si.max_shader_engines = 2; | |
1584 | rdev->config.si.max_pipes_per_simd = 4; | |
1585 | rdev->config.si.max_tile_pipes = 12; | |
1586 | rdev->config.si.max_simds_per_se = 8; | |
1587 | rdev->config.si.max_backends_per_se = 4; | |
1588 | rdev->config.si.max_texture_channel_caches = 12; | |
1589 | rdev->config.si.max_gprs = 256; | |
1590 | rdev->config.si.max_gs_threads = 32; | |
1591 | rdev->config.si.max_hw_contexts = 8; | |
1592 | ||
1593 | rdev->config.si.sc_prim_fifo_size_frontend = 0x20; | |
1594 | rdev->config.si.sc_prim_fifo_size_backend = 0x100; | |
1595 | rdev->config.si.sc_hiz_tile_fifo_size = 0x30; | |
1596 | rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; | |
1597 | break; | |
1598 | case CHIP_PITCAIRN: | |
1599 | rdev->config.si.max_shader_engines = 2; | |
1600 | rdev->config.si.max_pipes_per_simd = 4; | |
1601 | rdev->config.si.max_tile_pipes = 8; | |
1602 | rdev->config.si.max_simds_per_se = 5; | |
1603 | rdev->config.si.max_backends_per_se = 4; | |
1604 | rdev->config.si.max_texture_channel_caches = 8; | |
1605 | rdev->config.si.max_gprs = 256; | |
1606 | rdev->config.si.max_gs_threads = 32; | |
1607 | rdev->config.si.max_hw_contexts = 8; | |
1608 | ||
1609 | rdev->config.si.sc_prim_fifo_size_frontend = 0x20; | |
1610 | rdev->config.si.sc_prim_fifo_size_backend = 0x100; | |
1611 | rdev->config.si.sc_hiz_tile_fifo_size = 0x30; | |
1612 | rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; | |
1613 | break; | |
1614 | case CHIP_VERDE: | |
1615 | default: | |
1616 | rdev->config.si.max_shader_engines = 1; | |
1617 | rdev->config.si.max_pipes_per_simd = 4; | |
1618 | rdev->config.si.max_tile_pipes = 4; | |
1619 | rdev->config.si.max_simds_per_se = 2; | |
1620 | rdev->config.si.max_backends_per_se = 4; | |
1621 | rdev->config.si.max_texture_channel_caches = 4; | |
1622 | rdev->config.si.max_gprs = 256; | |
1623 | rdev->config.si.max_gs_threads = 32; | |
1624 | rdev->config.si.max_hw_contexts = 8; | |
1625 | ||
1626 | rdev->config.si.sc_prim_fifo_size_frontend = 0x20; | |
1627 | rdev->config.si.sc_prim_fifo_size_backend = 0x40; | |
1628 | rdev->config.si.sc_hiz_tile_fifo_size = 0x30; | |
1629 | rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; | |
1630 | break; | |
1631 | } | |
1632 | ||
1633 | /* Initialize HDP */ | |
1634 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1635 | WREG32((0x2c14 + j), 0x00000000); | |
1636 | WREG32((0x2c18 + j), 0x00000000); | |
1637 | WREG32((0x2c1c + j), 0x00000000); | |
1638 | WREG32((0x2c20 + j), 0x00000000); | |
1639 | WREG32((0x2c24 + j), 0x00000000); | |
1640 | } | |
1641 | ||
1642 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1643 | ||
1644 | evergreen_fix_pci_max_read_req_size(rdev); | |
1645 | ||
1646 | WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); | |
1647 | ||
1648 | mc_shared_chmap = RREG32(MC_SHARED_CHMAP); | |
1649 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); | |
1650 | ||
1651 | cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); | |
1652 | cc_gc_shader_array_config = RREG32(CC_GC_SHADER_ARRAY_CONFIG); | |
1653 | cgts_tcc_disable = 0xffff0000; | |
1654 | for (i = 0; i < rdev->config.si.max_texture_channel_caches; i++) | |
1655 | cgts_tcc_disable &= ~(1 << (16 + i)); | |
1656 | gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE); | |
1657 | gc_user_shader_array_config = RREG32(GC_USER_SHADER_ARRAY_CONFIG); | |
1658 | cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE); | |
1659 | ||
1660 | rdev->config.si.num_shader_engines = rdev->config.si.max_shader_engines; | |
1661 | rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; | |
1662 | tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; | |
1663 | rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp); | |
1664 | tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT; | |
1665 | rdev->config.si.backend_disable_mask_per_asic = | |
1666 | si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK, | |
1667 | rdev->config.si.num_shader_engines); | |
1668 | rdev->config.si.backend_map = | |
1669 | si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes, | |
1670 | rdev->config.si.num_backends_per_se * | |
1671 | rdev->config.si.num_shader_engines, | |
1672 | &rdev->config.si.backend_disable_mask_per_asic, | |
1673 | rdev->config.si.num_shader_engines); | |
1674 | tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT; | |
1675 | rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp); | |
1676 | rdev->config.si.mem_max_burst_length_bytes = 256; | |
1677 | tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; | |
1678 | rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; | |
1679 | if (rdev->config.si.mem_row_size_in_kb > 4) | |
1680 | rdev->config.si.mem_row_size_in_kb = 4; | |
1681 | /* XXX use MC settings? */ | |
1682 | rdev->config.si.shader_engine_tile_size = 32; | |
1683 | rdev->config.si.num_gpus = 1; | |
1684 | rdev->config.si.multi_gpu_tile_size = 64; | |
1685 | ||
1686 | gb_addr_config = 0; | |
1687 | switch (rdev->config.si.num_tile_pipes) { | |
1688 | case 1: | |
1689 | gb_addr_config |= NUM_PIPES(0); | |
1690 | break; | |
1691 | case 2: | |
1692 | gb_addr_config |= NUM_PIPES(1); | |
1693 | break; | |
1694 | case 4: | |
1695 | gb_addr_config |= NUM_PIPES(2); | |
1696 | break; | |
1697 | case 8: | |
1698 | default: | |
1699 | gb_addr_config |= NUM_PIPES(3); | |
1700 | break; | |
1701 | } | |
1702 | ||
1703 | tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1; | |
1704 | gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp); | |
1705 | gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.si.num_shader_engines - 1); | |
1706 | tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1; | |
1707 | gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp); | |
1708 | switch (rdev->config.si.num_gpus) { | |
1709 | case 1: | |
1710 | default: | |
1711 | gb_addr_config |= NUM_GPUS(0); | |
1712 | break; | |
1713 | case 2: | |
1714 | gb_addr_config |= NUM_GPUS(1); | |
1715 | break; | |
1716 | case 4: | |
1717 | gb_addr_config |= NUM_GPUS(2); | |
1718 | break; | |
1719 | } | |
1720 | switch (rdev->config.si.multi_gpu_tile_size) { | |
1721 | case 16: | |
1722 | gb_addr_config |= MULTI_GPU_TILE_SIZE(0); | |
1723 | break; | |
1724 | case 32: | |
1725 | default: | |
1726 | gb_addr_config |= MULTI_GPU_TILE_SIZE(1); | |
1727 | break; | |
1728 | case 64: | |
1729 | gb_addr_config |= MULTI_GPU_TILE_SIZE(2); | |
1730 | break; | |
1731 | case 128: | |
1732 | gb_addr_config |= MULTI_GPU_TILE_SIZE(3); | |
1733 | break; | |
1734 | } | |
1735 | switch (rdev->config.si.mem_row_size_in_kb) { | |
1736 | case 1: | |
1737 | default: | |
1738 | gb_addr_config |= ROW_SIZE(0); | |
1739 | break; | |
1740 | case 2: | |
1741 | gb_addr_config |= ROW_SIZE(1); | |
1742 | break; | |
1743 | case 4: | |
1744 | gb_addr_config |= ROW_SIZE(2); | |
1745 | break; | |
1746 | } | |
1747 | ||
1748 | tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; | |
1749 | rdev->config.si.num_tile_pipes = (1 << tmp); | |
1750 | tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; | |
1751 | rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256; | |
1752 | tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; | |
1753 | rdev->config.si.num_shader_engines = tmp + 1; | |
1754 | tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; | |
1755 | rdev->config.si.num_gpus = tmp + 1; | |
1756 | tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; | |
1757 | rdev->config.si.multi_gpu_tile_size = 1 << tmp; | |
1758 | tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; | |
1759 | rdev->config.si.mem_row_size_in_kb = 1 << tmp; | |
1760 | ||
1761 | gb_backend_map = | |
1762 | si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes, | |
1763 | rdev->config.si.num_backends_per_se * | |
1764 | rdev->config.si.num_shader_engines, | |
1765 | &rdev->config.si.backend_disable_mask_per_asic, | |
1766 | rdev->config.si.num_shader_engines); | |
1767 | ||
1768 | /* setup tiling info dword. gb_addr_config is not adequate since it does | |
1769 | * not have bank info, so create a custom tiling dword. | |
1770 | * bits 3:0 num_pipes | |
1771 | * bits 7:4 num_banks | |
1772 | * bits 11:8 group_size | |
1773 | * bits 15:12 row_size | |
1774 | */ | |
1775 | rdev->config.si.tile_config = 0; | |
1776 | switch (rdev->config.si.num_tile_pipes) { | |
1777 | case 1: | |
1778 | rdev->config.si.tile_config |= (0 << 0); | |
1779 | break; | |
1780 | case 2: | |
1781 | rdev->config.si.tile_config |= (1 << 0); | |
1782 | break; | |
1783 | case 4: | |
1784 | rdev->config.si.tile_config |= (2 << 0); | |
1785 | break; | |
1786 | case 8: | |
1787 | default: | |
1788 | /* XXX what about 12? */ | |
1789 | rdev->config.si.tile_config |= (3 << 0); | |
1790 | break; | |
1791 | } | |
1792 | rdev->config.si.tile_config |= | |
1793 | ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; | |
1794 | rdev->config.si.tile_config |= | |
1795 | ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; | |
1796 | rdev->config.si.tile_config |= | |
1797 | ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; | |
1798 | ||
1799 | rdev->config.si.backend_map = gb_backend_map; | |
1800 | WREG32(GB_ADDR_CONFIG, gb_addr_config); | |
1801 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); | |
1802 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); | |
1803 | ||
1804 | /* primary versions */ | |
1805 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
1806 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
1807 | WREG32(CC_GC_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config); | |
1808 | ||
1809 | WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable); | |
1810 | ||
1811 | /* user versions */ | |
1812 | WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
1813 | WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
1814 | WREG32(GC_USER_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config); | |
1815 | ||
1816 | WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); | |
1817 | ||
1818 | si_tiling_mode_table_init(rdev); | |
1819 | ||
1820 | /* set HW defaults for 3D engine */ | |
1821 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | | |
1822 | ROQ_IB2_START(0x2b))); | |
1823 | WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); | |
1824 | ||
1825 | sx_debug_1 = RREG32(SX_DEBUG_1); | |
1826 | WREG32(SX_DEBUG_1, sx_debug_1); | |
1827 | ||
1828 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); | |
1829 | ||
1830 | WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | | |
1831 | SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) | | |
1832 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) | | |
1833 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size))); | |
1834 | ||
1835 | WREG32(VGT_NUM_INSTANCES, 1); | |
1836 | ||
1837 | WREG32(CP_PERFMON_CNTL, 0); | |
1838 | ||
1839 | WREG32(SQ_CONFIG, 0); | |
1840 | ||
1841 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | | |
1842 | FORCE_EOV_MAX_REZ_CNT(255))); | |
1843 | ||
1844 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | | |
1845 | AUTO_INVLD_EN(ES_AND_GS_AUTO)); | |
1846 | ||
1847 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
1848 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
1849 | ||
1850 | WREG32(CB_PERFCOUNTER0_SELECT0, 0); | |
1851 | WREG32(CB_PERFCOUNTER0_SELECT1, 0); | |
1852 | WREG32(CB_PERFCOUNTER1_SELECT0, 0); | |
1853 | WREG32(CB_PERFCOUNTER1_SELECT1, 0); | |
1854 | WREG32(CB_PERFCOUNTER2_SELECT0, 0); | |
1855 | WREG32(CB_PERFCOUNTER2_SELECT1, 0); | |
1856 | WREG32(CB_PERFCOUNTER3_SELECT0, 0); | |
1857 | WREG32(CB_PERFCOUNTER3_SELECT1, 0); | |
1858 | ||
1859 | tmp = RREG32(HDP_MISC_CNTL); | |
1860 | tmp |= HDP_FLUSH_INVALIDATE_CACHE; | |
1861 | WREG32(HDP_MISC_CNTL, tmp); | |
1862 | ||
1863 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); | |
1864 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | |
1865 | ||
1866 | WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); | |
1867 | ||
1868 | udelay(50); | |
1869 | } | |
c476dde2 | 1870 | |
2ece2e8b AD |
1871 | /* |
1872 | * GPU scratch registers helpers function. | |
1873 | */ | |
1874 | static void si_scratch_init(struct radeon_device *rdev) | |
1875 | { | |
1876 | int i; | |
1877 | ||
1878 | rdev->scratch.num_reg = 7; | |
1879 | rdev->scratch.reg_base = SCRATCH_REG0; | |
1880 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
1881 | rdev->scratch.free[i] = true; | |
1882 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); | |
1883 | } | |
1884 | } | |
1885 | ||
1886 | void si_fence_ring_emit(struct radeon_device *rdev, | |
1887 | struct radeon_fence *fence) | |
1888 | { | |
1889 | struct radeon_ring *ring = &rdev->ring[fence->ring]; | |
1890 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; | |
1891 | ||
1892 | /* flush read cache over gart */ | |
1893 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1894 | radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); | |
1895 | radeon_ring_write(ring, 0); | |
1896 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); | |
1897 | radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | | |
1898 | PACKET3_TC_ACTION_ENA | | |
1899 | PACKET3_SH_KCACHE_ACTION_ENA | | |
1900 | PACKET3_SH_ICACHE_ACTION_ENA); | |
1901 | radeon_ring_write(ring, 0xFFFFFFFF); | |
1902 | radeon_ring_write(ring, 0); | |
1903 | radeon_ring_write(ring, 10); /* poll interval */ | |
1904 | /* EVENT_WRITE_EOP - flush caches, send int */ | |
1905 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); | |
1906 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); | |
1907 | radeon_ring_write(ring, addr & 0xffffffff); | |
1908 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); | |
1909 | radeon_ring_write(ring, fence->seq); | |
1910 | radeon_ring_write(ring, 0); | |
1911 | } | |
1912 | ||
1913 | /* | |
1914 | * IB stuff | |
1915 | */ | |
1916 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
1917 | { | |
1918 | struct radeon_ring *ring = &rdev->ring[ib->fence->ring]; | |
1919 | u32 header; | |
1920 | ||
1921 | if (ib->is_const_ib) | |
1922 | header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); | |
1923 | else | |
1924 | header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); | |
1925 | ||
1926 | radeon_ring_write(ring, header); | |
1927 | radeon_ring_write(ring, | |
1928 | #ifdef __BIG_ENDIAN | |
1929 | (2 << 0) | | |
1930 | #endif | |
1931 | (ib->gpu_addr & 0xFFFFFFFC)); | |
1932 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); | |
1933 | radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24)); | |
1934 | ||
1935 | /* flush read cache over gart for this vmid */ | |
1936 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1937 | radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); | |
1938 | radeon_ring_write(ring, ib->vm_id); | |
1939 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); | |
1940 | radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | | |
1941 | PACKET3_TC_ACTION_ENA | | |
1942 | PACKET3_SH_KCACHE_ACTION_ENA | | |
1943 | PACKET3_SH_ICACHE_ACTION_ENA); | |
1944 | radeon_ring_write(ring, 0xFFFFFFFF); | |
1945 | radeon_ring_write(ring, 0); | |
1946 | radeon_ring_write(ring, 10); /* poll interval */ | |
1947 | } | |
1948 | ||
48c0c902 AD |
1949 | /* |
1950 | * CP. | |
1951 | */ | |
1952 | static void si_cp_enable(struct radeon_device *rdev, bool enable) | |
1953 | { | |
1954 | if (enable) | |
1955 | WREG32(CP_ME_CNTL, 0); | |
1956 | else { | |
1957 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
1958 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); | |
1959 | WREG32(SCRATCH_UMSK, 0); | |
1960 | } | |
1961 | udelay(50); | |
1962 | } | |
1963 | ||
1964 | static int si_cp_load_microcode(struct radeon_device *rdev) | |
1965 | { | |
1966 | const __be32 *fw_data; | |
1967 | int i; | |
1968 | ||
1969 | if (!rdev->me_fw || !rdev->pfp_fw) | |
1970 | return -EINVAL; | |
1971 | ||
1972 | si_cp_enable(rdev, false); | |
1973 | ||
1974 | /* PFP */ | |
1975 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
1976 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1977 | for (i = 0; i < SI_PFP_UCODE_SIZE; i++) | |
1978 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); | |
1979 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1980 | ||
1981 | /* CE */ | |
1982 | fw_data = (const __be32 *)rdev->ce_fw->data; | |
1983 | WREG32(CP_CE_UCODE_ADDR, 0); | |
1984 | for (i = 0; i < SI_CE_UCODE_SIZE; i++) | |
1985 | WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); | |
1986 | WREG32(CP_CE_UCODE_ADDR, 0); | |
1987 | ||
1988 | /* ME */ | |
1989 | fw_data = (const __be32 *)rdev->me_fw->data; | |
1990 | WREG32(CP_ME_RAM_WADDR, 0); | |
1991 | for (i = 0; i < SI_PM4_UCODE_SIZE; i++) | |
1992 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); | |
1993 | WREG32(CP_ME_RAM_WADDR, 0); | |
1994 | ||
1995 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1996 | WREG32(CP_CE_UCODE_ADDR, 0); | |
1997 | WREG32(CP_ME_RAM_WADDR, 0); | |
1998 | WREG32(CP_ME_RAM_RADDR, 0); | |
1999 | return 0; | |
2000 | } | |
2001 | ||
2002 | static int si_cp_start(struct radeon_device *rdev) | |
2003 | { | |
2004 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | |
2005 | int r, i; | |
2006 | ||
2007 | r = radeon_ring_lock(rdev, ring, 7 + 4); | |
2008 | if (r) { | |
2009 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
2010 | return r; | |
2011 | } | |
2012 | /* init the CP */ | |
2013 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); | |
2014 | radeon_ring_write(ring, 0x1); | |
2015 | radeon_ring_write(ring, 0x0); | |
2016 | radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); | |
2017 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | |
2018 | radeon_ring_write(ring, 0); | |
2019 | radeon_ring_write(ring, 0); | |
2020 | ||
2021 | /* init the CE partitions */ | |
2022 | radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); | |
2023 | radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); | |
2024 | radeon_ring_write(ring, 0xc000); | |
2025 | radeon_ring_write(ring, 0xe000); | |
2026 | radeon_ring_unlock_commit(rdev, ring); | |
2027 | ||
2028 | si_cp_enable(rdev, true); | |
2029 | ||
2030 | r = radeon_ring_lock(rdev, ring, si_default_size + 10); | |
2031 | if (r) { | |
2032 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
2033 | return r; | |
2034 | } | |
2035 | ||
2036 | /* setup clear context state */ | |
2037 | radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
2038 | radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); | |
2039 | ||
2040 | for (i = 0; i < si_default_size; i++) | |
2041 | radeon_ring_write(ring, si_default_state[i]); | |
2042 | ||
2043 | radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); | |
2044 | radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); | |
2045 | ||
2046 | /* set clear context state */ | |
2047 | radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); | |
2048 | radeon_ring_write(ring, 0); | |
2049 | ||
2050 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); | |
2051 | radeon_ring_write(ring, 0x00000316); | |
2052 | radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ | |
2053 | radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ | |
2054 | ||
2055 | radeon_ring_unlock_commit(rdev, ring); | |
2056 | ||
2057 | for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { | |
2058 | ring = &rdev->ring[i]; | |
2059 | r = radeon_ring_lock(rdev, ring, 2); | |
2060 | ||
2061 | /* clear the compute context state */ | |
2062 | radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); | |
2063 | radeon_ring_write(ring, 0); | |
2064 | ||
2065 | radeon_ring_unlock_commit(rdev, ring); | |
2066 | } | |
2067 | ||
2068 | return 0; | |
2069 | } | |
2070 | ||
2071 | static void si_cp_fini(struct radeon_device *rdev) | |
2072 | { | |
2073 | si_cp_enable(rdev, false); | |
2074 | radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); | |
2075 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); | |
2076 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); | |
2077 | } | |
2078 | ||
2079 | static int si_cp_resume(struct radeon_device *rdev) | |
2080 | { | |
2081 | struct radeon_ring *ring; | |
2082 | u32 tmp; | |
2083 | u32 rb_bufsz; | |
2084 | int r; | |
2085 | ||
2086 | /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ | |
2087 | WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | | |
2088 | SOFT_RESET_PA | | |
2089 | SOFT_RESET_VGT | | |
2090 | SOFT_RESET_SPI | | |
2091 | SOFT_RESET_SX)); | |
2092 | RREG32(GRBM_SOFT_RESET); | |
2093 | mdelay(15); | |
2094 | WREG32(GRBM_SOFT_RESET, 0); | |
2095 | RREG32(GRBM_SOFT_RESET); | |
2096 | ||
2097 | WREG32(CP_SEM_WAIT_TIMER, 0x0); | |
2098 | WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); | |
2099 | ||
2100 | /* Set the write pointer delay */ | |
2101 | WREG32(CP_RB_WPTR_DELAY, 0); | |
2102 | ||
2103 | WREG32(CP_DEBUG, 0); | |
2104 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | |
2105 | ||
2106 | /* ring 0 - compute and gfx */ | |
2107 | /* Set ring buffer size */ | |
2108 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | |
2109 | rb_bufsz = drm_order(ring->ring_size / 8); | |
2110 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | |
2111 | #ifdef __BIG_ENDIAN | |
2112 | tmp |= BUF_SWAP_32BIT; | |
2113 | #endif | |
2114 | WREG32(CP_RB0_CNTL, tmp); | |
2115 | ||
2116 | /* Initialize the ring buffer's read and write pointers */ | |
2117 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); | |
2118 | ring->wptr = 0; | |
2119 | WREG32(CP_RB0_WPTR, ring->wptr); | |
2120 | ||
2121 | /* set the wb address wether it's enabled or not */ | |
2122 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); | |
2123 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); | |
2124 | ||
2125 | if (rdev->wb.enabled) | |
2126 | WREG32(SCRATCH_UMSK, 0xff); | |
2127 | else { | |
2128 | tmp |= RB_NO_UPDATE; | |
2129 | WREG32(SCRATCH_UMSK, 0); | |
2130 | } | |
2131 | ||
2132 | mdelay(1); | |
2133 | WREG32(CP_RB0_CNTL, tmp); | |
2134 | ||
2135 | WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); | |
2136 | ||
2137 | ring->rptr = RREG32(CP_RB0_RPTR); | |
2138 | ||
2139 | /* ring1 - compute only */ | |
2140 | /* Set ring buffer size */ | |
2141 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; | |
2142 | rb_bufsz = drm_order(ring->ring_size / 8); | |
2143 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | |
2144 | #ifdef __BIG_ENDIAN | |
2145 | tmp |= BUF_SWAP_32BIT; | |
2146 | #endif | |
2147 | WREG32(CP_RB1_CNTL, tmp); | |
2148 | ||
2149 | /* Initialize the ring buffer's read and write pointers */ | |
2150 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); | |
2151 | ring->wptr = 0; | |
2152 | WREG32(CP_RB1_WPTR, ring->wptr); | |
2153 | ||
2154 | /* set the wb address wether it's enabled or not */ | |
2155 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); | |
2156 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); | |
2157 | ||
2158 | mdelay(1); | |
2159 | WREG32(CP_RB1_CNTL, tmp); | |
2160 | ||
2161 | WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); | |
2162 | ||
2163 | ring->rptr = RREG32(CP_RB1_RPTR); | |
2164 | ||
2165 | /* ring2 - compute only */ | |
2166 | /* Set ring buffer size */ | |
2167 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; | |
2168 | rb_bufsz = drm_order(ring->ring_size / 8); | |
2169 | tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | |
2170 | #ifdef __BIG_ENDIAN | |
2171 | tmp |= BUF_SWAP_32BIT; | |
2172 | #endif | |
2173 | WREG32(CP_RB2_CNTL, tmp); | |
2174 | ||
2175 | /* Initialize the ring buffer's read and write pointers */ | |
2176 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); | |
2177 | ring->wptr = 0; | |
2178 | WREG32(CP_RB2_WPTR, ring->wptr); | |
2179 | ||
2180 | /* set the wb address wether it's enabled or not */ | |
2181 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); | |
2182 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); | |
2183 | ||
2184 | mdelay(1); | |
2185 | WREG32(CP_RB2_CNTL, tmp); | |
2186 | ||
2187 | WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); | |
2188 | ||
2189 | ring->rptr = RREG32(CP_RB2_RPTR); | |
2190 | ||
2191 | /* start the rings */ | |
2192 | si_cp_start(rdev); | |
2193 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; | |
2194 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true; | |
2195 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true; | |
2196 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); | |
2197 | if (r) { | |
2198 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; | |
2199 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; | |
2200 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; | |
2201 | return r; | |
2202 | } | |
2203 | r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); | |
2204 | if (r) { | |
2205 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; | |
2206 | } | |
2207 | r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); | |
2208 | if (r) { | |
2209 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; | |
2210 | } | |
2211 | ||
2212 | return 0; | |
2213 | } | |
2214 | ||
c476dde2 AD |
2215 | bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
2216 | { | |
2217 | u32 srbm_status; | |
2218 | u32 grbm_status, grbm_status2; | |
2219 | u32 grbm_status_se0, grbm_status_se1; | |
c476dde2 AD |
2220 | |
2221 | srbm_status = RREG32(SRBM_STATUS); | |
2222 | grbm_status = RREG32(GRBM_STATUS); | |
2223 | grbm_status2 = RREG32(GRBM_STATUS2); | |
2224 | grbm_status_se0 = RREG32(GRBM_STATUS_SE0); | |
2225 | grbm_status_se1 = RREG32(GRBM_STATUS_SE1); | |
2226 | if (!(grbm_status & GUI_ACTIVE)) { | |
069211e5 | 2227 | radeon_ring_lockup_update(ring); |
c476dde2 AD |
2228 | return false; |
2229 | } | |
2230 | /* force CP activities */ | |
7b9ef16b | 2231 | radeon_ring_force_activity(rdev, ring); |
069211e5 | 2232 | return radeon_ring_test_lockup(rdev, ring); |
c476dde2 AD |
2233 | } |
2234 | ||
2235 | static int si_gpu_soft_reset(struct radeon_device *rdev) | |
2236 | { | |
2237 | struct evergreen_mc_save save; | |
2238 | u32 grbm_reset = 0; | |
2239 | ||
2240 | if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) | |
2241 | return 0; | |
2242 | ||
2243 | dev_info(rdev->dev, "GPU softreset \n"); | |
2244 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", | |
2245 | RREG32(GRBM_STATUS)); | |
2246 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", | |
2247 | RREG32(GRBM_STATUS2)); | |
2248 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", | |
2249 | RREG32(GRBM_STATUS_SE0)); | |
2250 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", | |
2251 | RREG32(GRBM_STATUS_SE1)); | |
2252 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", | |
2253 | RREG32(SRBM_STATUS)); | |
2254 | evergreen_mc_stop(rdev, &save); | |
2255 | if (radeon_mc_wait_for_idle(rdev)) { | |
2256 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
2257 | } | |
2258 | /* Disable CP parsing/prefetching */ | |
2259 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); | |
2260 | ||
2261 | /* reset all the gfx blocks */ | |
2262 | grbm_reset = (SOFT_RESET_CP | | |
2263 | SOFT_RESET_CB | | |
2264 | SOFT_RESET_DB | | |
2265 | SOFT_RESET_GDS | | |
2266 | SOFT_RESET_PA | | |
2267 | SOFT_RESET_SC | | |
6f789301 | 2268 | SOFT_RESET_BCI | |
c476dde2 AD |
2269 | SOFT_RESET_SPI | |
2270 | SOFT_RESET_SX | | |
2271 | SOFT_RESET_TC | | |
2272 | SOFT_RESET_TA | | |
2273 | SOFT_RESET_VGT | | |
2274 | SOFT_RESET_IA); | |
2275 | ||
2276 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); | |
2277 | WREG32(GRBM_SOFT_RESET, grbm_reset); | |
2278 | (void)RREG32(GRBM_SOFT_RESET); | |
2279 | udelay(50); | |
2280 | WREG32(GRBM_SOFT_RESET, 0); | |
2281 | (void)RREG32(GRBM_SOFT_RESET); | |
2282 | /* Wait a little for things to settle down */ | |
2283 | udelay(50); | |
2284 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", | |
2285 | RREG32(GRBM_STATUS)); | |
2286 | dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", | |
2287 | RREG32(GRBM_STATUS2)); | |
2288 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", | |
2289 | RREG32(GRBM_STATUS_SE0)); | |
2290 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", | |
2291 | RREG32(GRBM_STATUS_SE1)); | |
2292 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", | |
2293 | RREG32(SRBM_STATUS)); | |
2294 | evergreen_mc_resume(rdev, &save); | |
2295 | return 0; | |
2296 | } | |
2297 | ||
2298 | int si_asic_reset(struct radeon_device *rdev) | |
2299 | { | |
2300 | return si_gpu_soft_reset(rdev); | |
2301 | } | |
2302 | ||
d2800ee5 AD |
2303 | /* MC */ |
2304 | static void si_mc_program(struct radeon_device *rdev) | |
2305 | { | |
2306 | struct evergreen_mc_save save; | |
2307 | u32 tmp; | |
2308 | int i, j; | |
2309 | ||
2310 | /* Initialize HDP */ | |
2311 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
2312 | WREG32((0x2c14 + j), 0x00000000); | |
2313 | WREG32((0x2c18 + j), 0x00000000); | |
2314 | WREG32((0x2c1c + j), 0x00000000); | |
2315 | WREG32((0x2c20 + j), 0x00000000); | |
2316 | WREG32((0x2c24 + j), 0x00000000); | |
2317 | } | |
2318 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
2319 | ||
2320 | evergreen_mc_stop(rdev, &save); | |
2321 | if (radeon_mc_wait_for_idle(rdev)) { | |
2322 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
2323 | } | |
2324 | /* Lockout access through VGA aperture*/ | |
2325 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); | |
2326 | /* Update configuration */ | |
2327 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
2328 | rdev->mc.vram_start >> 12); | |
2329 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
2330 | rdev->mc.vram_end >> 12); | |
2331 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, | |
2332 | rdev->vram_scratch.gpu_addr >> 12); | |
2333 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; | |
2334 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); | |
2335 | WREG32(MC_VM_FB_LOCATION, tmp); | |
2336 | /* XXX double check these! */ | |
2337 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
2338 | WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); | |
2339 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); | |
2340 | WREG32(MC_VM_AGP_BASE, 0); | |
2341 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
2342 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
2343 | if (radeon_mc_wait_for_idle(rdev)) { | |
2344 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
2345 | } | |
2346 | evergreen_mc_resume(rdev, &save); | |
2347 | /* we need to own VRAM, so turn off the VGA renderer here | |
2348 | * to stop it overwriting our objects */ | |
2349 | rv515_vga_render_disable(rdev); | |
2350 | } | |
2351 | ||
2352 | /* SI MC address space is 40 bits */ | |
2353 | static void si_vram_location(struct radeon_device *rdev, | |
2354 | struct radeon_mc *mc, u64 base) | |
2355 | { | |
2356 | mc->vram_start = base; | |
2357 | if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) { | |
2358 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); | |
2359 | mc->real_vram_size = mc->aper_size; | |
2360 | mc->mc_vram_size = mc->aper_size; | |
2361 | } | |
2362 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
2363 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", | |
2364 | mc->mc_vram_size >> 20, mc->vram_start, | |
2365 | mc->vram_end, mc->real_vram_size >> 20); | |
2366 | } | |
2367 | ||
2368 | static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) | |
2369 | { | |
2370 | u64 size_af, size_bf; | |
2371 | ||
2372 | size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; | |
2373 | size_bf = mc->vram_start & ~mc->gtt_base_align; | |
2374 | if (size_bf > size_af) { | |
2375 | if (mc->gtt_size > size_bf) { | |
2376 | dev_warn(rdev->dev, "limiting GTT\n"); | |
2377 | mc->gtt_size = size_bf; | |
2378 | } | |
2379 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; | |
2380 | } else { | |
2381 | if (mc->gtt_size > size_af) { | |
2382 | dev_warn(rdev->dev, "limiting GTT\n"); | |
2383 | mc->gtt_size = size_af; | |
2384 | } | |
2385 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; | |
2386 | } | |
2387 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; | |
2388 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", | |
2389 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); | |
2390 | } | |
2391 | ||
2392 | static void si_vram_gtt_location(struct radeon_device *rdev, | |
2393 | struct radeon_mc *mc) | |
2394 | { | |
2395 | if (mc->mc_vram_size > 0xFFC0000000ULL) { | |
2396 | /* leave room for at least 1024M GTT */ | |
2397 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
2398 | mc->real_vram_size = 0xFFC0000000ULL; | |
2399 | mc->mc_vram_size = 0xFFC0000000ULL; | |
2400 | } | |
2401 | si_vram_location(rdev, &rdev->mc, 0); | |
2402 | rdev->mc.gtt_base_align = 0; | |
2403 | si_gtt_location(rdev, mc); | |
2404 | } | |
2405 | ||
2406 | static int si_mc_init(struct radeon_device *rdev) | |
2407 | { | |
2408 | u32 tmp; | |
2409 | int chansize, numchan; | |
2410 | ||
2411 | /* Get VRAM informations */ | |
2412 | rdev->mc.vram_is_ddr = true; | |
2413 | tmp = RREG32(MC_ARB_RAMCFG); | |
2414 | if (tmp & CHANSIZE_OVERRIDE) { | |
2415 | chansize = 16; | |
2416 | } else if (tmp & CHANSIZE_MASK) { | |
2417 | chansize = 64; | |
2418 | } else { | |
2419 | chansize = 32; | |
2420 | } | |
2421 | tmp = RREG32(MC_SHARED_CHMAP); | |
2422 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
2423 | case 0: | |
2424 | default: | |
2425 | numchan = 1; | |
2426 | break; | |
2427 | case 1: | |
2428 | numchan = 2; | |
2429 | break; | |
2430 | case 2: | |
2431 | numchan = 4; | |
2432 | break; | |
2433 | case 3: | |
2434 | numchan = 8; | |
2435 | break; | |
2436 | case 4: | |
2437 | numchan = 3; | |
2438 | break; | |
2439 | case 5: | |
2440 | numchan = 6; | |
2441 | break; | |
2442 | case 6: | |
2443 | numchan = 10; | |
2444 | break; | |
2445 | case 7: | |
2446 | numchan = 12; | |
2447 | break; | |
2448 | case 8: | |
2449 | numchan = 16; | |
2450 | break; | |
2451 | } | |
2452 | rdev->mc.vram_width = numchan * chansize; | |
2453 | /* Could aper size report 0 ? */ | |
2454 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); | |
2455 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
2456 | /* size in MB on si */ | |
2457 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | |
2458 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; | |
2459 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | |
2460 | si_vram_gtt_location(rdev, &rdev->mc); | |
2461 | radeon_update_bandwidth_info(rdev); | |
2462 | ||
2463 | return 0; | |
2464 | } | |
2465 | ||
2466 | /* | |
2467 | * GART | |
2468 | */ | |
2469 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev) | |
2470 | { | |
2471 | /* flush hdp cache */ | |
2472 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
2473 | ||
2474 | /* bits 0-15 are the VM contexts0-15 */ | |
2475 | WREG32(VM_INVALIDATE_REQUEST, 1); | |
2476 | } | |
2477 | ||
2478 | int si_pcie_gart_enable(struct radeon_device *rdev) | |
2479 | { | |
2480 | int r, i; | |
2481 | ||
2482 | if (rdev->gart.robj == NULL) { | |
2483 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
2484 | return -EINVAL; | |
2485 | } | |
2486 | r = radeon_gart_table_vram_pin(rdev); | |
2487 | if (r) | |
2488 | return r; | |
2489 | radeon_gart_restore(rdev); | |
2490 | /* Setup TLB control */ | |
2491 | WREG32(MC_VM_MX_L1_TLB_CNTL, | |
2492 | (0xA << 7) | | |
2493 | ENABLE_L1_TLB | | |
2494 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
2495 | ENABLE_ADVANCED_DRIVER_MODEL | | |
2496 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); | |
2497 | /* Setup L2 cache */ | |
2498 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | | |
2499 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
2500 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | | |
2501 | EFFECTIVE_L2_QUEUE_SIZE(7) | | |
2502 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); | |
2503 | WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); | |
2504 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | | |
2505 | L2_CACHE_BIGK_FRAGMENT_SIZE(0)); | |
2506 | /* setup context0 */ | |
2507 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
2508 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); | |
2509 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); | |
2510 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
2511 | (u32)(rdev->dummy_page.addr >> 12)); | |
2512 | WREG32(VM_CONTEXT0_CNTL2, 0); | |
2513 | WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
2514 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); | |
2515 | ||
2516 | WREG32(0x15D4, 0); | |
2517 | WREG32(0x15D8, 0); | |
2518 | WREG32(0x15DC, 0); | |
2519 | ||
2520 | /* empty context1-15 */ | |
2521 | /* FIXME start with 1G, once using 2 level pt switch to full | |
2522 | * vm size space | |
2523 | */ | |
2524 | /* set vm size, must be a multiple of 4 */ | |
2525 | WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); | |
2526 | WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, (1 << 30) / RADEON_GPU_PAGE_SIZE); | |
2527 | for (i = 1; i < 16; i++) { | |
2528 | if (i < 8) | |
2529 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), | |
2530 | rdev->gart.table_addr >> 12); | |
2531 | else | |
2532 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), | |
2533 | rdev->gart.table_addr >> 12); | |
2534 | } | |
2535 | ||
2536 | /* enable context1-15 */ | |
2537 | WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, | |
2538 | (u32)(rdev->dummy_page.addr >> 12)); | |
2539 | WREG32(VM_CONTEXT1_CNTL2, 0); | |
2540 | WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
2541 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
2542 | ||
2543 | si_pcie_gart_tlb_flush(rdev); | |
2544 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", | |
2545 | (unsigned)(rdev->mc.gtt_size >> 20), | |
2546 | (unsigned long long)rdev->gart.table_addr); | |
2547 | rdev->gart.ready = true; | |
2548 | return 0; | |
2549 | } | |
2550 | ||
2551 | void si_pcie_gart_disable(struct radeon_device *rdev) | |
2552 | { | |
2553 | /* Disable all tables */ | |
2554 | WREG32(VM_CONTEXT0_CNTL, 0); | |
2555 | WREG32(VM_CONTEXT1_CNTL, 0); | |
2556 | /* Setup TLB control */ | |
2557 | WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
2558 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); | |
2559 | /* Setup L2 cache */ | |
2560 | WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
2561 | ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | | |
2562 | EFFECTIVE_L2_QUEUE_SIZE(7) | | |
2563 | CONTEXT1_IDENTITY_ACCESS_MODE(1)); | |
2564 | WREG32(VM_L2_CNTL2, 0); | |
2565 | WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | | |
2566 | L2_CACHE_BIGK_FRAGMENT_SIZE(0)); | |
2567 | radeon_gart_table_vram_unpin(rdev); | |
2568 | } | |
2569 | ||
2570 | void si_pcie_gart_fini(struct radeon_device *rdev) | |
2571 | { | |
2572 | si_pcie_gart_disable(rdev); | |
2573 | radeon_gart_table_vram_free(rdev); | |
2574 | radeon_gart_fini(rdev); | |
2575 | } | |
2576 | ||
498dd8b3 AD |
2577 | /* vm parser */ |
2578 | static bool si_vm_reg_valid(u32 reg) | |
2579 | { | |
2580 | /* context regs are fine */ | |
2581 | if (reg >= 0x28000) | |
2582 | return true; | |
2583 | ||
2584 | /* check config regs */ | |
2585 | switch (reg) { | |
2586 | case GRBM_GFX_INDEX: | |
2587 | case VGT_VTX_VECT_EJECT_REG: | |
2588 | case VGT_CACHE_INVALIDATION: | |
2589 | case VGT_ESGS_RING_SIZE: | |
2590 | case VGT_GSVS_RING_SIZE: | |
2591 | case VGT_GS_VERTEX_REUSE: | |
2592 | case VGT_PRIMITIVE_TYPE: | |
2593 | case VGT_INDEX_TYPE: | |
2594 | case VGT_NUM_INDICES: | |
2595 | case VGT_NUM_INSTANCES: | |
2596 | case VGT_TF_RING_SIZE: | |
2597 | case VGT_HS_OFFCHIP_PARAM: | |
2598 | case VGT_TF_MEMORY_BASE: | |
2599 | case PA_CL_ENHANCE: | |
2600 | case PA_SU_LINE_STIPPLE_VALUE: | |
2601 | case PA_SC_LINE_STIPPLE_STATE: | |
2602 | case PA_SC_ENHANCE: | |
2603 | case SQC_CACHES: | |
2604 | case SPI_STATIC_THREAD_MGMT_1: | |
2605 | case SPI_STATIC_THREAD_MGMT_2: | |
2606 | case SPI_STATIC_THREAD_MGMT_3: | |
2607 | case SPI_PS_MAX_WAVE_ID: | |
2608 | case SPI_CONFIG_CNTL: | |
2609 | case SPI_CONFIG_CNTL_1: | |
2610 | case TA_CNTL_AUX: | |
2611 | return true; | |
2612 | default: | |
2613 | DRM_ERROR("Invalid register 0x%x in CS\n", reg); | |
2614 | return false; | |
2615 | } | |
2616 | } | |
2617 | ||
2618 | static int si_vm_packet3_ce_check(struct radeon_device *rdev, | |
2619 | u32 *ib, struct radeon_cs_packet *pkt) | |
2620 | { | |
2621 | switch (pkt->opcode) { | |
2622 | case PACKET3_NOP: | |
2623 | case PACKET3_SET_BASE: | |
2624 | case PACKET3_SET_CE_DE_COUNTERS: | |
2625 | case PACKET3_LOAD_CONST_RAM: | |
2626 | case PACKET3_WRITE_CONST_RAM: | |
2627 | case PACKET3_WRITE_CONST_RAM_OFFSET: | |
2628 | case PACKET3_DUMP_CONST_RAM: | |
2629 | case PACKET3_INCREMENT_CE_COUNTER: | |
2630 | case PACKET3_WAIT_ON_DE_COUNTER: | |
2631 | case PACKET3_CE_WRITE: | |
2632 | break; | |
2633 | default: | |
2634 | DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode); | |
2635 | return -EINVAL; | |
2636 | } | |
2637 | return 0; | |
2638 | } | |
2639 | ||
2640 | static int si_vm_packet3_gfx_check(struct radeon_device *rdev, | |
2641 | u32 *ib, struct radeon_cs_packet *pkt) | |
2642 | { | |
2643 | u32 idx = pkt->idx + 1; | |
2644 | u32 idx_value = ib[idx]; | |
2645 | u32 start_reg, end_reg, reg, i; | |
2646 | ||
2647 | switch (pkt->opcode) { | |
2648 | case PACKET3_NOP: | |
2649 | case PACKET3_SET_BASE: | |
2650 | case PACKET3_CLEAR_STATE: | |
2651 | case PACKET3_INDEX_BUFFER_SIZE: | |
2652 | case PACKET3_DISPATCH_DIRECT: | |
2653 | case PACKET3_DISPATCH_INDIRECT: | |
2654 | case PACKET3_ALLOC_GDS: | |
2655 | case PACKET3_WRITE_GDS_RAM: | |
2656 | case PACKET3_ATOMIC_GDS: | |
2657 | case PACKET3_ATOMIC: | |
2658 | case PACKET3_OCCLUSION_QUERY: | |
2659 | case PACKET3_SET_PREDICATION: | |
2660 | case PACKET3_COND_EXEC: | |
2661 | case PACKET3_PRED_EXEC: | |
2662 | case PACKET3_DRAW_INDIRECT: | |
2663 | case PACKET3_DRAW_INDEX_INDIRECT: | |
2664 | case PACKET3_INDEX_BASE: | |
2665 | case PACKET3_DRAW_INDEX_2: | |
2666 | case PACKET3_CONTEXT_CONTROL: | |
2667 | case PACKET3_INDEX_TYPE: | |
2668 | case PACKET3_DRAW_INDIRECT_MULTI: | |
2669 | case PACKET3_DRAW_INDEX_AUTO: | |
2670 | case PACKET3_DRAW_INDEX_IMMD: | |
2671 | case PACKET3_NUM_INSTANCES: | |
2672 | case PACKET3_DRAW_INDEX_MULTI_AUTO: | |
2673 | case PACKET3_STRMOUT_BUFFER_UPDATE: | |
2674 | case PACKET3_DRAW_INDEX_OFFSET_2: | |
2675 | case PACKET3_DRAW_INDEX_MULTI_ELEMENT: | |
2676 | case PACKET3_DRAW_INDEX_INDIRECT_MULTI: | |
2677 | case PACKET3_MPEG_INDEX: | |
2678 | case PACKET3_WAIT_REG_MEM: | |
2679 | case PACKET3_MEM_WRITE: | |
2680 | case PACKET3_PFP_SYNC_ME: | |
2681 | case PACKET3_SURFACE_SYNC: | |
2682 | case PACKET3_EVENT_WRITE: | |
2683 | case PACKET3_EVENT_WRITE_EOP: | |
2684 | case PACKET3_EVENT_WRITE_EOS: | |
2685 | case PACKET3_SET_CONTEXT_REG: | |
2686 | case PACKET3_SET_CONTEXT_REG_INDIRECT: | |
2687 | case PACKET3_SET_SH_REG: | |
2688 | case PACKET3_SET_SH_REG_OFFSET: | |
2689 | case PACKET3_INCREMENT_DE_COUNTER: | |
2690 | case PACKET3_WAIT_ON_CE_COUNTER: | |
2691 | case PACKET3_WAIT_ON_AVAIL_BUFFER: | |
2692 | case PACKET3_ME_WRITE: | |
2693 | break; | |
2694 | case PACKET3_COPY_DATA: | |
2695 | if ((idx_value & 0xf00) == 0) { | |
2696 | reg = ib[idx + 3] * 4; | |
2697 | if (!si_vm_reg_valid(reg)) | |
2698 | return -EINVAL; | |
2699 | } | |
2700 | break; | |
2701 | case PACKET3_WRITE_DATA: | |
2702 | if ((idx_value & 0xf00) == 0) { | |
2703 | start_reg = ib[idx + 1] * 4; | |
2704 | if (idx_value & 0x10000) { | |
2705 | if (!si_vm_reg_valid(start_reg)) | |
2706 | return -EINVAL; | |
2707 | } else { | |
2708 | for (i = 0; i < (pkt->count - 2); i++) { | |
2709 | reg = start_reg + (4 * i); | |
2710 | if (!si_vm_reg_valid(reg)) | |
2711 | return -EINVAL; | |
2712 | } | |
2713 | } | |
2714 | } | |
2715 | break; | |
2716 | case PACKET3_COND_WRITE: | |
2717 | if (idx_value & 0x100) { | |
2718 | reg = ib[idx + 5] * 4; | |
2719 | if (!si_vm_reg_valid(reg)) | |
2720 | return -EINVAL; | |
2721 | } | |
2722 | break; | |
2723 | case PACKET3_COPY_DW: | |
2724 | if (idx_value & 0x2) { | |
2725 | reg = ib[idx + 3] * 4; | |
2726 | if (!si_vm_reg_valid(reg)) | |
2727 | return -EINVAL; | |
2728 | } | |
2729 | break; | |
2730 | case PACKET3_SET_CONFIG_REG: | |
2731 | start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; | |
2732 | end_reg = 4 * pkt->count + start_reg - 4; | |
2733 | if ((start_reg < PACKET3_SET_CONFIG_REG_START) || | |
2734 | (start_reg >= PACKET3_SET_CONFIG_REG_END) || | |
2735 | (end_reg >= PACKET3_SET_CONFIG_REG_END)) { | |
2736 | DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); | |
2737 | return -EINVAL; | |
2738 | } | |
2739 | for (i = 0; i < pkt->count; i++) { | |
2740 | reg = start_reg + (4 * i); | |
2741 | if (!si_vm_reg_valid(reg)) | |
2742 | return -EINVAL; | |
2743 | } | |
2744 | break; | |
2745 | default: | |
2746 | DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode); | |
2747 | return -EINVAL; | |
2748 | } | |
2749 | return 0; | |
2750 | } | |
2751 | ||
2752 | static int si_vm_packet3_compute_check(struct radeon_device *rdev, | |
2753 | u32 *ib, struct radeon_cs_packet *pkt) | |
2754 | { | |
2755 | u32 idx = pkt->idx + 1; | |
2756 | u32 idx_value = ib[idx]; | |
2757 | u32 start_reg, reg, i; | |
2758 | ||
2759 | switch (pkt->opcode) { | |
2760 | case PACKET3_NOP: | |
2761 | case PACKET3_SET_BASE: | |
2762 | case PACKET3_CLEAR_STATE: | |
2763 | case PACKET3_DISPATCH_DIRECT: | |
2764 | case PACKET3_DISPATCH_INDIRECT: | |
2765 | case PACKET3_ALLOC_GDS: | |
2766 | case PACKET3_WRITE_GDS_RAM: | |
2767 | case PACKET3_ATOMIC_GDS: | |
2768 | case PACKET3_ATOMIC: | |
2769 | case PACKET3_OCCLUSION_QUERY: | |
2770 | case PACKET3_SET_PREDICATION: | |
2771 | case PACKET3_COND_EXEC: | |
2772 | case PACKET3_PRED_EXEC: | |
2773 | case PACKET3_CONTEXT_CONTROL: | |
2774 | case PACKET3_STRMOUT_BUFFER_UPDATE: | |
2775 | case PACKET3_WAIT_REG_MEM: | |
2776 | case PACKET3_MEM_WRITE: | |
2777 | case PACKET3_PFP_SYNC_ME: | |
2778 | case PACKET3_SURFACE_SYNC: | |
2779 | case PACKET3_EVENT_WRITE: | |
2780 | case PACKET3_EVENT_WRITE_EOP: | |
2781 | case PACKET3_EVENT_WRITE_EOS: | |
2782 | case PACKET3_SET_CONTEXT_REG: | |
2783 | case PACKET3_SET_CONTEXT_REG_INDIRECT: | |
2784 | case PACKET3_SET_SH_REG: | |
2785 | case PACKET3_SET_SH_REG_OFFSET: | |
2786 | case PACKET3_INCREMENT_DE_COUNTER: | |
2787 | case PACKET3_WAIT_ON_CE_COUNTER: | |
2788 | case PACKET3_WAIT_ON_AVAIL_BUFFER: | |
2789 | case PACKET3_ME_WRITE: | |
2790 | break; | |
2791 | case PACKET3_COPY_DATA: | |
2792 | if ((idx_value & 0xf00) == 0) { | |
2793 | reg = ib[idx + 3] * 4; | |
2794 | if (!si_vm_reg_valid(reg)) | |
2795 | return -EINVAL; | |
2796 | } | |
2797 | break; | |
2798 | case PACKET3_WRITE_DATA: | |
2799 | if ((idx_value & 0xf00) == 0) { | |
2800 | start_reg = ib[idx + 1] * 4; | |
2801 | if (idx_value & 0x10000) { | |
2802 | if (!si_vm_reg_valid(start_reg)) | |
2803 | return -EINVAL; | |
2804 | } else { | |
2805 | for (i = 0; i < (pkt->count - 2); i++) { | |
2806 | reg = start_reg + (4 * i); | |
2807 | if (!si_vm_reg_valid(reg)) | |
2808 | return -EINVAL; | |
2809 | } | |
2810 | } | |
2811 | } | |
2812 | break; | |
2813 | case PACKET3_COND_WRITE: | |
2814 | if (idx_value & 0x100) { | |
2815 | reg = ib[idx + 5] * 4; | |
2816 | if (!si_vm_reg_valid(reg)) | |
2817 | return -EINVAL; | |
2818 | } | |
2819 | break; | |
2820 | case PACKET3_COPY_DW: | |
2821 | if (idx_value & 0x2) { | |
2822 | reg = ib[idx + 3] * 4; | |
2823 | if (!si_vm_reg_valid(reg)) | |
2824 | return -EINVAL; | |
2825 | } | |
2826 | break; | |
2827 | default: | |
2828 | DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode); | |
2829 | return -EINVAL; | |
2830 | } | |
2831 | return 0; | |
2832 | } | |
2833 | ||
2834 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) | |
2835 | { | |
2836 | int ret = 0; | |
2837 | u32 idx = 0; | |
2838 | struct radeon_cs_packet pkt; | |
2839 | ||
2840 | do { | |
2841 | pkt.idx = idx; | |
2842 | pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); | |
2843 | pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); | |
2844 | pkt.one_reg_wr = 0; | |
2845 | switch (pkt.type) { | |
2846 | case PACKET_TYPE0: | |
2847 | dev_err(rdev->dev, "Packet0 not allowed!\n"); | |
2848 | ret = -EINVAL; | |
2849 | break; | |
2850 | case PACKET_TYPE2: | |
2851 | idx += 1; | |
2852 | break; | |
2853 | case PACKET_TYPE3: | |
2854 | pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); | |
2855 | if (ib->is_const_ib) | |
2856 | ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt); | |
2857 | else { | |
2858 | switch (ib->fence->ring) { | |
2859 | case RADEON_RING_TYPE_GFX_INDEX: | |
2860 | ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt); | |
2861 | break; | |
2862 | case CAYMAN_RING_TYPE_CP1_INDEX: | |
2863 | case CAYMAN_RING_TYPE_CP2_INDEX: | |
2864 | ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt); | |
2865 | break; | |
2866 | default: | |
2867 | dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->fence->ring); | |
2868 | ret = -EINVAL; | |
2869 | break; | |
2870 | } | |
2871 | } | |
2872 | idx += pkt.count + 2; | |
2873 | break; | |
2874 | default: | |
2875 | dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); | |
2876 | ret = -EINVAL; | |
2877 | break; | |
2878 | } | |
2879 | if (ret) | |
2880 | break; | |
2881 | } while (idx < ib->length_dw); | |
2882 | ||
2883 | return ret; | |
2884 | } | |
2885 | ||
d2800ee5 AD |
2886 | /* |
2887 | * vm | |
2888 | */ | |
2889 | int si_vm_init(struct radeon_device *rdev) | |
2890 | { | |
2891 | /* number of VMs */ | |
2892 | rdev->vm_manager.nvm = 16; | |
2893 | /* base offset of vram pages */ | |
2894 | rdev->vm_manager.vram_base_offset = 0; | |
2895 | ||
2896 | return 0; | |
2897 | } | |
2898 | ||
2899 | void si_vm_fini(struct radeon_device *rdev) | |
2900 | { | |
2901 | } | |
2902 | ||
2903 | int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id) | |
2904 | { | |
2905 | if (id < 8) | |
2906 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12); | |
2907 | else | |
2908 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((id - 8) << 2), | |
2909 | vm->pt_gpu_addr >> 12); | |
2910 | /* flush hdp cache */ | |
2911 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
2912 | /* bits 0-15 are the VM contexts0-15 */ | |
2913 | WREG32(VM_INVALIDATE_REQUEST, 1 << id); | |
2914 | return 0; | |
2915 | } | |
2916 | ||
2917 | void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm) | |
2918 | { | |
2919 | if (vm->id < 8) | |
2920 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0); | |
2921 | else | |
2922 | WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2), 0); | |
2923 | /* flush hdp cache */ | |
2924 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
2925 | /* bits 0-15 are the VM contexts0-15 */ | |
2926 | WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id); | |
2927 | } | |
2928 | ||
2929 | void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm) | |
2930 | { | |
2931 | if (vm->id == -1) | |
2932 | return; | |
2933 | ||
2934 | /* flush hdp cache */ | |
2935 | WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
2936 | /* bits 0-15 are the VM contexts0-15 */ | |
2937 | WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id); | |
2938 | } | |
2939 | ||
347e7592 AD |
2940 | /* |
2941 | * RLC | |
2942 | */ | |
c420c745 | 2943 | void si_rlc_fini(struct radeon_device *rdev) |
347e7592 AD |
2944 | { |
2945 | int r; | |
2946 | ||
2947 | /* save restore block */ | |
2948 | if (rdev->rlc.save_restore_obj) { | |
2949 | r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); | |
2950 | if (unlikely(r != 0)) | |
2951 | dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r); | |
2952 | radeon_bo_unpin(rdev->rlc.save_restore_obj); | |
2953 | radeon_bo_unreserve(rdev->rlc.save_restore_obj); | |
2954 | ||
2955 | radeon_bo_unref(&rdev->rlc.save_restore_obj); | |
2956 | rdev->rlc.save_restore_obj = NULL; | |
2957 | } | |
2958 | ||
2959 | /* clear state block */ | |
2960 | if (rdev->rlc.clear_state_obj) { | |
2961 | r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); | |
2962 | if (unlikely(r != 0)) | |
2963 | dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); | |
2964 | radeon_bo_unpin(rdev->rlc.clear_state_obj); | |
2965 | radeon_bo_unreserve(rdev->rlc.clear_state_obj); | |
2966 | ||
2967 | radeon_bo_unref(&rdev->rlc.clear_state_obj); | |
2968 | rdev->rlc.clear_state_obj = NULL; | |
2969 | } | |
2970 | } | |
2971 | ||
c420c745 | 2972 | int si_rlc_init(struct radeon_device *rdev) |
347e7592 AD |
2973 | { |
2974 | int r; | |
2975 | ||
2976 | /* save restore block */ | |
2977 | if (rdev->rlc.save_restore_obj == NULL) { | |
2978 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, | |
40f5cf99 AD |
2979 | RADEON_GEM_DOMAIN_VRAM, NULL, |
2980 | &rdev->rlc.save_restore_obj); | |
347e7592 AD |
2981 | if (r) { |
2982 | dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); | |
2983 | return r; | |
2984 | } | |
2985 | } | |
2986 | ||
2987 | r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); | |
2988 | if (unlikely(r != 0)) { | |
2989 | si_rlc_fini(rdev); | |
2990 | return r; | |
2991 | } | |
2992 | r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, | |
2993 | &rdev->rlc.save_restore_gpu_addr); | |
5273db70 | 2994 | radeon_bo_unreserve(rdev->rlc.save_restore_obj); |
347e7592 | 2995 | if (r) { |
347e7592 AD |
2996 | dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); |
2997 | si_rlc_fini(rdev); | |
2998 | return r; | |
2999 | } | |
3000 | ||
3001 | /* clear state block */ | |
3002 | if (rdev->rlc.clear_state_obj == NULL) { | |
3003 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, | |
40f5cf99 AD |
3004 | RADEON_GEM_DOMAIN_VRAM, NULL, |
3005 | &rdev->rlc.clear_state_obj); | |
347e7592 AD |
3006 | if (r) { |
3007 | dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); | |
3008 | si_rlc_fini(rdev); | |
3009 | return r; | |
3010 | } | |
3011 | } | |
3012 | r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); | |
3013 | if (unlikely(r != 0)) { | |
3014 | si_rlc_fini(rdev); | |
3015 | return r; | |
3016 | } | |
3017 | r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, | |
3018 | &rdev->rlc.clear_state_gpu_addr); | |
5273db70 | 3019 | radeon_bo_unreserve(rdev->rlc.clear_state_obj); |
347e7592 | 3020 | if (r) { |
347e7592 AD |
3021 | dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); |
3022 | si_rlc_fini(rdev); | |
3023 | return r; | |
3024 | } | |
3025 | ||
3026 | return 0; | |
3027 | } | |
3028 | ||
3029 | static void si_rlc_stop(struct radeon_device *rdev) | |
3030 | { | |
3031 | WREG32(RLC_CNTL, 0); | |
3032 | } | |
3033 | ||
3034 | static void si_rlc_start(struct radeon_device *rdev) | |
3035 | { | |
3036 | WREG32(RLC_CNTL, RLC_ENABLE); | |
3037 | } | |
3038 | ||
3039 | static int si_rlc_resume(struct radeon_device *rdev) | |
3040 | { | |
3041 | u32 i; | |
3042 | const __be32 *fw_data; | |
3043 | ||
3044 | if (!rdev->rlc_fw) | |
3045 | return -EINVAL; | |
3046 | ||
3047 | si_rlc_stop(rdev); | |
3048 | ||
3049 | WREG32(RLC_RL_BASE, 0); | |
3050 | WREG32(RLC_RL_SIZE, 0); | |
3051 | WREG32(RLC_LB_CNTL, 0); | |
3052 | WREG32(RLC_LB_CNTR_MAX, 0xffffffff); | |
3053 | WREG32(RLC_LB_CNTR_INIT, 0); | |
3054 | ||
3055 | WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); | |
3056 | WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); | |
3057 | ||
3058 | WREG32(RLC_MC_CNTL, 0); | |
3059 | WREG32(RLC_UCODE_CNTL, 0); | |
3060 | ||
3061 | fw_data = (const __be32 *)rdev->rlc_fw->data; | |
3062 | for (i = 0; i < SI_RLC_UCODE_SIZE; i++) { | |
3063 | WREG32(RLC_UCODE_ADDR, i); | |
3064 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
3065 | } | |
3066 | WREG32(RLC_UCODE_ADDR, 0); | |
3067 | ||
3068 | si_rlc_start(rdev); | |
3069 | ||
3070 | return 0; | |
3071 | } | |
3072 | ||
25a857fb AD |
3073 | static void si_enable_interrupts(struct radeon_device *rdev) |
3074 | { | |
3075 | u32 ih_cntl = RREG32(IH_CNTL); | |
3076 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
3077 | ||
3078 | ih_cntl |= ENABLE_INTR; | |
3079 | ih_rb_cntl |= IH_RB_ENABLE; | |
3080 | WREG32(IH_CNTL, ih_cntl); | |
3081 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3082 | rdev->ih.enabled = true; | |
3083 | } | |
3084 | ||
3085 | static void si_disable_interrupts(struct radeon_device *rdev) | |
3086 | { | |
3087 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
3088 | u32 ih_cntl = RREG32(IH_CNTL); | |
3089 | ||
3090 | ih_rb_cntl &= ~IH_RB_ENABLE; | |
3091 | ih_cntl &= ~ENABLE_INTR; | |
3092 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3093 | WREG32(IH_CNTL, ih_cntl); | |
3094 | /* set rptr, wptr to 0 */ | |
3095 | WREG32(IH_RB_RPTR, 0); | |
3096 | WREG32(IH_RB_WPTR, 0); | |
3097 | rdev->ih.enabled = false; | |
3098 | rdev->ih.wptr = 0; | |
3099 | rdev->ih.rptr = 0; | |
3100 | } | |
3101 | ||
3102 | static void si_disable_interrupt_state(struct radeon_device *rdev) | |
3103 | { | |
3104 | u32 tmp; | |
3105 | ||
3106 | WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); | |
3107 | WREG32(CP_INT_CNTL_RING1, 0); | |
3108 | WREG32(CP_INT_CNTL_RING2, 0); | |
3109 | WREG32(GRBM_INT_CNTL, 0); | |
3110 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
3111 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
3112 | if (rdev->num_crtc >= 4) { | |
3113 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | |
3114 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
3115 | } | |
3116 | if (rdev->num_crtc >= 6) { | |
3117 | WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); | |
3118 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
3119 | } | |
3120 | ||
3121 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | |
3122 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | |
3123 | if (rdev->num_crtc >= 4) { | |
3124 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | |
3125 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | |
3126 | } | |
3127 | if (rdev->num_crtc >= 6) { | |
3128 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); | |
3129 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | |
3130 | } | |
3131 | ||
3132 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
3133 | ||
3134 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3135 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
3136 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3137 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
3138 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3139 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
3140 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3141 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
3142 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3143 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
3144 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3145 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
3146 | ||
3147 | } | |
3148 | ||
3149 | static int si_irq_init(struct radeon_device *rdev) | |
3150 | { | |
3151 | int ret = 0; | |
3152 | int rb_bufsz; | |
3153 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; | |
3154 | ||
3155 | /* allocate ring */ | |
3156 | ret = r600_ih_ring_alloc(rdev); | |
3157 | if (ret) | |
3158 | return ret; | |
3159 | ||
3160 | /* disable irqs */ | |
3161 | si_disable_interrupts(rdev); | |
3162 | ||
3163 | /* init rlc */ | |
3164 | ret = si_rlc_resume(rdev); | |
3165 | if (ret) { | |
3166 | r600_ih_ring_fini(rdev); | |
3167 | return ret; | |
3168 | } | |
3169 | ||
3170 | /* setup interrupt control */ | |
3171 | /* set dummy read address to ring address */ | |
3172 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); | |
3173 | interrupt_cntl = RREG32(INTERRUPT_CNTL); | |
3174 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi | |
3175 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN | |
3176 | */ | |
3177 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; | |
3178 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ | |
3179 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; | |
3180 | WREG32(INTERRUPT_CNTL, interrupt_cntl); | |
3181 | ||
3182 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); | |
3183 | rb_bufsz = drm_order(rdev->ih.ring_size / 4); | |
3184 | ||
3185 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | | |
3186 | IH_WPTR_OVERFLOW_CLEAR | | |
3187 | (rb_bufsz << 1)); | |
3188 | ||
3189 | if (rdev->wb.enabled) | |
3190 | ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; | |
3191 | ||
3192 | /* set the writeback address whether it's enabled or not */ | |
3193 | WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); | |
3194 | WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); | |
3195 | ||
3196 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3197 | ||
3198 | /* set rptr, wptr to 0 */ | |
3199 | WREG32(IH_RB_RPTR, 0); | |
3200 | WREG32(IH_RB_WPTR, 0); | |
3201 | ||
3202 | /* Default settings for IH_CNTL (disabled at first) */ | |
3203 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); | |
3204 | /* RPTR_REARM only works if msi's are enabled */ | |
3205 | if (rdev->msi_enabled) | |
3206 | ih_cntl |= RPTR_REARM; | |
3207 | WREG32(IH_CNTL, ih_cntl); | |
3208 | ||
3209 | /* force the active interrupt state to all disabled */ | |
3210 | si_disable_interrupt_state(rdev); | |
3211 | ||
2099810f DA |
3212 | pci_set_master(rdev->pdev); |
3213 | ||
25a857fb AD |
3214 | /* enable irqs */ |
3215 | si_enable_interrupts(rdev); | |
3216 | ||
3217 | return ret; | |
3218 | } | |
3219 | ||
3220 | int si_irq_set(struct radeon_device *rdev) | |
3221 | { | |
3222 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; | |
3223 | u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; | |
3224 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; | |
3225 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; | |
3226 | u32 grbm_int_cntl = 0; | |
3227 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; | |
3228 | ||
3229 | if (!rdev->irq.installed) { | |
3230 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); | |
3231 | return -EINVAL; | |
3232 | } | |
3233 | /* don't enable anything if the ih is disabled */ | |
3234 | if (!rdev->ih.enabled) { | |
3235 | si_disable_interrupts(rdev); | |
3236 | /* force the active interrupt state to all disabled */ | |
3237 | si_disable_interrupt_state(rdev); | |
3238 | return 0; | |
3239 | } | |
3240 | ||
3241 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3242 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3243 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3244 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3245 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3246 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3247 | ||
3248 | /* enable CP interrupts on all rings */ | |
3249 | if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { | |
3250 | DRM_DEBUG("si_irq_set: sw int gfx\n"); | |
3251 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; | |
3252 | } | |
3253 | if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) { | |
3254 | DRM_DEBUG("si_irq_set: sw int cp1\n"); | |
3255 | cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; | |
3256 | } | |
3257 | if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) { | |
3258 | DRM_DEBUG("si_irq_set: sw int cp2\n"); | |
3259 | cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; | |
3260 | } | |
3261 | if (rdev->irq.crtc_vblank_int[0] || | |
3262 | rdev->irq.pflip[0]) { | |
3263 | DRM_DEBUG("si_irq_set: vblank 0\n"); | |
3264 | crtc1 |= VBLANK_INT_MASK; | |
3265 | } | |
3266 | if (rdev->irq.crtc_vblank_int[1] || | |
3267 | rdev->irq.pflip[1]) { | |
3268 | DRM_DEBUG("si_irq_set: vblank 1\n"); | |
3269 | crtc2 |= VBLANK_INT_MASK; | |
3270 | } | |
3271 | if (rdev->irq.crtc_vblank_int[2] || | |
3272 | rdev->irq.pflip[2]) { | |
3273 | DRM_DEBUG("si_irq_set: vblank 2\n"); | |
3274 | crtc3 |= VBLANK_INT_MASK; | |
3275 | } | |
3276 | if (rdev->irq.crtc_vblank_int[3] || | |
3277 | rdev->irq.pflip[3]) { | |
3278 | DRM_DEBUG("si_irq_set: vblank 3\n"); | |
3279 | crtc4 |= VBLANK_INT_MASK; | |
3280 | } | |
3281 | if (rdev->irq.crtc_vblank_int[4] || | |
3282 | rdev->irq.pflip[4]) { | |
3283 | DRM_DEBUG("si_irq_set: vblank 4\n"); | |
3284 | crtc5 |= VBLANK_INT_MASK; | |
3285 | } | |
3286 | if (rdev->irq.crtc_vblank_int[5] || | |
3287 | rdev->irq.pflip[5]) { | |
3288 | DRM_DEBUG("si_irq_set: vblank 5\n"); | |
3289 | crtc6 |= VBLANK_INT_MASK; | |
3290 | } | |
3291 | if (rdev->irq.hpd[0]) { | |
3292 | DRM_DEBUG("si_irq_set: hpd 1\n"); | |
3293 | hpd1 |= DC_HPDx_INT_EN; | |
3294 | } | |
3295 | if (rdev->irq.hpd[1]) { | |
3296 | DRM_DEBUG("si_irq_set: hpd 2\n"); | |
3297 | hpd2 |= DC_HPDx_INT_EN; | |
3298 | } | |
3299 | if (rdev->irq.hpd[2]) { | |
3300 | DRM_DEBUG("si_irq_set: hpd 3\n"); | |
3301 | hpd3 |= DC_HPDx_INT_EN; | |
3302 | } | |
3303 | if (rdev->irq.hpd[3]) { | |
3304 | DRM_DEBUG("si_irq_set: hpd 4\n"); | |
3305 | hpd4 |= DC_HPDx_INT_EN; | |
3306 | } | |
3307 | if (rdev->irq.hpd[4]) { | |
3308 | DRM_DEBUG("si_irq_set: hpd 5\n"); | |
3309 | hpd5 |= DC_HPDx_INT_EN; | |
3310 | } | |
3311 | if (rdev->irq.hpd[5]) { | |
3312 | DRM_DEBUG("si_irq_set: hpd 6\n"); | |
3313 | hpd6 |= DC_HPDx_INT_EN; | |
3314 | } | |
3315 | if (rdev->irq.gui_idle) { | |
3316 | DRM_DEBUG("gui idle\n"); | |
3317 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; | |
3318 | } | |
3319 | ||
3320 | WREG32(CP_INT_CNTL_RING0, cp_int_cntl); | |
3321 | WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); | |
3322 | WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); | |
3323 | ||
3324 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); | |
3325 | ||
3326 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); | |
3327 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); | |
3328 | if (rdev->num_crtc >= 4) { | |
3329 | WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); | |
3330 | WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); | |
3331 | } | |
3332 | if (rdev->num_crtc >= 6) { | |
3333 | WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); | |
3334 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); | |
3335 | } | |
3336 | ||
3337 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); | |
3338 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); | |
3339 | if (rdev->num_crtc >= 4) { | |
3340 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); | |
3341 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); | |
3342 | } | |
3343 | if (rdev->num_crtc >= 6) { | |
3344 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); | |
3345 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); | |
3346 | } | |
3347 | ||
3348 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | |
3349 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
3350 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
3351 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
3352 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
3353 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
3354 | ||
3355 | return 0; | |
3356 | } | |
3357 | ||
3358 | static inline void si_irq_ack(struct radeon_device *rdev) | |
3359 | { | |
3360 | u32 tmp; | |
3361 | ||
3362 | rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); | |
3363 | rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
3364 | rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); | |
3365 | rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); | |
3366 | rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); | |
3367 | rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); | |
3368 | rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); | |
3369 | rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); | |
3370 | if (rdev->num_crtc >= 4) { | |
3371 | rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); | |
3372 | rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); | |
3373 | } | |
3374 | if (rdev->num_crtc >= 6) { | |
3375 | rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); | |
3376 | rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); | |
3377 | } | |
3378 | ||
3379 | if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) | |
3380 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
3381 | if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) | |
3382 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
3383 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) | |
3384 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); | |
3385 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) | |
3386 | WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); | |
3387 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) | |
3388 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); | |
3389 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) | |
3390 | WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); | |
3391 | ||
3392 | if (rdev->num_crtc >= 4) { | |
3393 | if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) | |
3394 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
3395 | if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) | |
3396 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
3397 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) | |
3398 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); | |
3399 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) | |
3400 | WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); | |
3401 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) | |
3402 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); | |
3403 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) | |
3404 | WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); | |
3405 | } | |
3406 | ||
3407 | if (rdev->num_crtc >= 6) { | |
3408 | if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) | |
3409 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
3410 | if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) | |
3411 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | |
3412 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) | |
3413 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); | |
3414 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) | |
3415 | WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); | |
3416 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) | |
3417 | WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); | |
3418 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) | |
3419 | WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); | |
3420 | } | |
3421 | ||
3422 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { | |
3423 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
3424 | tmp |= DC_HPDx_INT_ACK; | |
3425 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
3426 | } | |
3427 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { | |
3428 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
3429 | tmp |= DC_HPDx_INT_ACK; | |
3430 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
3431 | } | |
3432 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { | |
3433 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
3434 | tmp |= DC_HPDx_INT_ACK; | |
3435 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
3436 | } | |
3437 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { | |
3438 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
3439 | tmp |= DC_HPDx_INT_ACK; | |
3440 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
3441 | } | |
3442 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { | |
3443 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
3444 | tmp |= DC_HPDx_INT_ACK; | |
3445 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
3446 | } | |
3447 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { | |
3448 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
3449 | tmp |= DC_HPDx_INT_ACK; | |
3450 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
3451 | } | |
3452 | } | |
3453 | ||
3454 | static void si_irq_disable(struct radeon_device *rdev) | |
3455 | { | |
3456 | si_disable_interrupts(rdev); | |
3457 | /* Wait and acknowledge irq */ | |
3458 | mdelay(1); | |
3459 | si_irq_ack(rdev); | |
3460 | si_disable_interrupt_state(rdev); | |
3461 | } | |
3462 | ||
3463 | static void si_irq_suspend(struct radeon_device *rdev) | |
3464 | { | |
3465 | si_irq_disable(rdev); | |
3466 | si_rlc_stop(rdev); | |
3467 | } | |
3468 | ||
9b136d51 AD |
3469 | static void si_irq_fini(struct radeon_device *rdev) |
3470 | { | |
3471 | si_irq_suspend(rdev); | |
3472 | r600_ih_ring_fini(rdev); | |
3473 | } | |
3474 | ||
25a857fb AD |
3475 | static inline u32 si_get_ih_wptr(struct radeon_device *rdev) |
3476 | { | |
3477 | u32 wptr, tmp; | |
3478 | ||
3479 | if (rdev->wb.enabled) | |
3480 | wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); | |
3481 | else | |
3482 | wptr = RREG32(IH_RB_WPTR); | |
3483 | ||
3484 | if (wptr & RB_OVERFLOW) { | |
3485 | /* When a ring buffer overflow happen start parsing interrupt | |
3486 | * from the last not overwritten vector (wptr + 16). Hopefully | |
3487 | * this should allow us to catchup. | |
3488 | */ | |
3489 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", | |
3490 | wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); | |
3491 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; | |
3492 | tmp = RREG32(IH_RB_CNTL); | |
3493 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
3494 | WREG32(IH_RB_CNTL, tmp); | |
3495 | } | |
3496 | return (wptr & rdev->ih.ptr_mask); | |
3497 | } | |
3498 | ||
3499 | /* SI IV Ring | |
3500 | * Each IV ring entry is 128 bits: | |
3501 | * [7:0] - interrupt source id | |
3502 | * [31:8] - reserved | |
3503 | * [59:32] - interrupt source data | |
3504 | * [63:60] - reserved | |
3505 | * [71:64] - RINGID | |
3506 | * [79:72] - VMID | |
3507 | * [127:80] - reserved | |
3508 | */ | |
3509 | int si_irq_process(struct radeon_device *rdev) | |
3510 | { | |
3511 | u32 wptr; | |
3512 | u32 rptr; | |
3513 | u32 src_id, src_data, ring_id; | |
3514 | u32 ring_index; | |
3515 | unsigned long flags; | |
3516 | bool queue_hotplug = false; | |
3517 | ||
3518 | if (!rdev->ih.enabled || rdev->shutdown) | |
3519 | return IRQ_NONE; | |
3520 | ||
3521 | wptr = si_get_ih_wptr(rdev); | |
3522 | rptr = rdev->ih.rptr; | |
3523 | DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
3524 | ||
3525 | spin_lock_irqsave(&rdev->ih.lock, flags); | |
3526 | if (rptr == wptr) { | |
3527 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
3528 | return IRQ_NONE; | |
3529 | } | |
3530 | restart_ih: | |
3531 | /* Order reading of wptr vs. reading of IH ring data */ | |
3532 | rmb(); | |
3533 | ||
3534 | /* display interrupts */ | |
3535 | si_irq_ack(rdev); | |
3536 | ||
3537 | rdev->ih.wptr = wptr; | |
3538 | while (rptr != wptr) { | |
3539 | /* wptr/rptr are in bytes! */ | |
3540 | ring_index = rptr / 4; | |
3541 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; | |
3542 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; | |
3543 | ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; | |
3544 | ||
3545 | switch (src_id) { | |
3546 | case 1: /* D1 vblank/vline */ | |
3547 | switch (src_data) { | |
3548 | case 0: /* D1 vblank */ | |
3549 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { | |
3550 | if (rdev->irq.crtc_vblank_int[0]) { | |
3551 | drm_handle_vblank(rdev->ddev, 0); | |
3552 | rdev->pm.vblank_sync = true; | |
3553 | wake_up(&rdev->irq.vblank_queue); | |
3554 | } | |
3555 | if (rdev->irq.pflip[0]) | |
3556 | radeon_crtc_handle_flip(rdev, 0); | |
3557 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; | |
3558 | DRM_DEBUG("IH: D1 vblank\n"); | |
3559 | } | |
3560 | break; | |
3561 | case 1: /* D1 vline */ | |
3562 | if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { | |
3563 | rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
3564 | DRM_DEBUG("IH: D1 vline\n"); | |
3565 | } | |
3566 | break; | |
3567 | default: | |
3568 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3569 | break; | |
3570 | } | |
3571 | break; | |
3572 | case 2: /* D2 vblank/vline */ | |
3573 | switch (src_data) { | |
3574 | case 0: /* D2 vblank */ | |
3575 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { | |
3576 | if (rdev->irq.crtc_vblank_int[1]) { | |
3577 | drm_handle_vblank(rdev->ddev, 1); | |
3578 | rdev->pm.vblank_sync = true; | |
3579 | wake_up(&rdev->irq.vblank_queue); | |
3580 | } | |
3581 | if (rdev->irq.pflip[1]) | |
3582 | radeon_crtc_handle_flip(rdev, 1); | |
3583 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; | |
3584 | DRM_DEBUG("IH: D2 vblank\n"); | |
3585 | } | |
3586 | break; | |
3587 | case 1: /* D2 vline */ | |
3588 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { | |
3589 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; | |
3590 | DRM_DEBUG("IH: D2 vline\n"); | |
3591 | } | |
3592 | break; | |
3593 | default: | |
3594 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3595 | break; | |
3596 | } | |
3597 | break; | |
3598 | case 3: /* D3 vblank/vline */ | |
3599 | switch (src_data) { | |
3600 | case 0: /* D3 vblank */ | |
3601 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { | |
3602 | if (rdev->irq.crtc_vblank_int[2]) { | |
3603 | drm_handle_vblank(rdev->ddev, 2); | |
3604 | rdev->pm.vblank_sync = true; | |
3605 | wake_up(&rdev->irq.vblank_queue); | |
3606 | } | |
3607 | if (rdev->irq.pflip[2]) | |
3608 | radeon_crtc_handle_flip(rdev, 2); | |
3609 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; | |
3610 | DRM_DEBUG("IH: D3 vblank\n"); | |
3611 | } | |
3612 | break; | |
3613 | case 1: /* D3 vline */ | |
3614 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { | |
3615 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; | |
3616 | DRM_DEBUG("IH: D3 vline\n"); | |
3617 | } | |
3618 | break; | |
3619 | default: | |
3620 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3621 | break; | |
3622 | } | |
3623 | break; | |
3624 | case 4: /* D4 vblank/vline */ | |
3625 | switch (src_data) { | |
3626 | case 0: /* D4 vblank */ | |
3627 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { | |
3628 | if (rdev->irq.crtc_vblank_int[3]) { | |
3629 | drm_handle_vblank(rdev->ddev, 3); | |
3630 | rdev->pm.vblank_sync = true; | |
3631 | wake_up(&rdev->irq.vblank_queue); | |
3632 | } | |
3633 | if (rdev->irq.pflip[3]) | |
3634 | radeon_crtc_handle_flip(rdev, 3); | |
3635 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; | |
3636 | DRM_DEBUG("IH: D4 vblank\n"); | |
3637 | } | |
3638 | break; | |
3639 | case 1: /* D4 vline */ | |
3640 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { | |
3641 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; | |
3642 | DRM_DEBUG("IH: D4 vline\n"); | |
3643 | } | |
3644 | break; | |
3645 | default: | |
3646 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3647 | break; | |
3648 | } | |
3649 | break; | |
3650 | case 5: /* D5 vblank/vline */ | |
3651 | switch (src_data) { | |
3652 | case 0: /* D5 vblank */ | |
3653 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { | |
3654 | if (rdev->irq.crtc_vblank_int[4]) { | |
3655 | drm_handle_vblank(rdev->ddev, 4); | |
3656 | rdev->pm.vblank_sync = true; | |
3657 | wake_up(&rdev->irq.vblank_queue); | |
3658 | } | |
3659 | if (rdev->irq.pflip[4]) | |
3660 | radeon_crtc_handle_flip(rdev, 4); | |
3661 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; | |
3662 | DRM_DEBUG("IH: D5 vblank\n"); | |
3663 | } | |
3664 | break; | |
3665 | case 1: /* D5 vline */ | |
3666 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { | |
3667 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; | |
3668 | DRM_DEBUG("IH: D5 vline\n"); | |
3669 | } | |
3670 | break; | |
3671 | default: | |
3672 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3673 | break; | |
3674 | } | |
3675 | break; | |
3676 | case 6: /* D6 vblank/vline */ | |
3677 | switch (src_data) { | |
3678 | case 0: /* D6 vblank */ | |
3679 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { | |
3680 | if (rdev->irq.crtc_vblank_int[5]) { | |
3681 | drm_handle_vblank(rdev->ddev, 5); | |
3682 | rdev->pm.vblank_sync = true; | |
3683 | wake_up(&rdev->irq.vblank_queue); | |
3684 | } | |
3685 | if (rdev->irq.pflip[5]) | |
3686 | radeon_crtc_handle_flip(rdev, 5); | |
3687 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; | |
3688 | DRM_DEBUG("IH: D6 vblank\n"); | |
3689 | } | |
3690 | break; | |
3691 | case 1: /* D6 vline */ | |
3692 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { | |
3693 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; | |
3694 | DRM_DEBUG("IH: D6 vline\n"); | |
3695 | } | |
3696 | break; | |
3697 | default: | |
3698 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3699 | break; | |
3700 | } | |
3701 | break; | |
3702 | case 42: /* HPD hotplug */ | |
3703 | switch (src_data) { | |
3704 | case 0: | |
3705 | if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { | |
3706 | rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; | |
3707 | queue_hotplug = true; | |
3708 | DRM_DEBUG("IH: HPD1\n"); | |
3709 | } | |
3710 | break; | |
3711 | case 1: | |
3712 | if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { | |
3713 | rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; | |
3714 | queue_hotplug = true; | |
3715 | DRM_DEBUG("IH: HPD2\n"); | |
3716 | } | |
3717 | break; | |
3718 | case 2: | |
3719 | if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { | |
3720 | rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; | |
3721 | queue_hotplug = true; | |
3722 | DRM_DEBUG("IH: HPD3\n"); | |
3723 | } | |
3724 | break; | |
3725 | case 3: | |
3726 | if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { | |
3727 | rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; | |
3728 | queue_hotplug = true; | |
3729 | DRM_DEBUG("IH: HPD4\n"); | |
3730 | } | |
3731 | break; | |
3732 | case 4: | |
3733 | if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { | |
3734 | rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; | |
3735 | queue_hotplug = true; | |
3736 | DRM_DEBUG("IH: HPD5\n"); | |
3737 | } | |
3738 | break; | |
3739 | case 5: | |
3740 | if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { | |
3741 | rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; | |
3742 | queue_hotplug = true; | |
3743 | DRM_DEBUG("IH: HPD6\n"); | |
3744 | } | |
3745 | break; | |
3746 | default: | |
3747 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3748 | break; | |
3749 | } | |
3750 | break; | |
3751 | case 176: /* RINGID0 CP_INT */ | |
3752 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); | |
3753 | break; | |
3754 | case 177: /* RINGID1 CP_INT */ | |
3755 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); | |
3756 | break; | |
3757 | case 178: /* RINGID2 CP_INT */ | |
3758 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); | |
3759 | break; | |
3760 | case 181: /* CP EOP event */ | |
3761 | DRM_DEBUG("IH: CP EOP\n"); | |
3762 | switch (ring_id) { | |
3763 | case 0: | |
3764 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); | |
3765 | break; | |
3766 | case 1: | |
3767 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); | |
3768 | break; | |
3769 | case 2: | |
3770 | radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); | |
3771 | break; | |
3772 | } | |
3773 | break; | |
3774 | case 233: /* GUI IDLE */ | |
3775 | DRM_DEBUG("IH: GUI idle\n"); | |
3776 | rdev->pm.gui_idle = true; | |
3777 | wake_up(&rdev->irq.idle_queue); | |
3778 | break; | |
3779 | default: | |
3780 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); | |
3781 | break; | |
3782 | } | |
3783 | ||
3784 | /* wptr/rptr are in bytes! */ | |
3785 | rptr += 16; | |
3786 | rptr &= rdev->ih.ptr_mask; | |
3787 | } | |
3788 | /* make sure wptr hasn't changed while processing */ | |
3789 | wptr = si_get_ih_wptr(rdev); | |
3790 | if (wptr != rdev->ih.wptr) | |
3791 | goto restart_ih; | |
3792 | if (queue_hotplug) | |
3793 | schedule_work(&rdev->hotplug_work); | |
3794 | rdev->ih.rptr = rptr; | |
3795 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
3796 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
3797 | return IRQ_HANDLED; | |
3798 | } | |
3799 | ||
9b136d51 AD |
3800 | /* |
3801 | * startup/shutdown callbacks | |
3802 | */ | |
3803 | static int si_startup(struct radeon_device *rdev) | |
3804 | { | |
3805 | struct radeon_ring *ring; | |
3806 | int r; | |
3807 | ||
3808 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || | |
3809 | !rdev->rlc_fw || !rdev->mc_fw) { | |
3810 | r = si_init_microcode(rdev); | |
3811 | if (r) { | |
3812 | DRM_ERROR("Failed to load firmware!\n"); | |
3813 | return r; | |
3814 | } | |
3815 | } | |
3816 | ||
3817 | r = si_mc_load_microcode(rdev); | |
3818 | if (r) { | |
3819 | DRM_ERROR("Failed to load MC firmware!\n"); | |
3820 | return r; | |
3821 | } | |
3822 | ||
3823 | r = r600_vram_scratch_init(rdev); | |
3824 | if (r) | |
3825 | return r; | |
3826 | ||
3827 | si_mc_program(rdev); | |
3828 | r = si_pcie_gart_enable(rdev); | |
3829 | if (r) | |
3830 | return r; | |
3831 | si_gpu_init(rdev); | |
3832 | ||
3833 | #if 0 | |
3834 | r = evergreen_blit_init(rdev); | |
3835 | if (r) { | |
3836 | r600_blit_fini(rdev); | |
3837 | rdev->asic->copy = NULL; | |
3838 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); | |
3839 | } | |
3840 | #endif | |
3841 | /* allocate rlc buffers */ | |
3842 | r = si_rlc_init(rdev); | |
3843 | if (r) { | |
3844 | DRM_ERROR("Failed to init rlc BOs!\n"); | |
3845 | return r; | |
3846 | } | |
3847 | ||
3848 | /* allocate wb buffer */ | |
3849 | r = radeon_wb_init(rdev); | |
3850 | if (r) | |
3851 | return r; | |
3852 | ||
3853 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); | |
3854 | if (r) { | |
3855 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
3856 | return r; | |
3857 | } | |
3858 | ||
3859 | r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); | |
3860 | if (r) { | |
3861 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
3862 | return r; | |
3863 | } | |
3864 | ||
3865 | r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); | |
3866 | if (r) { | |
3867 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
3868 | return r; | |
3869 | } | |
3870 | ||
3871 | /* Enable IRQ */ | |
3872 | r = si_irq_init(rdev); | |
3873 | if (r) { | |
3874 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
3875 | radeon_irq_kms_fini(rdev); | |
3876 | return r; | |
3877 | } | |
3878 | si_irq_set(rdev); | |
3879 | ||
3880 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | |
3881 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, | |
3882 | CP_RB0_RPTR, CP_RB0_WPTR, | |
3883 | 0, 0xfffff, RADEON_CP_PACKET2); | |
3884 | if (r) | |
3885 | return r; | |
3886 | ||
3887 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; | |
3888 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, | |
3889 | CP_RB1_RPTR, CP_RB1_WPTR, | |
3890 | 0, 0xfffff, RADEON_CP_PACKET2); | |
3891 | if (r) | |
3892 | return r; | |
3893 | ||
3894 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; | |
3895 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, | |
3896 | CP_RB2_RPTR, CP_RB2_WPTR, | |
3897 | 0, 0xfffff, RADEON_CP_PACKET2); | |
3898 | if (r) | |
3899 | return r; | |
3900 | ||
3901 | r = si_cp_load_microcode(rdev); | |
3902 | if (r) | |
3903 | return r; | |
3904 | r = si_cp_resume(rdev); | |
3905 | if (r) | |
3906 | return r; | |
3907 | ||
3908 | r = radeon_ib_pool_start(rdev); | |
3909 | if (r) | |
3910 | return r; | |
3911 | ||
3912 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); | |
3913 | if (r) { | |
3914 | DRM_ERROR("radeon: failed testing IB (%d) on CP ring 0\n", r); | |
3915 | rdev->accel_working = false; | |
3916 | return r; | |
3917 | } | |
3918 | ||
3919 | r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); | |
3920 | if (r) { | |
3921 | DRM_ERROR("radeon: failed testing IB (%d) on CP ring 1\n", r); | |
3922 | rdev->accel_working = false; | |
3923 | return r; | |
3924 | } | |
3925 | ||
3926 | r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); | |
3927 | if (r) { | |
3928 | DRM_ERROR("radeon: failed testing IB (%d) on CP ring 2\n", r); | |
3929 | rdev->accel_working = false; | |
3930 | return r; | |
3931 | } | |
3932 | ||
3933 | r = radeon_vm_manager_start(rdev); | |
3934 | if (r) | |
3935 | return r; | |
3936 | ||
3937 | return 0; | |
3938 | } | |
3939 | ||
3940 | int si_resume(struct radeon_device *rdev) | |
3941 | { | |
3942 | int r; | |
3943 | ||
3944 | /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, | |
3945 | * posting will perform necessary task to bring back GPU into good | |
3946 | * shape. | |
3947 | */ | |
3948 | /* post card */ | |
3949 | atom_asic_init(rdev->mode_info.atom_context); | |
3950 | ||
3951 | rdev->accel_working = true; | |
3952 | r = si_startup(rdev); | |
3953 | if (r) { | |
3954 | DRM_ERROR("si startup failed on resume\n"); | |
3955 | rdev->accel_working = false; | |
3956 | return r; | |
3957 | } | |
3958 | ||
3959 | return r; | |
3960 | ||
3961 | } | |
3962 | ||
3963 | int si_suspend(struct radeon_device *rdev) | |
3964 | { | |
3965 | /* FIXME: we should wait for ring to be empty */ | |
3966 | radeon_ib_pool_suspend(rdev); | |
3967 | radeon_vm_manager_suspend(rdev); | |
3968 | #if 0 | |
3969 | r600_blit_suspend(rdev); | |
3970 | #endif | |
3971 | si_cp_enable(rdev, false); | |
3972 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; | |
3973 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; | |
3974 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; | |
3975 | si_irq_suspend(rdev); | |
3976 | radeon_wb_disable(rdev); | |
3977 | si_pcie_gart_disable(rdev); | |
3978 | return 0; | |
3979 | } | |
3980 | ||
3981 | /* Plan is to move initialization in that function and use | |
3982 | * helper function so that radeon_device_init pretty much | |
3983 | * do nothing more than calling asic specific function. This | |
3984 | * should also allow to remove a bunch of callback function | |
3985 | * like vram_info. | |
3986 | */ | |
3987 | int si_init(struct radeon_device *rdev) | |
3988 | { | |
3989 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | |
3990 | int r; | |
3991 | ||
9b136d51 AD |
3992 | /* Read BIOS */ |
3993 | if (!radeon_get_bios(rdev)) { | |
3994 | if (ASIC_IS_AVIVO(rdev)) | |
3995 | return -EINVAL; | |
3996 | } | |
3997 | /* Must be an ATOMBIOS */ | |
3998 | if (!rdev->is_atom_bios) { | |
3999 | dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); | |
4000 | return -EINVAL; | |
4001 | } | |
4002 | r = radeon_atombios_init(rdev); | |
4003 | if (r) | |
4004 | return r; | |
4005 | ||
4006 | /* Post card if necessary */ | |
4007 | if (!radeon_card_posted(rdev)) { | |
4008 | if (!rdev->bios) { | |
4009 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
4010 | return -EINVAL; | |
4011 | } | |
4012 | DRM_INFO("GPU not posted. posting now...\n"); | |
4013 | atom_asic_init(rdev->mode_info.atom_context); | |
4014 | } | |
4015 | /* Initialize scratch registers */ | |
4016 | si_scratch_init(rdev); | |
4017 | /* Initialize surface registers */ | |
4018 | radeon_surface_init(rdev); | |
4019 | /* Initialize clocks */ | |
4020 | radeon_get_clock_info(rdev->ddev); | |
4021 | ||
4022 | /* Fence driver */ | |
4023 | r = radeon_fence_driver_init(rdev); | |
4024 | if (r) | |
4025 | return r; | |
4026 | ||
4027 | /* initialize memory controller */ | |
4028 | r = si_mc_init(rdev); | |
4029 | if (r) | |
4030 | return r; | |
4031 | /* Memory manager */ | |
4032 | r = radeon_bo_init(rdev); | |
4033 | if (r) | |
4034 | return r; | |
4035 | ||
4036 | r = radeon_irq_kms_init(rdev); | |
4037 | if (r) | |
4038 | return r; | |
4039 | ||
4040 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | |
4041 | ring->ring_obj = NULL; | |
4042 | r600_ring_init(rdev, ring, 1024 * 1024); | |
4043 | ||
4044 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; | |
4045 | ring->ring_obj = NULL; | |
4046 | r600_ring_init(rdev, ring, 1024 * 1024); | |
4047 | ||
4048 | ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; | |
4049 | ring->ring_obj = NULL; | |
4050 | r600_ring_init(rdev, ring, 1024 * 1024); | |
4051 | ||
4052 | rdev->ih.ring_obj = NULL; | |
4053 | r600_ih_ring_init(rdev, 64 * 1024); | |
4054 | ||
4055 | r = r600_pcie_gart_init(rdev); | |
4056 | if (r) | |
4057 | return r; | |
4058 | ||
4059 | r = radeon_ib_pool_init(rdev); | |
4060 | rdev->accel_working = true; | |
4061 | if (r) { | |
4062 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
4063 | rdev->accel_working = false; | |
4064 | } | |
4065 | r = radeon_vm_manager_init(rdev); | |
4066 | if (r) { | |
4067 | dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); | |
4068 | } | |
4069 | ||
4070 | r = si_startup(rdev); | |
4071 | if (r) { | |
4072 | dev_err(rdev->dev, "disabling GPU acceleration\n"); | |
4073 | si_cp_fini(rdev); | |
4074 | si_irq_fini(rdev); | |
4075 | si_rlc_fini(rdev); | |
4076 | radeon_wb_fini(rdev); | |
4077 | r100_ib_fini(rdev); | |
4078 | radeon_vm_manager_fini(rdev); | |
4079 | radeon_irq_kms_fini(rdev); | |
4080 | si_pcie_gart_fini(rdev); | |
4081 | rdev->accel_working = false; | |
4082 | } | |
4083 | ||
4084 | /* Don't start up if the MC ucode is missing. | |
4085 | * The default clocks and voltages before the MC ucode | |
4086 | * is loaded are not suffient for advanced operations. | |
4087 | */ | |
4088 | if (!rdev->mc_fw) { | |
4089 | DRM_ERROR("radeon: MC ucode required for NI+.\n"); | |
4090 | return -EINVAL; | |
4091 | } | |
4092 | ||
4093 | return 0; | |
4094 | } | |
4095 | ||
4096 | void si_fini(struct radeon_device *rdev) | |
4097 | { | |
4098 | #if 0 | |
4099 | r600_blit_fini(rdev); | |
4100 | #endif | |
4101 | si_cp_fini(rdev); | |
4102 | si_irq_fini(rdev); | |
4103 | si_rlc_fini(rdev); | |
4104 | radeon_wb_fini(rdev); | |
4105 | radeon_vm_manager_fini(rdev); | |
4106 | r100_ib_fini(rdev); | |
4107 | radeon_irq_kms_fini(rdev); | |
4108 | si_pcie_gart_fini(rdev); | |
4109 | r600_vram_scratch_fini(rdev); | |
4110 | radeon_gem_fini(rdev); | |
9b136d51 AD |
4111 | radeon_fence_driver_fini(rdev); |
4112 | radeon_bo_fini(rdev); | |
4113 | radeon_atombios_fini(rdev); | |
4114 | kfree(rdev->bios); | |
4115 | rdev->bios = NULL; | |
4116 | } | |
4117 |