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drm/radeon: fall back to GTT if bo creation/validation in VRAM fails.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / rv770.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
3ce0a23d
JG		 28#include <linux/firmware.h>
29#include <linux/platform_device.h>
5a0e3ad6 30#include <linux/slab.h>
771fe6b9 31#include "drmP.h"
771fe6b9 32#include "radeon.h"
e6990375 33#include "radeon_asic.h"
4153e584 34#include "radeon_drm.h"
3ce0a23d 35#include "rv770d.h"
3ce0a23d 36#include "atom.h"
d39c3b89 37#include "avivod.h"
771fe6b9 38
3ce0a23d
JG		 39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
771fe6b9 41
3ce0a23d
JG		 42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev);
771fe6b9 44
21a8122a
AD		 45/* get temperature in millidegrees */
46u32 rv770_get_temp(struct radeon_device *rdev)
47{
48 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
49 ASIC_T_SHIFT;
50 u32 actual_temp = 0;
51
52 if ((temp >> 9) & 1)
53 actual_temp = 0;
54 else
55 actual_temp = (temp >> 1) & 0xff;
56
57 return actual_temp * 1000;
58}
59
49e02b73
AD		 60void rv770_pm_misc(struct radeon_device *rdev)
61{
a081a9d6
RM		 62 int req_ps_idx = rdev->pm.requested_power_state_index;
63 int req_cm_idx = rdev->pm.requested_clock_mode_index;
64 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
65 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
4d60173f
AD		 66
67 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
68 if (voltage->voltage != rdev->pm.current_vddc) {
69 radeon_atom_set_voltage(rdev, voltage->voltage);
70 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 71 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 72 }
73 }
49e02b73 74}
771fe6b9
JG		 75
76/*
3ce0a23d 77 * GART
771fe6b9 78 */
3ce0a23d 79int rv770_pcie_gart_enable(struct radeon_device *rdev)
771fe6b9 80{
3ce0a23d
JG		 81 u32 tmp;
82 int r, i;
771fe6b9 83
4aac0473
JG		 84 if (rdev->gart.table.vram.robj == NULL) {
85 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
86 return -EINVAL;
3ce0a23d 87 }
4aac0473
JG		 88 r = radeon_gart_table_vram_pin(rdev);
89 if (r)
3ce0a23d 90 return r;
82568565 91 radeon_gart_restore(rdev);
3ce0a23d
JG		 92 /* Setup L2 cache */
93 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
94 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
95 EFFECTIVE_L2_QUEUE_SIZE(7));
96 WREG32(VM_L2_CNTL2, 0);
97 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
98 /* Setup TLB control */
99 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
100 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
101 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
102 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
103 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
104 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
105 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
106 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
107 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
108 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
109 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
110 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 111 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 112 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
113 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
114 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
115 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
116 (u32)(rdev->dummy_page.addr >> 12));
117 for (i = 1; i < 7; i++)
118 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 119
3ce0a23d
JG		 120 r600_pcie_gart_tlb_flush(rdev);
121 rdev->gart.ready = true;
771fe6b9
JG		 122 return 0;
123}
124
3ce0a23d 125void rv770_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 126{
3ce0a23d 127 u32 tmp;
4c788679 128 int i, r;
3ce0a23d 129
3ce0a23d
JG		 130 /* Disable all tables */
131 for (i = 0; i < 7; i++)
132 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
133
134 /* Setup L2 cache */
135 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
136 EFFECTIVE_L2_QUEUE_SIZE(7));
137 WREG32(VM_L2_CNTL2, 0);
138 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
139 /* Setup TLB control */
140 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
141 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
142 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
143 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
144 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
145 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
146 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
147 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
4aac0473 148 if (rdev->gart.table.vram.robj) {
4c788679
JG		 149 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
150 if (likely(r == 0)) {
151 radeon_bo_kunmap(rdev->gart.table.vram.robj);
152 radeon_bo_unpin(rdev->gart.table.vram.robj);
153 radeon_bo_unreserve(rdev->gart.table.vram.robj);
154 }
4aac0473
JG		 155 }
156}
157
158void rv770_pcie_gart_fini(struct radeon_device *rdev)
159{
f9274562 160 radeon_gart_fini(rdev);
4aac0473
JG		 161 rv770_pcie_gart_disable(rdev);
162 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 163}
164
165
1a029b76
JG		 166void rv770_agp_enable(struct radeon_device *rdev)
167{
168 u32 tmp;
169 int i;
170
171 /* Setup L2 cache */
172 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
173 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
174 EFFECTIVE_L2_QUEUE_SIZE(7));
175 WREG32(VM_L2_CNTL2, 0);
176 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
177 /* Setup TLB control */
178 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
179 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
180 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
181 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
182 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
183 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
184 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
185 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
186 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
187 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
188 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
189 for (i = 0; i < 7; i++)
190 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
191}
192
a3c1945a 193static void rv770_mc_program(struct radeon_device *rdev)
771fe6b9 194{
a3c1945a 195 struct rv515_mc_save save;
3ce0a23d
JG		 196 u32 tmp;
197 int i, j;
198
199 /* Initialize HDP */
200 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
201 WREG32((0x2c14 + j), 0x00000000);
202 WREG32((0x2c18 + j), 0x00000000);
203 WREG32((0x2c1c + j), 0x00000000);
204 WREG32((0x2c20 + j), 0x00000000);
205 WREG32((0x2c24 + j), 0x00000000);
206 }
207 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
208
a3c1945a 209 rv515_mc_stop(rdev, &save);
3ce0a23d 210 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 211 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 212 }
3ce0a23d
JG		 213 /* Lockout access through VGA aperture*/
214 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 215 /* Update configuration */
1a029b76
JG		 216 if (rdev->flags & RADEON_IS_AGP) {
217 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
218 /* VRAM before AGP */
219 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
220 rdev->mc.vram_start >> 12);
221 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
222 rdev->mc.gtt_end >> 12);
223 } else {
224 /* VRAM after AGP */
225 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
226 rdev->mc.gtt_start >> 12);
227 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
228 rdev->mc.vram_end >> 12);
229 }
230 } else {
231 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
232 rdev->mc.vram_start >> 12);
233 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
234 rdev->mc.vram_end >> 12);
235 }
3ce0a23d 236 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 237 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 238 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
239 WREG32(MC_VM_FB_LOCATION, tmp);
240 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
241 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 242 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 243 if (rdev->flags & RADEON_IS_AGP) {
1a029b76 244 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
3ce0a23d
JG		 245 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
246 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
247 } else {
248 WREG32(MC_VM_AGP_BASE, 0);
249 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
250 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
251 }
3ce0a23d 252 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 253 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 254 }
a3c1945a 255 rv515_mc_resume(rdev, &save);
698443d9
DA		 256 /* we need to own VRAM, so turn off the VGA renderer here
257 * to stop it overwriting our objects */
d39c3b89 258 rv515_vga_render_disable(rdev);
771fe6b9
JG		 259}
260
3ce0a23d
JG		 261
262/*
263 * CP.
264 */
265void r700_cp_stop(struct radeon_device *rdev)
771fe6b9 266{
3ce0a23d 267 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
771fe6b9
JG		 268}
269
3ce0a23d 270static int rv770_cp_load_microcode(struct radeon_device *rdev)
771fe6b9 271{
3ce0a23d
JG		 272 const __be32 *fw_data;
273 int i;
274
275 if (!rdev->me_fw || !rdev->pfp_fw)
276 return -EINVAL;
277
278 r700_cp_stop(rdev);
279 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
280
281 /* Reset cp */
282 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
283 RREG32(GRBM_SOFT_RESET);
284 mdelay(15);
285 WREG32(GRBM_SOFT_RESET, 0);
286
287 fw_data = (const __be32 *)rdev->pfp_fw->data;
288 WREG32(CP_PFP_UCODE_ADDR, 0);
289 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
290 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
291 WREG32(CP_PFP_UCODE_ADDR, 0);
292
293 fw_data = (const __be32 *)rdev->me_fw->data;
294 WREG32(CP_ME_RAM_WADDR, 0);
295 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
296 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
297
298 WREG32(CP_PFP_UCODE_ADDR, 0);
299 WREG32(CP_ME_RAM_WADDR, 0);
300 WREG32(CP_ME_RAM_RADDR, 0);
301 return 0;
771fe6b9
JG		 302}
303
fe251e2f
AD		 304void r700_cp_fini(struct radeon_device *rdev)
305{
306 r700_cp_stop(rdev);
307 radeon_ring_fini(rdev);
308}
771fe6b9
JG		 309
310/*
3ce0a23d 311 * Core functions
771fe6b9 312 */
d03f5d59
AD		 313static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
314 u32 num_tile_pipes,
315 u32 num_backends,
316 u32 backend_disable_mask)
771fe6b9 317{
3ce0a23d
JG		 318 u32 backend_map = 0;
319 u32 enabled_backends_mask;
320 u32 enabled_backends_count;
321 u32 cur_pipe;
322 u32 swizzle_pipe[R7XX_MAX_PIPES];
323 u32 cur_backend;
324 u32 i;
d03f5d59 325 bool force_no_swizzle;
3ce0a23d
JG		 326
327 if (num_tile_pipes > R7XX_MAX_PIPES)
328 num_tile_pipes = R7XX_MAX_PIPES;
329 if (num_tile_pipes < 1)
330 num_tile_pipes = 1;
331 if (num_backends > R7XX_MAX_BACKENDS)
332 num_backends = R7XX_MAX_BACKENDS;
333 if (num_backends < 1)
334 num_backends = 1;
335
336 enabled_backends_mask = 0;
337 enabled_backends_count = 0;
338 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
339 if (((backend_disable_mask >> i) & 1) == 0) {
340 enabled_backends_mask |= (1 << i);
341 ++enabled_backends_count;
342 }
343 if (enabled_backends_count == num_backends)
344 break;
345 }
346
347 if (enabled_backends_count == 0) {
348 enabled_backends_mask = 1;
349 enabled_backends_count = 1;
350 }
351
352 if (enabled_backends_count != num_backends)
353 num_backends = enabled_backends_count;
354
d03f5d59
AD		 355 switch (rdev->family) {
356 case CHIP_RV770:
357 case CHIP_RV730:
358 force_no_swizzle = false;
359 break;
360 case CHIP_RV710:
361 case CHIP_RV740:
362 default:
363 force_no_swizzle = true;
364 break;
365 }
366
3ce0a23d
JG		 367 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
368 switch (num_tile_pipes) {
369 case 1:
370 swizzle_pipe[0] = 0;
371 break;
372 case 2:
373 swizzle_pipe[0] = 0;
374 swizzle_pipe[1] = 1;
375 break;
376 case 3:
d03f5d59
AD		 377 if (force_no_swizzle) {
378 swizzle_pipe[0] = 0;
379 swizzle_pipe[1] = 1;
380 swizzle_pipe[2] = 2;
381 } else {
382 swizzle_pipe[0] = 0;
383 swizzle_pipe[1] = 2;
384 swizzle_pipe[2] = 1;
385 }
3ce0a23d
JG		 386 break;
387 case 4:
d03f5d59
AD		 388 if (force_no_swizzle) {
389 swizzle_pipe[0] = 0;
390 swizzle_pipe[1] = 1;
391 swizzle_pipe[2] = 2;
392 swizzle_pipe[3] = 3;
393 } else {
394 swizzle_pipe[0] = 0;
395 swizzle_pipe[1] = 2;
396 swizzle_pipe[2] = 3;
397 swizzle_pipe[3] = 1;
398 }
3ce0a23d
JG		 399 break;
400 case 5:
d03f5d59
AD		 401 if (force_no_swizzle) {
402 swizzle_pipe[0] = 0;
403 swizzle_pipe[1] = 1;
404 swizzle_pipe[2] = 2;
405 swizzle_pipe[3] = 3;
406 swizzle_pipe[4] = 4;
407 } else {
408 swizzle_pipe[0] = 0;
409 swizzle_pipe[1] = 2;
410 swizzle_pipe[2] = 4;
411 swizzle_pipe[3] = 1;
412 swizzle_pipe[4] = 3;
413 }
3ce0a23d
JG		 414 break;
415 case 6:
d03f5d59
AD		 416 if (force_no_swizzle) {
417 swizzle_pipe[0] = 0;
418 swizzle_pipe[1] = 1;
419 swizzle_pipe[2] = 2;
420 swizzle_pipe[3] = 3;
421 swizzle_pipe[4] = 4;
422 swizzle_pipe[5] = 5;
423 } else {
424 swizzle_pipe[0] = 0;
425 swizzle_pipe[1] = 2;
426 swizzle_pipe[2] = 4;
427 swizzle_pipe[3] = 5;
428 swizzle_pipe[4] = 3;
429 swizzle_pipe[5] = 1;
430 }
3ce0a23d
JG		 431 break;
432 case 7:
d03f5d59
AD		 433 if (force_no_swizzle) {
434 swizzle_pipe[0] = 0;
435 swizzle_pipe[1] = 1;
436 swizzle_pipe[2] = 2;
437 swizzle_pipe[3] = 3;
438 swizzle_pipe[4] = 4;
439 swizzle_pipe[5] = 5;
440 swizzle_pipe[6] = 6;
441 } else {
442 swizzle_pipe[0] = 0;
443 swizzle_pipe[1] = 2;
444 swizzle_pipe[2] = 4;
445 swizzle_pipe[3] = 6;
446 swizzle_pipe[4] = 3;
447 swizzle_pipe[5] = 1;
448 swizzle_pipe[6] = 5;
449 }
3ce0a23d
JG		 450 break;
451 case 8:
d03f5d59
AD		 452 if (force_no_swizzle) {
453 swizzle_pipe[0] = 0;
454 swizzle_pipe[1] = 1;
455 swizzle_pipe[2] = 2;
456 swizzle_pipe[3] = 3;
457 swizzle_pipe[4] = 4;
458 swizzle_pipe[5] = 5;
459 swizzle_pipe[6] = 6;
460 swizzle_pipe[7] = 7;
461 } else {
462 swizzle_pipe[0] = 0;
463 swizzle_pipe[1] = 2;
464 swizzle_pipe[2] = 4;
465 swizzle_pipe[3] = 6;
466 swizzle_pipe[4] = 3;
467 swizzle_pipe[5] = 1;
468 swizzle_pipe[6] = 7;
469 swizzle_pipe[7] = 5;
470 }
3ce0a23d
JG		 471 break;
472 }
473
474 cur_backend = 0;
475 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
476 while (((1 << cur_backend) & enabled_backends_mask) == 0)
477 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
478
479 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
480
481 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
482 }
483
484 return backend_map;
771fe6b9
JG		 485}
486
3ce0a23d 487static void rv770_gpu_init(struct radeon_device *rdev)
771fe6b9 488{
3ce0a23d 489 int i, j, num_qd_pipes;
d03f5d59 490 u32 ta_aux_cntl;
3ce0a23d
JG		 491 u32 sx_debug_1;
492 u32 smx_dc_ctl0;
d03f5d59 493 u32 db_debug3;
3ce0a23d
JG		 494 u32 num_gs_verts_per_thread;
495 u32 vgt_gs_per_es;
496 u32 gs_prim_buffer_depth = 0;
497 u32 sq_ms_fifo_sizes;
498 u32 sq_config;
499 u32 sq_thread_resource_mgmt;
500 u32 hdp_host_path_cntl;
501 u32 sq_dyn_gpr_size_simd_ab_0;
502 u32 backend_map;
503 u32 gb_tiling_config = 0;
504 u32 cc_rb_backend_disable = 0;
505 u32 cc_gc_shader_pipe_config = 0;
506 u32 mc_arb_ramcfg;
507 u32 db_debug4;
771fe6b9 508
3ce0a23d
JG		 509 /* setup chip specs */
510 switch (rdev->family) {
511 case CHIP_RV770:
512 rdev->config.rv770.max_pipes = 4;
513 rdev->config.rv770.max_tile_pipes = 8;
514 rdev->config.rv770.max_simds = 10;
515 rdev->config.rv770.max_backends = 4;
516 rdev->config.rv770.max_gprs = 256;
517 rdev->config.rv770.max_threads = 248;
518 rdev->config.rv770.max_stack_entries = 512;
519 rdev->config.rv770.max_hw_contexts = 8;
520 rdev->config.rv770.max_gs_threads = 16 * 2;
521 rdev->config.rv770.sx_max_export_size = 128;
522 rdev->config.rv770.sx_max_export_pos_size = 16;
523 rdev->config.rv770.sx_max_export_smx_size = 112;
524 rdev->config.rv770.sq_num_cf_insts = 2;
525
526 rdev->config.rv770.sx_num_of_sets = 7;
527 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
528 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
529 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
530 break;
531 case CHIP_RV730:
532 rdev->config.rv770.max_pipes = 2;
533 rdev->config.rv770.max_tile_pipes = 4;
534 rdev->config.rv770.max_simds = 8;
535 rdev->config.rv770.max_backends = 2;
536 rdev->config.rv770.max_gprs = 128;
537 rdev->config.rv770.max_threads = 248;
538 rdev->config.rv770.max_stack_entries = 256;
539 rdev->config.rv770.max_hw_contexts = 8;
540 rdev->config.rv770.max_gs_threads = 16 * 2;
541 rdev->config.rv770.sx_max_export_size = 256;
542 rdev->config.rv770.sx_max_export_pos_size = 32;
543 rdev->config.rv770.sx_max_export_smx_size = 224;
544 rdev->config.rv770.sq_num_cf_insts = 2;
545
546 rdev->config.rv770.sx_num_of_sets = 7;
547 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
548 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
549 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
550 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
551 rdev->config.rv770.sx_max_export_pos_size -= 16;
552 rdev->config.rv770.sx_max_export_smx_size += 16;
553 }
554 break;
555 case CHIP_RV710:
556 rdev->config.rv770.max_pipes = 2;
557 rdev->config.rv770.max_tile_pipes = 2;
558 rdev->config.rv770.max_simds = 2;
559 rdev->config.rv770.max_backends = 1;
560 rdev->config.rv770.max_gprs = 256;
561 rdev->config.rv770.max_threads = 192;
562 rdev->config.rv770.max_stack_entries = 256;
563 rdev->config.rv770.max_hw_contexts = 4;
564 rdev->config.rv770.max_gs_threads = 8 * 2;
565 rdev->config.rv770.sx_max_export_size = 128;
566 rdev->config.rv770.sx_max_export_pos_size = 16;
567 rdev->config.rv770.sx_max_export_smx_size = 112;
568 rdev->config.rv770.sq_num_cf_insts = 1;
569
570 rdev->config.rv770.sx_num_of_sets = 7;
571 rdev->config.rv770.sc_prim_fifo_size = 0x40;
572 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
573 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
574 break;
575 case CHIP_RV740:
576 rdev->config.rv770.max_pipes = 4;
577 rdev->config.rv770.max_tile_pipes = 4;
578 rdev->config.rv770.max_simds = 8;
579 rdev->config.rv770.max_backends = 4;
580 rdev->config.rv770.max_gprs = 256;
581 rdev->config.rv770.max_threads = 248;
582 rdev->config.rv770.max_stack_entries = 512;
583 rdev->config.rv770.max_hw_contexts = 8;
584 rdev->config.rv770.max_gs_threads = 16 * 2;
585 rdev->config.rv770.sx_max_export_size = 256;
586 rdev->config.rv770.sx_max_export_pos_size = 32;
587 rdev->config.rv770.sx_max_export_smx_size = 224;
588 rdev->config.rv770.sq_num_cf_insts = 2;
589
590 rdev->config.rv770.sx_num_of_sets = 7;
591 rdev->config.rv770.sc_prim_fifo_size = 0x100;
592 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
593 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
594
595 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
596 rdev->config.rv770.sx_max_export_pos_size -= 16;
597 rdev->config.rv770.sx_max_export_smx_size += 16;
598 }
599 break;
600 default:
601 break;
602 }
603
604 /* Initialize HDP */
605 j = 0;
606 for (i = 0; i < 32; i++) {
607 WREG32((0x2c14 + j), 0x00000000);
608 WREG32((0x2c18 + j), 0x00000000);
609 WREG32((0x2c1c + j), 0x00000000);
610 WREG32((0x2c20 + j), 0x00000000);
611 WREG32((0x2c24 + j), 0x00000000);
612 j += 0x18;
613 }
614
615 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
616
617 /* setup tiling, simd, pipe config */
618 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
619
620 switch (rdev->config.rv770.max_tile_pipes) {
621 case 1:
d03f5d59 622 default:
3ce0a23d
JG		 623 gb_tiling_config |= PIPE_TILING(0);
624 break;
625 case 2:
626 gb_tiling_config |= PIPE_TILING(1);
627 break;
628 case 4:
629 gb_tiling_config |= PIPE_TILING(2);
630 break;
631 case 8:
632 gb_tiling_config |= PIPE_TILING(3);
3ce0a23d
JG		 633 break;
634 }
d03f5d59 635 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
3ce0a23d
JG		 636
637 if (rdev->family == CHIP_RV770)
638 gb_tiling_config |= BANK_TILING(1);
639 else
e29649db 640 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
961fb597 641 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
3ce0a23d
JG		 642
643 gb_tiling_config |= GROUP_SIZE(0);
961fb597 644 rdev->config.rv770.tiling_group_size = 256;
3ce0a23d 645
e29649db 646 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
3ce0a23d
JG		 647 gb_tiling_config |= ROW_TILING(3);
648 gb_tiling_config |= SAMPLE_SPLIT(3);
649 } else {
650 gb_tiling_config |=
651 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
652 gb_tiling_config |=
653 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
654 }
655
656 gb_tiling_config |= BANK_SWAPS(1);
657
d03f5d59
AD		 658 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
659 cc_rb_backend_disable |=
660 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
3ce0a23d 661
d03f5d59
AD		 662 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
663 cc_gc_shader_pipe_config |=
3ce0a23d
JG		 664 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
665 cc_gc_shader_pipe_config |=
666 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
667
d03f5d59
AD		 668 if (rdev->family == CHIP_RV740)
669 backend_map = 0x28;
670 else
671 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
672 rdev->config.rv770.max_tile_pipes,
673 (R7XX_MAX_BACKENDS -
674 r600_count_pipe_bits((cc_rb_backend_disable &
675 R7XX_MAX_BACKENDS_MASK) >> 16)),
676 (cc_rb_backend_disable >> 16));
d03f5d59 677
e7aeeba6
AD		 678 rdev->config.rv770.tile_config = gb_tiling_config;
679 gb_tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 680
681 WREG32(GB_TILING_CONFIG, gb_tiling_config);
682 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
683 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
684
685 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
686 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 687 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
d03f5d59 688 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
3ce0a23d 689
3ce0a23d
JG		 690 WREG32(CGTS_SYS_TCC_DISABLE, 0);
691 WREG32(CGTS_TCC_DISABLE, 0);
f867c60d
AD		 692 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
693 WREG32(CGTS_USER_TCC_DISABLE, 0);
3ce0a23d
JG		 694
695 num_qd_pipes =
d03f5d59 696 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 697 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
698 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
699
700 /* set HW defaults for 3D engine */
701 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
e29649db 702 ROQ_IB2_START(0x2b)));
3ce0a23d
JG		 703
704 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
705
d03f5d59
AD		 706 ta_aux_cntl = RREG32(TA_CNTL_AUX);
707 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
3ce0a23d
JG		 708
709 sx_debug_1 = RREG32(SX_DEBUG_1);
710 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
711 WREG32(SX_DEBUG_1, sx_debug_1);
712
713 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
714 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
715 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
716 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
717
d03f5d59
AD		 718 if (rdev->family != CHIP_RV740)
719 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
720 GS_FLUSH_CTL(4) |
721 ACK_FLUSH_CTL(3) |
722 SYNC_FLUSH_CTL));
3ce0a23d 723
d03f5d59
AD		 724 db_debug3 = RREG32(DB_DEBUG3);
725 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
726 switch (rdev->family) {
727 case CHIP_RV770:
728 case CHIP_RV740:
729 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
730 break;
731 case CHIP_RV710:
732 case CHIP_RV730:
733 default:
734 db_debug3 |= DB_CLK_OFF_DELAY(2);
735 break;
736 }
737 WREG32(DB_DEBUG3, db_debug3);
738
739 if (rdev->family != CHIP_RV770) {
3ce0a23d
JG		 740 db_debug4 = RREG32(DB_DEBUG4);
741 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
742 WREG32(DB_DEBUG4, db_debug4);
743 }
744
745 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
e29649db
AD		 746 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
747 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
3ce0a23d
JG		 748
749 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
e29649db
AD		 750 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
751 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
3ce0a23d
JG		 752
753 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
754
755 WREG32(VGT_NUM_INSTANCES, 1);
756
757 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
758
759 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
760
761 WREG32(CP_PERFMON_CNTL, 0);
762
763 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
764 DONE_FIFO_HIWATER(0xe0) |
765 ALU_UPDATE_FIFO_HIWATER(0x8));
766 switch (rdev->family) {
767 case CHIP_RV770:
3ce0a23d
JG		 768 case CHIP_RV730:
769 case CHIP_RV710:
d03f5d59
AD		 770 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
771 break;
3ce0a23d
JG		 772 case CHIP_RV740:
773 default:
774 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
775 break;
776 }
777 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
778
779 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
780 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
781 */
782 sq_config = RREG32(SQ_CONFIG);
783 sq_config &= ~(PS_PRIO(3) |
784 VS_PRIO(3) |
785 GS_PRIO(3) |
786 ES_PRIO(3));
787 sq_config |= (DX9_CONSTS |
788 VC_ENABLE |
789 EXPORT_SRC_C |
790 PS_PRIO(0) |
791 VS_PRIO(1) |
792 GS_PRIO(2) |
793 ES_PRIO(3));
794 if (rdev->family == CHIP_RV710)
795 /* no vertex cache */
796 sq_config &= ~VC_ENABLE;
797
798 WREG32(SQ_CONFIG, sq_config);
799
800 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
fe62e1a4
DA		 801 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
802 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
3ce0a23d
JG		 803
804 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
fe62e1a4 805 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
3ce0a23d
JG		 806
807 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
808 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
809 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
810 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
811 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
812 else
813 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
814 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
815
816 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
817 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
818
819 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
820 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
821
822 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
823 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
824 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
825 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
826
827 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
828 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
829 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
830 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
831 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
832 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
833 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
834 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
835
836 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
fe62e1a4 837 FORCE_EOV_MAX_REZ_CNT(255)));
3ce0a23d
JG		 838
839 if (rdev->family == CHIP_RV710)
840 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
fe62e1a4 841 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 842 else
843 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
fe62e1a4 844 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
3ce0a23d
JG		 845
846 switch (rdev->family) {
847 case CHIP_RV770:
848 case CHIP_RV730:
849 case CHIP_RV740:
850 gs_prim_buffer_depth = 384;
851 break;
852 case CHIP_RV710:
853 gs_prim_buffer_depth = 128;
854 break;
855 default:
856 break;
857 }
858
859 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
860 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
861 /* Max value for this is 256 */
862 if (vgt_gs_per_es > 256)
863 vgt_gs_per_es = 256;
864
865 WREG32(VGT_ES_PER_GS, 128);
866 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
867 WREG32(VGT_GS_PER_VS, 2);
868
869 /* more default values. 2D/3D driver should adjust as needed */
870 WREG32(VGT_GS_VERTEX_REUSE, 16);
871 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
872 WREG32(VGT_STRMOUT_EN, 0);
873 WREG32(SX_MISC, 0);
874 WREG32(PA_SC_MODE_CNTL, 0);
875 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
876 WREG32(PA_SC_AA_CONFIG, 0);
877 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
878 WREG32(PA_SC_LINE_STIPPLE, 0);
879 WREG32(SPI_INPUT_Z, 0);
880 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
881 WREG32(CB_COLOR7_FRAG, 0);
882
883 /* clear render buffer base addresses */
884 WREG32(CB_COLOR0_BASE, 0);
885 WREG32(CB_COLOR1_BASE, 0);
886 WREG32(CB_COLOR2_BASE, 0);
887 WREG32(CB_COLOR3_BASE, 0);
888 WREG32(CB_COLOR4_BASE, 0);
889 WREG32(CB_COLOR5_BASE, 0);
890 WREG32(CB_COLOR6_BASE, 0);
891 WREG32(CB_COLOR7_BASE, 0);
892
893 WREG32(TCP_CNTL, 0);
894
895 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
896 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
897
898 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
899
900 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
901 NUM_CLIP_SEQ(3)));
902
903}
904
905int rv770_mc_init(struct radeon_device *rdev)
906{
3ce0a23d 907 u32 tmp;
5885b7a9 908 int chansize, numchan;
3ce0a23d
JG		 909
910 /* Get VRAM informations */
3ce0a23d 911 rdev->mc.vram_is_ddr = true;
5885b7a9
AD		 912 tmp = RREG32(MC_ARB_RAMCFG);
913 if (tmp & CHANSIZE_OVERRIDE) {
914 chansize = 16;
915 } else if (tmp & CHANSIZE_MASK) {
916 chansize = 64;
917 } else {
918 chansize = 32;
919 }
920 tmp = RREG32(MC_SHARED_CHMAP);
921 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
922 case 0:
923 default:
924 numchan = 1;
925 break;
926 case 1:
927 numchan = 2;
928 break;
929 case 2:
930 numchan = 4;
931 break;
932 case 3:
933 numchan = 8;
934 break;
935 }
936 rdev->mc.vram_width = numchan * chansize;
771fe6b9 937 /* Could aper size report 0 ? */
01d73a69
JC		 938 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
939 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 940 /* Setup GPU memory space */
941 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
942 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 943 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 944 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 945 radeon_update_bandwidth_info(rdev);
946
3ce0a23d
JG		 947 return 0;
948}
d594e46a 949
fc30b8ef 950static int rv770_startup(struct radeon_device *rdev)
3ce0a23d
JG		 951{
952 int r;
953
779720a3
AD		 954 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
955 r = r600_init_microcode(rdev);
956 if (r) {
957 DRM_ERROR("Failed to load firmware!\n");
958 return r;
959 }
960 }
961
a3c1945a 962 rv770_mc_program(rdev);
1a029b76
JG		 963 if (rdev->flags & RADEON_IS_AGP) {
964 rv770_agp_enable(rdev);
965 } else {
966 r = rv770_pcie_gart_enable(rdev);
967 if (r)
968 return r;
969 }
3ce0a23d 970 rv770_gpu_init(rdev);
c38c7b64
JG		 971 r = r600_blit_init(rdev);
972 if (r) {
973 r600_blit_fini(rdev);
974 rdev->asic->copy = NULL;
975 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
976 }
ff82f052
JG		 977 /* pin copy shader into vram */
978 if (rdev->r600_blit.shader_obj) {
979 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
980 if (unlikely(r != 0))
981 return r;
982 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
983 &rdev->r600_blit.shader_gpu_addr);
984 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
7923c615 985 if (r) {
ff82f052 986 DRM_ERROR("failed to pin blit object %d\n", r);
7923c615
AD		 987 return r;
988 }
989 }
d8f60cfc 990 /* Enable IRQ */
d8f60cfc
AD		 991 r = r600_irq_init(rdev);
992 if (r) {
993 DRM_ERROR("radeon: IH init failed (%d).\n", r);
994 radeon_irq_kms_fini(rdev);
995 return r;
996 }
997 r600_irq_set(rdev);
998
3ce0a23d
JG		 999 r = radeon_ring_init(rdev, rdev->cp.ring_size);
1000 if (r)
1001 return r;
1002 r = rv770_cp_load_microcode(rdev);
1003 if (r)
1004 return r;
1005 r = r600_cp_resume(rdev);
1006 if (r)
1007 return r;
81cc35bf
JG		 1008 /* write back buffer are not vital so don't worry about failure */
1009 r600_wb_enable(rdev);
3ce0a23d
JG		 1010 return 0;
1011}
1012
fc30b8ef
DA		 1013int rv770_resume(struct radeon_device *rdev)
1014{
1015 int r;
1016
1a029b76
JG		 1017 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1018 * posting will perform necessary task to bring back GPU into good
1019 * shape.
1020 */
fc30b8ef 1021 /* post card */
e7d40b9a 1022 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 1023 /* Initialize clocks */
1024 r = radeon_clocks_init(rdev);
1025 if (r) {
1026 return r;
1027 }
1028
1029 r = rv770_startup(rdev);
1030 if (r) {
1031 DRM_ERROR("r600 startup failed on resume\n");
1032 return r;
1033 }
1034
62a8ea3f 1035 r = r600_ib_test(rdev);
fc30b8ef
DA		 1036 if (r) {
1037 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1038 return r;
1039 }
8a8c6e7c
RM		 1040
1041 r = r600_audio_init(rdev);
1042 if (r) {
1043 dev_err(rdev->dev, "radeon: audio init failed\n");
1044 return r;
1045 }
1046
fc30b8ef
DA		 1047 return r;
1048
1049}
1050
3ce0a23d
JG		 1051int rv770_suspend(struct radeon_device *rdev)
1052{
4c788679
JG		 1053 int r;
1054
8a8c6e7c 1055 r600_audio_fini(rdev);
3ce0a23d
JG		 1056 /* FIXME: we should wait for ring to be empty */
1057 r700_cp_stop(rdev);
4153e584 1058 rdev->cp.ready = false;
0c45249f 1059 r600_irq_suspend(rdev);
81cc35bf 1060 r600_wb_disable(rdev);
4aac0473 1061 rv770_pcie_gart_disable(rdev);
4153e584 1062 /* unpin shaders bo */
30d2d9a5
JG		 1063 if (rdev->r600_blit.shader_obj) {
1064 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1065 if (likely(r == 0)) {
1066 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1067 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1068 }
4c788679 1069 }
3ce0a23d
JG		 1070 return 0;
1071}
1072
1073/* Plan is to move initialization in that function and use
1074 * helper function so that radeon_device_init pretty much
1075 * do nothing more than calling asic specific function. This
1076 * should also allow to remove a bunch of callback function
1077 * like vram_info.
1078 */
1079int rv770_init(struct radeon_device *rdev)
1080{
1081 int r;
1082
3ce0a23d
JG		 1083 r = radeon_dummy_page_init(rdev);
1084 if (r)
1085 return r;
1086 /* This don't do much */
1087 r = radeon_gem_init(rdev);
1088 if (r)
1089 return r;
1090 /* Read BIOS */
1091 if (!radeon_get_bios(rdev)) {
1092 if (ASIC_IS_AVIVO(rdev))
1093 return -EINVAL;
1094 }
1095 /* Must be an ATOMBIOS */
e7d40b9a
JG		 1096 if (!rdev->is_atom_bios) {
1097 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 1098 return -EINVAL;
e7d40b9a 1099 }
3ce0a23d
JG		 1100 r = radeon_atombios_init(rdev);
1101 if (r)
1102 return r;
1103 /* Post card if necessary */
72542d77
DA		 1104 if (!r600_card_posted(rdev)) {
1105 if (!rdev->bios) {
1106 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1107 return -EINVAL;
1108 }
3ce0a23d
JG		 1109 DRM_INFO("GPU not posted. posting now...\n");
1110 atom_asic_init(rdev->mode_info.atom_context);
1111 }
1112 /* Initialize scratch registers */
1113 r600_scratch_init(rdev);
1114 /* Initialize surface registers */
1115 radeon_surface_init(rdev);
7433874e 1116 /* Initialize clocks */
5e6dde7e 1117 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 1118 r = radeon_clocks_init(rdev);
1119 if (r)
1120 return r;
1121 /* Fence driver */
1122 r = radeon_fence_driver_init(rdev);
1123 if (r)
1124 return r;
d594e46a 1125 /* initialize AGP */
700a0cc0
JG		 1126 if (rdev->flags & RADEON_IS_AGP) {
1127 r = radeon_agp_init(rdev);
1128 if (r)
1129 radeon_agp_disable(rdev);
1130 }
3ce0a23d 1131 r = rv770_mc_init(rdev);
b574f251 1132 if (r)
3ce0a23d 1133 return r;
3ce0a23d 1134 /* Memory manager */
4c788679 1135 r = radeon_bo_init(rdev);
3ce0a23d
JG		 1136 if (r)
1137 return r;
d8f60cfc
AD		 1138
1139 r = radeon_irq_kms_init(rdev);
1140 if (r)
1141 return r;
1142
3ce0a23d
JG		 1143 rdev->cp.ring_obj = NULL;
1144 r600_ring_init(rdev, 1024 * 1024);
1145
d8f60cfc
AD		 1146 rdev->ih.ring_obj = NULL;
1147 r600_ih_ring_init(rdev, 64 * 1024);
1148
4aac0473
JG		 1149 r = r600_pcie_gart_init(rdev);
1150 if (r)
1151 return r;
1152
779720a3 1153 rdev->accel_working = true;
fc30b8ef 1154 r = rv770_startup(rdev);
3ce0a23d 1155 if (r) {
655efd3d 1156 dev_err(rdev->dev, "disabling GPU acceleration\n");
fe251e2f 1157 r700_cp_fini(rdev);
75c81298 1158 r600_wb_fini(rdev);
655efd3d
JG		 1159 r600_irq_fini(rdev);
1160 radeon_irq_kms_fini(rdev);
75c81298 1161 rv770_pcie_gart_fini(rdev);
733289c2 1162 rdev->accel_working = false;
3ce0a23d 1163 }
733289c2 1164 if (rdev->accel_working) {
733289c2
JG		 1165 r = radeon_ib_pool_init(rdev);
1166 if (r) {
db96380e 1167 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 1168 rdev->accel_working = false;
db96380e
JG		 1169 } else {
1170 r = r600_ib_test(rdev);
1171 if (r) {
1172 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1173 rdev->accel_working = false;
1174 }
733289c2 1175 }
3ce0a23d 1176 }
8a8c6e7c
RM		 1177
1178 r = r600_audio_init(rdev);
1179 if (r) {
1180 dev_err(rdev->dev, "radeon: audio init failed\n");
1181 return r;
1182 }
1183
3ce0a23d
JG		 1184 return 0;
1185}
1186
1187void rv770_fini(struct radeon_device *rdev)
1188{
1189 r600_blit_fini(rdev);
fe251e2f 1190 r700_cp_fini(rdev);
655efd3d 1191 r600_wb_fini(rdev);
d8f60cfc
AD		 1192 r600_irq_fini(rdev);
1193 radeon_irq_kms_fini(rdev);
4aac0473 1194 rv770_pcie_gart_fini(rdev);
3ce0a23d
JG		 1195 radeon_gem_fini(rdev);
1196 radeon_fence_driver_fini(rdev);
1197 radeon_clocks_fini(rdev);
d0269ed8 1198 radeon_agp_fini(rdev);
4c788679 1199 radeon_bo_fini(rdev);
e7d40b9a 1200 radeon_atombios_fini(rdev);
3ce0a23d
JG		 1201 kfree(rdev->bios);
1202 rdev->bios = NULL;
1203 radeon_dummy_page_fini(rdev);
771fe6b9 1204}
kernel source for telekom puls (alcatel/mediatek)