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UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e 22 */
760285e7 23#include <drm/drmP.h>
7433874e 24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370
AD		 27#ifdef CONFIG_ACPI
28#include <linux/acpi.h>
29#endif
30#include <linux/power_supply.h>
21a8122a
AD		 31#include <linux/hwmon.h>
32#include <linux/hwmon-sysfs.h>
7433874e 33
c913e23a
RM		 34#define RADEON_IDLE_LOOP_MS 100
35#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 36#define RADEON_WAIT_VBLANK_TIMEOUT 200
c913e23a 37
f712d0c7
RM		 38static const char *radeon_pm_state_type_name[5] = {
39 "Default",
40 "Powersave",
41 "Battery",
42 "Balanced",
43 "Performance",
44};
45
ce8f5370 46static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 47static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 48static bool radeon_pm_in_vbl(struct radeon_device *rdev);
49static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
50static void radeon_pm_update_profile(struct radeon_device *rdev);
51static void radeon_pm_set_clocks(struct radeon_device *rdev);
52
53#define ACPI_AC_CLASS "ac_adapter"
54
a4c9e2ee
AD		 55int radeon_pm_get_type_index(struct radeon_device *rdev,
56 enum radeon_pm_state_type ps_type,
57 int instance)
58{
59 int i;
60 int found_instance = -1;
61
62 for (i = 0; i < rdev->pm.num_power_states; i++) {
63 if (rdev->pm.power_state[i].type == ps_type) {
64 found_instance++;
65 if (found_instance == instance)
66 return i;
67 }
68 }
69 /* return default if no match */
70 return rdev->pm.default_power_state_index;
71}
72
ce8f5370
AD		 73#ifdef CONFIG_ACPI
74static int radeon_acpi_event(struct notifier_block *nb,
75 unsigned long val,
76 void *data)
77{
78 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
79 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
80
81 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
82 if (power_supply_is_system_supplied() > 0)
d9fdaafb 83 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 84 else
d9fdaafb 85 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 86
87 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
88 if (rdev->pm.profile == PM_PROFILE_AUTO) {
89 mutex_lock(&rdev->pm.mutex);
90 radeon_pm_update_profile(rdev);
91 radeon_pm_set_clocks(rdev);
92 mutex_unlock(&rdev->pm.mutex);
93 }
94 }
95 }
96
97 return NOTIFY_OK;
98}
99#endif
100
101static void radeon_pm_update_profile(struct radeon_device *rdev)
102{
103 switch (rdev->pm.profile) {
104 case PM_PROFILE_DEFAULT:
105 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
106 break;
107 case PM_PROFILE_AUTO:
108 if (power_supply_is_system_supplied() > 0) {
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
111 else
112 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
113 } else {
114 if (rdev->pm.active_crtc_count > 1)
c9e75b21 115 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 116 else
c9e75b21 117 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 118 }
119 break;
120 case PM_PROFILE_LOW:
121 if (rdev->pm.active_crtc_count > 1)
122 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
123 else
124 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
125 break;
c9e75b21
AD		 126 case PM_PROFILE_MID:
127 if (rdev->pm.active_crtc_count > 1)
128 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
129 else
130 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
131 break;
ce8f5370
AD		 132 case PM_PROFILE_HIGH:
133 if (rdev->pm.active_crtc_count > 1)
134 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
135 else
136 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
137 break;
138 }
139
140 if (rdev->pm.active_crtc_count == 0) {
141 rdev->pm.requested_power_state_index =
142 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
143 rdev->pm.requested_clock_mode_index =
144 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
145 } else {
146 rdev->pm.requested_power_state_index =
147 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
148 rdev->pm.requested_clock_mode_index =
149 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
150 }
151}
c913e23a 152
5876dd24
MG		 153static void radeon_unmap_vram_bos(struct radeon_device *rdev)
154{
155 struct radeon_bo *bo, *n;
156
157 if (list_empty(&rdev->gem.objects))
158 return;
159
160 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
161 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
162 ttm_bo_unmap_virtual(&bo->tbo);
163 }
5876dd24
MG		 164}
165
ce8f5370 166static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 167{
ce8f5370
AD		 168 if (rdev->pm.active_crtcs) {
169 rdev->pm.vblank_sync = false;
170 wait_event_timeout(
171 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
172 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
173 }
174}
175
176static void radeon_set_power_state(struct radeon_device *rdev)
177{
178 u32 sclk, mclk;
92645879 179 bool misc_after = false;
ce8f5370
AD		 180
181 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
182 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
183 return;
184
185 if (radeon_gui_idle(rdev)) {
186 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
187 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 188 if (sclk > rdev->pm.default_sclk)
189 sclk = rdev->pm.default_sclk;
ce8f5370
AD		 190
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.requested_clock_mode_index].mclk;
9ace9f7b
AD		 193 if (mclk > rdev->pm.default_mclk)
194 mclk = rdev->pm.default_mclk;
ce8f5370 195
92645879
AD		 196 /* upvolt before raising clocks, downvolt after lowering clocks */
197 if (sclk < rdev->pm.current_sclk)
198 misc_after = true;
ce8f5370 199
92645879 200 radeon_sync_with_vblank(rdev);
ce8f5370 201
92645879 202 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 203 if (!radeon_pm_in_vbl(rdev))
204 return;
92645879 205 }
ce8f5370 206
92645879 207 radeon_pm_prepare(rdev);
ce8f5370 208
92645879
AD		 209 if (!misc_after)
210 /* voltage, pcie lanes, etc.*/
211 radeon_pm_misc(rdev);
212
213 /* set engine clock */
214 if (sclk != rdev->pm.current_sclk) {
215 radeon_pm_debug_check_in_vbl(rdev, false);
216 radeon_set_engine_clock(rdev, sclk);
217 radeon_pm_debug_check_in_vbl(rdev, true);
218 rdev->pm.current_sclk = sclk;
d9fdaafb 219 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 220 }
221
222 /* set memory clock */
798bcf73 223 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
92645879
AD		 224 radeon_pm_debug_check_in_vbl(rdev, false);
225 radeon_set_memory_clock(rdev, mclk);
226 radeon_pm_debug_check_in_vbl(rdev, true);
227 rdev->pm.current_mclk = mclk;
d9fdaafb 228 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 229 }
2aba631c 230
92645879
AD		 231 if (misc_after)
232 /* voltage, pcie lanes, etc.*/
233 radeon_pm_misc(rdev);
234
235 radeon_pm_finish(rdev);
236
ce8f5370
AD		 237 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
238 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
239 } else
d9fdaafb 240 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 241}
242
243static void radeon_pm_set_clocks(struct radeon_device *rdev)
244{
245 int i;
c37d230a 246
4e186b2d
AD		 247 /* no need to take locks, etc. if nothing's going to change */
248 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
249 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
250 return;
251
612e06ce 252 mutex_lock(&rdev->ddev->struct_mutex);
db7fce39 253 down_write(&rdev->pm.mclk_lock);
d6999bc7 254 mutex_lock(&rdev->ring_lock);
4f3218cb
AD		 255
256 /* gui idle int has issues on older chips it seems */
257 if (rdev->family >= CHIP_R600) {
ce8f5370 258 if (rdev->irq.installed) {
fb98257a
CK		 259 /* wait for GPU to become idle */
260 radeon_irq_kms_wait_gui_idle(rdev);
ce8f5370 261 }
01434b4b 262 } else {
e32eb50d
CK		 263 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
264 if (ring->ready) {
8a47cc9e 265 radeon_fence_wait_empty_locked(rdev, RADEON_RING_TYPE_GFX_INDEX);
ce8f5370 266 }
4f3218cb 267 }
5876dd24
MG		 268 radeon_unmap_vram_bos(rdev);
269
ce8f5370 270 if (rdev->irq.installed) {
2aba631c
MG		 271 for (i = 0; i < rdev->num_crtc; i++) {
272 if (rdev->pm.active_crtcs & (1 << i)) {
273 rdev->pm.req_vblank |= (1 << i);
274 drm_vblank_get(rdev->ddev, i);
275 }
276 }
277 }
539d2418 278
ce8f5370 279 radeon_set_power_state(rdev);
2aba631c 280
ce8f5370 281 if (rdev->irq.installed) {
2aba631c
MG		 282 for (i = 0; i < rdev->num_crtc; i++) {
283 if (rdev->pm.req_vblank & (1 << i)) {
284 rdev->pm.req_vblank &= ~(1 << i);
285 drm_vblank_put(rdev->ddev, i);
286 }
287 }
288 }
5876dd24 289
a424816f
AD		 290 /* update display watermarks based on new power state */
291 radeon_update_bandwidth_info(rdev);
292 if (rdev->pm.active_crtc_count)
293 radeon_bandwidth_update(rdev);
294
ce8f5370 295 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 296
d6999bc7 297 mutex_unlock(&rdev->ring_lock);
db7fce39 298 up_write(&rdev->pm.mclk_lock);
612e06ce 299 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 300}
301
f712d0c7
RM		 302static void radeon_pm_print_states(struct radeon_device *rdev)
303{
304 int i, j;
305 struct radeon_power_state *power_state;
306 struct radeon_pm_clock_info *clock_info;
307
d9fdaafb 308 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 309 for (i = 0; i < rdev->pm.num_power_states; i++) {
310 power_state = &rdev->pm.power_state[i];
d9fdaafb 311 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 312 radeon_pm_state_type_name[power_state->type]);
313 if (i == rdev->pm.default_power_state_index)
d9fdaafb 314 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 315 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 316 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 317 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 318 DRM_DEBUG_DRIVER("\tSingle display only\n");
319 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 320 for (j = 0; j < power_state->num_clock_modes; j++) {
321 clock_info = &(power_state->clock_info[j]);
322 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 323 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 324 j,
325 clock_info->sclk * 10,
326 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
327 else
d9fdaafb 328 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 329 j,
330 clock_info->sclk * 10,
331 clock_info->mclk * 10,
332 clock_info->voltage.voltage,
333 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
334 }
335 }
336}
337
ce8f5370
AD		 338static ssize_t radeon_get_pm_profile(struct device *dev,
339 struct device_attribute *attr,
340 char *buf)
a424816f
AD		 341{
342 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
343 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 344 int cp = rdev->pm.profile;
a424816f 345
ce8f5370
AD		 346 return snprintf(buf, PAGE_SIZE, "%s\n",
347 (cp == PM_PROFILE_AUTO) ? "auto" :
348 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 349 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 350 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 351}
352
ce8f5370
AD		 353static ssize_t radeon_set_pm_profile(struct device *dev,
354 struct device_attribute *attr,
355 const char *buf,
356 size_t count)
a424816f
AD		 357{
358 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
359 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 360
361 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 362 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
363 if (strncmp("default", buf, strlen("default")) == 0)
364 rdev->pm.profile = PM_PROFILE_DEFAULT;
365 else if (strncmp("auto", buf, strlen("auto")) == 0)
366 rdev->pm.profile = PM_PROFILE_AUTO;
367 else if (strncmp("low", buf, strlen("low")) == 0)
368 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 369 else if (strncmp("mid", buf, strlen("mid")) == 0)
370 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 371 else if (strncmp("high", buf, strlen("high")) == 0)
372 rdev->pm.profile = PM_PROFILE_HIGH;
373 else {
1783e4bf 374 count = -EINVAL;
ce8f5370 375 goto fail;
a424816f 376 }
ce8f5370
AD		 377 radeon_pm_update_profile(rdev);
378 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 379 } else
380 count = -EINVAL;
381
ce8f5370 382fail:
a424816f
AD		 383 mutex_unlock(&rdev->pm.mutex);
384
385 return count;
386}
387
ce8f5370
AD		 388static ssize_t radeon_get_pm_method(struct device *dev,
389 struct device_attribute *attr,
390 char *buf)
a424816f
AD		 391{
392 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
393 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 394 int pm = rdev->pm.pm_method;
a424816f
AD		 395
396 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 397 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 398}
399
ce8f5370
AD		 400static ssize_t radeon_set_pm_method(struct device *dev,
401 struct device_attribute *attr,
402 const char *buf,
403 size_t count)
a424816f
AD		 404{
405 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
406 struct radeon_device *rdev = ddev->dev_private;
a424816f 407
ce8f5370
AD		 408
409 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 410 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 411 rdev->pm.pm_method = PM_METHOD_DYNPM;
412 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 414 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 415 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
416 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 417 /* disable dynpm */
418 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
419 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 420 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 421 mutex_unlock(&rdev->pm.mutex);
32c87fca 422 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 423 } else {
1783e4bf 424 count = -EINVAL;
ce8f5370
AD		 425 goto fail;
426 }
427 radeon_pm_compute_clocks(rdev);
428fail:
a424816f
AD		 429 return count;
430}
431
ce8f5370
AD		 432static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
433static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 434
21a8122a
AD		 435static ssize_t radeon_hwmon_show_temp(struct device *dev,
436 struct device_attribute *attr,
437 char *buf)
438{
439 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
440 struct radeon_device *rdev = ddev->dev_private;
20d391d7 441 int temp;
21a8122a
AD		 442
443 switch (rdev->pm.int_thermal_type) {
444 case THERMAL_TYPE_RV6XX:
445 temp = rv6xx_get_temp(rdev);
446 break;
447 case THERMAL_TYPE_RV770:
448 temp = rv770_get_temp(rdev);
449 break;
450 case THERMAL_TYPE_EVERGREEN:
4fddba1f 451 case THERMAL_TYPE_NI:
21a8122a
AD		 452 temp = evergreen_get_temp(rdev);
453 break;
e33df25f
AD		 454 case THERMAL_TYPE_SUMO:
455 temp = sumo_get_temp(rdev);
456 break;
1bd47d2e
AD		 457 case THERMAL_TYPE_SI:
458 temp = si_get_temp(rdev);
459 break;
21a8122a
AD		 460 default:
461 temp = 0;
462 break;
463 }
464
465 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
466}
467
468static ssize_t radeon_hwmon_show_name(struct device *dev,
469 struct device_attribute *attr,
470 char *buf)
471{
472 return sprintf(buf, "radeon\n");
473}
474
475static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
476static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
477
478static struct attribute *hwmon_attributes[] = {
479 &sensor_dev_attr_temp1_input.dev_attr.attr,
480 &sensor_dev_attr_name.dev_attr.attr,
481 NULL
482};
483
484static const struct attribute_group hwmon_attrgroup = {
485 .attrs = hwmon_attributes,
486};
487
0d18abed 488static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 489{
0d18abed 490 int err = 0;
21a8122a
AD		 491
492 rdev->pm.int_hwmon_dev = NULL;
493
494 switch (rdev->pm.int_thermal_type) {
495 case THERMAL_TYPE_RV6XX:
496 case THERMAL_TYPE_RV770:
497 case THERMAL_TYPE_EVERGREEN:
457558ed 498 case THERMAL_TYPE_NI:
e33df25f 499 case THERMAL_TYPE_SUMO:
1bd47d2e 500 case THERMAL_TYPE_SI:
5d7486c7
AD		 501 /* No support for TN yet */
502 if (rdev->family == CHIP_ARUBA)
503 return err;
21a8122a 504 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 505 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
506 err = PTR_ERR(rdev->pm.int_hwmon_dev);
507 dev_err(rdev->dev,
508 "Unable to register hwmon device: %d\n", err);
509 break;
510 }
21a8122a
AD		 511 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
512 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
513 &hwmon_attrgroup);
0d18abed
DC		 514 if (err) {
515 dev_err(rdev->dev,
516 "Unable to create hwmon sysfs file: %d\n", err);
517 hwmon_device_unregister(rdev->dev);
518 }
21a8122a
AD		 519 break;
520 default:
521 break;
522 }
0d18abed
DC		 523
524 return err;
21a8122a
AD		 525}
526
527static void radeon_hwmon_fini(struct radeon_device *rdev)
528{
529 if (rdev->pm.int_hwmon_dev) {
530 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
531 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
532 }
533}
534
ce8f5370 535void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 536{
ce8f5370 537 mutex_lock(&rdev->pm.mutex);
3f53eb6f 538 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 539 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
540 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 541 }
ce8f5370 542 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 543
544 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 545}
546
ce8f5370 547void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 548{
ed18a360
AD		 549 /* set up the default clocks if the MC ucode is loaded */
550 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
551 if (rdev->pm.default_vddc)
8a83ec5e
AD		 552 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
553 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 554 if (rdev->pm.default_vddci)
555 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
556 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 557 if (rdev->pm.default_sclk)
558 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
559 if (rdev->pm.default_mclk)
560 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
561 }
f8ed8b4c
AD		 562 /* asic init will reset the default power state */
563 mutex_lock(&rdev->pm.mutex);
564 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
565 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 566 rdev->pm.current_sclk = rdev->pm.default_sclk;
567 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 568 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 569 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 570 if (rdev->pm.pm_method == PM_METHOD_DYNPM
571 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
572 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 573 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
574 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 575 }
f8ed8b4c 576 mutex_unlock(&rdev->pm.mutex);
ce8f5370 577 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 578}
579
7433874e
RM		 580int radeon_pm_init(struct radeon_device *rdev)
581{
26481fb1 582 int ret;
0d18abed 583
ce8f5370
AD		 584 /* default to profile method */
585 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 586 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 587 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
588 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
589 rdev->pm.dynpm_can_upclock = true;
590 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 591 rdev->pm.default_sclk = rdev->clock.default_sclk;
592 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 593 rdev->pm.current_sclk = rdev->clock.default_sclk;
594 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 595 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 596
56278a8e
AD		 597 if (rdev->bios) {
598 if (rdev->is_atom_bios)
599 radeon_atombios_get_power_modes(rdev);
600 else
601 radeon_combios_get_power_modes(rdev);
f712d0c7 602 radeon_pm_print_states(rdev);
ce8f5370 603 radeon_pm_init_profile(rdev);
ed18a360
AD		 604 /* set up the default clocks if the MC ucode is loaded */
605 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
606 if (rdev->pm.default_vddc)
8a83ec5e
AD		 607 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
608 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 609 if (rdev->pm.default_vddci)
610 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
611 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 612 if (rdev->pm.default_sclk)
613 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
614 if (rdev->pm.default_mclk)
615 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
616 }
56278a8e
AD		 617 }
618
21a8122a 619 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 620 ret = radeon_hwmon_init(rdev);
621 if (ret)
622 return ret;
32c87fca
TH		 623
624 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
625
ce8f5370 626 if (rdev->pm.num_power_states > 1) {
ce8f5370 627 /* where's the best place to put these? */
26481fb1
DA		 628 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
629 if (ret)
630 DRM_ERROR("failed to create device file for power profile\n");
631 ret = device_create_file(rdev->dev, &dev_attr_power_method);
632 if (ret)
633 DRM_ERROR("failed to create device file for power method\n");
a424816f 634
ce8f5370
AD		 635#ifdef CONFIG_ACPI
636 rdev->acpi_nb.notifier_call = radeon_acpi_event;
637 register_acpi_notifier(&rdev->acpi_nb);
638#endif
ce8f5370
AD		 639 if (radeon_debugfs_pm_init(rdev)) {
640 DRM_ERROR("Failed to register debugfs file for PM!\n");
641 }
c913e23a 642
ce8f5370
AD		 643 DRM_INFO("radeon: power management initialized\n");
644 }
c913e23a 645
7433874e
RM		 646 return 0;
647}
648
29fb52ca
AD		 649void radeon_pm_fini(struct radeon_device *rdev)
650{
ce8f5370 651 if (rdev->pm.num_power_states > 1) {
a424816f 652 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 653 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
654 rdev->pm.profile = PM_PROFILE_DEFAULT;
655 radeon_pm_update_profile(rdev);
656 radeon_pm_set_clocks(rdev);
657 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 658 /* reset default clocks */
659 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
660 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
661 radeon_pm_set_clocks(rdev);
662 }
a424816f 663 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 664
665 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 666
ce8f5370
AD		 667 device_remove_file(rdev->dev, &dev_attr_power_profile);
668 device_remove_file(rdev->dev, &dev_attr_power_method);
669#ifdef CONFIG_ACPI
670 unregister_acpi_notifier(&rdev->acpi_nb);
671#endif
672 }
a424816f 673
0975b162
AD		 674 if (rdev->pm.power_state)
675 kfree(rdev->pm.power_state);
676
21a8122a 677 radeon_hwmon_fini(rdev);
29fb52ca
AD		 678}
679
c913e23a
RM		 680void radeon_pm_compute_clocks(struct radeon_device *rdev)
681{
682 struct drm_device *ddev = rdev->ddev;
a48b9b4e 683 struct drm_crtc *crtc;
c913e23a 684 struct radeon_crtc *radeon_crtc;
c913e23a 685
ce8f5370
AD		 686 if (rdev->pm.num_power_states < 2)
687 return;
688
c913e23a
RM		 689 mutex_lock(&rdev->pm.mutex);
690
691 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 692 rdev->pm.active_crtc_count = 0;
693 list_for_each_entry(crtc,
694 &ddev->mode_config.crtc_list, head) {
695 radeon_crtc = to_radeon_crtc(crtc);
696 if (radeon_crtc->enabled) {
c913e23a 697 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 698 rdev->pm.active_crtc_count++;
c913e23a
RM		 699 }
700 }
701
ce8f5370
AD		 702 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
703 radeon_pm_update_profile(rdev);
704 radeon_pm_set_clocks(rdev);
705 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
706 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
707 if (rdev->pm.active_crtc_count > 1) {
708 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
709 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
710
711 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
712 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
713 radeon_pm_get_dynpm_state(rdev);
714 radeon_pm_set_clocks(rdev);
715
d9fdaafb 716 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 717 }
718 } else if (rdev->pm.active_crtc_count == 1) {
719 /* TODO: Increase clocks if needed for current mode */
720
721 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
722 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
723 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
724 radeon_pm_get_dynpm_state(rdev);
725 radeon_pm_set_clocks(rdev);
726
32c87fca
TH		 727 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
728 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 729 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
730 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 731 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
732 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 733 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 734 }
735 } else { /* count == 0 */
736 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
737 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
738
739 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
740 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
741 radeon_pm_get_dynpm_state(rdev);
742 radeon_pm_set_clocks(rdev);
743 }
744 }
c913e23a 745 }
c913e23a 746 }
73a6d3fc
RM		 747
748 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 749}
750
ce8f5370 751static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 752{
75fa0b08 753 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 754 bool in_vbl = true;
755
75fa0b08
MK		 756 /* Iterate over all active crtc's. All crtc's must be in vblank,
757 * otherwise return in_vbl == false.
758 */
759 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
760 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 761 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
762 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
763 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 764 in_vbl = false;
765 }
766 }
f81f2024
MG		 767
768 return in_vbl;
769}
770
ce8f5370 771static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 772{
773 u32 stat_crtc = 0;
774 bool in_vbl = radeon_pm_in_vbl(rdev);
775
f735261b 776 if (in_vbl == false)
d9fdaafb 777 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 778 finish ? "exit" : "entry");
f735261b
DA		 779 return in_vbl;
780}
c913e23a 781
ce8f5370 782static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 783{
784 struct radeon_device *rdev;
d9932a32 785 int resched;
c913e23a 786 rdev = container_of(work, struct radeon_device,
ce8f5370 787 pm.dynpm_idle_work.work);
c913e23a 788
d9932a32 789 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 790 mutex_lock(&rdev->pm.mutex);
ce8f5370 791 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a 792 int not_processed = 0;
7465280c
AD		 793 int i;
794
7465280c 795 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
0ec0612a
AD		 796 struct radeon_ring *ring = &rdev->ring[i];
797
798 if (ring->ready) {
799 not_processed += radeon_fence_count_emitted(rdev, i);
800 if (not_processed >= 3)
801 break;
802 }
c913e23a 803 }
c913e23a
RM		 804
805 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 806 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
807 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
808 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
809 rdev->pm.dynpm_can_upclock) {
810 rdev->pm.dynpm_planned_action =
811 DYNPM_ACTION_UPCLOCK;
812 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 813 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
814 }
815 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 816 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
817 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
818 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
819 rdev->pm.dynpm_can_downclock) {
820 rdev->pm.dynpm_planned_action =
821 DYNPM_ACTION_DOWNCLOCK;
822 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 823 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
824 }
825 }
826
d7311171
AD		 827 /* Note, radeon_pm_set_clocks is called with static_switch set
828 * to false since we want to wait for vbl to avoid flicker.
829 */
ce8f5370
AD		 830 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
831 jiffies > rdev->pm.dynpm_action_timeout) {
832 radeon_pm_get_dynpm_state(rdev);
833 radeon_pm_set_clocks(rdev);
c913e23a 834 }
3f53eb6f 835
32c87fca
TH		 836 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
837 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 838 }
839 mutex_unlock(&rdev->pm.mutex);
d9932a32 840 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 841}
842
7433874e
RM		 843/*
844 * Debugfs info
845 */
846#if defined(CONFIG_DEBUG_FS)
847
848static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
849{
850 struct drm_info_node *node = (struct drm_info_node *) m->private;
851 struct drm_device *dev = node->minor->dev;
852 struct radeon_device *rdev = dev->dev_private;
853
9ace9f7b 854 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
6234077d 855 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 856 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
798bcf73 857 if (rdev->asic->pm.get_memory_clock)
6234077d 858 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 859 if (rdev->pm.current_vddc)
860 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
798bcf73 861 if (rdev->asic->pm.get_pcie_lanes)
aa5120d2 862 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 863
864 return 0;
865}
866
867static struct drm_info_list radeon_pm_info_list[] = {
868 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
869};
870#endif
871
c913e23a 872static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 873{
874#if defined(CONFIG_DEBUG_FS)
875 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
876#else
877 return 0;
878#endif
879}
kernel source for telekom puls (alcatel/mediatek)