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Merge branch 'iommu/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/joro...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_pm.c
CommitLineData
7433874e
RM		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
56278a8e 21 * Alex Deucher <alexdeucher@gmail.com>
7433874e
RM		 22 */
23#include "drmP.h"
24#include "radeon.h"
f735261b 25#include "avivod.h"
8a83ec5e 26#include "atom.h"
ce8f5370
AD		 27#ifdef CONFIG_ACPI
28#include <linux/acpi.h>
29#endif
30#include <linux/power_supply.h>
21a8122a
AD		 31#include <linux/hwmon.h>
32#include <linux/hwmon-sysfs.h>
7433874e 33
c913e23a
RM		 34#define RADEON_IDLE_LOOP_MS 100
35#define RADEON_RECLOCK_DELAY_MS 200
73a6d3fc 36#define RADEON_WAIT_VBLANK_TIMEOUT 200
2031f77c 37#define RADEON_WAIT_IDLE_TIMEOUT 200
c913e23a 38
f712d0c7
RM		 39static const char *radeon_pm_state_type_name[5] = {
40 "Default",
41 "Powersave",
42 "Battery",
43 "Balanced",
44 "Performance",
45};
46
ce8f5370 47static void radeon_dynpm_idle_work_handler(struct work_struct *work);
c913e23a 48static int radeon_debugfs_pm_init(struct radeon_device *rdev);
ce8f5370
AD		 49static bool radeon_pm_in_vbl(struct radeon_device *rdev);
50static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
51static void radeon_pm_update_profile(struct radeon_device *rdev);
52static void radeon_pm_set_clocks(struct radeon_device *rdev);
53
54#define ACPI_AC_CLASS "ac_adapter"
55
a4c9e2ee
AD		 56int radeon_pm_get_type_index(struct radeon_device *rdev,
57 enum radeon_pm_state_type ps_type,
58 int instance)
59{
60 int i;
61 int found_instance = -1;
62
63 for (i = 0; i < rdev->pm.num_power_states; i++) {
64 if (rdev->pm.power_state[i].type == ps_type) {
65 found_instance++;
66 if (found_instance == instance)
67 return i;
68 }
69 }
70 /* return default if no match */
71 return rdev->pm.default_power_state_index;
72}
73
ce8f5370
AD		 74#ifdef CONFIG_ACPI
75static int radeon_acpi_event(struct notifier_block *nb,
76 unsigned long val,
77 void *data)
78{
79 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
80 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
81
82 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
83 if (power_supply_is_system_supplied() > 0)
d9fdaafb 84 DRM_DEBUG_DRIVER("pm: AC\n");
ce8f5370 85 else
d9fdaafb 86 DRM_DEBUG_DRIVER("pm: DC\n");
ce8f5370
AD		 87
88 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
89 if (rdev->pm.profile == PM_PROFILE_AUTO) {
90 mutex_lock(&rdev->pm.mutex);
91 radeon_pm_update_profile(rdev);
92 radeon_pm_set_clocks(rdev);
93 mutex_unlock(&rdev->pm.mutex);
94 }
95 }
96 }
97
98 return NOTIFY_OK;
99}
100#endif
101
102static void radeon_pm_update_profile(struct radeon_device *rdev)
103{
104 switch (rdev->pm.profile) {
105 case PM_PROFILE_DEFAULT:
106 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
107 break;
108 case PM_PROFILE_AUTO:
109 if (power_supply_is_system_supplied() > 0) {
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
112 else
113 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
114 } else {
115 if (rdev->pm.active_crtc_count > 1)
c9e75b21 116 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
ce8f5370 117 else
c9e75b21 118 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
ce8f5370
AD		 119 }
120 break;
121 case PM_PROFILE_LOW:
122 if (rdev->pm.active_crtc_count > 1)
123 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
124 else
125 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
126 break;
c9e75b21
AD		 127 case PM_PROFILE_MID:
128 if (rdev->pm.active_crtc_count > 1)
129 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
130 else
131 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
132 break;
ce8f5370
AD		 133 case PM_PROFILE_HIGH:
134 if (rdev->pm.active_crtc_count > 1)
135 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
136 else
137 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
138 break;
139 }
140
141 if (rdev->pm.active_crtc_count == 0) {
142 rdev->pm.requested_power_state_index =
143 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
144 rdev->pm.requested_clock_mode_index =
145 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
146 } else {
147 rdev->pm.requested_power_state_index =
148 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
149 rdev->pm.requested_clock_mode_index =
150 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
151 }
152}
c913e23a 153
5876dd24
MG		 154static void radeon_unmap_vram_bos(struct radeon_device *rdev)
155{
156 struct radeon_bo *bo, *n;
157
158 if (list_empty(&rdev->gem.objects))
159 return;
160
161 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
162 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
163 ttm_bo_unmap_virtual(&bo->tbo);
164 }
5876dd24
MG		 165}
166
ce8f5370 167static void radeon_sync_with_vblank(struct radeon_device *rdev)
a424816f 168{
ce8f5370
AD		 169 if (rdev->pm.active_crtcs) {
170 rdev->pm.vblank_sync = false;
171 wait_event_timeout(
172 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
173 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
174 }
175}
176
177static void radeon_set_power_state(struct radeon_device *rdev)
178{
179 u32 sclk, mclk;
92645879 180 bool misc_after = false;
ce8f5370
AD		 181
182 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
183 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
184 return;
185
186 if (radeon_gui_idle(rdev)) {
187 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
188 clock_info[rdev->pm.requested_clock_mode_index].sclk;
9ace9f7b
AD		 189 if (sclk > rdev->pm.default_sclk)
190 sclk = rdev->pm.default_sclk;
ce8f5370
AD		 191
192 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
193 clock_info[rdev->pm.requested_clock_mode_index].mclk;
9ace9f7b
AD		 194 if (mclk > rdev->pm.default_mclk)
195 mclk = rdev->pm.default_mclk;
ce8f5370 196
92645879
AD		 197 /* upvolt before raising clocks, downvolt after lowering clocks */
198 if (sclk < rdev->pm.current_sclk)
199 misc_after = true;
ce8f5370 200
92645879 201 radeon_sync_with_vblank(rdev);
ce8f5370 202
92645879 203 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 204 if (!radeon_pm_in_vbl(rdev))
205 return;
92645879 206 }
ce8f5370 207
92645879 208 radeon_pm_prepare(rdev);
ce8f5370 209
92645879
AD		 210 if (!misc_after)
211 /* voltage, pcie lanes, etc.*/
212 radeon_pm_misc(rdev);
213
214 /* set engine clock */
215 if (sclk != rdev->pm.current_sclk) {
216 radeon_pm_debug_check_in_vbl(rdev, false);
217 radeon_set_engine_clock(rdev, sclk);
218 radeon_pm_debug_check_in_vbl(rdev, true);
219 rdev->pm.current_sclk = sclk;
d9fdaafb 220 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
92645879
AD		 221 }
222
223 /* set memory clock */
224 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
225 radeon_pm_debug_check_in_vbl(rdev, false);
226 radeon_set_memory_clock(rdev, mclk);
227 radeon_pm_debug_check_in_vbl(rdev, true);
228 rdev->pm.current_mclk = mclk;
d9fdaafb 229 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
ce8f5370 230 }
2aba631c 231
92645879
AD		 232 if (misc_after)
233 /* voltage, pcie lanes, etc.*/
234 radeon_pm_misc(rdev);
235
236 radeon_pm_finish(rdev);
237
ce8f5370
AD		 238 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
239 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
240 } else
d9fdaafb 241 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
ce8f5370
AD		 242}
243
244static void radeon_pm_set_clocks(struct radeon_device *rdev)
245{
246 int i;
c37d230a 247
4e186b2d
AD		 248 /* no need to take locks, etc. if nothing's going to change */
249 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
250 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
251 return;
252
612e06ce
MG		 253 mutex_lock(&rdev->ddev->struct_mutex);
254 mutex_lock(&rdev->vram_mutex);
a424816f 255 mutex_lock(&rdev->cp.mutex);
4f3218cb
AD		 256
257 /* gui idle int has issues on older chips it seems */
258 if (rdev->family >= CHIP_R600) {
ce8f5370
AD		 259 if (rdev->irq.installed) {
260 /* wait for GPU idle */
261 rdev->pm.gui_idle = false;
262 rdev->irq.gui_idle = true;
263 radeon_irq_set(rdev);
264 wait_event_interruptible_timeout(
265 rdev->irq.idle_queue, rdev->pm.gui_idle,
266 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
267 rdev->irq.gui_idle = false;
268 radeon_irq_set(rdev);
269 }
01434b4b 270 } else {
ce8f5370
AD		 271 if (rdev->cp.ready) {
272 struct radeon_fence *fence;
273 radeon_ring_alloc(rdev, 64);
274 radeon_fence_create(rdev, &fence);
275 radeon_fence_emit(rdev, fence);
276 radeon_ring_commit(rdev);
277 radeon_fence_wait(fence, false);
278 radeon_fence_unref(&fence);
279 }
4f3218cb 280 }
5876dd24
MG		 281 radeon_unmap_vram_bos(rdev);
282
ce8f5370 283 if (rdev->irq.installed) {
2aba631c
MG		 284 for (i = 0; i < rdev->num_crtc; i++) {
285 if (rdev->pm.active_crtcs & (1 << i)) {
286 rdev->pm.req_vblank |= (1 << i);
287 drm_vblank_get(rdev->ddev, i);
288 }
289 }
290 }
539d2418 291
ce8f5370 292 radeon_set_power_state(rdev);
2aba631c 293
ce8f5370 294 if (rdev->irq.installed) {
2aba631c
MG		 295 for (i = 0; i < rdev->num_crtc; i++) {
296 if (rdev->pm.req_vblank & (1 << i)) {
297 rdev->pm.req_vblank &= ~(1 << i);
298 drm_vblank_put(rdev->ddev, i);
299 }
300 }
301 }
5876dd24 302
a424816f
AD		 303 /* update display watermarks based on new power state */
304 radeon_update_bandwidth_info(rdev);
305 if (rdev->pm.active_crtc_count)
306 radeon_bandwidth_update(rdev);
307
ce8f5370 308 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
2aba631c 309
a424816f 310 mutex_unlock(&rdev->cp.mutex);
612e06ce
MG		 311 mutex_unlock(&rdev->vram_mutex);
312 mutex_unlock(&rdev->ddev->struct_mutex);
a424816f
AD		 313}
314
f712d0c7
RM		 315static void radeon_pm_print_states(struct radeon_device *rdev)
316{
317 int i, j;
318 struct radeon_power_state *power_state;
319 struct radeon_pm_clock_info *clock_info;
320
d9fdaafb 321 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
f712d0c7
RM		 322 for (i = 0; i < rdev->pm.num_power_states; i++) {
323 power_state = &rdev->pm.power_state[i];
d9fdaafb 324 DRM_DEBUG_DRIVER("State %d: %s\n", i,
f712d0c7
RM		 325 radeon_pm_state_type_name[power_state->type]);
326 if (i == rdev->pm.default_power_state_index)
d9fdaafb 327 DRM_DEBUG_DRIVER("\tDefault");
f712d0c7 328 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
d9fdaafb 329 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
f712d0c7 330 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
d9fdaafb
DA		 331 DRM_DEBUG_DRIVER("\tSingle display only\n");
332 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
f712d0c7
RM		 333 for (j = 0; j < power_state->num_clock_modes; j++) {
334 clock_info = &(power_state->clock_info[j]);
335 if (rdev->flags & RADEON_IS_IGP)
d9fdaafb 336 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
f712d0c7
RM		 337 j,
338 clock_info->sclk * 10,
339 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
340 else
d9fdaafb 341 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
f712d0c7
RM		 342 j,
343 clock_info->sclk * 10,
344 clock_info->mclk * 10,
345 clock_info->voltage.voltage,
346 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
347 }
348 }
349}
350
ce8f5370
AD		 351static ssize_t radeon_get_pm_profile(struct device *dev,
352 struct device_attribute *attr,
353 char *buf)
a424816f
AD		 354{
355 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
356 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 357 int cp = rdev->pm.profile;
a424816f 358
ce8f5370
AD		 359 return snprintf(buf, PAGE_SIZE, "%s\n",
360 (cp == PM_PROFILE_AUTO) ? "auto" :
361 (cp == PM_PROFILE_LOW) ? "low" :
12e27be8 362 (cp == PM_PROFILE_MID) ? "mid" :
ce8f5370 363 (cp == PM_PROFILE_HIGH) ? "high" : "default");
a424816f
AD		 364}
365
ce8f5370
AD		 366static ssize_t radeon_set_pm_profile(struct device *dev,
367 struct device_attribute *attr,
368 const char *buf,
369 size_t count)
a424816f
AD		 370{
371 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
372 struct radeon_device *rdev = ddev->dev_private;
a424816f
AD		 373
374 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 375 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
376 if (strncmp("default", buf, strlen("default")) == 0)
377 rdev->pm.profile = PM_PROFILE_DEFAULT;
378 else if (strncmp("auto", buf, strlen("auto")) == 0)
379 rdev->pm.profile = PM_PROFILE_AUTO;
380 else if (strncmp("low", buf, strlen("low")) == 0)
381 rdev->pm.profile = PM_PROFILE_LOW;
c9e75b21
AD		 382 else if (strncmp("mid", buf, strlen("mid")) == 0)
383 rdev->pm.profile = PM_PROFILE_MID;
ce8f5370
AD		 384 else if (strncmp("high", buf, strlen("high")) == 0)
385 rdev->pm.profile = PM_PROFILE_HIGH;
386 else {
1783e4bf 387 count = -EINVAL;
ce8f5370 388 goto fail;
a424816f 389 }
ce8f5370
AD		 390 radeon_pm_update_profile(rdev);
391 radeon_pm_set_clocks(rdev);
1783e4bf
TR		 392 } else
393 count = -EINVAL;
394
ce8f5370 395fail:
a424816f
AD		 396 mutex_unlock(&rdev->pm.mutex);
397
398 return count;
399}
400
ce8f5370
AD		 401static ssize_t radeon_get_pm_method(struct device *dev,
402 struct device_attribute *attr,
403 char *buf)
a424816f
AD		 404{
405 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
406 struct radeon_device *rdev = ddev->dev_private;
ce8f5370 407 int pm = rdev->pm.pm_method;
a424816f
AD		 408
409 return snprintf(buf, PAGE_SIZE, "%s\n",
ce8f5370 410 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
a424816f
AD		 411}
412
ce8f5370
AD		 413static ssize_t radeon_set_pm_method(struct device *dev,
414 struct device_attribute *attr,
415 const char *buf,
416 size_t count)
a424816f
AD		 417{
418 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
419 struct radeon_device *rdev = ddev->dev_private;
a424816f 420
ce8f5370
AD		 421
422 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
a424816f 423 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 424 rdev->pm.pm_method = PM_METHOD_DYNPM;
425 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
426 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
a424816f 427 mutex_unlock(&rdev->pm.mutex);
ce8f5370
AD		 428 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
429 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 430 /* disable dynpm */
431 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
432 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
3f53eb6f 433 rdev->pm.pm_method = PM_METHOD_PROFILE;
ce8f5370 434 mutex_unlock(&rdev->pm.mutex);
32c87fca 435 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
ce8f5370 436 } else {
1783e4bf 437 count = -EINVAL;
ce8f5370
AD		 438 goto fail;
439 }
440 radeon_pm_compute_clocks(rdev);
441fail:
a424816f
AD		 442 return count;
443}
444
ce8f5370
AD		 445static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
446static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
a424816f 447
21a8122a
AD		 448static ssize_t radeon_hwmon_show_temp(struct device *dev,
449 struct device_attribute *attr,
450 char *buf)
451{
452 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
453 struct radeon_device *rdev = ddev->dev_private;
20d391d7 454 int temp;
21a8122a
AD		 455
456 switch (rdev->pm.int_thermal_type) {
457 case THERMAL_TYPE_RV6XX:
458 temp = rv6xx_get_temp(rdev);
459 break;
460 case THERMAL_TYPE_RV770:
461 temp = rv770_get_temp(rdev);
462 break;
463 case THERMAL_TYPE_EVERGREEN:
4fddba1f 464 case THERMAL_TYPE_NI:
21a8122a
AD		 465 temp = evergreen_get_temp(rdev);
466 break;
e33df25f
AD		 467 case THERMAL_TYPE_SUMO:
468 temp = sumo_get_temp(rdev);
469 break;
21a8122a
AD		 470 default:
471 temp = 0;
472 break;
473 }
474
475 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
476}
477
478static ssize_t radeon_hwmon_show_name(struct device *dev,
479 struct device_attribute *attr,
480 char *buf)
481{
482 return sprintf(buf, "radeon\n");
483}
484
485static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
486static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
487
488static struct attribute *hwmon_attributes[] = {
489 &sensor_dev_attr_temp1_input.dev_attr.attr,
490 &sensor_dev_attr_name.dev_attr.attr,
491 NULL
492};
493
494static const struct attribute_group hwmon_attrgroup = {
495 .attrs = hwmon_attributes,
496};
497
0d18abed 498static int radeon_hwmon_init(struct radeon_device *rdev)
21a8122a 499{
0d18abed 500 int err = 0;
21a8122a
AD		 501
502 rdev->pm.int_hwmon_dev = NULL;
503
504 switch (rdev->pm.int_thermal_type) {
505 case THERMAL_TYPE_RV6XX:
506 case THERMAL_TYPE_RV770:
507 case THERMAL_TYPE_EVERGREEN:
457558ed 508 case THERMAL_TYPE_NI:
e33df25f 509 case THERMAL_TYPE_SUMO:
21a8122a 510 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
0d18abed
DC		 511 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
512 err = PTR_ERR(rdev->pm.int_hwmon_dev);
513 dev_err(rdev->dev,
514 "Unable to register hwmon device: %d\n", err);
515 break;
516 }
21a8122a
AD		 517 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
518 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
519 &hwmon_attrgroup);
0d18abed
DC		 520 if (err) {
521 dev_err(rdev->dev,
522 "Unable to create hwmon sysfs file: %d\n", err);
523 hwmon_device_unregister(rdev->dev);
524 }
21a8122a
AD		 525 break;
526 default:
527 break;
528 }
0d18abed
DC		 529
530 return err;
21a8122a
AD		 531}
532
533static void radeon_hwmon_fini(struct radeon_device *rdev)
534{
535 if (rdev->pm.int_hwmon_dev) {
536 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
537 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
538 }
539}
540
ce8f5370 541void radeon_pm_suspend(struct radeon_device *rdev)
56278a8e 542{
ce8f5370 543 mutex_lock(&rdev->pm.mutex);
3f53eb6f 544 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
3f53eb6f
RW		 545 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
546 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
3f53eb6f 547 }
ce8f5370 548 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 549
550 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
56278a8e
AD		 551}
552
ce8f5370 553void radeon_pm_resume(struct radeon_device *rdev)
d0d6cb81 554{
ed18a360
AD		 555 /* set up the default clocks if the MC ucode is loaded */
556 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
557 if (rdev->pm.default_vddc)
8a83ec5e
AD		 558 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
559 SET_VOLTAGE_TYPE_ASIC_VDDC);
2feea49a
AD		 560 if (rdev->pm.default_vddci)
561 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
562 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 563 if (rdev->pm.default_sclk)
564 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
565 if (rdev->pm.default_mclk)
566 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
567 }
f8ed8b4c
AD		 568 /* asic init will reset the default power state */
569 mutex_lock(&rdev->pm.mutex);
570 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
571 rdev->pm.current_clock_mode_index = 0;
9ace9f7b
AD		 572 rdev->pm.current_sclk = rdev->pm.default_sclk;
573 rdev->pm.current_mclk = rdev->pm.default_mclk;
4d60173f 574 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2feea49a 575 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
3f53eb6f
RW		 576 if (rdev->pm.pm_method == PM_METHOD_DYNPM
577 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
578 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 579 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
580 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
3f53eb6f 581 }
f8ed8b4c 582 mutex_unlock(&rdev->pm.mutex);
ce8f5370 583 radeon_pm_compute_clocks(rdev);
d0d6cb81
RM		 584}
585
7433874e
RM		 586int radeon_pm_init(struct radeon_device *rdev)
587{
26481fb1 588 int ret;
0d18abed 589
ce8f5370
AD		 590 /* default to profile method */
591 rdev->pm.pm_method = PM_METHOD_PROFILE;
f8ed8b4c 592 rdev->pm.profile = PM_PROFILE_DEFAULT;
ce8f5370
AD		 593 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
594 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
595 rdev->pm.dynpm_can_upclock = true;
596 rdev->pm.dynpm_can_downclock = true;
9ace9f7b
AD		 597 rdev->pm.default_sclk = rdev->clock.default_sclk;
598 rdev->pm.default_mclk = rdev->clock.default_mclk;
f8ed8b4c
AD		 599 rdev->pm.current_sclk = rdev->clock.default_sclk;
600 rdev->pm.current_mclk = rdev->clock.default_mclk;
21a8122a 601 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
c913e23a 602
56278a8e
AD		 603 if (rdev->bios) {
604 if (rdev->is_atom_bios)
605 radeon_atombios_get_power_modes(rdev);
606 else
607 radeon_combios_get_power_modes(rdev);
f712d0c7 608 radeon_pm_print_states(rdev);
ce8f5370 609 radeon_pm_init_profile(rdev);
ed18a360
AD		 610 /* set up the default clocks if the MC ucode is loaded */
611 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
612 if (rdev->pm.default_vddc)
8a83ec5e
AD		 613 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
614 SET_VOLTAGE_TYPE_ASIC_VDDC);
4639dd21
AD		 615 if (rdev->pm.default_vddci)
616 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
617 SET_VOLTAGE_TYPE_ASIC_VDDCI);
ed18a360
AD		 618 if (rdev->pm.default_sclk)
619 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
620 if (rdev->pm.default_mclk)
621 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
622 }
56278a8e
AD		 623 }
624
21a8122a 625 /* set up the internal thermal sensor if applicable */
0d18abed
DC		 626 ret = radeon_hwmon_init(rdev);
627 if (ret)
628 return ret;
32c87fca
TH		 629
630 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
631
ce8f5370 632 if (rdev->pm.num_power_states > 1) {
ce8f5370 633 /* where's the best place to put these? */
26481fb1
DA		 634 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
635 if (ret)
636 DRM_ERROR("failed to create device file for power profile\n");
637 ret = device_create_file(rdev->dev, &dev_attr_power_method);
638 if (ret)
639 DRM_ERROR("failed to create device file for power method\n");
a424816f 640
ce8f5370
AD		 641#ifdef CONFIG_ACPI
642 rdev->acpi_nb.notifier_call = radeon_acpi_event;
643 register_acpi_notifier(&rdev->acpi_nb);
644#endif
ce8f5370
AD		 645 if (radeon_debugfs_pm_init(rdev)) {
646 DRM_ERROR("Failed to register debugfs file for PM!\n");
647 }
c913e23a 648
ce8f5370
AD		 649 DRM_INFO("radeon: power management initialized\n");
650 }
c913e23a 651
7433874e
RM		 652 return 0;
653}
654
29fb52ca
AD		 655void radeon_pm_fini(struct radeon_device *rdev)
656{
ce8f5370 657 if (rdev->pm.num_power_states > 1) {
a424816f 658 mutex_lock(&rdev->pm.mutex);
ce8f5370
AD		 659 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
660 rdev->pm.profile = PM_PROFILE_DEFAULT;
661 radeon_pm_update_profile(rdev);
662 radeon_pm_set_clocks(rdev);
663 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
ce8f5370
AD		 664 /* reset default clocks */
665 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
666 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
667 radeon_pm_set_clocks(rdev);
668 }
a424816f 669 mutex_unlock(&rdev->pm.mutex);
32c87fca
TH		 670
671 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
58e21dff 672
ce8f5370
AD		 673 device_remove_file(rdev->dev, &dev_attr_power_profile);
674 device_remove_file(rdev->dev, &dev_attr_power_method);
675#ifdef CONFIG_ACPI
676 unregister_acpi_notifier(&rdev->acpi_nb);
677#endif
678 }
a424816f 679
0975b162
AD		 680 if (rdev->pm.power_state)
681 kfree(rdev->pm.power_state);
682
21a8122a 683 radeon_hwmon_fini(rdev);
29fb52ca
AD		 684}
685
c913e23a
RM		 686void radeon_pm_compute_clocks(struct radeon_device *rdev)
687{
688 struct drm_device *ddev = rdev->ddev;
a48b9b4e 689 struct drm_crtc *crtc;
c913e23a 690 struct radeon_crtc *radeon_crtc;
c913e23a 691
ce8f5370
AD		 692 if (rdev->pm.num_power_states < 2)
693 return;
694
c913e23a
RM		 695 mutex_lock(&rdev->pm.mutex);
696
697 rdev->pm.active_crtcs = 0;
a48b9b4e
AD		 698 rdev->pm.active_crtc_count = 0;
699 list_for_each_entry(crtc,
700 &ddev->mode_config.crtc_list, head) {
701 radeon_crtc = to_radeon_crtc(crtc);
702 if (radeon_crtc->enabled) {
c913e23a 703 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
a48b9b4e 704 rdev->pm.active_crtc_count++;
c913e23a
RM		 705 }
706 }
707
ce8f5370
AD		 708 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
709 radeon_pm_update_profile(rdev);
710 radeon_pm_set_clocks(rdev);
711 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
712 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
713 if (rdev->pm.active_crtc_count > 1) {
714 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
715 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
716
717 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
718 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
719 radeon_pm_get_dynpm_state(rdev);
720 radeon_pm_set_clocks(rdev);
721
d9fdaafb 722 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
ce8f5370
AD		 723 }
724 } else if (rdev->pm.active_crtc_count == 1) {
725 /* TODO: Increase clocks if needed for current mode */
726
727 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
728 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
729 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
730 radeon_pm_get_dynpm_state(rdev);
731 radeon_pm_set_clocks(rdev);
732
32c87fca
TH		 733 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
734 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
ce8f5370
AD		 735 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
736 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
32c87fca
TH		 737 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
738 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
d9fdaafb 739 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
ce8f5370
AD		 740 }
741 } else { /* count == 0 */
742 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
743 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
744
745 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
746 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
747 radeon_pm_get_dynpm_state(rdev);
748 radeon_pm_set_clocks(rdev);
749 }
750 }
c913e23a 751 }
c913e23a 752 }
73a6d3fc
RM		 753
754 mutex_unlock(&rdev->pm.mutex);
c913e23a
RM		 755}
756
ce8f5370 757static bool radeon_pm_in_vbl(struct radeon_device *rdev)
f735261b 758{
75fa0b08 759 int crtc, vpos, hpos, vbl_status;
f735261b
DA		 760 bool in_vbl = true;
761
75fa0b08
MK		 762 /* Iterate over all active crtc's. All crtc's must be in vblank,
763 * otherwise return in_vbl == false.
764 */
765 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
766 if (rdev->pm.active_crtcs & (1 << crtc)) {
f5a80209
MK		 767 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
768 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
769 !(vbl_status & DRM_SCANOUTPOS_INVBL))
f735261b
DA		 770 in_vbl = false;
771 }
772 }
f81f2024
MG		 773
774 return in_vbl;
775}
776
ce8f5370 777static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
f81f2024
MG		 778{
779 u32 stat_crtc = 0;
780 bool in_vbl = radeon_pm_in_vbl(rdev);
781
f735261b 782 if (in_vbl == false)
d9fdaafb 783 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
bae6b562 784 finish ? "exit" : "entry");
f735261b
DA		 785 return in_vbl;
786}
c913e23a 787
ce8f5370 788static void radeon_dynpm_idle_work_handler(struct work_struct *work)
c913e23a
RM		 789{
790 struct radeon_device *rdev;
d9932a32 791 int resched;
c913e23a 792 rdev = container_of(work, struct radeon_device,
ce8f5370 793 pm.dynpm_idle_work.work);
c913e23a 794
d9932a32 795 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
c913e23a 796 mutex_lock(&rdev->pm.mutex);
ce8f5370 797 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
c913e23a
RM		 798 unsigned long irq_flags;
799 int not_processed = 0;
800
801 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
802 if (!list_empty(&rdev->fence_drv.emited)) {
803 struct list_head *ptr;
804 list_for_each(ptr, &rdev->fence_drv.emited) {
805 /* count up to 3, that's enought info */
806 if (++not_processed >= 3)
807 break;
808 }
809 }
810 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
811
812 if (not_processed >= 3) { /* should upclock */
ce8f5370
AD		 813 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
814 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
815 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
816 rdev->pm.dynpm_can_upclock) {
817 rdev->pm.dynpm_planned_action =
818 DYNPM_ACTION_UPCLOCK;
819 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 820 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
821 }
822 } else if (not_processed == 0) { /* should downclock */
ce8f5370
AD		 823 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
824 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
825 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
826 rdev->pm.dynpm_can_downclock) {
827 rdev->pm.dynpm_planned_action =
828 DYNPM_ACTION_DOWNCLOCK;
829 rdev->pm.dynpm_action_timeout = jiffies +
c913e23a
RM		 830 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
831 }
832 }
833
d7311171
AD		 834 /* Note, radeon_pm_set_clocks is called with static_switch set
835 * to false since we want to wait for vbl to avoid flicker.
836 */
ce8f5370
AD		 837 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
838 jiffies > rdev->pm.dynpm_action_timeout) {
839 radeon_pm_get_dynpm_state(rdev);
840 radeon_pm_set_clocks(rdev);
c913e23a 841 }
3f53eb6f 842
32c87fca
TH		 843 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
844 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
c913e23a
RM		 845 }
846 mutex_unlock(&rdev->pm.mutex);
d9932a32 847 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
c913e23a
RM		 848}
849
7433874e
RM		 850/*
851 * Debugfs info
852 */
853#if defined(CONFIG_DEBUG_FS)
854
855static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
856{
857 struct drm_info_node *node = (struct drm_info_node *) m->private;
858 struct drm_device *dev = node->minor->dev;
859 struct radeon_device *rdev = dev->dev_private;
860
9ace9f7b 861 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
6234077d 862 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
9ace9f7b 863 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
6234077d
RM		 864 if (rdev->asic->get_memory_clock)
865 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
0fcbe947
RM		 866 if (rdev->pm.current_vddc)
867 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
aa5120d2
RM		 868 if (rdev->asic->get_pcie_lanes)
869 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
7433874e
RM		 870
871 return 0;
872}
873
874static struct drm_info_list radeon_pm_info_list[] = {
875 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
876};
877#endif
878
c913e23a 879static int radeon_debugfs_pm_init(struct radeon_device *rdev)
7433874e
RM		 880{
881#if defined(CONFIG_DEBUG_FS)
882 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
883#else
884 return 0;
885#endif
886}
kernel source for telekom puls (alcatel/mediatek)