Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2009 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | |
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | |
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | |
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | |
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | |
20 | * | |
21 | * The above copyright notice and this permission notice (including the | |
22 | * next paragraph) shall be included in all copies or substantial portions | |
23 | * of the Software. | |
24 | * | |
25 | */ | |
26 | /* | |
27 | * Authors: | |
28 | * Jerome Glisse <glisse@freedesktop.org> | |
29 | * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> | |
30 | * Dave Airlie | |
31 | */ | |
32 | #include <linux/list.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
771fe6b9 JG |
34 | #include <drm/drmP.h> |
35 | #include "radeon_drm.h" | |
36 | #include "radeon.h" | |
37 | ||
771fe6b9 JG |
38 | |
39 | int radeon_ttm_init(struct radeon_device *rdev); | |
40 | void radeon_ttm_fini(struct radeon_device *rdev); | |
4c788679 | 41 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); |
771fe6b9 JG |
42 | |
43 | /* | |
44 | * To exclude mutual BO access we rely on bo_reserve exclusion, as all | |
45 | * function are calling it. | |
46 | */ | |
47 | ||
4c788679 | 48 | static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) |
771fe6b9 | 49 | { |
4c788679 | 50 | struct radeon_bo *bo; |
771fe6b9 | 51 | |
4c788679 JG |
52 | bo = container_of(tbo, struct radeon_bo, tbo); |
53 | mutex_lock(&bo->rdev->gem.mutex); | |
54 | list_del_init(&bo->list); | |
55 | mutex_unlock(&bo->rdev->gem.mutex); | |
56 | radeon_bo_clear_surface_reg(bo); | |
57 | kfree(bo); | |
771fe6b9 JG |
58 | } |
59 | ||
d03d8589 JG |
60 | bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) |
61 | { | |
62 | if (bo->destroy == &radeon_ttm_bo_destroy) | |
63 | return true; | |
64 | return false; | |
65 | } | |
66 | ||
312ea8da JG |
67 | void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) |
68 | { | |
69 | u32 c = 0; | |
70 | ||
71 | rbo->placement.fpfn = 0; | |
72 | rbo->placement.lpfn = 0; | |
73 | rbo->placement.placement = rbo->placements; | |
74 | rbo->placement.busy_placement = rbo->placements; | |
75 | if (domain & RADEON_GEM_DOMAIN_VRAM) | |
76 | rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | | |
77 | TTM_PL_FLAG_VRAM; | |
78 | if (domain & RADEON_GEM_DOMAIN_GTT) | |
79 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; | |
80 | if (domain & RADEON_GEM_DOMAIN_CPU) | |
81 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
9fb03e63 JG |
82 | if (!c) |
83 | rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; | |
312ea8da JG |
84 | rbo->placement.num_placement = c; |
85 | rbo->placement.num_busy_placement = c; | |
86 | } | |
87 | ||
4c788679 JG |
88 | int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj, |
89 | unsigned long size, bool kernel, u32 domain, | |
90 | struct radeon_bo **bo_ptr) | |
771fe6b9 | 91 | { |
4c788679 | 92 | struct radeon_bo *bo; |
771fe6b9 | 93 | enum ttm_bo_type type; |
771fe6b9 JG |
94 | int r; |
95 | ||
96 | if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) { | |
97 | rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; | |
98 | } | |
99 | if (kernel) { | |
100 | type = ttm_bo_type_kernel; | |
101 | } else { | |
102 | type = ttm_bo_type_device; | |
103 | } | |
4c788679 JG |
104 | *bo_ptr = NULL; |
105 | bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); | |
106 | if (bo == NULL) | |
771fe6b9 | 107 | return -ENOMEM; |
4c788679 JG |
108 | bo->rdev = rdev; |
109 | bo->gobj = gobj; | |
110 | bo->surface_reg = -1; | |
111 | INIT_LIST_HEAD(&bo->list); | |
112 | ||
1fb107fc | 113 | radeon_ttm_placement_from_domain(bo, domain); |
5cc6fbab | 114 | /* Kernel allocation are uninterruptible */ |
1fb107fc JG |
115 | r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, |
116 | &bo->placement, 0, 0, !kernel, NULL, size, | |
117 | &radeon_ttm_bo_destroy); | |
771fe6b9 | 118 | if (unlikely(r != 0)) { |
5cc6fbab TH |
119 | if (r != -ERESTARTSYS) |
120 | dev_err(rdev->dev, | |
1fb107fc JG |
121 | "object_init failed for (%lu, 0x%08X)\n", |
122 | size, domain); | |
771fe6b9 JG |
123 | return r; |
124 | } | |
4c788679 | 125 | *bo_ptr = bo; |
771fe6b9 | 126 | if (gobj) { |
4c788679 JG |
127 | mutex_lock(&bo->rdev->gem.mutex); |
128 | list_add_tail(&bo->list, &rdev->gem.objects); | |
129 | mutex_unlock(&bo->rdev->gem.mutex); | |
771fe6b9 JG |
130 | } |
131 | return 0; | |
132 | } | |
133 | ||
4c788679 | 134 | int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) |
771fe6b9 | 135 | { |
4c788679 | 136 | bool is_iomem; |
771fe6b9 JG |
137 | int r; |
138 | ||
4c788679 | 139 | if (bo->kptr) { |
771fe6b9 | 140 | if (ptr) { |
4c788679 | 141 | *ptr = bo->kptr; |
771fe6b9 | 142 | } |
771fe6b9 JG |
143 | return 0; |
144 | } | |
4c788679 | 145 | r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); |
771fe6b9 JG |
146 | if (r) { |
147 | return r; | |
148 | } | |
4c788679 | 149 | bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); |
771fe6b9 | 150 | if (ptr) { |
4c788679 | 151 | *ptr = bo->kptr; |
771fe6b9 | 152 | } |
4c788679 | 153 | radeon_bo_check_tiling(bo, 0, 0); |
771fe6b9 JG |
154 | return 0; |
155 | } | |
156 | ||
4c788679 | 157 | void radeon_bo_kunmap(struct radeon_bo *bo) |
771fe6b9 | 158 | { |
4c788679 | 159 | if (bo->kptr == NULL) |
771fe6b9 | 160 | return; |
4c788679 JG |
161 | bo->kptr = NULL; |
162 | radeon_bo_check_tiling(bo, 0, 0); | |
163 | ttm_bo_kunmap(&bo->kmap); | |
771fe6b9 JG |
164 | } |
165 | ||
4c788679 | 166 | void radeon_bo_unref(struct radeon_bo **bo) |
771fe6b9 | 167 | { |
4c788679 | 168 | struct ttm_buffer_object *tbo; |
771fe6b9 | 169 | |
4c788679 | 170 | if ((*bo) == NULL) |
771fe6b9 | 171 | return; |
4c788679 JG |
172 | tbo = &((*bo)->tbo); |
173 | ttm_bo_unref(&tbo); | |
174 | if (tbo == NULL) | |
175 | *bo = NULL; | |
771fe6b9 JG |
176 | } |
177 | ||
4c788679 | 178 | int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) |
771fe6b9 | 179 | { |
312ea8da | 180 | int r, i; |
771fe6b9 | 181 | |
4c788679 JG |
182 | if (bo->pin_count) { |
183 | bo->pin_count++; | |
184 | if (gpu_addr) | |
185 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 JG |
186 | return 0; |
187 | } | |
312ea8da | 188 | radeon_ttm_placement_from_domain(bo, domain); |
51e5fcd3 JG |
189 | /* force to pin into visible video ram */ |
190 | bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; | |
312ea8da JG |
191 | for (i = 0; i < bo->placement.num_placement; i++) |
192 | bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; | |
1fb107fc | 193 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
4c788679 JG |
194 | if (likely(r == 0)) { |
195 | bo->pin_count = 1; | |
196 | if (gpu_addr != NULL) | |
197 | *gpu_addr = radeon_bo_gpu_offset(bo); | |
771fe6b9 | 198 | } |
5cc6fbab | 199 | if (unlikely(r != 0)) |
4c788679 | 200 | dev_err(bo->rdev->dev, "%p pin failed\n", bo); |
771fe6b9 JG |
201 | return r; |
202 | } | |
203 | ||
4c788679 | 204 | int radeon_bo_unpin(struct radeon_bo *bo) |
771fe6b9 | 205 | { |
312ea8da | 206 | int r, i; |
771fe6b9 | 207 | |
4c788679 JG |
208 | if (!bo->pin_count) { |
209 | dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); | |
210 | return 0; | |
771fe6b9 | 211 | } |
4c788679 JG |
212 | bo->pin_count--; |
213 | if (bo->pin_count) | |
214 | return 0; | |
312ea8da JG |
215 | for (i = 0; i < bo->placement.num_placement; i++) |
216 | bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; | |
1fb107fc | 217 | r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); |
5cc6fbab | 218 | if (unlikely(r != 0)) |
4c788679 | 219 | dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); |
5cc6fbab | 220 | return r; |
cefb87ef DA |
221 | } |
222 | ||
4c788679 | 223 | int radeon_bo_evict_vram(struct radeon_device *rdev) |
771fe6b9 | 224 | { |
d796d844 DA |
225 | /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ |
226 | if (0 && (rdev->flags & RADEON_IS_IGP)) { | |
06b6476d AD |
227 | if (rdev->mc.igp_sideport_enabled == false) |
228 | /* Useless to evict on IGP chips */ | |
229 | return 0; | |
771fe6b9 JG |
230 | } |
231 | return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); | |
232 | } | |
233 | ||
4c788679 | 234 | void radeon_bo_force_delete(struct radeon_device *rdev) |
771fe6b9 | 235 | { |
4c788679 | 236 | struct radeon_bo *bo, *n; |
771fe6b9 JG |
237 | struct drm_gem_object *gobj; |
238 | ||
239 | if (list_empty(&rdev->gem.objects)) { | |
240 | return; | |
241 | } | |
4c788679 JG |
242 | dev_err(rdev->dev, "Userspace still has active objects !\n"); |
243 | list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { | |
771fe6b9 | 244 | mutex_lock(&rdev->ddev->struct_mutex); |
4c788679 JG |
245 | gobj = bo->gobj; |
246 | dev_err(rdev->dev, "%p %p %lu %lu force free\n", | |
247 | gobj, bo, (unsigned long)gobj->size, | |
248 | *((unsigned long *)&gobj->refcount)); | |
249 | mutex_lock(&bo->rdev->gem.mutex); | |
250 | list_del_init(&bo->list); | |
251 | mutex_unlock(&bo->rdev->gem.mutex); | |
252 | radeon_bo_unref(&bo); | |
771fe6b9 JG |
253 | gobj->driver_private = NULL; |
254 | drm_gem_object_unreference(gobj); | |
255 | mutex_unlock(&rdev->ddev->struct_mutex); | |
256 | } | |
257 | } | |
258 | ||
4c788679 | 259 | int radeon_bo_init(struct radeon_device *rdev) |
771fe6b9 | 260 | { |
a4d68279 JG |
261 | /* Add an MTRR for the VRAM */ |
262 | rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, | |
263 | MTRR_TYPE_WRCOMB, 1); | |
264 | DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", | |
265 | rdev->mc.mc_vram_size >> 20, | |
266 | (unsigned long long)rdev->mc.aper_size >> 20); | |
267 | DRM_INFO("RAM width %dbits %cDR\n", | |
268 | rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); | |
771fe6b9 JG |
269 | return radeon_ttm_init(rdev); |
270 | } | |
271 | ||
4c788679 | 272 | void radeon_bo_fini(struct radeon_device *rdev) |
771fe6b9 JG |
273 | { |
274 | radeon_ttm_fini(rdev); | |
275 | } | |
276 | ||
4c788679 JG |
277 | void radeon_bo_list_add_object(struct radeon_bo_list *lobj, |
278 | struct list_head *head) | |
771fe6b9 JG |
279 | { |
280 | if (lobj->wdomain) { | |
281 | list_add(&lobj->list, head); | |
282 | } else { | |
283 | list_add_tail(&lobj->list, head); | |
284 | } | |
285 | } | |
286 | ||
4c788679 | 287 | int radeon_bo_list_reserve(struct list_head *head) |
771fe6b9 | 288 | { |
4c788679 | 289 | struct radeon_bo_list *lobj; |
771fe6b9 JG |
290 | int r; |
291 | ||
9d8401fc | 292 | list_for_each_entry(lobj, head, list){ |
4c788679 JG |
293 | r = radeon_bo_reserve(lobj->bo, false); |
294 | if (unlikely(r != 0)) | |
295 | return r; | |
771fe6b9 JG |
296 | } |
297 | return 0; | |
298 | } | |
299 | ||
4c788679 | 300 | void radeon_bo_list_unreserve(struct list_head *head) |
771fe6b9 | 301 | { |
4c788679 | 302 | struct radeon_bo_list *lobj; |
771fe6b9 | 303 | |
9d8401fc | 304 | list_for_each_entry(lobj, head, list) { |
4c788679 JG |
305 | /* only unreserve object we successfully reserved */ |
306 | if (radeon_bo_is_reserved(lobj->bo)) | |
307 | radeon_bo_unreserve(lobj->bo); | |
771fe6b9 JG |
308 | } |
309 | } | |
310 | ||
6cb8e1f7 | 311 | int radeon_bo_list_validate(struct list_head *head) |
771fe6b9 | 312 | { |
4c788679 JG |
313 | struct radeon_bo_list *lobj; |
314 | struct radeon_bo *bo; | |
771fe6b9 JG |
315 | int r; |
316 | ||
4c788679 | 317 | r = radeon_bo_list_reserve(head); |
771fe6b9 | 318 | if (unlikely(r != 0)) { |
771fe6b9 JG |
319 | return r; |
320 | } | |
9d8401fc | 321 | list_for_each_entry(lobj, head, list) { |
4c788679 JG |
322 | bo = lobj->bo; |
323 | if (!bo->pin_count) { | |
664f8659 | 324 | if (lobj->wdomain) { |
312ea8da JG |
325 | radeon_ttm_placement_from_domain(bo, |
326 | lobj->wdomain); | |
664f8659 | 327 | } else { |
312ea8da JG |
328 | radeon_ttm_placement_from_domain(bo, |
329 | lobj->rdomain); | |
664f8659 | 330 | } |
1fb107fc | 331 | r = ttm_bo_validate(&bo->tbo, &bo->placement, |
4c788679 | 332 | true, false); |
5cc6fbab | 333 | if (unlikely(r)) |
771fe6b9 | 334 | return r; |
771fe6b9 | 335 | } |
4c788679 JG |
336 | lobj->gpu_offset = radeon_bo_gpu_offset(bo); |
337 | lobj->tiling_flags = bo->tiling_flags; | |
771fe6b9 JG |
338 | } |
339 | return 0; | |
340 | } | |
341 | ||
6cb8e1f7 | 342 | void radeon_bo_list_fence(struct list_head *head, void *fence) |
771fe6b9 | 343 | { |
4c788679 | 344 | struct radeon_bo_list *lobj; |
6cb8e1f7 JG |
345 | struct radeon_bo *bo; |
346 | struct radeon_fence *old_fence = NULL; | |
347 | ||
348 | list_for_each_entry(lobj, head, list) { | |
349 | bo = lobj->bo; | |
350 | spin_lock(&bo->tbo.lock); | |
351 | old_fence = (struct radeon_fence *)bo->tbo.sync_obj; | |
352 | bo->tbo.sync_obj = radeon_fence_ref(fence); | |
353 | bo->tbo.sync_obj_arg = NULL; | |
354 | spin_unlock(&bo->tbo.lock); | |
355 | if (old_fence) { | |
356 | radeon_fence_unref(&old_fence); | |
771fe6b9 | 357 | } |
6cb8e1f7 | 358 | } |
771fe6b9 JG |
359 | } |
360 | ||
4c788679 | 361 | int radeon_bo_fbdev_mmap(struct radeon_bo *bo, |
771fe6b9 JG |
362 | struct vm_area_struct *vma) |
363 | { | |
4c788679 | 364 | return ttm_fbdev_mmap(vma, &bo->tbo); |
771fe6b9 JG |
365 | } |
366 | ||
550e2d92 | 367 | int radeon_bo_get_surface_reg(struct radeon_bo *bo) |
771fe6b9 | 368 | { |
4c788679 | 369 | struct radeon_device *rdev = bo->rdev; |
e024e110 | 370 | struct radeon_surface_reg *reg; |
4c788679 | 371 | struct radeon_bo *old_object; |
e024e110 DA |
372 | int steal; |
373 | int i; | |
374 | ||
4c788679 JG |
375 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
376 | ||
377 | if (!bo->tiling_flags) | |
e024e110 DA |
378 | return 0; |
379 | ||
4c788679 JG |
380 | if (bo->surface_reg >= 0) { |
381 | reg = &rdev->surface_regs[bo->surface_reg]; | |
382 | i = bo->surface_reg; | |
e024e110 DA |
383 | goto out; |
384 | } | |
385 | ||
386 | steal = -1; | |
387 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { | |
388 | ||
389 | reg = &rdev->surface_regs[i]; | |
4c788679 | 390 | if (!reg->bo) |
e024e110 DA |
391 | break; |
392 | ||
4c788679 | 393 | old_object = reg->bo; |
e024e110 DA |
394 | if (old_object->pin_count == 0) |
395 | steal = i; | |
396 | } | |
397 | ||
398 | /* if we are all out */ | |
399 | if (i == RADEON_GEM_MAX_SURFACES) { | |
400 | if (steal == -1) | |
401 | return -ENOMEM; | |
402 | /* find someone with a surface reg and nuke their BO */ | |
403 | reg = &rdev->surface_regs[steal]; | |
4c788679 | 404 | old_object = reg->bo; |
e024e110 DA |
405 | /* blow away the mapping */ |
406 | DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); | |
4c788679 | 407 | ttm_bo_unmap_virtual(&old_object->tbo); |
e024e110 DA |
408 | old_object->surface_reg = -1; |
409 | i = steal; | |
410 | } | |
411 | ||
4c788679 JG |
412 | bo->surface_reg = i; |
413 | reg->bo = bo; | |
e024e110 DA |
414 | |
415 | out: | |
4c788679 JG |
416 | radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, |
417 | bo->tbo.mem.mm_node->start << PAGE_SHIFT, | |
418 | bo->tbo.num_pages << PAGE_SHIFT); | |
e024e110 DA |
419 | return 0; |
420 | } | |
421 | ||
4c788679 | 422 | static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) |
e024e110 | 423 | { |
4c788679 | 424 | struct radeon_device *rdev = bo->rdev; |
e024e110 DA |
425 | struct radeon_surface_reg *reg; |
426 | ||
4c788679 | 427 | if (bo->surface_reg == -1) |
e024e110 DA |
428 | return; |
429 | ||
4c788679 JG |
430 | reg = &rdev->surface_regs[bo->surface_reg]; |
431 | radeon_clear_surface_reg(rdev, bo->surface_reg); | |
e024e110 | 432 | |
4c788679 JG |
433 | reg->bo = NULL; |
434 | bo->surface_reg = -1; | |
e024e110 DA |
435 | } |
436 | ||
4c788679 JG |
437 | int radeon_bo_set_tiling_flags(struct radeon_bo *bo, |
438 | uint32_t tiling_flags, uint32_t pitch) | |
e024e110 | 439 | { |
4c788679 JG |
440 | int r; |
441 | ||
442 | r = radeon_bo_reserve(bo, false); | |
443 | if (unlikely(r != 0)) | |
444 | return r; | |
445 | bo->tiling_flags = tiling_flags; | |
446 | bo->pitch = pitch; | |
447 | radeon_bo_unreserve(bo); | |
448 | return 0; | |
e024e110 DA |
449 | } |
450 | ||
4c788679 JG |
451 | void radeon_bo_get_tiling_flags(struct radeon_bo *bo, |
452 | uint32_t *tiling_flags, | |
453 | uint32_t *pitch) | |
e024e110 | 454 | { |
4c788679 | 455 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
e024e110 | 456 | if (tiling_flags) |
4c788679 | 457 | *tiling_flags = bo->tiling_flags; |
e024e110 | 458 | if (pitch) |
4c788679 | 459 | *pitch = bo->pitch; |
e024e110 DA |
460 | } |
461 | ||
4c788679 JG |
462 | int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, |
463 | bool force_drop) | |
e024e110 | 464 | { |
4c788679 JG |
465 | BUG_ON(!atomic_read(&bo->tbo.reserved)); |
466 | ||
467 | if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) | |
e024e110 DA |
468 | return 0; |
469 | ||
470 | if (force_drop) { | |
4c788679 | 471 | radeon_bo_clear_surface_reg(bo); |
e024e110 DA |
472 | return 0; |
473 | } | |
474 | ||
4c788679 | 475 | if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { |
e024e110 DA |
476 | if (!has_moved) |
477 | return 0; | |
478 | ||
4c788679 JG |
479 | if (bo->surface_reg >= 0) |
480 | radeon_bo_clear_surface_reg(bo); | |
e024e110 DA |
481 | return 0; |
482 | } | |
483 | ||
4c788679 | 484 | if ((bo->surface_reg >= 0) && !has_moved) |
e024e110 DA |
485 | return 0; |
486 | ||
4c788679 | 487 | return radeon_bo_get_surface_reg(bo); |
e024e110 DA |
488 | } |
489 | ||
490 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
d03d8589 | 491 | struct ttm_mem_reg *mem) |
e024e110 | 492 | { |
d03d8589 JG |
493 | struct radeon_bo *rbo; |
494 | if (!radeon_ttm_bo_is_radeon_bo(bo)) | |
495 | return; | |
496 | rbo = container_of(bo, struct radeon_bo, tbo); | |
4c788679 | 497 | radeon_bo_check_tiling(rbo, 0, 1); |
e024e110 DA |
498 | } |
499 | ||
500 | void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) | |
501 | { | |
d03d8589 JG |
502 | struct radeon_bo *rbo; |
503 | if (!radeon_ttm_bo_is_radeon_bo(bo)) | |
504 | return; | |
505 | rbo = container_of(bo, struct radeon_bo, tbo); | |
4c788679 | 506 | radeon_bo_check_tiling(rbo, 0, 0); |
e024e110 | 507 | } |