[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon.h"
#include "radeon_reg.h"

/*
 * Common GART table functions.
 */
int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
{
	void *ptr;

	ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
				   &rdev->gart.table_addr);
	if (ptr == NULL) {
		return -ENOMEM;
	}
#ifdef CONFIG_X86
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
		set_memory_uc((unsigned long)ptr,
			      rdev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	rdev->gart.table.ram.ptr = ptr;
	memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
	return 0;
}

void radeon_gart_table_ram_free(struct radeon_device *rdev)
{
	if (rdev->gart.table.ram.ptr == NULL) {
		return;
	}
#ifdef CONFIG_X86
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
	    rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
		set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
			      rdev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	pci_free_consistent(rdev->pdev, rdev->gart.table_size,
			    (void *)rdev->gart.table.ram.ptr,
			    rdev->gart.table_addr);
	rdev->gart.table.ram.ptr = NULL;
	rdev->gart.table_addr = 0;
}

int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.table.vram.robj == NULL) {
		r = radeon_bo_create(rdev, rdev->gart.table_size,
				     PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
				     &rdev->gart.table.vram.robj);
		if (r) {
			return r;
		}
	}
	return 0;
}

int radeon_gart_table_vram_pin(struct radeon_device *rdev)
{
	uint64_t gpu_addr;
	int r;

	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
	if (unlikely(r != 0))
		return r;
	r = radeon_bo_pin(rdev->gart.table.vram.robj,
				RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->gart.table.vram.robj);
		return r;
	}
	r = radeon_bo_kmap(rdev->gart.table.vram.robj,
				(void **)&rdev->gart.table.vram.ptr);
	if (r)
		radeon_bo_unpin(rdev->gart.table.vram.robj);
	radeon_bo_unreserve(rdev->gart.table.vram.robj);
	rdev->gart.table_addr = gpu_addr;
	return r;
}

void radeon_gart_table_vram_free(struct radeon_device *rdev)
{
	int r;

	if (rdev->gart.table.vram.robj == NULL) {
		return;
	}
	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
	if (likely(r == 0)) {
		radeon_bo_kunmap(rdev->gart.table.vram.robj);
		radeon_bo_unpin(rdev->gart.table.vram.robj);
		radeon_bo_unreserve(rdev->gart.table.vram.robj);
	}
	radeon_bo_unref(&rdev->gart.table.vram.robj);
}


/*
 * Common gart functions.
 */
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;
	u64 page_base;

	if (!rdev->gart.ready) {
		WARN(1, "trying to unbind memory to unitialized GART !\n");
		return;
	}
	t = offset / RADEON_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
	for (i = 0; i < pages; i++, p++) {
		if (rdev->gart.pages[p]) {
			if (!rdev->gart.ttm_alloced[p])
				pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
				       		PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
			rdev->gart.pages[p] = NULL;
			rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
			page_base = rdev->gart.pages_addr[p];
			for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
				radeon_gart_set_page(rdev, t, page_base);
				page_base += RADEON_GPU_PAGE_SIZE;
			}
		}
	}
	mb();
	radeon_gart_tlb_flush(rdev);
}

int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
		     int pages, struct page **pagelist, dma_addr_t *dma_addr)
{
	unsigned t;
	unsigned p;
	uint64_t page_base;
	int i, j;

	if (!rdev->gart.ready) {
		WARN(1, "trying to bind memory to unitialized GART !\n");
		return -EINVAL;
	}
	t = offset / RADEON_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);

	for (i = 0; i < pages; i++, p++) {
		/* On TTM path, we only use the DMA API if TTM_PAGE_FLAG_DMA32
		 * is requested. */
		if (dma_addr[i] != DMA_ERROR_CODE) {
			rdev->gart.ttm_alloced[p] = true;
			rdev->gart.pages_addr[p] = dma_addr[i];
		} else {
			/* we need to support large memory configurations */
			/* assume that unbind have already been call on the range */
			rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i],
							0, PAGE_SIZE,
							PCI_DMA_BIDIRECTIONAL);
			if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) {
				/* FIXME: failed to map page (return -ENOMEM?) */
				radeon_gart_unbind(rdev, offset, pages);
				return -ENOMEM;
			}
		}
		rdev->gart.pages[p] = pagelist[i];
		page_base = rdev->gart.pages_addr[p];
		for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
			radeon_gart_set_page(rdev, t, page_base);
			page_base += RADEON_GPU_PAGE_SIZE;
		}
	}
	mb();
	radeon_gart_tlb_flush(rdev);
	return 0;
}

void radeon_gart_restore(struct radeon_device *rdev)
{
	int i, j, t;
	u64 page_base;

	for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
		page_base = rdev->gart.pages_addr[i];
		for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
			radeon_gart_set_page(rdev, t, page_base);
			page_base += RADEON_GPU_PAGE_SIZE;
		}
	}
	mb();
	radeon_gart_tlb_flush(rdev);
}

int radeon_gart_init(struct radeon_device *rdev)
{
	int r, i;

	if (rdev->gart.pages) {
		return 0;
	}
	/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
	if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = radeon_dummy_page_init(rdev);
	if (r)
		return r;
	/* Compute table size */
	rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
	rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
	/* Allocate pages table */
	rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages,
				   GFP_KERNEL);
	if (rdev->gart.pages == NULL) {
		radeon_gart_fini(rdev);
		return -ENOMEM;
	}
	rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
					rdev->gart.num_cpu_pages, GFP_KERNEL);
	if (rdev->gart.pages_addr == NULL) {
		radeon_gart_fini(rdev);
		return -ENOMEM;
	}
	rdev->gart.ttm_alloced = kzalloc(sizeof(bool) *
					 rdev->gart.num_cpu_pages, GFP_KERNEL);
	if (rdev->gart.ttm_alloced == NULL) {
		radeon_gart_fini(rdev);
		return -ENOMEM;
	}
	/* set GART entry to point to the dummy page by default */
	for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
		rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
	}
	return 0;
}

void radeon_gart_fini(struct radeon_device *rdev)
{
	if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
		/* unbind pages */
		radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
	}
	rdev->gart.ready = false;
	kfree(rdev->gart.pages);
	kfree(rdev->gart.pages_addr);
	kfree(rdev->gart.ttm_alloced);
	rdev->gart.pages = NULL;
	rdev->gart.pages_addr = NULL;
	rdev->gart.ttm_alloced = NULL;

	radeon_dummy_page_fini(rdev);
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include "drmP.h"
	29	#include "radeon_drm.h"
	30	#include "radeon.h"
	31	#include "radeon_reg.h"
	32
	33	/*
	34	* Common GART table functions.
	35	*/
	36	int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
	37	{
	38	void *ptr;
	39
	40	ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
	41	&rdev->gart.table_addr);
	42	if (ptr == NULL) {
	43	return -ENOMEM;
	44	}
	45	#ifdef CONFIG_X86
	46	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480 \|\|
	47	rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
	48	set_memory_uc((unsigned long)ptr,
	49	rdev->gart.table_size >> PAGE_SHIFT);
	50	}
	51	#endif
	52	rdev->gart.table.ram.ptr = ptr;
	53	memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
	54	return 0;
	55	}
	56
	57	void radeon_gart_table_ram_free(struct radeon_device *rdev)
	58	{
	59	if (rdev->gart.table.ram.ptr == NULL) {
	60	return;
	61	}
	62	#ifdef CONFIG_X86
	63	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480 \|\|
	64	rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
65	set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
66	rdev->gart.table_size >> PAGE_SHIFT);
67	}
68	#endif
69	pci_free_consistent(rdev->pdev, rdev->gart.table_size,
70	(void *)rdev->gart.table.ram.ptr,
71	rdev->gart.table_addr);
72	rdev->gart.table.ram.ptr = NULL;
73	rdev->gart.table_addr = 0;
74	}
75
76	int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
77	{
771fe6b9 JG	78	int r;
	79
	80	if (rdev->gart.table.vram.robj == NULL) {
441921d5	81	r = radeon_bo_create(rdev, rdev->gart.table_size,
268b2510 AD	82	PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
268b2510 AD	83	&rdev->gart.table.vram.robj);
771fe6b9 JG	84	if (r) {
	85	return r;
	86	}
	87	}
4aac0473 JG	88	return 0;
	89	}
	90
	91	int radeon_gart_table_vram_pin(struct radeon_device *rdev)
	92	{
	93	uint64_t gpu_addr;
	94	int r;
	95
4c788679 JG	96	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
4c788679 JG	97	if (unlikely(r != 0))
771fe6b9	98	return r;
4c788679 JG	99	r = radeon_bo_pin(rdev->gart.table.vram.robj,
4c788679 JG	100	RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
771fe6b9	101	if (r) {
4c788679	102	radeon_bo_unreserve(rdev->gart.table.vram.robj);
771fe6b9 JG	103	return r;
771fe6b9 JG	104	}
4c788679 JG	105	r = radeon_bo_kmap(rdev->gart.table.vram.robj,
	106	(void **)&rdev->gart.table.vram.ptr);
	107	if (r)
	108	radeon_bo_unpin(rdev->gart.table.vram.robj);
	109	radeon_bo_unreserve(rdev->gart.table.vram.robj);
771fe6b9	110	rdev->gart.table_addr = gpu_addr;
4c788679	111	return r;
771fe6b9 JG	112	}
	113
	114	void radeon_gart_table_vram_free(struct radeon_device *rdev)
	115	{
4c788679 JG	116	int r;
4c788679 JG	117
771fe6b9 JG	118	if (rdev->gart.table.vram.robj == NULL) {
	119	return;
	120	}
4c788679 JG	121	r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
	122	if (likely(r == 0)) {
	123	radeon_bo_kunmap(rdev->gart.table.vram.robj);
	124	radeon_bo_unpin(rdev->gart.table.vram.robj);
	125	radeon_bo_unreserve(rdev->gart.table.vram.robj);
	126	}
	127	radeon_bo_unref(&rdev->gart.table.vram.robj);
771fe6b9 JG	128	}
	129
	130
	131
	132
	133	/*
	134	* Common gart functions.
	135	*/
	136	void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
	137	int pages)
	138	{
	139	unsigned t;
	140	unsigned p;
	141	int i, j;
82568565	142	u64 page_base;
771fe6b9 JG	143
	144	if (!rdev->gart.ready) {
	145	WARN(1, "trying to unbind memory to unitialized GART !\n");
	146	return;
	147	}
a77f1718 MT	148	t = offset / RADEON_GPU_PAGE_SIZE;
a77f1718 MT	149	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
771fe6b9 JG	150	for (i = 0; i < pages; i++, p++) {
771fe6b9 JG	151	if (rdev->gart.pages[p]) {
c39d3516 KRW	152	if (!rdev->gart.ttm_alloced[p])
	153	pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
	154	PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
771fe6b9	155	rdev->gart.pages[p] = NULL;
82568565 DA	156	rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
82568565 DA	157	page_base = rdev->gart.pages_addr[p];
a77f1718	158	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
82568565 DA	159	radeon_gart_set_page(rdev, t, page_base);
82568565 DA	160	page_base += RADEON_GPU_PAGE_SIZE;
771fe6b9 JG	161	}
	162	}
	163	}
	164	mb();
	165	radeon_gart_tlb_flush(rdev);
	166	}
	167
	168	int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516	169	int pages, struct page *pagelist, dma_addr_t dma_addr)
771fe6b9 JG	170	{
	171	unsigned t;
	172	unsigned p;
	173	uint64_t page_base;
	174	int i, j;
	175
	176	if (!rdev->gart.ready) {
90aca4d2	177	WARN(1, "trying to bind memory to unitialized GART !\n");
771fe6b9 JG	178	return -EINVAL;
771fe6b9 JG	179	}
a77f1718 MT	180	t = offset / RADEON_GPU_PAGE_SIZE;
a77f1718 MT	181	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
771fe6b9 JG	182
771fe6b9 JG	183	for (i = 0; i < pages; i++, p++) {
c39d3516 KRW	184	/* On TTM path, we only use the DMA API if TTM_PAGE_FLAG_DMA32
	185	* is requested. */
	186	if (dma_addr[i] != DMA_ERROR_CODE) {
	187	rdev->gart.ttm_alloced[p] = true;
	188	rdev->gart.pages_addr[p] = dma_addr[i];
	189	} else {
	190	/* we need to support large memory configurations */
	191	/* assume that unbind have already been call on the range */
	192	rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i],
771fe6b9 JG	193	0, PAGE_SIZE,
771fe6b9 JG	194	PCI_DMA_BIDIRECTIONAL);
c39d3516 KRW	195	if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) {
	196	/* FIXME: failed to map page (return -ENOMEM?) */
	197	radeon_gart_unbind(rdev, offset, pages);
	198	return -ENOMEM;
	199	}
771fe6b9 JG	200	}
771fe6b9 JG	201	rdev->gart.pages[p] = pagelist[i];
ed10f95d	202	page_base = rdev->gart.pages_addr[p];
a77f1718	203	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
771fe6b9	204	radeon_gart_set_page(rdev, t, page_base);
a77f1718	205	page_base += RADEON_GPU_PAGE_SIZE;
771fe6b9 JG	206	}
	207	}
	208	mb();
	209	radeon_gart_tlb_flush(rdev);
	210	return 0;
	211	}
	212
82568565 DA	213	void radeon_gart_restore(struct radeon_device *rdev)
	214	{
	215	int i, j, t;
	216	u64 page_base;
	217
	218	for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
	219	page_base = rdev->gart.pages_addr[i];
	220	for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
	221	radeon_gart_set_page(rdev, t, page_base);
	222	page_base += RADEON_GPU_PAGE_SIZE;
	223	}
	224	}
	225	mb();
	226	radeon_gart_tlb_flush(rdev);
	227	}
	228
771fe6b9 JG	229	int radeon_gart_init(struct radeon_device *rdev)
771fe6b9 JG	230	{
82568565 DA	231	int r, i;
82568565 DA	232
771fe6b9 JG	233	if (rdev->gart.pages) {
	234	return 0;
	235	}
a77f1718 MT	236	/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
a77f1718 MT	237	if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
771fe6b9 JG	238	DRM_ERROR("Page size is smaller than GPU page size!\n");
	239	return -EINVAL;
	240	}
82568565 DA	241	r = radeon_dummy_page_init(rdev);
	242	if (r)
	243	return r;
771fe6b9 JG	244	/* Compute table size */
771fe6b9 JG	245	rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
a77f1718	246	rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
771fe6b9 JG	247	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
	248	rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
	249	/* Allocate pages table */
	250	rdev->gart.pages = kzalloc(sizeof(void ) rdev->gart.num_cpu_pages,
	251	GFP_KERNEL);
	252	if (rdev->gart.pages == NULL) {
	253	radeon_gart_fini(rdev);
	254	return -ENOMEM;
	255	}
	256	rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
	257	rdev->gart.num_cpu_pages, GFP_KERNEL);
	258	if (rdev->gart.pages_addr == NULL) {
	259	radeon_gart_fini(rdev);
	260	return -ENOMEM;
	261	}
c39d3516 KRW	262	rdev->gart.ttm_alloced = kzalloc(sizeof(bool) *
	263	rdev->gart.num_cpu_pages, GFP_KERNEL);
	264	if (rdev->gart.ttm_alloced == NULL) {
	265	radeon_gart_fini(rdev);
	266	return -ENOMEM;
	267	}
82568565 DA	268	/* set GART entry to point to the dummy page by default */
	269	for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
	270	rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
	271	}
771fe6b9 JG	272	return 0;
	273	}
	274
	275	void radeon_gart_fini(struct radeon_device *rdev)
	276	{
	277	if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
	278	/* unbind pages */
	279	radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
	280	}
	281	rdev->gart.ready = false;
	282	kfree(rdev->gart.pages);
	283	kfree(rdev->gart.pages_addr);
c39d3516	284	kfree(rdev->gart.ttm_alloced);
771fe6b9 JG	285	rdev->gart.pages = NULL;
771fe6b9 JG	286	rdev->gart.pages_addr = NULL;
c39d3516	287	rdev->gart.ttm_alloced = NULL;
92656d70 AD	288
92656d70 AD	289	radeon_dummy_page_fini(rdev);
771fe6b9	290	}