[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
    /*
     *  Modularization
     */

#include <linux/module.h>
#include <linux/fb.h>

#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "radeon_drm.h"
#include "radeon.h"

#include "drm_fb_helper.h"

struct radeon_fb_device {
	struct drm_fb_helper helper;
	struct radeon_framebuffer	*rfb;
	struct radeon_device		*rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_setcolreg = drm_fb_helper_setcolreg,
	.fb_fillrect = cfb_fillrect,
	.fb_copyarea = cfb_copyarea,
	.fb_imageblit = cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
};

/**
 * Curretly it is assumed that the old framebuffer is reused.
 *
 * LOCKING
 * caller should hold the mode config lock.
 *
 */
int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
{
	struct fb_info *info;
	struct drm_framebuffer *fb;
	struct drm_display_mode *mode = crtc->desired_mode;

	fb = crtc->fb;
	if (fb == NULL) {
		return 1;
	}
	info = fb->fbdev;
	if (info == NULL) {
		return 1;
	}
	if (mode == NULL) {
		return 1;
	}
	info->var.xres = mode->hdisplay;
	info->var.right_margin = mode->hsync_start - mode->hdisplay;
	info->var.hsync_len = mode->hsync_end - mode->hsync_start;
	info->var.left_margin = mode->htotal - mode->hsync_end;
	info->var.yres = mode->vdisplay;
	info->var.lower_margin = mode->vsync_start - mode->vdisplay;
	info->var.vsync_len = mode->vsync_end - mode->vsync_start;
	info->var.upper_margin = mode->vtotal - mode->vsync_end;
	info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
	/* avoid overflow */
	info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;

	return 0;
}
EXPORT_SYMBOL(radeonfb_resize);

static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
};

int radeonfb_create(struct drm_device *dev,
		    uint32_t fb_width, uint32_t fb_height,
		    uint32_t surface_width, uint32_t surface_height,
		    uint32_t surface_depth, uint32_t surface_bpp,
		    struct drm_framebuffer **fb_p)
{
	struct radeon_device *rdev = dev->dev_private;
	struct fb_info *info;
	struct radeon_fb_device *rfbdev;
	struct drm_framebuffer *fb = NULL;
	struct radeon_framebuffer *rfb;
	struct drm_mode_fb_cmd mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_object *robj = NULL;
	struct device *device = &rdev->pdev->dev;
	int size, aligned_size, ret;
	u64 fb_gpuaddr;
	void *fbptr = NULL;
	unsigned long tmp;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;

	mode_cmd.width = surface_width;
	mode_cmd.height = surface_height;
	mode_cmd.bpp = surface_bpp;
	/* need to align pitch with crtc limits */
	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
	mode_cmd.depth = surface_depth;

	size = mode_cmd.pitch * mode_cmd.height;
	aligned_size = ALIGN(size, PAGE_SIZE);

	ret = radeon_gem_object_create(rdev, aligned_size, 0,
			RADEON_GEM_DOMAIN_VRAM,
			false, ttm_bo_type_kernel,
			false, &gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
		       surface_width, surface_height);
		ret = -ENOMEM;
		goto out;
	}
	robj = gobj->driver_private;

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (mode_cmd.bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags)
		radeon_object_set_tiling_flags(robj, tiling_flags | RADEON_TILING_SURFACE, mode_cmd.pitch);
	mutex_lock(&rdev->ddev->struct_mutex);
	fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
	if (fb == NULL) {
		DRM_ERROR("failed to allocate fb.\n");
		ret = -ENOMEM;
		goto out_unref;
	}
	ret = radeon_object_pin(robj, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	if (ret) {
		printk(KERN_ERR "failed to pin framebuffer\n");
		ret = -ENOMEM;
		goto out_unref;
	}

	list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);

	*fb_p = fb;
	rfb = to_radeon_framebuffer(fb);
	rdev->fbdev_rfb = rfb;
	rdev->fbdev_robj = robj;

	info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
	if (info == NULL) {
		ret = -ENOMEM;
		goto out_unref;
	}

	rdev->fbdev_info = info;
	rfbdev = info->par;
	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
	rfbdev->helper.dev = dev;
	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2,
					    RADEONFB_CONN_LIMIT);
	if (ret)
		goto out_unref;

	if (fb_tiled)
		radeon_object_check_tiling(robj, 0, 0);

	ret = radeon_object_kmap(robj, &fbptr);
	if (ret) {
		goto out_unref;
	}

	memset_io(fbptr, 0, aligned_size);

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitch);

	info->flags = FBINFO_DEFAULT;
	info->fbops = &radeonfb_ops;

	tmp = fb_gpuaddr - rdev->mc.vram_location;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = size;
	info->screen_base = fbptr;
	info->screen_size = size;

	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->aperture_base = rdev->ddev->mode_config.fb_base;
	info->aperture_size = rdev->mc.real_vram_size;

	info->fix.mmio_start = 0;
	info->fix.mmio_len = 0;
	info->pixmap.size = 64*1024;
	info->pixmap.buf_align = 8;
	info->pixmap.access_align = 32;
	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	info->pixmap.scan_align = 1;
	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_unref;
	}
	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)size);
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitch);

	fb->fbdev = info;
	rfbdev->rfb = rfb;
	rfbdev->rdev = rdev;

	mutex_unlock(&rdev->ddev->struct_mutex);
	return 0;

out_unref:
	if (robj) {
		radeon_object_kunmap(robj);
	}
	if (fb && ret) {
		list_del(&fb->filp_head);
		drm_gem_object_unreference(gobj);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	drm_gem_object_unreference(gobj);
	mutex_unlock(&rdev->ddev->struct_mutex);
out:
	return ret;
}

static char *mode_option;
int radeon_parse_options(char *options)
{
	char *this_opt;

	if (!options || !*options)
		return 0;

	while ((this_opt = strsep(&options, ",")) != NULL) {
		if (!*this_opt)
			continue;
		mode_option = this_opt;
	}
	return 0;
}

int radeonfb_probe(struct drm_device *dev)
{
	return drm_fb_helper_single_fb_probe(dev, &radeonfb_create);
}

int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
{
	struct fb_info *info;
	struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
	struct radeon_object *robj;

	if (!fb) {
		return -EINVAL;
	}
	info = fb->fbdev;
	if (info) {
		struct radeon_fb_device *rfbdev = info->par;
		robj = rfb->obj->driver_private;
		unregister_framebuffer(info);
		radeon_object_kunmap(robj);
		radeon_object_unpin(robj);
		drm_fb_helper_free(&rfbdev->helper);
		framebuffer_release(info);
	}

	printk(KERN_INFO "unregistered panic notifier\n");

	return 0;
}
EXPORT_SYMBOL(radeonfb_remove);
MODULE_LICENSE("GPL");
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
	26	/*
	27	* Modularization
	28	*/
	29
	30	#include <linux/module.h>
771fe6b9	31	#include <linux/fb.h>
771fe6b9 JG	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "drm_crtc.h"
	36	#include "drm_crtc_helper.h"
	37	#include "radeon_drm.h"
	38	#include "radeon.h"
	39
785b93ef DA	40	#include "drm_fb_helper.h"
785b93ef DA	41
771fe6b9	42	struct radeon_fb_device {
785b93ef	43	struct drm_fb_helper helper;
771fe6b9	44	struct radeon_framebuffer *rfb;
785b93ef	45	struct radeon_device *rdev;
771fe6b9 JG	46	};
771fe6b9 JG	47
771fe6b9 JG	48	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	49	.owner = THIS_MODULE,
c88f9f0c	50	.fb_check_var = drm_fb_helper_check_var,
785b93ef DA	51	.fb_set_par = drm_fb_helper_set_par,
785b93ef DA	52	.fb_setcolreg = drm_fb_helper_setcolreg,
771fe6b9 JG	53	.fb_fillrect = cfb_fillrect,
	54	.fb_copyarea = cfb_copyarea,
	55	.fb_imageblit = cfb_imageblit,
785b93ef DA	56	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	57	.fb_blank = drm_fb_helper_blank,
771fe6b9 JG	58	};
	59
	60	/**
	61	* Curretly it is assumed that the old framebuffer is reused.
	62	*
	63	* LOCKING
	64	* caller should hold the mode config lock.
	65	*
	66	*/
	67	int radeonfb_resize(struct drm_device dev, struct drm_crtc crtc)
	68	{
	69	struct fb_info *info;
	70	struct drm_framebuffer *fb;
	71	struct drm_display_mode *mode = crtc->desired_mode;
	72
	73	fb = crtc->fb;
	74	if (fb == NULL) {
	75	return 1;
	76	}
	77	info = fb->fbdev;
	78	if (info == NULL) {
	79	return 1;
	80	}
	81	if (mode == NULL) {
	82	return 1;
	83	}
	84	info->var.xres = mode->hdisplay;
	85	info->var.right_margin = mode->hsync_start - mode->hdisplay;
	86	info->var.hsync_len = mode->hsync_end - mode->hsync_start;
	87	info->var.left_margin = mode->htotal - mode->hsync_end;
	88	info->var.yres = mode->vdisplay;
	89	info->var.lower_margin = mode->vsync_start - mode->vdisplay;
	90	info->var.vsync_len = mode->vsync_end - mode->vsync_start;
	91	info->var.upper_margin = mode->vtotal - mode->vsync_end;
	92	info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
	93	/* avoid overflow */
	94	info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;
	95
	96	return 0;
	97	}
	98	EXPORT_SYMBOL(radeonfb_resize);
	99
e024e110	100	static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	101	{
771fe6b9 JG	102	int aligned = width;
e024e110	103	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	104	int pitch_mask = 0;
	105
	106	switch (bpp / 8) {
	107	case 1:
	108	pitch_mask = align_large ? 255 : 127;
	109	break;
	110	case 2:
	111	pitch_mask = align_large ? 127 : 31;
	112	break;
	113	case 3:
	114	case 4:
	115	pitch_mask = align_large ? 63 : 15;
	116	break;
	117	}
	118
	119	aligned += pitch_mask;
	120	aligned &= ~pitch_mask;
	121	return aligned;
	122	}
	123
785b93ef DA	124	static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	125	.gamma_set = radeon_crtc_fb_gamma_set,
	126	};
	127
	128	int radeonfb_create(struct drm_device *dev,
771fe6b9 JG	129	uint32_t fb_width, uint32_t fb_height,
771fe6b9 JG	130	uint32_t surface_width, uint32_t surface_height,
d50ba256	131	uint32_t surface_depth, uint32_t surface_bpp,
785b93ef	132	struct drm_framebuffer **fb_p)
771fe6b9	133	{
785b93ef	134	struct radeon_device *rdev = dev->dev_private;
771fe6b9 JG	135	struct fb_info *info;
771fe6b9 JG	136	struct radeon_fb_device *rfbdev;
f92e93eb	137	struct drm_framebuffer *fb = NULL;
771fe6b9 JG	138	struct radeon_framebuffer *rfb;
	139	struct drm_mode_fb_cmd mode_cmd;
	140	struct drm_gem_object *gobj = NULL;
	141	struct radeon_object *robj = NULL;
	142	struct device *device = &rdev->pdev->dev;
	143	int size, aligned_size, ret;
f92e93eb	144	u64 fb_gpuaddr;
771fe6b9	145	void *fbptr = NULL;
f92e93eb	146	unsigned long tmp;
e024e110	147	bool fb_tiled = false; /* useful for testing */
c88f9f0c	148	u32 tiling_flags = 0;
771fe6b9 JG	149
	150	mode_cmd.width = surface_width;
	151	mode_cmd.height = surface_height;
d50ba256	152	mode_cmd.bpp = surface_bpp;
771fe6b9	153	/* need to align pitch with crtc limits */
e024e110	154	mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
d50ba256	155	mode_cmd.depth = surface_depth;
771fe6b9 JG	156
	157	size = mode_cmd.pitch * mode_cmd.height;
	158	aligned_size = ALIGN(size, PAGE_SIZE);
	159
	160	ret = radeon_gem_object_create(rdev, aligned_size, 0,
f92e93eb JG	161	RADEON_GEM_DOMAIN_VRAM,
	162	false, ttm_bo_type_kernel,
	163	false, &gobj);
771fe6b9	164	if (ret) {
f92e93eb JG	165	printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
f92e93eb JG	166	surface_width, surface_height);
771fe6b9 JG	167	ret = -ENOMEM;
	168	goto out;
	169	}
	170	robj = gobj->driver_private;
	171
e024e110	172	if (fb_tiled)
c88f9f0c MD	173	tiling_flags = RADEON_TILING_MACRO;
	174
	175	#ifdef __BIG_ENDIAN
	176	switch (mode_cmd.bpp) {
	177	case 32:
	178	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	179	break;
	180	case 16:
	181	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	182	default:
	183	break;
	184	}
	185	#endif
	186
	187	if (tiling_flags)
	188	radeon_object_set_tiling_flags(robj, tiling_flags \| RADEON_TILING_SURFACE, mode_cmd.pitch);
771fe6b9 JG	189	mutex_lock(&rdev->ddev->struct_mutex);
	190	fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
	191	if (fb == NULL) {
	192	DRM_ERROR("failed to allocate fb.\n");
	193	ret = -ENOMEM;
	194	goto out_unref;
	195	}
f92e93eb JG	196	ret = radeon_object_pin(robj, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
	197	if (ret) {
	198	printk(KERN_ERR "failed to pin framebuffer\n");
	199	ret = -ENOMEM;
	200	goto out_unref;
	201	}
771fe6b9 JG	202
	203	list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
	204
785b93ef	205	*fb_p = fb;
771fe6b9	206	rfb = to_radeon_framebuffer(fb);
771fe6b9	207	rdev->fbdev_rfb = rfb;
f92e93eb	208	rdev->fbdev_robj = robj;
771fe6b9 JG	209
	210	info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
	211	if (info == NULL) {
	212	ret = -ENOMEM;
	213	goto out_unref;
	214	}
785b93ef	215
2f9a60d7	216	rdev->fbdev_info = info;
771fe6b9	217	rfbdev = info->par;
785b93ef DA	218	rfbdev->helper.funcs = &radeon_fb_helper_funcs;
	219	rfbdev->helper.dev = dev;
	220	ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2,
	221	RADEONFB_CONN_LIMIT);
	222	if (ret)
	223	goto out_unref;
771fe6b9	224
e024e110 DA	225	if (fb_tiled)
	226	radeon_object_check_tiling(robj, 0, 0);
	227
771fe6b9 JG	228	ret = radeon_object_kmap(robj, &fbptr);
	229	if (ret) {
	230	goto out_unref;
	231	}
	232
bf8e828b DA	233	memset_io(fbptr, 0, aligned_size);
bf8e828b DA	234
771fe6b9	235	strcpy(info->fix.id, "radeondrmfb");
785b93ef DA	236
	237	drm_fb_helper_fill_fix(info, fb->pitch);
	238
771fe6b9 JG	239	info->flags = FBINFO_DEFAULT;
771fe6b9 JG	240	info->fbops = &radeonfb_ops;
785b93ef	241
f92e93eb JG	242	tmp = fb_gpuaddr - rdev->mc.vram_location;
f92e93eb JG	243	info->fix.smem_start = rdev->mc.aper_base + tmp;
771fe6b9 JG	244	info->fix.smem_len = size;
	245	info->screen_base = fbptr;
	246	info->screen_size = size;
785b93ef DA	247
785b93ef DA	248	drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
ed8f0d9e DA	249
	250	/* setup aperture base/size for vesafb takeover */
	251	info->aperture_base = rdev->ddev->mode_config.fb_base;
	252	info->aperture_size = rdev->mc.real_vram_size;
	253
696d4df1 MD	254	info->fix.mmio_start = 0;
696d4df1 MD	255	info->fix.mmio_len = 0;
771fe6b9 JG	256	info->pixmap.size = 64*1024;
	257	info->pixmap.buf_align = 8;
	258	info->pixmap.access_align = 32;
	259	info->pixmap.flags = FB_PIXMAP_SYSTEM;
	260	info->pixmap.scan_align = 1;
	261	if (info->screen_base == NULL) {
	262	ret = -ENOSPC;
	263	goto out_unref;
	264	}
	265	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
	266	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
	267	DRM_INFO("size %lu\n", (unsigned long)size);
	268	DRM_INFO("fb depth is %d\n", fb->depth);
	269	DRM_INFO(" pitch is %d\n", fb->pitch);
	270
771fe6b9 JG	271	fb->fbdev = info;
	272	rfbdev->rfb = rfb;
	273	rfbdev->rdev = rdev;
	274
	275	mutex_unlock(&rdev->ddev->struct_mutex);
	276	return 0;
	277
	278	out_unref:
	279	if (robj) {
	280	radeon_object_kunmap(robj);
	281	}
f92e93eb	282	if (fb && ret) {
771fe6b9 JG	283	list_del(&fb->filp_head);
	284	drm_gem_object_unreference(gobj);
	285	drm_framebuffer_cleanup(fb);
	286	kfree(fb);
	287	}
	288	drm_gem_object_unreference(gobj);
	289	mutex_unlock(&rdev->ddev->struct_mutex);
	290	out:
	291	return ret;
	292	}
	293
d50ba256 DA	294	static char *mode_option;
	295	int radeon_parse_options(char *options)
	296	{
	297	char *this_opt;
	298
	299	if (!options \|\| !*options)
	300	return 0;
	301
	302	while ((this_opt = strsep(&options, ",")) != NULL) {
	303	if (!*this_opt)
	304	continue;
	305	mode_option = this_opt;
	306	}
	307	return 0;
	308	}
	309
771fe6b9 JG	310	int radeonfb_probe(struct drm_device *dev)
771fe6b9 JG	311	{
d50ba256	312	return drm_fb_helper_single_fb_probe(dev, &radeonfb_create);
771fe6b9	313	}
771fe6b9 JG	314
	315	int radeonfb_remove(struct drm_device dev, struct drm_framebuffer fb)
	316	{
	317	struct fb_info *info;
	318	struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
	319	struct radeon_object *robj;
	320
	321	if (!fb) {
	322	return -EINVAL;
	323	}
	324	info = fb->fbdev;
	325	if (info) {
785b93ef	326	struct radeon_fb_device *rfbdev = info->par;
771fe6b9 JG	327	robj = rfb->obj->driver_private;
	328	unregister_framebuffer(info);
	329	radeon_object_kunmap(robj);
f92e93eb	330	radeon_object_unpin(robj);
785b93ef	331	drm_fb_helper_free(&rfbdev->helper);
771fe6b9 JG	332	framebuffer_release(info);
	333	}
	334
	335	printk(KERN_INFO "unregistered panic notifier\n");
785b93ef	336
771fe6b9 JG	337	return 0;
	338	}
	339	EXPORT_SYMBOL(radeonfb_remove);
	340	MODULE_LICENSE("GPL");