Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright © 2007 David Airlie | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * David Airlie | |
25 | */ | |
771fe6b9 | 26 | #include <linux/module.h> |
771fe6b9 | 27 | #include <linux/fb.h> |
771fe6b9 JG |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "drm_crtc.h" | |
32 | #include "drm_crtc_helper.h" | |
33 | #include "radeon_drm.h" | |
34 | #include "radeon.h" | |
35 | ||
785b93ef DA |
36 | #include "drm_fb_helper.h" |
37 | ||
6a9ee8af DA |
38 | #include <linux/vga_switcheroo.h> |
39 | ||
38651674 DA |
40 | /* object hierarchy - |
41 | this contains a helper + a radeon fb | |
42 | the helper contains a pointer to radeon framebuffer baseclass. | |
43 | */ | |
8be48d92 | 44 | struct radeon_fbdev { |
785b93ef | 45 | struct drm_fb_helper helper; |
38651674 DA |
46 | struct radeon_framebuffer rfb; |
47 | struct list_head fbdev_list; | |
48 | struct radeon_device *rdev; | |
771fe6b9 JG |
49 | }; |
50 | ||
771fe6b9 JG |
51 | static struct fb_ops radeonfb_ops = { |
52 | .owner = THIS_MODULE, | |
c88f9f0c | 53 | .fb_check_var = drm_fb_helper_check_var, |
785b93ef DA |
54 | .fb_set_par = drm_fb_helper_set_par, |
55 | .fb_setcolreg = drm_fb_helper_setcolreg, | |
771fe6b9 JG |
56 | .fb_fillrect = cfb_fillrect, |
57 | .fb_copyarea = cfb_copyarea, | |
58 | .fb_imageblit = cfb_imageblit, | |
785b93ef DA |
59 | .fb_pan_display = drm_fb_helper_pan_display, |
60 | .fb_blank = drm_fb_helper_blank, | |
068143d3 | 61 | .fb_setcmap = drm_fb_helper_setcmap, |
771fe6b9 JG |
62 | }; |
63 | ||
771fe6b9 | 64 | |
e024e110 | 65 | static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) |
771fe6b9 JG |
66 | { |
67 | int aligned = width; | |
e024e110 | 68 | int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; |
771fe6b9 JG |
69 | int pitch_mask = 0; |
70 | ||
71 | switch (bpp / 8) { | |
72 | case 1: | |
73 | pitch_mask = align_large ? 255 : 127; | |
74 | break; | |
75 | case 2: | |
76 | pitch_mask = align_large ? 127 : 31; | |
77 | break; | |
78 | case 3: | |
79 | case 4: | |
80 | pitch_mask = align_large ? 63 : 15; | |
81 | break; | |
82 | } | |
83 | ||
84 | aligned += pitch_mask; | |
85 | aligned &= ~pitch_mask; | |
86 | return aligned; | |
87 | } | |
88 | ||
785b93ef DA |
89 | static struct drm_fb_helper_funcs radeon_fb_helper_funcs = { |
90 | .gamma_set = radeon_crtc_fb_gamma_set, | |
b8c00ac5 | 91 | .gamma_get = radeon_crtc_fb_gamma_get, |
785b93ef DA |
92 | }; |
93 | ||
8be48d92 | 94 | static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) |
771fe6b9 | 95 | { |
8be48d92 DA |
96 | struct radeon_bo *rbo = gobj->driver_private; |
97 | int ret; | |
98 | ||
99 | ret = radeon_bo_reserve(rbo, false); | |
100 | if (likely(ret == 0)) { | |
101 | radeon_bo_kunmap(rbo); | |
102 | radeon_bo_unreserve(rbo); | |
103 | } | |
104 | drm_gem_object_unreference_unlocked(gobj); | |
105 | } | |
106 | ||
107 | static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, | |
108 | struct drm_mode_fb_cmd *mode_cmd, | |
109 | struct drm_gem_object **gobj_p) | |
110 | { | |
111 | struct radeon_device *rdev = rfbdev->rdev; | |
771fe6b9 | 112 | struct drm_gem_object *gobj = NULL; |
4c788679 | 113 | struct radeon_bo *rbo = NULL; |
e024e110 | 114 | bool fb_tiled = false; /* useful for testing */ |
c88f9f0c | 115 | u32 tiling_flags = 0; |
8be48d92 DA |
116 | int ret; |
117 | int aligned_size, size; | |
771fe6b9 | 118 | |
771fe6b9 | 119 | /* need to align pitch with crtc limits */ |
8be48d92 | 120 | mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8); |
771fe6b9 | 121 | |
8be48d92 | 122 | size = mode_cmd->pitch * mode_cmd->height; |
771fe6b9 | 123 | aligned_size = ALIGN(size, PAGE_SIZE); |
771fe6b9 | 124 | ret = radeon_gem_object_create(rdev, aligned_size, 0, |
8be48d92 DA |
125 | RADEON_GEM_DOMAIN_VRAM, |
126 | false, ttm_bo_type_kernel, | |
127 | &gobj); | |
771fe6b9 | 128 | if (ret) { |
8be48d92 DA |
129 | printk(KERN_ERR "failed to allocate framebuffer (%d)\n", |
130 | aligned_size); | |
131 | return -ENOMEM; | |
771fe6b9 | 132 | } |
4c788679 | 133 | rbo = gobj->driver_private; |
771fe6b9 | 134 | |
e024e110 | 135 | if (fb_tiled) |
c88f9f0c MD |
136 | tiling_flags = RADEON_TILING_MACRO; |
137 | ||
138 | #ifdef __BIG_ENDIAN | |
8be48d92 | 139 | switch (mode_cmd->bpp) { |
c88f9f0c MD |
140 | case 32: |
141 | tiling_flags |= RADEON_TILING_SWAP_32BIT; | |
142 | break; | |
143 | case 16: | |
144 | tiling_flags |= RADEON_TILING_SWAP_16BIT; | |
145 | default: | |
146 | break; | |
147 | } | |
148 | #endif | |
149 | ||
4c788679 JG |
150 | if (tiling_flags) { |
151 | ret = radeon_bo_set_tiling_flags(rbo, | |
8be48d92 DA |
152 | tiling_flags | RADEON_TILING_SURFACE, |
153 | mode_cmd->pitch); | |
4c788679 JG |
154 | if (ret) |
155 | dev_err(rdev->dev, "FB failed to set tiling flags\n"); | |
156 | } | |
8be48d92 | 157 | |
38651674 | 158 | |
4c788679 JG |
159 | ret = radeon_bo_reserve(rbo, false); |
160 | if (unlikely(ret != 0)) | |
161 | goto out_unref; | |
8be48d92 | 162 | ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL); |
4c788679 JG |
163 | if (ret) { |
164 | radeon_bo_unreserve(rbo); | |
165 | goto out_unref; | |
166 | } | |
167 | if (fb_tiled) | |
168 | radeon_bo_check_tiling(rbo, 0, 0); | |
8be48d92 | 169 | ret = radeon_bo_kmap(rbo, NULL); |
4c788679 | 170 | radeon_bo_unreserve(rbo); |
f92e93eb | 171 | if (ret) { |
f92e93eb JG |
172 | goto out_unref; |
173 | } | |
771fe6b9 | 174 | |
8be48d92 DA |
175 | *gobj_p = gobj; |
176 | return 0; | |
177 | out_unref: | |
178 | radeonfb_destroy_pinned_object(gobj); | |
179 | *gobj_p = NULL; | |
180 | return ret; | |
181 | } | |
182 | ||
183 | static int radeonfb_create(struct radeon_fbdev *rfbdev, | |
184 | struct drm_fb_helper_surface_size *sizes) | |
185 | { | |
186 | struct radeon_device *rdev = rfbdev->rdev; | |
187 | struct fb_info *info; | |
188 | struct drm_framebuffer *fb = NULL; | |
189 | struct drm_mode_fb_cmd mode_cmd; | |
190 | struct drm_gem_object *gobj = NULL; | |
191 | struct radeon_bo *rbo = NULL; | |
192 | struct device *device = &rdev->pdev->dev; | |
193 | int ret; | |
194 | unsigned long tmp; | |
195 | ||
196 | mode_cmd.width = sizes->surface_width; | |
197 | mode_cmd.height = sizes->surface_height; | |
198 | ||
199 | /* avivo can't scanout real 24bpp */ | |
200 | if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) | |
201 | sizes->surface_bpp = 32; | |
202 | ||
203 | mode_cmd.bpp = sizes->surface_bpp; | |
204 | mode_cmd.depth = sizes->surface_depth; | |
205 | ||
206 | ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj); | |
207 | rbo = gobj->driver_private; | |
208 | ||
209 | /* okay we have an object now allocate the framebuffer */ | |
210 | info = framebuffer_alloc(0, device); | |
771fe6b9 JG |
211 | if (info == NULL) { |
212 | ret = -ENOMEM; | |
213 | goto out_unref; | |
214 | } | |
785b93ef | 215 | |
8be48d92 DA |
216 | info->par = rfbdev; |
217 | ||
218 | radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); | |
219 | ||
38651674 DA |
220 | fb = &rfbdev->rfb.base; |
221 | ||
222 | /* setup helper */ | |
223 | rfbdev->helper.fb = fb; | |
224 | rfbdev->helper.fbdev = info; | |
785b93ef | 225 | rfbdev->helper.funcs = &radeon_fb_helper_funcs; |
38651674 | 226 | |
8be48d92 | 227 | memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo)); |
bf8e828b | 228 | |
771fe6b9 | 229 | strcpy(info->fix.id, "radeondrmfb"); |
785b93ef | 230 | |
068143d3 | 231 | drm_fb_helper_fill_fix(info, fb->pitch, fb->depth); |
785b93ef | 232 | |
771fe6b9 JG |
233 | info->flags = FBINFO_DEFAULT; |
234 | info->fbops = &radeonfb_ops; | |
785b93ef | 235 | |
8be48d92 | 236 | tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; |
f92e93eb | 237 | info->fix.smem_start = rdev->mc.aper_base + tmp; |
8be48d92 DA |
238 | info->fix.smem_len = radeon_bo_size(rbo); |
239 | info->screen_base = rbo->kptr; | |
240 | info->screen_size = radeon_bo_size(rbo); | |
785b93ef | 241 | |
38651674 | 242 | drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); |
ed8f0d9e DA |
243 | |
244 | /* setup aperture base/size for vesafb takeover */ | |
245 | info->aperture_base = rdev->ddev->mode_config.fb_base; | |
246 | info->aperture_size = rdev->mc.real_vram_size; | |
247 | ||
696d4df1 MD |
248 | info->fix.mmio_start = 0; |
249 | info->fix.mmio_len = 0; | |
771fe6b9 JG |
250 | info->pixmap.size = 64*1024; |
251 | info->pixmap.buf_align = 8; | |
252 | info->pixmap.access_align = 32; | |
253 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | |
254 | info->pixmap.scan_align = 1; | |
255 | if (info->screen_base == NULL) { | |
256 | ret = -ENOSPC; | |
257 | goto out_unref; | |
258 | } | |
259 | DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); | |
260 | DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); | |
8be48d92 | 261 | DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); |
771fe6b9 JG |
262 | DRM_INFO("fb depth is %d\n", fb->depth); |
263 | DRM_INFO(" pitch is %d\n", fb->pitch); | |
264 | ||
6a9ee8af | 265 | vga_switcheroo_client_fb_set(rdev->ddev->pdev, info); |
771fe6b9 JG |
266 | return 0; |
267 | ||
268 | out_unref: | |
4c788679 | 269 | if (rbo) { |
8be48d92 | 270 | |
771fe6b9 | 271 | } |
f92e93eb | 272 | if (fb && ret) { |
771fe6b9 JG |
273 | drm_gem_object_unreference(gobj); |
274 | drm_framebuffer_cleanup(fb); | |
275 | kfree(fb); | |
276 | } | |
8be48d92 | 277 | |
771fe6b9 JG |
278 | out: |
279 | return ret; | |
280 | } | |
281 | ||
8be48d92 DA |
282 | static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper, |
283 | struct drm_fb_helper_surface_size *sizes) | |
38651674 | 284 | { |
8be48d92 | 285 | struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper; |
38651674 DA |
286 | int new_fb = 0; |
287 | int ret; | |
288 | ||
8be48d92 DA |
289 | if (!helper->fb) { |
290 | ret = radeonfb_create(rfbdev, sizes); | |
38651674 DA |
291 | if (ret) |
292 | return ret; | |
38651674 | 293 | new_fb = 1; |
38651674 | 294 | } |
38651674 DA |
295 | return new_fb; |
296 | } | |
297 | ||
d50ba256 DA |
298 | static char *mode_option; |
299 | int radeon_parse_options(char *options) | |
300 | { | |
301 | char *this_opt; | |
302 | ||
303 | if (!options || !*options) | |
304 | return 0; | |
305 | ||
306 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
307 | if (!*this_opt) | |
308 | continue; | |
309 | mode_option = this_opt; | |
310 | } | |
311 | return 0; | |
312 | } | |
313 | ||
8be48d92 | 314 | static int radeonfb_probe(struct radeon_fbdev *rfbdev) |
771fe6b9 | 315 | { |
8be48d92 | 316 | struct radeon_device *rdev = rfbdev->rdev; |
47381156 DA |
317 | int bpp_sel = 32; |
318 | ||
319 | /* select 8 bpp console on RN50 or 16MB cards */ | |
320 | if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024)) | |
321 | bpp_sel = 8; | |
322 | ||
8be48d92 | 323 | return drm_fb_helper_single_fb_probe(&rfbdev->helper, bpp_sel); |
38651674 DA |
324 | } |
325 | ||
326 | void radeonfb_hotplug(struct drm_device *dev) | |
327 | { | |
8be48d92 DA |
328 | struct radeon_device *rdev = dev->dev_private; |
329 | int max_width, max_height; | |
330 | ||
331 | max_width = rdev->mode_info.rfbdev->rfb.base.width; | |
332 | max_height = rdev->mode_info.rfbdev->rfb.base.height; | |
333 | drm_helper_fb_hotplug_event(&rdev->mode_info.rfbdev->helper, max_width, max_height); | |
38651674 | 334 | |
8be48d92 | 335 | radeonfb_probe(rdev->mode_info.rfbdev); |
771fe6b9 | 336 | } |
771fe6b9 | 337 | |
8be48d92 | 338 | static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev) |
771fe6b9 JG |
339 | { |
340 | struct fb_info *info; | |
38651674 | 341 | struct radeon_framebuffer *rfb = &rfbdev->rfb; |
4c788679 JG |
342 | struct radeon_bo *rbo; |
343 | int r; | |
771fe6b9 | 344 | |
8be48d92 DA |
345 | if (rfbdev->helper.fbdev) { |
346 | info = rfbdev->helper.fbdev; | |
347 | unregister_framebuffer(info); | |
348 | framebuffer_release(info); | |
771fe6b9 JG |
349 | } |
350 | ||
8be48d92 DA |
351 | if (rfb->obj) { |
352 | rbo = rfb->obj->driver_private; | |
353 | r = radeon_bo_reserve(rbo, false); | |
354 | if (likely(r == 0)) { | |
355 | radeon_bo_kunmap(rbo); | |
356 | radeon_bo_unpin(rbo); | |
357 | radeon_bo_unreserve(rbo); | |
358 | } | |
359 | drm_gem_object_unreference_unlocked(rfb->obj); | |
360 | } | |
38651674 DA |
361 | drm_fb_helper_free(&rfbdev->helper); |
362 | drm_framebuffer_cleanup(&rfb->base); | |
785b93ef | 363 | |
771fe6b9 JG |
364 | return 0; |
365 | } | |
771fe6b9 | 366 | MODULE_LICENSE("GPL"); |
38651674 DA |
367 | |
368 | int radeon_fbdev_init(struct radeon_device *rdev) | |
369 | { | |
8be48d92 DA |
370 | struct radeon_fbdev *rfbdev; |
371 | ||
372 | rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL); | |
373 | if (!rfbdev) | |
374 | return -ENOMEM; | |
375 | ||
376 | rfbdev->rdev = rdev; | |
377 | rdev->mode_info.rfbdev = rfbdev; | |
378 | ||
379 | drm_fb_helper_init_crtc_count(rdev->ddev, &rfbdev->helper, | |
380 | rdev->num_crtc, | |
381 | RADEONFB_CONN_LIMIT); | |
382 | rfbdev->helper.fb_probe = radeon_fb_find_or_create_single; | |
383 | drm_fb_helper_initial_config(&rfbdev->helper); | |
384 | radeonfb_probe(rfbdev); | |
38651674 | 385 | return 0; |
8be48d92 | 386 | |
38651674 DA |
387 | } |
388 | ||
389 | void radeon_fbdev_fini(struct radeon_device *rdev) | |
390 | { | |
8be48d92 DA |
391 | if (!rdev->mode_info.rfbdev) |
392 | return; | |
393 | ||
38651674 | 394 | radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev); |
8be48d92 | 395 | kfree(rdev->mode_info.rfbdev); |
38651674 DA |
396 | rdev->mode_info.rfbdev = NULL; |
397 | } | |
398 | ||
399 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state) | |
400 | { | |
401 | fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state); | |
402 | } | |
403 | ||
404 | int radeon_fbdev_total_size(struct radeon_device *rdev) | |
405 | { | |
406 | struct radeon_bo *robj; | |
407 | int size = 0; | |
408 | ||
409 | robj = rdev->mode_info.rfbdev->rfb.obj->driver_private; | |
410 | size += radeon_bo_size(robj); | |
411 | return size; | |
412 | } | |
413 | ||
414 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj) | |
415 | { | |
416 | if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private) | |
417 | return true; | |
418 | return false; | |
419 | } | |
420 |