Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright © 2007 David Airlie | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * David Airlie | |
25 | */ | |
771fe6b9 | 26 | #include <linux/module.h> |
771fe6b9 | 27 | #include <linux/fb.h> |
771fe6b9 JG |
28 | |
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "drm_crtc.h" | |
32 | #include "drm_crtc_helper.h" | |
33 | #include "radeon_drm.h" | |
34 | #include "radeon.h" | |
35 | ||
785b93ef DA |
36 | #include "drm_fb_helper.h" |
37 | ||
6a9ee8af DA |
38 | #include <linux/vga_switcheroo.h> |
39 | ||
38651674 DA |
40 | /* object hierarchy - |
41 | this contains a helper + a radeon fb | |
42 | the helper contains a pointer to radeon framebuffer baseclass. | |
43 | */ | |
8be48d92 | 44 | struct radeon_fbdev { |
785b93ef | 45 | struct drm_fb_helper helper; |
38651674 DA |
46 | struct radeon_framebuffer rfb; |
47 | struct list_head fbdev_list; | |
48 | struct radeon_device *rdev; | |
771fe6b9 JG |
49 | }; |
50 | ||
771fe6b9 JG |
51 | static struct fb_ops radeonfb_ops = { |
52 | .owner = THIS_MODULE, | |
c88f9f0c | 53 | .fb_check_var = drm_fb_helper_check_var, |
785b93ef DA |
54 | .fb_set_par = drm_fb_helper_set_par, |
55 | .fb_setcolreg = drm_fb_helper_setcolreg, | |
771fe6b9 JG |
56 | .fb_fillrect = cfb_fillrect, |
57 | .fb_copyarea = cfb_copyarea, | |
58 | .fb_imageblit = cfb_imageblit, | |
785b93ef DA |
59 | .fb_pan_display = drm_fb_helper_pan_display, |
60 | .fb_blank = drm_fb_helper_blank, | |
068143d3 | 61 | .fb_setcmap = drm_fb_helper_setcmap, |
771fe6b9 JG |
62 | }; |
63 | ||
771fe6b9 | 64 | |
e024e110 | 65 | static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) |
771fe6b9 JG |
66 | { |
67 | int aligned = width; | |
e024e110 | 68 | int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; |
771fe6b9 JG |
69 | int pitch_mask = 0; |
70 | ||
71 | switch (bpp / 8) { | |
72 | case 1: | |
73 | pitch_mask = align_large ? 255 : 127; | |
74 | break; | |
75 | case 2: | |
76 | pitch_mask = align_large ? 127 : 31; | |
77 | break; | |
78 | case 3: | |
79 | case 4: | |
80 | pitch_mask = align_large ? 63 : 15; | |
81 | break; | |
82 | } | |
83 | ||
84 | aligned += pitch_mask; | |
85 | aligned &= ~pitch_mask; | |
86 | return aligned; | |
87 | } | |
88 | ||
8be48d92 | 89 | static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) |
771fe6b9 | 90 | { |
8be48d92 DA |
91 | struct radeon_bo *rbo = gobj->driver_private; |
92 | int ret; | |
93 | ||
94 | ret = radeon_bo_reserve(rbo, false); | |
95 | if (likely(ret == 0)) { | |
96 | radeon_bo_kunmap(rbo); | |
97 | radeon_bo_unreserve(rbo); | |
98 | } | |
99 | drm_gem_object_unreference_unlocked(gobj); | |
100 | } | |
101 | ||
102 | static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, | |
103 | struct drm_mode_fb_cmd *mode_cmd, | |
104 | struct drm_gem_object **gobj_p) | |
105 | { | |
106 | struct radeon_device *rdev = rfbdev->rdev; | |
771fe6b9 | 107 | struct drm_gem_object *gobj = NULL; |
4c788679 | 108 | struct radeon_bo *rbo = NULL; |
e024e110 | 109 | bool fb_tiled = false; /* useful for testing */ |
c88f9f0c | 110 | u32 tiling_flags = 0; |
8be48d92 DA |
111 | int ret; |
112 | int aligned_size, size; | |
771fe6b9 | 113 | |
771fe6b9 | 114 | /* need to align pitch with crtc limits */ |
8be48d92 | 115 | mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8); |
771fe6b9 | 116 | |
8be48d92 | 117 | size = mode_cmd->pitch * mode_cmd->height; |
771fe6b9 | 118 | aligned_size = ALIGN(size, PAGE_SIZE); |
771fe6b9 | 119 | ret = radeon_gem_object_create(rdev, aligned_size, 0, |
8be48d92 DA |
120 | RADEON_GEM_DOMAIN_VRAM, |
121 | false, ttm_bo_type_kernel, | |
122 | &gobj); | |
771fe6b9 | 123 | if (ret) { |
8be48d92 DA |
124 | printk(KERN_ERR "failed to allocate framebuffer (%d)\n", |
125 | aligned_size); | |
126 | return -ENOMEM; | |
771fe6b9 | 127 | } |
4c788679 | 128 | rbo = gobj->driver_private; |
771fe6b9 | 129 | |
e024e110 | 130 | if (fb_tiled) |
c88f9f0c MD |
131 | tiling_flags = RADEON_TILING_MACRO; |
132 | ||
133 | #ifdef __BIG_ENDIAN | |
8be48d92 | 134 | switch (mode_cmd->bpp) { |
c88f9f0c MD |
135 | case 32: |
136 | tiling_flags |= RADEON_TILING_SWAP_32BIT; | |
137 | break; | |
138 | case 16: | |
139 | tiling_flags |= RADEON_TILING_SWAP_16BIT; | |
140 | default: | |
141 | break; | |
142 | } | |
143 | #endif | |
144 | ||
4c788679 JG |
145 | if (tiling_flags) { |
146 | ret = radeon_bo_set_tiling_flags(rbo, | |
8be48d92 DA |
147 | tiling_flags | RADEON_TILING_SURFACE, |
148 | mode_cmd->pitch); | |
4c788679 JG |
149 | if (ret) |
150 | dev_err(rdev->dev, "FB failed to set tiling flags\n"); | |
151 | } | |
8be48d92 | 152 | |
38651674 | 153 | |
4c788679 JG |
154 | ret = radeon_bo_reserve(rbo, false); |
155 | if (unlikely(ret != 0)) | |
156 | goto out_unref; | |
8be48d92 | 157 | ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL); |
4c788679 JG |
158 | if (ret) { |
159 | radeon_bo_unreserve(rbo); | |
160 | goto out_unref; | |
161 | } | |
162 | if (fb_tiled) | |
163 | radeon_bo_check_tiling(rbo, 0, 0); | |
8be48d92 | 164 | ret = radeon_bo_kmap(rbo, NULL); |
4c788679 | 165 | radeon_bo_unreserve(rbo); |
f92e93eb | 166 | if (ret) { |
f92e93eb JG |
167 | goto out_unref; |
168 | } | |
771fe6b9 | 169 | |
8be48d92 DA |
170 | *gobj_p = gobj; |
171 | return 0; | |
172 | out_unref: | |
173 | radeonfb_destroy_pinned_object(gobj); | |
174 | *gobj_p = NULL; | |
175 | return ret; | |
176 | } | |
177 | ||
178 | static int radeonfb_create(struct radeon_fbdev *rfbdev, | |
179 | struct drm_fb_helper_surface_size *sizes) | |
180 | { | |
181 | struct radeon_device *rdev = rfbdev->rdev; | |
182 | struct fb_info *info; | |
183 | struct drm_framebuffer *fb = NULL; | |
184 | struct drm_mode_fb_cmd mode_cmd; | |
185 | struct drm_gem_object *gobj = NULL; | |
186 | struct radeon_bo *rbo = NULL; | |
187 | struct device *device = &rdev->pdev->dev; | |
188 | int ret; | |
189 | unsigned long tmp; | |
190 | ||
191 | mode_cmd.width = sizes->surface_width; | |
192 | mode_cmd.height = sizes->surface_height; | |
193 | ||
194 | /* avivo can't scanout real 24bpp */ | |
195 | if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) | |
196 | sizes->surface_bpp = 32; | |
197 | ||
198 | mode_cmd.bpp = sizes->surface_bpp; | |
199 | mode_cmd.depth = sizes->surface_depth; | |
200 | ||
201 | ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj); | |
202 | rbo = gobj->driver_private; | |
203 | ||
204 | /* okay we have an object now allocate the framebuffer */ | |
205 | info = framebuffer_alloc(0, device); | |
771fe6b9 JG |
206 | if (info == NULL) { |
207 | ret = -ENOMEM; | |
208 | goto out_unref; | |
209 | } | |
785b93ef | 210 | |
8be48d92 DA |
211 | info->par = rfbdev; |
212 | ||
213 | radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); | |
214 | ||
38651674 DA |
215 | fb = &rfbdev->rfb.base; |
216 | ||
217 | /* setup helper */ | |
218 | rfbdev->helper.fb = fb; | |
219 | rfbdev->helper.fbdev = info; | |
38651674 | 220 | |
8be48d92 | 221 | memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo)); |
bf8e828b | 222 | |
771fe6b9 | 223 | strcpy(info->fix.id, "radeondrmfb"); |
785b93ef | 224 | |
068143d3 | 225 | drm_fb_helper_fill_fix(info, fb->pitch, fb->depth); |
785b93ef | 226 | |
771fe6b9 JG |
227 | info->flags = FBINFO_DEFAULT; |
228 | info->fbops = &radeonfb_ops; | |
785b93ef | 229 | |
8be48d92 | 230 | tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; |
f92e93eb | 231 | info->fix.smem_start = rdev->mc.aper_base + tmp; |
8be48d92 DA |
232 | info->fix.smem_len = radeon_bo_size(rbo); |
233 | info->screen_base = rbo->kptr; | |
234 | info->screen_size = radeon_bo_size(rbo); | |
785b93ef | 235 | |
38651674 | 236 | drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height); |
ed8f0d9e DA |
237 | |
238 | /* setup aperture base/size for vesafb takeover */ | |
239 | info->aperture_base = rdev->ddev->mode_config.fb_base; | |
240 | info->aperture_size = rdev->mc.real_vram_size; | |
241 | ||
696d4df1 MD |
242 | info->fix.mmio_start = 0; |
243 | info->fix.mmio_len = 0; | |
771fe6b9 JG |
244 | info->pixmap.size = 64*1024; |
245 | info->pixmap.buf_align = 8; | |
246 | info->pixmap.access_align = 32; | |
247 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | |
248 | info->pixmap.scan_align = 1; | |
4abe3520 | 249 | |
771fe6b9 JG |
250 | if (info->screen_base == NULL) { |
251 | ret = -ENOSPC; | |
252 | goto out_unref; | |
253 | } | |
4abe3520 DA |
254 | |
255 | ret = fb_alloc_cmap(&info->cmap, 256, 0); | |
256 | if (ret) { | |
257 | ret = -ENOMEM; | |
258 | goto out_unref; | |
259 | } | |
260 | ||
771fe6b9 JG |
261 | DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); |
262 | DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); | |
8be48d92 | 263 | DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); |
771fe6b9 JG |
264 | DRM_INFO("fb depth is %d\n", fb->depth); |
265 | DRM_INFO(" pitch is %d\n", fb->pitch); | |
266 | ||
6a9ee8af | 267 | vga_switcheroo_client_fb_set(rdev->ddev->pdev, info); |
771fe6b9 JG |
268 | return 0; |
269 | ||
270 | out_unref: | |
4c788679 | 271 | if (rbo) { |
8be48d92 | 272 | |
771fe6b9 | 273 | } |
f92e93eb | 274 | if (fb && ret) { |
771fe6b9 JG |
275 | drm_gem_object_unreference(gobj); |
276 | drm_framebuffer_cleanup(fb); | |
277 | kfree(fb); | |
278 | } | |
771fe6b9 JG |
279 | return ret; |
280 | } | |
281 | ||
8be48d92 DA |
282 | static int radeon_fb_find_or_create_single(struct drm_fb_helper *helper, |
283 | struct drm_fb_helper_surface_size *sizes) | |
38651674 | 284 | { |
8be48d92 | 285 | struct radeon_fbdev *rfbdev = (struct radeon_fbdev *)helper; |
38651674 DA |
286 | int new_fb = 0; |
287 | int ret; | |
288 | ||
8be48d92 DA |
289 | if (!helper->fb) { |
290 | ret = radeonfb_create(rfbdev, sizes); | |
38651674 DA |
291 | if (ret) |
292 | return ret; | |
38651674 | 293 | new_fb = 1; |
38651674 | 294 | } |
38651674 DA |
295 | return new_fb; |
296 | } | |
297 | ||
d50ba256 DA |
298 | static char *mode_option; |
299 | int radeon_parse_options(char *options) | |
300 | { | |
301 | char *this_opt; | |
302 | ||
303 | if (!options || !*options) | |
304 | return 0; | |
305 | ||
306 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
307 | if (!*this_opt) | |
308 | continue; | |
309 | mode_option = this_opt; | |
310 | } | |
311 | return 0; | |
312 | } | |
313 | ||
5c4426a7 | 314 | void radeonfb_hotplug(struct drm_device *dev, bool polled) |
38651674 | 315 | { |
8be48d92 | 316 | struct radeon_device *rdev = dev->dev_private; |
38651674 | 317 | |
4abe3520 | 318 | drm_helper_fb_hpd_irq_event(&rdev->mode_info.rfbdev->helper); |
771fe6b9 | 319 | } |
771fe6b9 | 320 | |
4abe3520 | 321 | static void radeon_fb_output_status_changed(struct drm_fb_helper *fb_helper) |
5c4426a7 | 322 | { |
4abe3520 | 323 | drm_helper_fb_hotplug_event(fb_helper, true); |
5c4426a7 DA |
324 | } |
325 | ||
8be48d92 | 326 | static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev) |
771fe6b9 JG |
327 | { |
328 | struct fb_info *info; | |
38651674 | 329 | struct radeon_framebuffer *rfb = &rfbdev->rfb; |
4c788679 JG |
330 | struct radeon_bo *rbo; |
331 | int r; | |
771fe6b9 | 332 | |
8be48d92 DA |
333 | if (rfbdev->helper.fbdev) { |
334 | info = rfbdev->helper.fbdev; | |
4abe3520 | 335 | |
8be48d92 | 336 | unregister_framebuffer(info); |
4abe3520 DA |
337 | if (info->cmap.len) |
338 | fb_dealloc_cmap(&info->cmap); | |
8be48d92 | 339 | framebuffer_release(info); |
771fe6b9 JG |
340 | } |
341 | ||
8be48d92 DA |
342 | if (rfb->obj) { |
343 | rbo = rfb->obj->driver_private; | |
344 | r = radeon_bo_reserve(rbo, false); | |
345 | if (likely(r == 0)) { | |
346 | radeon_bo_kunmap(rbo); | |
347 | radeon_bo_unpin(rbo); | |
348 | radeon_bo_unreserve(rbo); | |
349 | } | |
350 | drm_gem_object_unreference_unlocked(rfb->obj); | |
351 | } | |
4abe3520 | 352 | drm_fb_helper_fini(&rfbdev->helper); |
38651674 | 353 | drm_framebuffer_cleanup(&rfb->base); |
785b93ef | 354 | |
771fe6b9 JG |
355 | return 0; |
356 | } | |
4abe3520 DA |
357 | |
358 | static struct drm_fb_helper_funcs radeon_fb_helper_funcs = { | |
359 | .gamma_set = radeon_crtc_fb_gamma_set, | |
360 | .gamma_get = radeon_crtc_fb_gamma_get, | |
361 | .fb_probe = radeon_fb_find_or_create_single, | |
362 | .fb_output_status_changed = radeon_fb_output_status_changed, | |
363 | }; | |
38651674 DA |
364 | |
365 | int radeon_fbdev_init(struct radeon_device *rdev) | |
366 | { | |
8be48d92 | 367 | struct radeon_fbdev *rfbdev; |
4abe3520 DA |
368 | int bpp_sel = 32; |
369 | ||
370 | /* select 8 bpp console on RN50 or 16MB cards */ | |
371 | if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024)) | |
372 | bpp_sel = 8; | |
8be48d92 DA |
373 | |
374 | rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL); | |
375 | if (!rfbdev) | |
376 | return -ENOMEM; | |
377 | ||
378 | rfbdev->rdev = rdev; | |
379 | rdev->mode_info.rfbdev = rfbdev; | |
4abe3520 | 380 | rfbdev->helper.funcs = &radeon_fb_helper_funcs; |
8be48d92 | 381 | |
4abe3520 DA |
382 | drm_fb_helper_init(rdev->ddev, &rfbdev->helper, |
383 | rdev->num_crtc, | |
384 | RADEONFB_CONN_LIMIT, true); | |
0b4c0f3f | 385 | drm_fb_helper_single_add_all_connectors(&rfbdev->helper); |
4abe3520 | 386 | drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); |
38651674 | 387 | return 0; |
8be48d92 | 388 | |
38651674 DA |
389 | } |
390 | ||
391 | void radeon_fbdev_fini(struct radeon_device *rdev) | |
392 | { | |
8be48d92 DA |
393 | if (!rdev->mode_info.rfbdev) |
394 | return; | |
395 | ||
38651674 | 396 | radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev); |
8be48d92 | 397 | kfree(rdev->mode_info.rfbdev); |
38651674 DA |
398 | rdev->mode_info.rfbdev = NULL; |
399 | } | |
400 | ||
401 | void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state) | |
402 | { | |
403 | fb_set_suspend(rdev->mode_info.rfbdev->helper.fbdev, state); | |
404 | } | |
405 | ||
406 | int radeon_fbdev_total_size(struct radeon_device *rdev) | |
407 | { | |
408 | struct radeon_bo *robj; | |
409 | int size = 0; | |
410 | ||
411 | robj = rdev->mode_info.rfbdev->rfb.obj->driver_private; | |
412 | size += radeon_bo_size(robj); | |
413 | return size; | |
414 | } | |
415 | ||
416 | bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj) | |
417 | { | |
418 | if (robj == rdev->mode_info.rfbdev->rfb.obj->driver_private) | |
419 | return true; | |
420 | return false; | |
421 | } |