Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "drm_crtc_helper.h" | |
28 | #include "radeon_drm.h" | |
29 | #include "radeon.h" | |
30 | #include "atom.h" | |
31 | ||
32 | extern int atom_debug; | |
33 | ||
5a9bcacc AD |
34 | /* evil but including atombios.h is much worse */ |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, | |
36 | struct drm_display_mode *mode); | |
37 | ||
1f3b6a45 DA |
38 | static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) |
39 | { | |
40 | struct drm_device *dev = encoder->dev; | |
41 | struct radeon_device *rdev = dev->dev_private; | |
42 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
43 | struct drm_encoder *clone_encoder; | |
44 | uint32_t index_mask = 0; | |
45 | int count; | |
46 | ||
47 | /* DIG routing gets problematic */ | |
48 | if (rdev->family >= CHIP_R600) | |
49 | return index_mask; | |
50 | /* LVDS/TV are too wacky */ | |
51 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) | |
52 | return index_mask; | |
53 | /* DVO requires 2x ppll clocks depending on tmds chip */ | |
54 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) | |
55 | return index_mask; | |
bcc1c2a1 | 56 | |
1f3b6a45 DA |
57 | count = -1; |
58 | list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { | |
59 | struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); | |
60 | count++; | |
61 | ||
62 | if (clone_encoder == encoder) | |
63 | continue; | |
64 | if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
65 | continue; | |
66 | if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT) | |
67 | continue; | |
68 | else | |
69 | index_mask |= (1 << count); | |
70 | } | |
71 | return index_mask; | |
72 | } | |
73 | ||
74 | void radeon_setup_encoder_clones(struct drm_device *dev) | |
75 | { | |
76 | struct drm_encoder *encoder; | |
77 | ||
78 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
79 | encoder->possible_clones = radeon_encoder_clones(encoder); | |
80 | } | |
81 | } | |
82 | ||
771fe6b9 | 83 | uint32_t |
5137ee94 | 84 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
771fe6b9 JG |
85 | { |
86 | struct radeon_device *rdev = dev->dev_private; | |
87 | uint32_t ret = 0; | |
88 | ||
89 | switch (supported_device) { | |
90 | case ATOM_DEVICE_CRT1_SUPPORT: | |
91 | case ATOM_DEVICE_TV1_SUPPORT: | |
92 | case ATOM_DEVICE_TV2_SUPPORT: | |
93 | case ATOM_DEVICE_CRT2_SUPPORT: | |
94 | case ATOM_DEVICE_CV_SUPPORT: | |
95 | switch (dac) { | |
96 | case 1: /* dac a */ | |
97 | if ((rdev->family == CHIP_RS300) || | |
98 | (rdev->family == CHIP_RS400) || | |
99 | (rdev->family == CHIP_RS480)) | |
5137ee94 | 100 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
771fe6b9 | 101 | else if (ASIC_IS_AVIVO(rdev)) |
5137ee94 | 102 | ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1; |
771fe6b9 | 103 | else |
5137ee94 | 104 | ret = ENCODER_INTERNAL_DAC1_ENUM_ID1; |
771fe6b9 JG |
105 | break; |
106 | case 2: /* dac b */ | |
107 | if (ASIC_IS_AVIVO(rdev)) | |
5137ee94 | 108 | ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1; |
771fe6b9 JG |
109 | else { |
110 | /*if (rdev->family == CHIP_R200) | |
5137ee94 | 111 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
771fe6b9 | 112 | else*/ |
5137ee94 | 113 | ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; |
771fe6b9 JG |
114 | } |
115 | break; | |
116 | case 3: /* external dac */ | |
117 | if (ASIC_IS_AVIVO(rdev)) | |
5137ee94 | 118 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
771fe6b9 | 119 | else |
5137ee94 | 120 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
771fe6b9 JG |
121 | break; |
122 | } | |
123 | break; | |
124 | case ATOM_DEVICE_LCD1_SUPPORT: | |
125 | if (ASIC_IS_AVIVO(rdev)) | |
5137ee94 | 126 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
771fe6b9 | 127 | else |
5137ee94 | 128 | ret = ENCODER_INTERNAL_LVDS_ENUM_ID1; |
771fe6b9 JG |
129 | break; |
130 | case ATOM_DEVICE_DFP1_SUPPORT: | |
131 | if ((rdev->family == CHIP_RS300) || | |
132 | (rdev->family == CHIP_RS400) || | |
133 | (rdev->family == CHIP_RS480)) | |
5137ee94 | 134 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
771fe6b9 | 135 | else if (ASIC_IS_AVIVO(rdev)) |
5137ee94 | 136 | ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1; |
771fe6b9 | 137 | else |
5137ee94 | 138 | ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1; |
771fe6b9 JG |
139 | break; |
140 | case ATOM_DEVICE_LCD2_SUPPORT: | |
141 | case ATOM_DEVICE_DFP2_SUPPORT: | |
142 | if ((rdev->family == CHIP_RS600) || | |
143 | (rdev->family == CHIP_RS690) || | |
144 | (rdev->family == CHIP_RS740)) | |
5137ee94 | 145 | ret = ENCODER_INTERNAL_DDI_ENUM_ID1; |
771fe6b9 | 146 | else if (ASIC_IS_AVIVO(rdev)) |
5137ee94 | 147 | ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1; |
771fe6b9 | 148 | else |
5137ee94 | 149 | ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; |
771fe6b9 JG |
150 | break; |
151 | case ATOM_DEVICE_DFP3_SUPPORT: | |
5137ee94 | 152 | ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1; |
771fe6b9 JG |
153 | break; |
154 | } | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
f28cf339 DA |
159 | static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) |
160 | { | |
161 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
162 | switch (radeon_encoder->encoder_id) { | |
163 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
164 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
165 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
166 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
167 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
168 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
169 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
170 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
171 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
172 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
173 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
174 | return true; | |
175 | default: | |
176 | return false; | |
177 | } | |
178 | } | |
99999aaa | 179 | |
771fe6b9 JG |
180 | void |
181 | radeon_link_encoder_connector(struct drm_device *dev) | |
182 | { | |
183 | struct drm_connector *connector; | |
184 | struct radeon_connector *radeon_connector; | |
185 | struct drm_encoder *encoder; | |
186 | struct radeon_encoder *radeon_encoder; | |
187 | ||
188 | /* walk the list and link encoders to connectors */ | |
189 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
190 | radeon_connector = to_radeon_connector(connector); | |
191 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
192 | radeon_encoder = to_radeon_encoder(encoder); | |
193 | if (radeon_encoder->devices & radeon_connector->devices) | |
194 | drm_mode_connector_attach_encoder(connector, encoder); | |
195 | } | |
196 | } | |
197 | } | |
198 | ||
4ce001ab DA |
199 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
200 | { | |
201 | struct drm_device *dev = encoder->dev; | |
202 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
203 | struct drm_connector *connector; | |
204 | ||
205 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
206 | if (connector->encoder == encoder) { | |
207 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
208 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; | |
d9fdaafb | 209 | DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", |
f641e51e DA |
210 | radeon_encoder->active_device, radeon_encoder->devices, |
211 | radeon_connector->devices, encoder->encoder_type); | |
4ce001ab DA |
212 | } |
213 | } | |
214 | } | |
215 | ||
5b1714d3 | 216 | struct drm_connector * |
771fe6b9 JG |
217 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
218 | { | |
219 | struct drm_device *dev = encoder->dev; | |
220 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
221 | struct drm_connector *connector; | |
222 | struct radeon_connector *radeon_connector; | |
223 | ||
224 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
225 | radeon_connector = to_radeon_connector(connector); | |
43c33ed8 | 226 | if (radeon_encoder->active_device & radeon_connector->devices) |
771fe6b9 JG |
227 | return connector; |
228 | } | |
229 | return NULL; | |
230 | } | |
231 | ||
3e4b9982 AD |
232 | struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder) |
233 | { | |
234 | struct drm_device *dev = encoder->dev; | |
235 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
236 | struct drm_encoder *other_encoder; | |
237 | struct radeon_encoder *other_radeon_encoder; | |
238 | ||
239 | if (radeon_encoder->is_ext_encoder) | |
240 | return NULL; | |
241 | ||
242 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { | |
243 | if (other_encoder == encoder) | |
244 | continue; | |
245 | other_radeon_encoder = to_radeon_encoder(other_encoder); | |
246 | if (other_radeon_encoder->is_ext_encoder && | |
247 | (radeon_encoder->devices & other_radeon_encoder->devices)) | |
248 | return other_encoder; | |
249 | } | |
250 | return NULL; | |
251 | } | |
252 | ||
3515387b AD |
253 | void radeon_panel_mode_fixup(struct drm_encoder *encoder, |
254 | struct drm_display_mode *adjusted_mode) | |
255 | { | |
256 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
257 | struct drm_device *dev = encoder->dev; | |
258 | struct radeon_device *rdev = dev->dev_private; | |
259 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
260 | unsigned hblank = native_mode->htotal - native_mode->hdisplay; | |
261 | unsigned vblank = native_mode->vtotal - native_mode->vdisplay; | |
262 | unsigned hover = native_mode->hsync_start - native_mode->hdisplay; | |
263 | unsigned vover = native_mode->vsync_start - native_mode->vdisplay; | |
264 | unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; | |
265 | unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start; | |
266 | ||
267 | adjusted_mode->clock = native_mode->clock; | |
268 | adjusted_mode->flags = native_mode->flags; | |
269 | ||
270 | if (ASIC_IS_AVIVO(rdev)) { | |
271 | adjusted_mode->hdisplay = native_mode->hdisplay; | |
272 | adjusted_mode->vdisplay = native_mode->vdisplay; | |
273 | } | |
274 | ||
275 | adjusted_mode->htotal = native_mode->hdisplay + hblank; | |
276 | adjusted_mode->hsync_start = native_mode->hdisplay + hover; | |
277 | adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; | |
278 | ||
279 | adjusted_mode->vtotal = native_mode->vdisplay + vblank; | |
280 | adjusted_mode->vsync_start = native_mode->vdisplay + vover; | |
281 | adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width; | |
282 | ||
283 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | |
284 | ||
285 | if (ASIC_IS_AVIVO(rdev)) { | |
286 | adjusted_mode->crtc_hdisplay = native_mode->hdisplay; | |
287 | adjusted_mode->crtc_vdisplay = native_mode->vdisplay; | |
288 | } | |
289 | ||
290 | adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank; | |
291 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover; | |
292 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width; | |
293 | ||
294 | adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank; | |
295 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover; | |
296 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width; | |
297 | ||
298 | } | |
299 | ||
771fe6b9 JG |
300 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
301 | struct drm_display_mode *mode, | |
302 | struct drm_display_mode *adjusted_mode) | |
303 | { | |
771fe6b9 | 304 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
5a9bcacc AD |
305 | struct drm_device *dev = encoder->dev; |
306 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 | 307 | |
8c2a6d73 AD |
308 | /* set the active encoder to connector routing */ |
309 | radeon_encoder_set_active_device(encoder); | |
771fe6b9 JG |
310 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
311 | ||
771fe6b9 JG |
312 | /* hw bug */ |
313 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) | |
314 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) | |
315 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; | |
316 | ||
80297e87 | 317 | /* get the native mode for LVDS */ |
3515387b AD |
318 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
319 | radeon_panel_mode_fixup(encoder, adjusted_mode); | |
80297e87 AD |
320 | |
321 | /* get the native mode for TV */ | |
ceefedd8 | 322 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
5a9bcacc AD |
323 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
324 | if (tv_dac) { | |
325 | if (tv_dac->tv_std == TV_STD_NTSC || | |
326 | tv_dac->tv_std == TV_STD_NTSC_J || | |
327 | tv_dac->tv_std == TV_STD_PAL_M) | |
328 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); | |
329 | else | |
330 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); | |
331 | } | |
332 | } | |
333 | ||
5801ead6 | 334 | if (ASIC_IS_DCE3(rdev) && |
9f998ad7 | 335 | (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { |
5801ead6 AD |
336 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
337 | radeon_dp_set_link_config(connector, mode); | |
338 | } | |
339 | ||
771fe6b9 JG |
340 | return true; |
341 | } | |
342 | ||
343 | static void | |
344 | atombios_dac_setup(struct drm_encoder *encoder, int action) | |
345 | { | |
346 | struct drm_device *dev = encoder->dev; | |
347 | struct radeon_device *rdev = dev->dev_private; | |
348 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
349 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; | |
affd8589 | 350 | int index = 0; |
445282db | 351 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
445282db | 352 | |
771fe6b9 JG |
353 | memset(&args, 0, sizeof(args)); |
354 | ||
355 | switch (radeon_encoder->encoder_id) { | |
356 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
357 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
358 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); | |
771fe6b9 JG |
359 | break; |
360 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
361 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
362 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); | |
771fe6b9 JG |
363 | break; |
364 | } | |
365 | ||
366 | args.ucAction = action; | |
367 | ||
4ce001ab | 368 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
771fe6b9 | 369 | args.ucDacStandard = ATOM_DAC1_PS2; |
4ce001ab | 370 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
371 | args.ucDacStandard = ATOM_DAC1_CV; |
372 | else { | |
affd8589 | 373 | switch (dac_info->tv_std) { |
771fe6b9 JG |
374 | case TV_STD_PAL: |
375 | case TV_STD_PAL_M: | |
376 | case TV_STD_SCART_PAL: | |
377 | case TV_STD_SECAM: | |
378 | case TV_STD_PAL_CN: | |
379 | args.ucDacStandard = ATOM_DAC1_PAL; | |
380 | break; | |
381 | case TV_STD_NTSC: | |
382 | case TV_STD_NTSC_J: | |
383 | case TV_STD_PAL_60: | |
384 | default: | |
385 | args.ucDacStandard = ATOM_DAC1_NTSC; | |
386 | break; | |
387 | } | |
388 | } | |
389 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
390 | ||
391 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
392 | ||
393 | } | |
394 | ||
395 | static void | |
396 | atombios_tv_setup(struct drm_encoder *encoder, int action) | |
397 | { | |
398 | struct drm_device *dev = encoder->dev; | |
399 | struct radeon_device *rdev = dev->dev_private; | |
400 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
401 | TV_ENCODER_CONTROL_PS_ALLOCATION args; | |
402 | int index = 0; | |
445282db | 403 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
445282db | 404 | |
771fe6b9 JG |
405 | memset(&args, 0, sizeof(args)); |
406 | ||
407 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); | |
408 | ||
409 | args.sTVEncoder.ucAction = action; | |
410 | ||
4ce001ab | 411 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
412 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
413 | else { | |
affd8589 | 414 | switch (dac_info->tv_std) { |
771fe6b9 JG |
415 | case TV_STD_NTSC: |
416 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
417 | break; | |
418 | case TV_STD_PAL: | |
419 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; | |
420 | break; | |
421 | case TV_STD_PAL_M: | |
422 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; | |
423 | break; | |
424 | case TV_STD_PAL_60: | |
425 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; | |
426 | break; | |
427 | case TV_STD_NTSC_J: | |
428 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; | |
429 | break; | |
430 | case TV_STD_SCART_PAL: | |
431 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ | |
432 | break; | |
433 | case TV_STD_SECAM: | |
434 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; | |
435 | break; | |
436 | case TV_STD_PAL_CN: | |
437 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; | |
438 | break; | |
439 | default: | |
440 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; | |
441 | break; | |
442 | } | |
443 | } | |
444 | ||
445 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
446 | ||
447 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
448 | ||
449 | } | |
450 | ||
99999aaa AD |
451 | union dvo_encoder_control { |
452 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; | |
453 | DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; | |
454 | DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; | |
455 | }; | |
771fe6b9 | 456 | |
99999aaa AD |
457 | void |
458 | atombios_dvo_setup(struct drm_encoder *encoder, int action) | |
771fe6b9 JG |
459 | { |
460 | struct drm_device *dev = encoder->dev; | |
461 | struct radeon_device *rdev = dev->dev_private; | |
462 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
99999aaa AD |
463 | union dvo_encoder_control args; |
464 | int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); | |
771fe6b9 JG |
465 | |
466 | memset(&args, 0, sizeof(args)); | |
467 | ||
99999aaa AD |
468 | if (ASIC_IS_DCE3(rdev)) { |
469 | /* DCE3+ */ | |
470 | args.dvo_v3.ucAction = action; | |
471 | args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
472 | args.dvo_v3.ucDVOConfig = 0; /* XXX */ | |
473 | } else if (ASIC_IS_DCE2(rdev)) { | |
474 | /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */ | |
475 | args.dvo.sDVOEncoder.ucAction = action; | |
476 | args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
477 | /* DFP1, CRT1, TV1 depending on the type of port */ | |
478 | args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; | |
479 | ||
480 | if (radeon_encoder->pixel_clock > 165000) | |
481 | args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; | |
482 | } else { | |
483 | /* R4xx, R5xx */ | |
484 | args.ext_tmds.sXTmdsEncoder.ucEnable = action; | |
771fe6b9 | 485 | |
99999aaa AD |
486 | if (radeon_encoder->pixel_clock > 165000) |
487 | args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
771fe6b9 | 488 | |
99999aaa AD |
489 | /*if (pScrn->rgbBits == 8)*/ |
490 | args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; | |
491 | } | |
771fe6b9 JG |
492 | |
493 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
771fe6b9 JG |
494 | } |
495 | ||
496 | union lvds_encoder_control { | |
497 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; | |
498 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; | |
499 | }; | |
500 | ||
32f48ffe | 501 | void |
771fe6b9 JG |
502 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
503 | { | |
504 | struct drm_device *dev = encoder->dev; | |
505 | struct radeon_device *rdev = dev->dev_private; | |
506 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
9ae47867 | 507 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
771fe6b9 JG |
508 | union lvds_encoder_control args; |
509 | int index = 0; | |
dafc3bd5 | 510 | int hdmi_detected = 0; |
771fe6b9 | 511 | uint8_t frev, crev; |
771fe6b9 | 512 | |
4aab97e8 | 513 | if (!dig) |
771fe6b9 JG |
514 | return; |
515 | ||
9ae47867 | 516 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
dafc3bd5 CK |
517 | hdmi_detected = 1; |
518 | ||
771fe6b9 JG |
519 | memset(&args, 0, sizeof(args)); |
520 | ||
521 | switch (radeon_encoder->encoder_id) { | |
522 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
523 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
524 | break; | |
525 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
526 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
527 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); | |
528 | break; | |
529 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
530 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
531 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); | |
532 | else | |
533 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); | |
534 | break; | |
535 | } | |
536 | ||
a084e6ee AD |
537 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
538 | return; | |
771fe6b9 JG |
539 | |
540 | switch (frev) { | |
541 | case 1: | |
542 | case 2: | |
543 | switch (crev) { | |
544 | case 1: | |
545 | args.v1.ucMisc = 0; | |
546 | args.v1.ucAction = action; | |
dafc3bd5 | 547 | if (hdmi_detected) |
771fe6b9 JG |
548 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
549 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
550 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
ba032a58 | 551 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
771fe6b9 | 552 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
ba032a58 | 553 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
99999aaa | 554 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
771fe6b9 | 555 | } else { |
5137ee94 | 556 | if (dig->linkb) |
771fe6b9 JG |
557 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
558 | if (radeon_encoder->pixel_clock > 165000) | |
559 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
560 | /*if (pScrn->rgbBits == 8) */ | |
99999aaa | 561 | args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; |
771fe6b9 JG |
562 | } |
563 | break; | |
564 | case 2: | |
565 | case 3: | |
566 | args.v2.ucMisc = 0; | |
567 | args.v2.ucAction = action; | |
568 | if (crev == 3) { | |
569 | if (dig->coherent_mode) | |
570 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; | |
571 | } | |
dafc3bd5 | 572 | if (hdmi_detected) |
771fe6b9 JG |
573 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
574 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
575 | args.v2.ucTruncate = 0; | |
576 | args.v2.ucSpatial = 0; | |
577 | args.v2.ucTemporal = 0; | |
578 | args.v2.ucFRC = 0; | |
579 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
ba032a58 | 580 | if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) |
771fe6b9 | 581 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
ba032a58 | 582 | if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { |
771fe6b9 | 583 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
ba032a58 | 584 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
771fe6b9 JG |
585 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
586 | } | |
ba032a58 | 587 | if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { |
771fe6b9 | 588 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
ba032a58 | 589 | if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) |
771fe6b9 | 590 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
ba032a58 | 591 | if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) |
771fe6b9 JG |
592 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
593 | } | |
594 | } else { | |
5137ee94 | 595 | if (dig->linkb) |
771fe6b9 JG |
596 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
597 | if (radeon_encoder->pixel_clock > 165000) | |
598 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; | |
599 | } | |
600 | break; | |
601 | default: | |
602 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
603 | break; | |
604 | } | |
605 | break; | |
606 | default: | |
607 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); | |
608 | break; | |
609 | } | |
610 | ||
611 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
771fe6b9 JG |
612 | } |
613 | ||
614 | int | |
615 | atombios_get_encoder_mode(struct drm_encoder *encoder) | |
616 | { | |
c7a71fc7 | 617 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
d033af87 AD |
618 | struct drm_device *dev = encoder->dev; |
619 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 JG |
620 | struct drm_connector *connector; |
621 | struct radeon_connector *radeon_connector; | |
9ae47867 | 622 | struct radeon_connector_atom_dig *dig_connector; |
771fe6b9 JG |
623 | |
624 | connector = radeon_get_connector_for_encoder(encoder); | |
c7a71fc7 AD |
625 | if (!connector) { |
626 | switch (radeon_encoder->encoder_id) { | |
627 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
628 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
629 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
630 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
631 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
632 | return ATOM_ENCODER_MODE_DVI; | |
633 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
634 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
635 | default: | |
636 | return ATOM_ENCODER_MODE_CRT; | |
637 | } | |
638 | } | |
771fe6b9 JG |
639 | radeon_connector = to_radeon_connector(connector); |
640 | ||
641 | switch (connector->connector_type) { | |
642 | case DRM_MODE_CONNECTOR_DVII: | |
705af9c7 | 643 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
9453d621 | 644 | if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
d033af87 AD |
645 | /* fix me */ |
646 | if (ASIC_IS_DCE4(rdev)) | |
647 | return ATOM_ENCODER_MODE_DVI; | |
648 | else | |
649 | return ATOM_ENCODER_MODE_HDMI; | |
650 | } else if (radeon_connector->use_digital) | |
771fe6b9 JG |
651 | return ATOM_ENCODER_MODE_DVI; |
652 | else | |
653 | return ATOM_ENCODER_MODE_CRT; | |
654 | break; | |
655 | case DRM_MODE_CONNECTOR_DVID: | |
656 | case DRM_MODE_CONNECTOR_HDMIA: | |
771fe6b9 | 657 | default: |
9453d621 | 658 | if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
d033af87 AD |
659 | /* fix me */ |
660 | if (ASIC_IS_DCE4(rdev)) | |
661 | return ATOM_ENCODER_MODE_DVI; | |
662 | else | |
663 | return ATOM_ENCODER_MODE_HDMI; | |
664 | } else | |
771fe6b9 JG |
665 | return ATOM_ENCODER_MODE_DVI; |
666 | break; | |
667 | case DRM_MODE_CONNECTOR_LVDS: | |
668 | return ATOM_ENCODER_MODE_LVDS; | |
669 | break; | |
670 | case DRM_MODE_CONNECTOR_DisplayPort: | |
196c58d2 | 671 | case DRM_MODE_CONNECTOR_eDP: |
9ae47867 AD |
672 | dig_connector = radeon_connector->con_priv; |
673 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | |
674 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) | |
f92a8b67 | 675 | return ATOM_ENCODER_MODE_DP; |
9453d621 | 676 | else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) { |
d033af87 AD |
677 | /* fix me */ |
678 | if (ASIC_IS_DCE4(rdev)) | |
679 | return ATOM_ENCODER_MODE_DVI; | |
680 | else | |
681 | return ATOM_ENCODER_MODE_HDMI; | |
682 | } else | |
771fe6b9 JG |
683 | return ATOM_ENCODER_MODE_DVI; |
684 | break; | |
a5899fcc AD |
685 | case DRM_MODE_CONNECTOR_DVIA: |
686 | case DRM_MODE_CONNECTOR_VGA: | |
771fe6b9 JG |
687 | return ATOM_ENCODER_MODE_CRT; |
688 | break; | |
a5899fcc AD |
689 | case DRM_MODE_CONNECTOR_Composite: |
690 | case DRM_MODE_CONNECTOR_SVIDEO: | |
691 | case DRM_MODE_CONNECTOR_9PinDIN: | |
771fe6b9 JG |
692 | /* fix me */ |
693 | return ATOM_ENCODER_MODE_TV; | |
694 | /*return ATOM_ENCODER_MODE_CV;*/ | |
695 | break; | |
696 | } | |
697 | } | |
698 | ||
1a66c95a AD |
699 | /* |
700 | * DIG Encoder/Transmitter Setup | |
701 | * | |
702 | * DCE 3.0/3.1 | |
703 | * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. | |
704 | * Supports up to 3 digital outputs | |
705 | * - 2 DIG encoder blocks. | |
706 | * DIG1 can drive UNIPHY link A or link B | |
707 | * DIG2 can drive UNIPHY link B or LVTMA | |
708 | * | |
709 | * DCE 3.2 | |
710 | * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). | |
711 | * Supports up to 5 digital outputs | |
712 | * - 2 DIG encoder blocks. | |
713 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B | |
714 | * | |
a001182a | 715 | * DCE 4.0/5.0 |
4e8c65a1 | 716 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). |
bcc1c2a1 AD |
717 | * Supports up to 6 digital outputs |
718 | * - 6 DIG encoder blocks. | |
719 | * - DIG to PHY mapping is hardcoded | |
720 | * DIG1 drives UNIPHY0 link A, A+B | |
721 | * DIG2 drives UNIPHY0 link B | |
722 | * DIG3 drives UNIPHY1 link A, A+B | |
723 | * DIG4 drives UNIPHY1 link B | |
724 | * DIG5 drives UNIPHY2 link A, A+B | |
725 | * DIG6 drives UNIPHY2 link B | |
726 | * | |
4e8c65a1 AD |
727 | * DCE 4.1 |
728 | * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). | |
729 | * Supports up to 6 digital outputs | |
730 | * - 2 DIG encoder blocks. | |
731 | * DIG1/2 can drive UNIPHY0/1/2 link A or link B | |
732 | * | |
1a66c95a AD |
733 | * Routing |
734 | * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) | |
735 | * Examples: | |
736 | * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI | |
737 | * crtc1 -> dig1 -> UNIPHY0 link B -> DP | |
738 | * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS | |
739 | * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI | |
740 | */ | |
bcc1c2a1 AD |
741 | |
742 | union dig_encoder_control { | |
743 | DIG_ENCODER_CONTROL_PS_ALLOCATION v1; | |
744 | DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; | |
745 | DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; | |
badbb57b | 746 | DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; |
bcc1c2a1 AD |
747 | }; |
748 | ||
749 | void | |
771fe6b9 JG |
750 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) |
751 | { | |
752 | struct drm_device *dev = encoder->dev; | |
753 | struct radeon_device *rdev = dev->dev_private; | |
754 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
9ae47867 | 755 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
4aab97e8 | 756 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
bcc1c2a1 | 757 | union dig_encoder_control args; |
d9c9fe36 | 758 | int index = 0; |
771fe6b9 | 759 | uint8_t frev, crev; |
4aab97e8 AD |
760 | int dp_clock = 0; |
761 | int dp_lane_count = 0; | |
badbb57b | 762 | int hpd_id = RADEON_HPD_NONE; |
4aab97e8 AD |
763 | |
764 | if (connector) { | |
765 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
766 | struct radeon_connector_atom_dig *dig_connector = | |
767 | radeon_connector->con_priv; | |
771fe6b9 | 768 | |
4aab97e8 AD |
769 | dp_clock = dig_connector->dp_clock; |
770 | dp_lane_count = dig_connector->dp_lane_count; | |
badbb57b | 771 | hpd_id = radeon_connector->hpd.hpd; |
4aab97e8 AD |
772 | } |
773 | ||
774 | /* no dig encoder assigned */ | |
775 | if (dig->dig_encoder == -1) | |
771fe6b9 JG |
776 | return; |
777 | ||
771fe6b9 JG |
778 | memset(&args, 0, sizeof(args)); |
779 | ||
bcc1c2a1 AD |
780 | if (ASIC_IS_DCE4(rdev)) |
781 | index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); | |
782 | else { | |
783 | if (dig->dig_encoder) | |
784 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); | |
785 | else | |
786 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); | |
787 | } | |
771fe6b9 | 788 | |
a084e6ee AD |
789 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
790 | return; | |
771fe6b9 | 791 | |
bcc1c2a1 AD |
792 | args.v1.ucAction = action; |
793 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
794 | args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
771fe6b9 | 795 | |
badbb57b AD |
796 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || |
797 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) | |
4aab97e8 | 798 | args.v1.ucLaneNum = dp_lane_count; |
badbb57b | 799 | else if (radeon_encoder->pixel_clock > 165000) |
bcc1c2a1 AD |
800 | args.v1.ucLaneNum = 8; |
801 | else | |
802 | args.v1.ucLaneNum = 4; | |
803 | ||
badbb57b AD |
804 | if (ASIC_IS_DCE5(rdev)) { |
805 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) || | |
806 | (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) { | |
807 | if (dp_clock == 270000) | |
808 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; | |
809 | else if (dp_clock == 540000) | |
810 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; | |
811 | } | |
812 | args.v4.acConfig.ucDigSel = dig->dig_encoder; | |
813 | args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; | |
814 | if (hpd_id == RADEON_HPD_NONE) | |
815 | args.v4.ucHPD_ID = 0; | |
816 | else | |
817 | args.v4.ucHPD_ID = hpd_id + 1; | |
818 | } else if (ASIC_IS_DCE4(rdev)) { | |
819 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) | |
820 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; | |
bcc1c2a1 AD |
821 | args.v3.acConfig.ucDigSel = dig->dig_encoder; |
822 | args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; | |
823 | } else { | |
badbb57b AD |
824 | if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000)) |
825 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | |
771fe6b9 JG |
826 | switch (radeon_encoder->encoder_id) { |
827 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
bcc1c2a1 | 828 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
771fe6b9 JG |
829 | break; |
830 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
bcc1c2a1 AD |
831 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
832 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; | |
771fe6b9 JG |
833 | break; |
834 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
bcc1c2a1 | 835 | args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
771fe6b9 JG |
836 | break; |
837 | } | |
5137ee94 | 838 | if (dig->linkb) |
bcc1c2a1 AD |
839 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
840 | else | |
841 | args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; | |
771fe6b9 JG |
842 | } |
843 | ||
771fe6b9 JG |
844 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
845 | ||
846 | } | |
847 | ||
848 | union dig_transmitter_control { | |
849 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; | |
850 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; | |
bcc1c2a1 | 851 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; |
a001182a | 852 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; |
771fe6b9 JG |
853 | }; |
854 | ||
5801ead6 | 855 | void |
1a66c95a | 856 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) |
771fe6b9 JG |
857 | { |
858 | struct drm_device *dev = encoder->dev; | |
859 | struct radeon_device *rdev = dev->dev_private; | |
860 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
9ae47867 | 861 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
4aab97e8 | 862 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
771fe6b9 | 863 | union dig_transmitter_control args; |
d9c9fe36 | 864 | int index = 0; |
771fe6b9 | 865 | uint8_t frev, crev; |
f92a8b67 | 866 | bool is_dp = false; |
bcc1c2a1 | 867 | int pll_id = 0; |
4aab97e8 AD |
868 | int dp_clock = 0; |
869 | int dp_lane_count = 0; | |
870 | int connector_object_id = 0; | |
871 | int igp_lane_info = 0; | |
872 | ||
873 | if (connector) { | |
874 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
875 | struct radeon_connector_atom_dig *dig_connector = | |
876 | radeon_connector->con_priv; | |
877 | ||
878 | dp_clock = dig_connector->dp_clock; | |
879 | dp_lane_count = dig_connector->dp_lane_count; | |
880 | connector_object_id = | |
881 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
882 | igp_lane_info = dig_connector->igp_lane_info; | |
883 | } | |
771fe6b9 | 884 | |
4aab97e8 AD |
885 | /* no dig encoder assigned */ |
886 | if (dig->dig_encoder == -1) | |
771fe6b9 JG |
887 | return; |
888 | ||
f92a8b67 AD |
889 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) |
890 | is_dp = true; | |
891 | ||
771fe6b9 JG |
892 | memset(&args, 0, sizeof(args)); |
893 | ||
4aab97e8 | 894 | switch (radeon_encoder->encoder_id) { |
99999aaa AD |
895 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
896 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); | |
897 | break; | |
4aab97e8 AD |
898 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
899 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
900 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
771fe6b9 | 901 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
4aab97e8 AD |
902 | break; |
903 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
904 | index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); | |
905 | break; | |
771fe6b9 JG |
906 | } |
907 | ||
a084e6ee AD |
908 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
909 | return; | |
771fe6b9 JG |
910 | |
911 | args.v1.ucAction = action; | |
f95a9f0b | 912 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
4589433c | 913 | args.v1.usInitInfo = cpu_to_le16(connector_object_id); |
1a66c95a AD |
914 | } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { |
915 | args.v1.asMode.ucLaneSel = lane_num; | |
916 | args.v1.asMode.ucLaneSet = lane_set; | |
f95a9f0b | 917 | } else { |
f92a8b67 AD |
918 | if (is_dp) |
919 | args.v1.usPixelClock = | |
4aab97e8 | 920 | cpu_to_le16(dp_clock / 10); |
f92a8b67 | 921 | else if (radeon_encoder->pixel_clock > 165000) |
f95a9f0b AD |
922 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
923 | else | |
924 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
925 | } | |
bcc1c2a1 AD |
926 | if (ASIC_IS_DCE4(rdev)) { |
927 | if (is_dp) | |
4aab97e8 | 928 | args.v3.ucLaneNum = dp_lane_count; |
bcc1c2a1 AD |
929 | else if (radeon_encoder->pixel_clock > 165000) |
930 | args.v3.ucLaneNum = 8; | |
931 | else | |
932 | args.v3.ucLaneNum = 4; | |
933 | ||
b61c99de AD |
934 | if (dig->linkb) { |
935 | args.v3.acConfig.ucLinkSel = 1; | |
936 | args.v3.acConfig.ucEncoderSel = 1; | |
bcc1c2a1 AD |
937 | } |
938 | ||
939 | /* Select the PLL for the PHY | |
940 | * DP PHY should be clocked from external src if there is | |
941 | * one. | |
942 | */ | |
943 | if (encoder->crtc) { | |
944 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
945 | pll_id = radeon_crtc->pll_id; | |
946 | } | |
a001182a AD |
947 | |
948 | if (ASIC_IS_DCE5(rdev)) { | |
949 | if (is_dp && rdev->clock.dp_extclk) | |
950 | args.v4.acConfig.ucRefClkSource = 3; /* external src */ | |
951 | else | |
952 | args.v4.acConfig.ucRefClkSource = pll_id; | |
953 | } else { | |
954 | if (is_dp && rdev->clock.dp_extclk) | |
955 | args.v3.acConfig.ucRefClkSource = 2; /* external src */ | |
956 | else | |
957 | args.v3.acConfig.ucRefClkSource = pll_id; | |
958 | } | |
bcc1c2a1 AD |
959 | |
960 | switch (radeon_encoder->encoder_id) { | |
961 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
962 | args.v3.acConfig.ucTransmitterSel = 0; | |
bcc1c2a1 AD |
963 | break; |
964 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
965 | args.v3.acConfig.ucTransmitterSel = 1; | |
bcc1c2a1 AD |
966 | break; |
967 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
968 | args.v3.acConfig.ucTransmitterSel = 2; | |
bcc1c2a1 AD |
969 | break; |
970 | } | |
971 | ||
972 | if (is_dp) | |
973 | args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ | |
974 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
975 | if (dig->coherent_mode) | |
976 | args.v3.acConfig.fCoherentMode = 1; | |
b317a9ce AD |
977 | if (radeon_encoder->pixel_clock > 165000) |
978 | args.v3.acConfig.fDualLinkConnector = 1; | |
bcc1c2a1 AD |
979 | } |
980 | } else if (ASIC_IS_DCE32(rdev)) { | |
d9c9fe36 | 981 | args.v2.acConfig.ucEncoderSel = dig->dig_encoder; |
5137ee94 | 982 | if (dig->linkb) |
1a66c95a | 983 | args.v2.acConfig.ucLinkSel = 1; |
771fe6b9 JG |
984 | |
985 | switch (radeon_encoder->encoder_id) { | |
986 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
987 | args.v2.acConfig.ucTransmitterSel = 0; | |
771fe6b9 JG |
988 | break; |
989 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
990 | args.v2.acConfig.ucTransmitterSel = 1; | |
771fe6b9 JG |
991 | break; |
992 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
993 | args.v2.acConfig.ucTransmitterSel = 2; | |
771fe6b9 JG |
994 | break; |
995 | } | |
996 | ||
f92a8b67 AD |
997 | if (is_dp) |
998 | args.v2.acConfig.fCoherentMode = 1; | |
999 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
771fe6b9 JG |
1000 | if (dig->coherent_mode) |
1001 | args.v2.acConfig.fCoherentMode = 1; | |
b317a9ce AD |
1002 | if (radeon_encoder->pixel_clock > 165000) |
1003 | args.v2.acConfig.fDualLinkConnector = 1; | |
771fe6b9 JG |
1004 | } |
1005 | } else { | |
1006 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; | |
771fe6b9 | 1007 | |
f28cf339 DA |
1008 | if (dig->dig_encoder) |
1009 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; | |
1010 | else | |
1011 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; | |
1012 | ||
d9c9fe36 AD |
1013 | if ((rdev->flags & RADEON_IS_IGP) && |
1014 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { | |
1015 | if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { | |
4aab97e8 | 1016 | if (igp_lane_info & 0x1) |
d9c9fe36 | 1017 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
4aab97e8 | 1018 | else if (igp_lane_info & 0x2) |
d9c9fe36 | 1019 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
4aab97e8 | 1020 | else if (igp_lane_info & 0x4) |
d9c9fe36 | 1021 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
4aab97e8 | 1022 | else if (igp_lane_info & 0x8) |
d9c9fe36 AD |
1023 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
1024 | } else { | |
4aab97e8 | 1025 | if (igp_lane_info & 0x3) |
d9c9fe36 | 1026 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
4aab97e8 | 1027 | else if (igp_lane_info & 0xc) |
d9c9fe36 | 1028 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
771fe6b9 | 1029 | } |
771fe6b9 JG |
1030 | } |
1031 | ||
5137ee94 | 1032 | if (dig->linkb) |
1a66c95a AD |
1033 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; |
1034 | else | |
1035 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; | |
1036 | ||
f92a8b67 AD |
1037 | if (is_dp) |
1038 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
1039 | else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
771fe6b9 JG |
1040 | if (dig->coherent_mode) |
1041 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; | |
d9c9fe36 AD |
1042 | if (radeon_encoder->pixel_clock > 165000) |
1043 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; | |
771fe6b9 JG |
1044 | } |
1045 | } | |
1046 | ||
1047 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
771fe6b9 JG |
1048 | } |
1049 | ||
8b834852 AD |
1050 | void |
1051 | atombios_set_edp_panel_power(struct drm_connector *connector, int action) | |
1052 | { | |
1053 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1054 | struct drm_device *dev = radeon_connector->base.dev; | |
1055 | struct radeon_device *rdev = dev->dev_private; | |
1056 | union dig_transmitter_control args; | |
1057 | int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); | |
1058 | uint8_t frev, crev; | |
1059 | ||
1060 | if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
1061 | return; | |
1062 | ||
1063 | if (!ASIC_IS_DCE4(rdev)) | |
1064 | return; | |
1065 | ||
e468e001 | 1066 | if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && |
8b834852 AD |
1067 | (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) |
1068 | return; | |
1069 | ||
1070 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1071 | return; | |
1072 | ||
1073 | memset(&args, 0, sizeof(args)); | |
1074 | ||
1075 | args.v1.ucAction = action; | |
1076 | ||
1077 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1078 | } | |
1079 | ||
3e4b9982 AD |
1080 | union external_encoder_control { |
1081 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; | |
bf982ebf | 1082 | EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; |
3e4b9982 AD |
1083 | }; |
1084 | ||
1085 | static void | |
1086 | atombios_external_encoder_setup(struct drm_encoder *encoder, | |
1087 | struct drm_encoder *ext_encoder, | |
1088 | int action) | |
1089 | { | |
1090 | struct drm_device *dev = encoder->dev; | |
1091 | struct radeon_device *rdev = dev->dev_private; | |
1092 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
bf982ebf | 1093 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); |
3e4b9982 AD |
1094 | union external_encoder_control args; |
1095 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
1096 | int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); | |
1097 | u8 frev, crev; | |
1098 | int dp_clock = 0; | |
1099 | int dp_lane_count = 0; | |
1100 | int connector_object_id = 0; | |
bf982ebf | 1101 | u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
3e4b9982 AD |
1102 | |
1103 | if (connector) { | |
1104 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1105 | struct radeon_connector_atom_dig *dig_connector = | |
1106 | radeon_connector->con_priv; | |
1107 | ||
1108 | dp_clock = dig_connector->dp_clock; | |
1109 | dp_lane_count = dig_connector->dp_lane_count; | |
1110 | connector_object_id = | |
1111 | (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
1112 | } | |
1113 | ||
1114 | memset(&args, 0, sizeof(args)); | |
1115 | ||
1116 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) | |
1117 | return; | |
1118 | ||
1119 | switch (frev) { | |
1120 | case 1: | |
1121 | /* no params on frev 1 */ | |
1122 | break; | |
1123 | case 2: | |
1124 | switch (crev) { | |
1125 | case 1: | |
1126 | case 2: | |
1127 | args.v1.sDigEncoder.ucAction = action; | |
1128 | args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1129 | args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
1130 | ||
1131 | if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { | |
1132 | if (dp_clock == 270000) | |
1133 | args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; | |
1134 | args.v1.sDigEncoder.ucLaneNum = dp_lane_count; | |
1135 | } else if (radeon_encoder->pixel_clock > 165000) | |
1136 | args.v1.sDigEncoder.ucLaneNum = 8; | |
1137 | else | |
1138 | args.v1.sDigEncoder.ucLaneNum = 4; | |
1139 | break; | |
bf982ebf AD |
1140 | case 3: |
1141 | args.v3.sExtEncoder.ucAction = action; | |
1142 | if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) | |
4589433c | 1143 | args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); |
bf982ebf AD |
1144 | else |
1145 | args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); | |
1146 | args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); | |
1147 | ||
1148 | if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) { | |
1149 | if (dp_clock == 270000) | |
1150 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; | |
1151 | else if (dp_clock == 540000) | |
1152 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; | |
1153 | args.v3.sExtEncoder.ucLaneNum = dp_lane_count; | |
1154 | } else if (radeon_encoder->pixel_clock > 165000) | |
1155 | args.v3.sExtEncoder.ucLaneNum = 8; | |
1156 | else | |
1157 | args.v3.sExtEncoder.ucLaneNum = 4; | |
1158 | switch (ext_enum) { | |
1159 | case GRAPH_OBJECT_ENUM_ID1: | |
1160 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; | |
1161 | break; | |
1162 | case GRAPH_OBJECT_ENUM_ID2: | |
1163 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; | |
1164 | break; | |
1165 | case GRAPH_OBJECT_ENUM_ID3: | |
1166 | args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; | |
1167 | break; | |
1168 | } | |
1169 | args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR; | |
1170 | break; | |
3e4b9982 AD |
1171 | default: |
1172 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1173 | return; | |
1174 | } | |
1175 | break; | |
1176 | default: | |
1177 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
1178 | return; | |
1179 | } | |
1180 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1181 | } | |
1182 | ||
771fe6b9 JG |
1183 | static void |
1184 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) | |
1185 | { | |
1186 | struct drm_device *dev = encoder->dev; | |
1187 | struct radeon_device *rdev = dev->dev_private; | |
1188 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1189 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1190 | ENABLE_YUV_PS_ALLOCATION args; | |
1191 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); | |
1192 | uint32_t temp, reg; | |
1193 | ||
1194 | memset(&args, 0, sizeof(args)); | |
1195 | ||
1196 | if (rdev->family >= CHIP_R600) | |
1197 | reg = R600_BIOS_3_SCRATCH; | |
1198 | else | |
1199 | reg = RADEON_BIOS_3_SCRATCH; | |
1200 | ||
1201 | /* XXX: fix up scratch reg handling */ | |
1202 | temp = RREG32(reg); | |
4ce001ab | 1203 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 JG |
1204 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
1205 | (radeon_crtc->crtc_id << 18))); | |
4ce001ab | 1206 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1207 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
1208 | else | |
1209 | WREG32(reg, 0); | |
1210 | ||
1211 | if (enable) | |
1212 | args.ucEnable = ATOM_ENABLE; | |
1213 | args.ucCRTC = radeon_crtc->crtc_id; | |
1214 | ||
1215 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1216 | ||
1217 | WREG32(reg, temp); | |
1218 | } | |
1219 | ||
771fe6b9 JG |
1220 | static void |
1221 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) | |
1222 | { | |
1223 | struct drm_device *dev = encoder->dev; | |
1224 | struct radeon_device *rdev = dev->dev_private; | |
1225 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
3e4b9982 | 1226 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
771fe6b9 JG |
1227 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
1228 | int index = 0; | |
1229 | bool is_dig = false; | |
69c74525 | 1230 | bool is_dce5_dac = false; |
d07f4e83 | 1231 | bool is_dce5_dvo = false; |
771fe6b9 JG |
1232 | |
1233 | memset(&args, 0, sizeof(args)); | |
1234 | ||
d9fdaafb | 1235 | DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
f641e51e DA |
1236 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1237 | radeon_encoder->active_device); | |
771fe6b9 JG |
1238 | switch (radeon_encoder->encoder_id) { |
1239 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1240 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1241 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); | |
1242 | break; | |
1243 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1244 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1245 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1246 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1247 | is_dig = true; | |
1248 | break; | |
1249 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1250 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
771fe6b9 JG |
1251 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
1252 | break; | |
99999aaa | 1253 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
d07f4e83 AD |
1254 | if (ASIC_IS_DCE5(rdev)) |
1255 | is_dce5_dvo = true; | |
1256 | else if (ASIC_IS_DCE3(rdev)) | |
99999aaa AD |
1257 | is_dig = true; |
1258 | else | |
1259 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); | |
1260 | break; | |
771fe6b9 JG |
1261 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
1262 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1263 | break; | |
1264 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1265 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
1266 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); | |
1267 | else | |
1268 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); | |
1269 | break; | |
1270 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1271 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
69c74525 AD |
1272 | if (ASIC_IS_DCE5(rdev)) |
1273 | is_dce5_dac = true; | |
1274 | else { | |
1275 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
1276 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); | |
1277 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) | |
1278 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); | |
1279 | else | |
1280 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); | |
1281 | } | |
771fe6b9 JG |
1282 | break; |
1283 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1284 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
8c2a6d73 | 1285 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1286 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
8c2a6d73 | 1287 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1288 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
1289 | else | |
1290 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); | |
1291 | break; | |
1292 | } | |
1293 | ||
1294 | if (is_dig) { | |
1295 | switch (mode) { | |
1296 | case DRM_MODE_DPMS_ON: | |
e13b2ac1 | 1297 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
fb668c2f | 1298 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
58682f10 | 1299 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
fb668c2f | 1300 | |
8b834852 AD |
1301 | if (connector && |
1302 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
1303 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1304 | struct radeon_connector_atom_dig *radeon_dig_connector = | |
1305 | radeon_connector->con_priv; | |
1306 | atombios_set_edp_panel_power(connector, | |
1307 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
1308 | radeon_dig_connector->edp_on = true; | |
1309 | } | |
58682f10 | 1310 | dp_link_train(encoder, connector); |
fb668c2f AD |
1311 | if (ASIC_IS_DCE4(rdev)) |
1312 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON); | |
58682f10 | 1313 | } |
ba251bde AD |
1314 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1315 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); | |
771fe6b9 JG |
1316 | break; |
1317 | case DRM_MODE_DPMS_STANDBY: | |
1318 | case DRM_MODE_DPMS_SUSPEND: | |
1319 | case DRM_MODE_DPMS_OFF: | |
e13b2ac1 | 1320 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
fb668c2f | 1321 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { |
8b834852 AD |
1322 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
1323 | ||
fb668c2f AD |
1324 | if (ASIC_IS_DCE4(rdev)) |
1325 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); | |
8b834852 AD |
1326 | if (connector && |
1327 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
1328 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1329 | struct radeon_connector_atom_dig *radeon_dig_connector = | |
1330 | radeon_connector->con_priv; | |
1331 | atombios_set_edp_panel_power(connector, | |
1332 | ATOM_TRANSMITTER_ACTION_POWER_OFF); | |
1333 | radeon_dig_connector->edp_on = false; | |
1334 | } | |
fb668c2f | 1335 | } |
ba251bde AD |
1336 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
1337 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); | |
771fe6b9 JG |
1338 | break; |
1339 | } | |
69c74525 AD |
1340 | } else if (is_dce5_dac) { |
1341 | switch (mode) { | |
1342 | case DRM_MODE_DPMS_ON: | |
1343 | atombios_dac_setup(encoder, ATOM_ENABLE); | |
1344 | break; | |
1345 | case DRM_MODE_DPMS_STANDBY: | |
1346 | case DRM_MODE_DPMS_SUSPEND: | |
1347 | case DRM_MODE_DPMS_OFF: | |
1348 | atombios_dac_setup(encoder, ATOM_DISABLE); | |
1349 | break; | |
1350 | } | |
d07f4e83 AD |
1351 | } else if (is_dce5_dvo) { |
1352 | switch (mode) { | |
1353 | case DRM_MODE_DPMS_ON: | |
1354 | atombios_dvo_setup(encoder, ATOM_ENABLE); | |
1355 | break; | |
1356 | case DRM_MODE_DPMS_STANDBY: | |
1357 | case DRM_MODE_DPMS_SUSPEND: | |
1358 | case DRM_MODE_DPMS_OFF: | |
1359 | atombios_dvo_setup(encoder, ATOM_DISABLE); | |
1360 | break; | |
1361 | } | |
771fe6b9 JG |
1362 | } else { |
1363 | switch (mode) { | |
1364 | case DRM_MODE_DPMS_ON: | |
1365 | args.ucAction = ATOM_ENABLE; | |
ba251bde AD |
1366 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1367 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1368 | args.ucAction = ATOM_LCD_BLON; | |
1369 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1370 | } | |
771fe6b9 JG |
1371 | break; |
1372 | case DRM_MODE_DPMS_STANDBY: | |
1373 | case DRM_MODE_DPMS_SUSPEND: | |
1374 | case DRM_MODE_DPMS_OFF: | |
1375 | args.ucAction = ATOM_DISABLE; | |
ba251bde AD |
1376 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
1377 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
1378 | args.ucAction = ATOM_LCD_BLOFF; | |
1379 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1380 | } | |
771fe6b9 JG |
1381 | break; |
1382 | } | |
771fe6b9 | 1383 | } |
3e4b9982 AD |
1384 | |
1385 | if (ext_encoder) { | |
1386 | int action; | |
1387 | ||
1388 | switch (mode) { | |
1389 | case DRM_MODE_DPMS_ON: | |
1390 | default: | |
633b9164 | 1391 | if (ASIC_IS_DCE41(rdev)) |
bf982ebf AD |
1392 | action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT; |
1393 | else | |
1394 | action = ATOM_ENABLE; | |
3e4b9982 AD |
1395 | break; |
1396 | case DRM_MODE_DPMS_STANDBY: | |
1397 | case DRM_MODE_DPMS_SUSPEND: | |
1398 | case DRM_MODE_DPMS_OFF: | |
633b9164 | 1399 | if (ASIC_IS_DCE41(rdev)) |
bf982ebf AD |
1400 | action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT; |
1401 | else | |
1402 | action = ATOM_DISABLE; | |
3e4b9982 AD |
1403 | break; |
1404 | } | |
1405 | atombios_external_encoder_setup(encoder, ext_encoder, action); | |
1406 | } | |
1407 | ||
771fe6b9 | 1408 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
c913e23a | 1409 | |
771fe6b9 JG |
1410 | } |
1411 | ||
9ae47867 | 1412 | union crtc_source_param { |
771fe6b9 JG |
1413 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
1414 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; | |
1415 | }; | |
1416 | ||
1417 | static void | |
1418 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) | |
1419 | { | |
1420 | struct drm_device *dev = encoder->dev; | |
1421 | struct radeon_device *rdev = dev->dev_private; | |
1422 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1423 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
9ae47867 | 1424 | union crtc_source_param args; |
771fe6b9 JG |
1425 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
1426 | uint8_t frev, crev; | |
f28cf339 | 1427 | struct radeon_encoder_atom_dig *dig; |
771fe6b9 JG |
1428 | |
1429 | memset(&args, 0, sizeof(args)); | |
1430 | ||
a084e6ee AD |
1431 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1432 | return; | |
771fe6b9 JG |
1433 | |
1434 | switch (frev) { | |
1435 | case 1: | |
1436 | switch (crev) { | |
1437 | case 1: | |
1438 | default: | |
1439 | if (ASIC_IS_AVIVO(rdev)) | |
1440 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1441 | else { | |
1442 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { | |
1443 | args.v1.ucCRTC = radeon_crtc->crtc_id; | |
1444 | } else { | |
1445 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; | |
1446 | } | |
1447 | } | |
1448 | switch (radeon_encoder->encoder_id) { | |
1449 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1450 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1451 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; | |
1452 | break; | |
1453 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1454 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1455 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) | |
1456 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; | |
1457 | else | |
1458 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; | |
1459 | break; | |
1460 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
1461 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
1462 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1463 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; | |
1464 | break; | |
1465 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1466 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
4ce001ab | 1467 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1468 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
4ce001ab | 1469 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1470 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1471 | else | |
1472 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; | |
1473 | break; | |
1474 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1475 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
4ce001ab | 1476 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1477 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
4ce001ab | 1478 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1479 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
1480 | else | |
1481 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; | |
1482 | break; | |
1483 | } | |
1484 | break; | |
1485 | case 2: | |
1486 | args.v2.ucCRTC = radeon_crtc->crtc_id; | |
1487 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); | |
1488 | switch (radeon_encoder->encoder_id) { | |
1489 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1490 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1491 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
f28cf339 DA |
1492 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1493 | dig = radeon_encoder->enc_priv; | |
bcc1c2a1 AD |
1494 | switch (dig->dig_encoder) { |
1495 | case 0: | |
f28cf339 | 1496 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
bcc1c2a1 AD |
1497 | break; |
1498 | case 1: | |
1499 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; | |
1500 | break; | |
1501 | case 2: | |
1502 | args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; | |
1503 | break; | |
1504 | case 3: | |
1505 | args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; | |
1506 | break; | |
1507 | case 4: | |
1508 | args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; | |
1509 | break; | |
1510 | case 5: | |
1511 | args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; | |
1512 | break; | |
1513 | } | |
771fe6b9 JG |
1514 | break; |
1515 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
1516 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; | |
1517 | break; | |
771fe6b9 | 1518 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
4ce001ab | 1519 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1520 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
4ce001ab | 1521 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1522 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1523 | else | |
1524 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; | |
1525 | break; | |
1526 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
4ce001ab | 1527 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 | 1528 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
4ce001ab | 1529 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
771fe6b9 JG |
1530 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
1531 | else | |
1532 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; | |
1533 | break; | |
1534 | } | |
1535 | break; | |
1536 | } | |
1537 | break; | |
1538 | default: | |
1539 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); | |
99999aaa | 1540 | return; |
771fe6b9 JG |
1541 | } |
1542 | ||
1543 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
267364ac AD |
1544 | |
1545 | /* update scratch regs with new routing */ | |
1546 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); | |
771fe6b9 JG |
1547 | } |
1548 | ||
1549 | static void | |
1550 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, | |
1551 | struct drm_display_mode *mode) | |
1552 | { | |
1553 | struct drm_device *dev = encoder->dev; | |
1554 | struct radeon_device *rdev = dev->dev_private; | |
1555 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1556 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1557 | ||
1558 | /* Funky macbooks */ | |
1559 | if ((dev->pdev->device == 0x71C5) && | |
1560 | (dev->pdev->subsystem_vendor == 0x106b) && | |
1561 | (dev->pdev->subsystem_device == 0x0080)) { | |
1562 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
1563 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); | |
1564 | ||
1565 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; | |
1566 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; | |
1567 | ||
1568 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); | |
1569 | } | |
1570 | } | |
1571 | ||
1572 | /* set scaler clears this on some chips */ | |
c9417bdd AD |
1573 | if (ASIC_IS_AVIVO(rdev) && |
1574 | (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { | |
1575 | if (ASIC_IS_DCE4(rdev)) { | |
1576 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1577 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, | |
1578 | EVERGREEN_INTERLEAVE_EN); | |
1579 | else | |
1580 | WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | |
1581 | } else { | |
1582 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1583 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, | |
1584 | AVIVO_D1MODE_INTERLEAVE_EN); | |
1585 | else | |
1586 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); | |
1587 | } | |
ceefedd8 | 1588 | } |
771fe6b9 JG |
1589 | } |
1590 | ||
f28cf339 DA |
1591 | static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) |
1592 | { | |
1593 | struct drm_device *dev = encoder->dev; | |
1594 | struct radeon_device *rdev = dev->dev_private; | |
1595 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
1596 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1597 | struct drm_encoder *test_encoder; | |
1598 | struct radeon_encoder_atom_dig *dig; | |
1599 | uint32_t dig_enc_in_use = 0; | |
bcc1c2a1 | 1600 | |
badbb57b | 1601 | /* DCE4/5 */ |
bcc1c2a1 | 1602 | if (ASIC_IS_DCE4(rdev)) { |
5137ee94 | 1603 | dig = radeon_encoder->enc_priv; |
b61c99de | 1604 | if (ASIC_IS_DCE41(rdev)) { |
5137ee94 | 1605 | if (dig->linkb) |
bcc1c2a1 AD |
1606 | return 1; |
1607 | else | |
1608 | return 0; | |
b61c99de AD |
1609 | } else { |
1610 | switch (radeon_encoder->encoder_id) { | |
1611 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1612 | if (dig->linkb) | |
1613 | return 1; | |
1614 | else | |
1615 | return 0; | |
1616 | break; | |
1617 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1618 | if (dig->linkb) | |
1619 | return 3; | |
1620 | else | |
1621 | return 2; | |
1622 | break; | |
1623 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1624 | if (dig->linkb) | |
1625 | return 5; | |
1626 | else | |
1627 | return 4; | |
1628 | break; | |
1629 | } | |
bcc1c2a1 AD |
1630 | } |
1631 | } | |
1632 | ||
f28cf339 DA |
1633 | /* on DCE32 and encoder can driver any block so just crtc id */ |
1634 | if (ASIC_IS_DCE32(rdev)) { | |
1635 | return radeon_crtc->crtc_id; | |
1636 | } | |
1637 | ||
1638 | /* on DCE3 - LVTMA can only be driven by DIGB */ | |
1639 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { | |
1640 | struct radeon_encoder *radeon_test_encoder; | |
1641 | ||
1642 | if (encoder == test_encoder) | |
1643 | continue; | |
1644 | ||
1645 | if (!radeon_encoder_is_digital(test_encoder)) | |
1646 | continue; | |
1647 | ||
1648 | radeon_test_encoder = to_radeon_encoder(test_encoder); | |
1649 | dig = radeon_test_encoder->enc_priv; | |
1650 | ||
1651 | if (dig->dig_encoder >= 0) | |
1652 | dig_enc_in_use |= (1 << dig->dig_encoder); | |
1653 | } | |
1654 | ||
1655 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { | |
1656 | if (dig_enc_in_use & 0x2) | |
1657 | DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); | |
1658 | return 1; | |
1659 | } | |
1660 | if (!(dig_enc_in_use & 1)) | |
1661 | return 0; | |
1662 | return 1; | |
1663 | } | |
1664 | ||
771fe6b9 JG |
1665 | static void |
1666 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, | |
1667 | struct drm_display_mode *mode, | |
1668 | struct drm_display_mode *adjusted_mode) | |
1669 | { | |
1670 | struct drm_device *dev = encoder->dev; | |
1671 | struct radeon_device *rdev = dev->dev_private; | |
1672 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
3e4b9982 | 1673 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); |
771fe6b9 | 1674 | |
771fe6b9 JG |
1675 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
1676 | ||
c6f8505e | 1677 | if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { |
4ce001ab | 1678 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
771fe6b9 JG |
1679 | atombios_yuv_setup(encoder, true); |
1680 | else | |
1681 | atombios_yuv_setup(encoder, false); | |
1682 | } | |
1683 | ||
1684 | switch (radeon_encoder->encoder_id) { | |
1685 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1686 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1687 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1688 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1689 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); | |
1690 | break; | |
1691 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1692 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1693 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1694 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
bcc1c2a1 AD |
1695 | if (ASIC_IS_DCE4(rdev)) { |
1696 | /* disable the transmitter */ | |
1697 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1698 | /* setup and enable the encoder */ | |
1699 | atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP); | |
1700 | ||
1701 | /* init and enable the transmitter */ | |
1702 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); | |
1703 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
1704 | } else { | |
1705 | /* disable the encoder and transmitter */ | |
1706 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1707 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); | |
1708 | ||
1709 | /* setup and enable the encoder and transmitter */ | |
1710 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); | |
1711 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); | |
1712 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); | |
1713 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); | |
1714 | } | |
771fe6b9 JG |
1715 | break; |
1716 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
771fe6b9 JG |
1717 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1718 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
99999aaa | 1719 | atombios_dvo_setup(encoder, ATOM_ENABLE); |
771fe6b9 JG |
1720 | break; |
1721 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1722 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1723 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1724 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1725 | atombios_dac_setup(encoder, ATOM_ENABLE); | |
d3a67a43 AD |
1726 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { |
1727 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
1728 | atombios_tv_setup(encoder, ATOM_ENABLE); | |
1729 | else | |
1730 | atombios_tv_setup(encoder, ATOM_DISABLE); | |
1731 | } | |
771fe6b9 JG |
1732 | break; |
1733 | } | |
3e4b9982 AD |
1734 | |
1735 | if (ext_encoder) { | |
633b9164 | 1736 | if (ASIC_IS_DCE41(rdev)) { |
bf982ebf AD |
1737 | atombios_external_encoder_setup(encoder, ext_encoder, |
1738 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); | |
1739 | atombios_external_encoder_setup(encoder, ext_encoder, | |
1740 | EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); | |
1741 | } else | |
1742 | atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); | |
3e4b9982 AD |
1743 | } |
1744 | ||
771fe6b9 | 1745 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
dafc3bd5 | 1746 | |
2cd6218c RM |
1747 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
1748 | r600_hdmi_enable(encoder); | |
bcc1c2a1 | 1749 | r600_hdmi_setmode(encoder, adjusted_mode); |
2cd6218c | 1750 | } |
771fe6b9 JG |
1751 | } |
1752 | ||
1753 | static bool | |
4ce001ab | 1754 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
771fe6b9 JG |
1755 | { |
1756 | struct drm_device *dev = encoder->dev; | |
1757 | struct radeon_device *rdev = dev->dev_private; | |
1758 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4ce001ab | 1759 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
771fe6b9 JG |
1760 | |
1761 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | | |
1762 | ATOM_DEVICE_CV_SUPPORT | | |
1763 | ATOM_DEVICE_CRT_SUPPORT)) { | |
1764 | DAC_LOAD_DETECTION_PS_ALLOCATION args; | |
1765 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); | |
1766 | uint8_t frev, crev; | |
1767 | ||
1768 | memset(&args, 0, sizeof(args)); | |
1769 | ||
a084e6ee AD |
1770 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) |
1771 | return false; | |
771fe6b9 JG |
1772 | |
1773 | args.sDacload.ucMisc = 0; | |
1774 | ||
1775 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || | |
1776 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) | |
1777 | args.sDacload.ucDacType = ATOM_DAC_A; | |
1778 | else | |
1779 | args.sDacload.ucDacType = ATOM_DAC_B; | |
1780 | ||
4ce001ab | 1781 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
771fe6b9 | 1782 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
4ce001ab | 1783 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
771fe6b9 | 1784 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
4ce001ab | 1785 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
771fe6b9 JG |
1786 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
1787 | if (crev >= 3) | |
1788 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
4ce001ab | 1789 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
771fe6b9 JG |
1790 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
1791 | if (crev >= 3) | |
1792 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; | |
1793 | } | |
1794 | ||
1795 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1796 | ||
1797 | return true; | |
1798 | } else | |
1799 | return false; | |
1800 | } | |
1801 | ||
1802 | static enum drm_connector_status | |
1803 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) | |
1804 | { | |
1805 | struct drm_device *dev = encoder->dev; | |
1806 | struct radeon_device *rdev = dev->dev_private; | |
1807 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
4ce001ab | 1808 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
771fe6b9 JG |
1809 | uint32_t bios_0_scratch; |
1810 | ||
4ce001ab | 1811 | if (!atombios_dac_load_detect(encoder, connector)) { |
d9fdaafb | 1812 | DRM_DEBUG_KMS("detect returned false \n"); |
771fe6b9 JG |
1813 | return connector_status_unknown; |
1814 | } | |
1815 | ||
1816 | if (rdev->family >= CHIP_R600) | |
1817 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
1818 | else | |
1819 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
1820 | ||
d9fdaafb | 1821 | DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
4ce001ab | 1822 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
771fe6b9 JG |
1823 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
1824 | return connector_status_connected; | |
4ce001ab DA |
1825 | } |
1826 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
771fe6b9 JG |
1827 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
1828 | return connector_status_connected; | |
4ce001ab DA |
1829 | } |
1830 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { | |
771fe6b9 JG |
1831 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
1832 | return connector_status_connected; | |
4ce001ab DA |
1833 | } |
1834 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
771fe6b9 JG |
1835 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
1836 | return connector_status_connected; /* CTV */ | |
1837 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) | |
1838 | return connector_status_connected; /* STV */ | |
1839 | } | |
1840 | return connector_status_disconnected; | |
1841 | } | |
1842 | ||
1843 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) | |
1844 | { | |
267364ac | 1845 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
fb939dfc | 1846 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
267364ac AD |
1847 | |
1848 | if (radeon_encoder->active_device & | |
1849 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { | |
1850 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
1851 | if (dig) | |
1852 | dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); | |
1853 | } | |
1854 | ||
771fe6b9 JG |
1855 | radeon_atom_output_lock(encoder, true); |
1856 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); | |
267364ac | 1857 | |
fb939dfc AD |
1858 | /* select the clock/data port if it uses a router */ |
1859 | if (connector) { | |
1860 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1861 | if (radeon_connector->router.cd_valid) | |
1862 | radeon_router_select_cd_port(radeon_connector); | |
1863 | } | |
1864 | ||
267364ac AD |
1865 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
1866 | atombios_set_encoder_crtc_source(encoder); | |
771fe6b9 JG |
1867 | } |
1868 | ||
1869 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) | |
1870 | { | |
1871 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); | |
1872 | radeon_atom_output_lock(encoder, false); | |
1873 | } | |
1874 | ||
4ce001ab DA |
1875 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
1876 | { | |
aa961391 AD |
1877 | struct drm_device *dev = encoder->dev; |
1878 | struct radeon_device *rdev = dev->dev_private; | |
4ce001ab | 1879 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
f28cf339 | 1880 | struct radeon_encoder_atom_dig *dig; |
a0ae5864 AD |
1881 | |
1882 | /* check for pre-DCE3 cards with shared encoders; | |
1883 | * can't really use the links individually, so don't disable | |
1884 | * the encoder if it's in use by another connector | |
1885 | */ | |
1886 | if (!ASIC_IS_DCE3(rdev)) { | |
1887 | struct drm_encoder *other_encoder; | |
1888 | struct radeon_encoder *other_radeon_encoder; | |
1889 | ||
1890 | list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { | |
1891 | other_radeon_encoder = to_radeon_encoder(other_encoder); | |
1892 | if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && | |
1893 | drm_helper_encoder_in_use(other_encoder)) | |
1894 | goto disable_done; | |
1895 | } | |
1896 | } | |
1897 | ||
4ce001ab | 1898 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
f28cf339 | 1899 | |
aa961391 AD |
1900 | switch (radeon_encoder->encoder_id) { |
1901 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
1902 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
1903 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
1904 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
1905 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); | |
1906 | break; | |
1907 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
1908 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
1909 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
1910 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
1911 | if (ASIC_IS_DCE4(rdev)) | |
1912 | /* disable the transmitter */ | |
1913 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1914 | else { | |
1915 | /* disable the encoder and transmitter */ | |
1916 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); | |
1917 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); | |
1918 | } | |
1919 | break; | |
1920 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
aa961391 AD |
1921 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
1922 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
99999aaa | 1923 | atombios_dvo_setup(encoder, ATOM_DISABLE); |
aa961391 AD |
1924 | break; |
1925 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
1926 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
1927 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
1928 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
1929 | atombios_dac_setup(encoder, ATOM_DISABLE); | |
8bf3aae6 | 1930 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
aa961391 AD |
1931 | atombios_tv_setup(encoder, ATOM_DISABLE); |
1932 | break; | |
1933 | } | |
1934 | ||
a0ae5864 | 1935 | disable_done: |
f28cf339 | 1936 | if (radeon_encoder_is_digital(encoder)) { |
2cd6218c RM |
1937 | if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
1938 | r600_hdmi_disable(encoder); | |
f28cf339 DA |
1939 | dig = radeon_encoder->enc_priv; |
1940 | dig->dig_encoder = -1; | |
1941 | } | |
4ce001ab DA |
1942 | radeon_encoder->active_device = 0; |
1943 | } | |
1944 | ||
3e4b9982 AD |
1945 | /* these are handled by the primary encoders */ |
1946 | static void radeon_atom_ext_prepare(struct drm_encoder *encoder) | |
1947 | { | |
1948 | ||
1949 | } | |
1950 | ||
1951 | static void radeon_atom_ext_commit(struct drm_encoder *encoder) | |
1952 | { | |
1953 | ||
1954 | } | |
1955 | ||
1956 | static void | |
1957 | radeon_atom_ext_mode_set(struct drm_encoder *encoder, | |
1958 | struct drm_display_mode *mode, | |
1959 | struct drm_display_mode *adjusted_mode) | |
1960 | { | |
1961 | ||
1962 | } | |
1963 | ||
1964 | static void radeon_atom_ext_disable(struct drm_encoder *encoder) | |
1965 | { | |
1966 | ||
1967 | } | |
1968 | ||
1969 | static void | |
1970 | radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) | |
1971 | { | |
1972 | ||
1973 | } | |
1974 | ||
1975 | static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, | |
1976 | struct drm_display_mode *mode, | |
1977 | struct drm_display_mode *adjusted_mode) | |
1978 | { | |
1979 | return true; | |
1980 | } | |
1981 | ||
1982 | static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { | |
1983 | .dpms = radeon_atom_ext_dpms, | |
1984 | .mode_fixup = radeon_atom_ext_mode_fixup, | |
1985 | .prepare = radeon_atom_ext_prepare, | |
1986 | .mode_set = radeon_atom_ext_mode_set, | |
1987 | .commit = radeon_atom_ext_commit, | |
1988 | .disable = radeon_atom_ext_disable, | |
1989 | /* no detect for TMDS/LVDS yet */ | |
1990 | }; | |
1991 | ||
771fe6b9 JG |
1992 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
1993 | .dpms = radeon_atom_encoder_dpms, | |
1994 | .mode_fixup = radeon_atom_mode_fixup, | |
1995 | .prepare = radeon_atom_encoder_prepare, | |
1996 | .mode_set = radeon_atom_encoder_mode_set, | |
1997 | .commit = radeon_atom_encoder_commit, | |
4ce001ab | 1998 | .disable = radeon_atom_encoder_disable, |
771fe6b9 JG |
1999 | /* no detect for TMDS/LVDS yet */ |
2000 | }; | |
2001 | ||
2002 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { | |
2003 | .dpms = radeon_atom_encoder_dpms, | |
2004 | .mode_fixup = radeon_atom_mode_fixup, | |
2005 | .prepare = radeon_atom_encoder_prepare, | |
2006 | .mode_set = radeon_atom_encoder_mode_set, | |
2007 | .commit = radeon_atom_encoder_commit, | |
2008 | .detect = radeon_atom_dac_detect, | |
2009 | }; | |
2010 | ||
2011 | void radeon_enc_destroy(struct drm_encoder *encoder) | |
2012 | { | |
2013 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2014 | kfree(radeon_encoder->enc_priv); | |
2015 | drm_encoder_cleanup(encoder); | |
2016 | kfree(radeon_encoder); | |
2017 | } | |
2018 | ||
2019 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { | |
2020 | .destroy = radeon_enc_destroy, | |
2021 | }; | |
2022 | ||
4ce001ab DA |
2023 | struct radeon_encoder_atom_dac * |
2024 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) | |
2025 | { | |
affd8589 AD |
2026 | struct drm_device *dev = radeon_encoder->base.dev; |
2027 | struct radeon_device *rdev = dev->dev_private; | |
4ce001ab DA |
2028 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
2029 | ||
2030 | if (!dac) | |
2031 | return NULL; | |
2032 | ||
affd8589 | 2033 | dac->tv_std = radeon_atombios_get_tv_info(rdev); |
4ce001ab DA |
2034 | return dac; |
2035 | } | |
2036 | ||
771fe6b9 JG |
2037 | struct radeon_encoder_atom_dig * |
2038 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) | |
2039 | { | |
5137ee94 | 2040 | int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
771fe6b9 JG |
2041 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
2042 | ||
2043 | if (!dig) | |
2044 | return NULL; | |
2045 | ||
2046 | /* coherent mode by default */ | |
2047 | dig->coherent_mode = true; | |
f28cf339 | 2048 | dig->dig_encoder = -1; |
771fe6b9 | 2049 | |
5137ee94 AD |
2050 | if (encoder_enum == 2) |
2051 | dig->linkb = true; | |
2052 | else | |
2053 | dig->linkb = false; | |
2054 | ||
771fe6b9 JG |
2055 | return dig; |
2056 | } | |
2057 | ||
2058 | void | |
36868bda AD |
2059 | radeon_add_atom_encoder(struct drm_device *dev, |
2060 | uint32_t encoder_enum, | |
2061 | uint32_t supported_device, | |
2062 | u16 caps) | |
771fe6b9 | 2063 | { |
dfee5614 | 2064 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
2065 | struct drm_encoder *encoder; |
2066 | struct radeon_encoder *radeon_encoder; | |
2067 | ||
2068 | /* see if we already added it */ | |
2069 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
2070 | radeon_encoder = to_radeon_encoder(encoder); | |
5137ee94 | 2071 | if (radeon_encoder->encoder_enum == encoder_enum) { |
771fe6b9 JG |
2072 | radeon_encoder->devices |= supported_device; |
2073 | return; | |
2074 | } | |
2075 | ||
2076 | } | |
2077 | ||
2078 | /* add a new one */ | |
2079 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); | |
2080 | if (!radeon_encoder) | |
2081 | return; | |
2082 | ||
2083 | encoder = &radeon_encoder->base; | |
bcc1c2a1 AD |
2084 | switch (rdev->num_crtc) { |
2085 | case 1: | |
dfee5614 | 2086 | encoder->possible_crtcs = 0x1; |
bcc1c2a1 AD |
2087 | break; |
2088 | case 2: | |
2089 | default: | |
dfee5614 | 2090 | encoder->possible_crtcs = 0x3; |
bcc1c2a1 AD |
2091 | break; |
2092 | case 6: | |
2093 | encoder->possible_crtcs = 0x3f; | |
2094 | break; | |
2095 | } | |
771fe6b9 JG |
2096 | |
2097 | radeon_encoder->enc_priv = NULL; | |
2098 | ||
5137ee94 AD |
2099 | radeon_encoder->encoder_enum = encoder_enum; |
2100 | radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
771fe6b9 | 2101 | radeon_encoder->devices = supported_device; |
c93bb85b | 2102 | radeon_encoder->rmx_type = RMX_OFF; |
5b1714d3 | 2103 | radeon_encoder->underscan_type = UNDERSCAN_OFF; |
3e4b9982 | 2104 | radeon_encoder->is_ext_encoder = false; |
36868bda | 2105 | radeon_encoder->caps = caps; |
771fe6b9 JG |
2106 | |
2107 | switch (radeon_encoder->encoder_id) { | |
2108 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: | |
2109 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: | |
2110 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
2111 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
2112 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
2113 | radeon_encoder->rmx_type = RMX_FULL; | |
2114 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
2115 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
2116 | } else { | |
2117 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
2118 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
430f70d5 AD |
2119 | if (ASIC_IS_AVIVO(rdev)) |
2120 | radeon_encoder->underscan_type = UNDERSCAN_AUTO; | |
771fe6b9 JG |
2121 | } |
2122 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); | |
2123 | break; | |
2124 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: | |
2125 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); | |
affd8589 | 2126 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
771fe6b9 JG |
2127 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2128 | break; | |
2129 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: | |
2130 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: | |
2131 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: | |
2132 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); | |
4ce001ab | 2133 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
771fe6b9 JG |
2134 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
2135 | break; | |
2136 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: | |
2137 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
2138 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
2139 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: | |
2140 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: | |
2141 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: | |
2142 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: | |
60d15f55 AD |
2143 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
2144 | radeon_encoder->rmx_type = RMX_FULL; | |
2145 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
2146 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); | |
3e4b9982 AD |
2147 | } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
2148 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); | |
2149 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
60d15f55 AD |
2150 | } else { |
2151 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
2152 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); | |
430f70d5 AD |
2153 | if (ASIC_IS_AVIVO(rdev)) |
2154 | radeon_encoder->underscan_type = UNDERSCAN_AUTO; | |
60d15f55 | 2155 | } |
771fe6b9 JG |
2156 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
2157 | break; | |
3e4b9982 AD |
2158 | case ENCODER_OBJECT_ID_SI170B: |
2159 | case ENCODER_OBJECT_ID_CH7303: | |
2160 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: | |
2161 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: | |
2162 | case ENCODER_OBJECT_ID_TITFP513: | |
2163 | case ENCODER_OBJECT_ID_VT1623: | |
2164 | case ENCODER_OBJECT_ID_HDMI_SI1930: | |
bf982ebf AD |
2165 | case ENCODER_OBJECT_ID_TRAVIS: |
2166 | case ENCODER_OBJECT_ID_NUTMEG: | |
3e4b9982 AD |
2167 | /* these are handled by the primary encoders */ |
2168 | radeon_encoder->is_ext_encoder = true; | |
2169 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
2170 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); | |
2171 | else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) | |
2172 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); | |
2173 | else | |
2174 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); | |
2175 | drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); | |
2176 | break; | |
771fe6b9 JG |
2177 | } |
2178 | } |