[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_cs.c

/*
 * Copyright 2008 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon_reg.h"
#include "radeon.h"

void r100_cs_dump_packet(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt);

int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
{
	struct drm_device *ddev = p->rdev->ddev;
	struct radeon_cs_chunk *chunk;
	unsigned i, j;
	bool duplicate;

	if (p->chunk_relocs_idx == -1) {
		return 0;
	}
	chunk = &p->chunks[p->chunk_relocs_idx];
	/* FIXME: we assume that each relocs use 4 dwords */
	p->nrelocs = chunk->length_dw / 4;
	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	if (p->relocs_ptr == NULL) {
		return -ENOMEM;
	}
	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	if (p->relocs == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nrelocs; i++) {
		struct drm_radeon_cs_reloc *r;

		duplicate = false;
		r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
		for (j = 0; j < i; j++) {
			if (r->handle == p->relocs[j].handle) {
				p->relocs_ptr[i] = &p->relocs[j];
				duplicate = true;
				break;
			}
		}
		if (!duplicate) {
			p->relocs[i].gobj = drm_gem_object_lookup(ddev,
								  p->filp,
								  r->handle);
			if (p->relocs[i].gobj == NULL) {
				DRM_ERROR("gem object lookup failed 0x%x\n",
					  r->handle);
				return -ENOENT;
			}
			p->relocs_ptr[i] = &p->relocs[i];
			p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
			p->relocs[i].lobj.bo = p->relocs[i].robj;
			p->relocs[i].lobj.wdomain = r->write_domain;
			p->relocs[i].lobj.rdomain = r->read_domains;
			p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
			p->relocs[i].handle = r->handle;
			p->relocs[i].flags = r->flags;
			radeon_bo_list_add_object(&p->relocs[i].lobj,
						  &p->validated);

		} else
			p->relocs[i].handle = 0;
	}
	return radeon_bo_list_validate(&p->validated);
}

static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
{
	p->priority = priority;

	switch (ring) {
	default:
		DRM_ERROR("unknown ring id: %d\n", ring);
		return -EINVAL;
	case RADEON_CS_RING_GFX:
		p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	case RADEON_CS_RING_COMPUTE:
		if (p->rdev->family >= CHIP_TAHITI) {
			if (p->priority > 0)
				p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
			else
				p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
		} else
			p->ring = RADEON_RING_TYPE_GFX_INDEX;
		break;
	}
	return 0;
}

static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
{
	bool sync_to_ring[RADEON_NUM_RINGS] = { };
	int i, r;

	for (i = 0; i < p->nrelocs; i++) {
		if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
			continue;

		if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
			struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
			if (!radeon_fence_signaled(fence)) {
				sync_to_ring[fence->ring] = true;
			}
		}
	}

	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
		/* no need to sync to our own or unused rings */
		if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready)
			continue;

		if (!p->ib->fence->semaphore) {
			r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
			if (r)
				return r;
		}

		r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
		if (r)
			return r;
		radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
		radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);

		r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
		if (r)
			return r;
		radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
		radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
	}
	return 0;
}

int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
{
	struct drm_radeon_cs *cs = data;
	uint64_t *chunk_array_ptr;
	unsigned size, i;
	u32 ring = RADEON_CS_RING_GFX;
	s32 priority = 0;

	if (!cs->num_chunks) {
		return 0;
	}
	/* get chunks */
	INIT_LIST_HEAD(&p->validated);
	p->idx = 0;
	p->chunk_ib_idx = -1;
	p->chunk_relocs_idx = -1;
	p->chunk_flags_idx = -1;
	p->chunk_const_ib_idx = -1;
	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	if (p->chunks_array == NULL) {
		return -ENOMEM;
	}
	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
			       sizeof(uint64_t)*cs->num_chunks)) {
		return -EFAULT;
	}
	p->cs_flags = 0;
	p->nchunks = cs->num_chunks;
	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	if (p->chunks == NULL) {
		return -ENOMEM;
	}
	for (i = 0; i < p->nchunks; i++) {
		struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
		struct drm_radeon_cs_chunk user_chunk;
		uint32_t __user *cdata;

		chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
		if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
				       sizeof(struct drm_radeon_cs_chunk))) {
			return -EFAULT;
		}
		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].kdata = NULL;
		p->chunks[i].chunk_id = user_chunk.chunk_id;

		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
			p->chunk_relocs_idx = i;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
			p->chunk_ib_idx = i;
			/* zero length IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
			p->chunk_const_ib_idx = i;
			/* zero length CONST IB isn't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}
		if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
			p->chunk_flags_idx = i;
			/* zero length flags aren't useful */
			if (p->chunks[i].length_dw == 0)
				return -EINVAL;
		}

		p->chunks[i].length_dw = user_chunk.length_dw;
		p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;

		cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
		if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
		    (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
			size = p->chunks[i].length_dw * sizeof(uint32_t);
			p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
			if (p->chunks[i].kdata == NULL) {
				return -ENOMEM;
			}
			if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
					       p->chunks[i].user_ptr, size)) {
				return -EFAULT;
			}
			if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
				p->cs_flags = p->chunks[i].kdata[0];
				if (p->chunks[i].length_dw > 1)
					ring = p->chunks[i].kdata[1];
				if (p->chunks[i].length_dw > 2)
					priority = (s32)p->chunks[i].kdata[2];
			}
		}
	}

	if ((p->cs_flags & RADEON_CS_USE_VM) &&
	    !p->rdev->vm_manager.enabled) {
		DRM_ERROR("VM not active on asic!\n");
		return -EINVAL;
	}

	/* we only support VM on SI+ */
	if ((p->rdev->family >= CHIP_TAHITI) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
		DRM_ERROR("VM required on SI+!\n");
		return -EINVAL;
	}

	if (radeon_cs_get_ring(p, ring, priority))
		return -EINVAL;


	/* deal with non-vm */
	if ((p->chunk_ib_idx != -1) &&
	    ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	    (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
		if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
			DRM_ERROR("cs IB too big: %d\n",
				  p->chunks[p->chunk_ib_idx].length_dw);
			return -EINVAL;
		}
		if ((p->rdev->flags & RADEON_IS_AGP)) {
			p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
			p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
			if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
			    p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
				kfree(p->chunks[i].kpage[0]);
				kfree(p->chunks[i].kpage[1]);
				return -ENOMEM;
			}
		}
		p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
		p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
		p->chunks[p->chunk_ib_idx].last_copied_page = -1;
		p->chunks[p->chunk_ib_idx].last_page_index =
			((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	}

	return 0;
}

/**
 * cs_parser_fini() - clean parser states
 * @parser:	parser structure holding parsing context.
 * @error:	error number
 *
 * If error is set than unvalidate buffer, otherwise just free memory
 * used by parsing context.
 **/
static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
{
	unsigned i;


	if (!error && parser->ib)
		ttm_eu_fence_buffer_objects(&parser->validated,
					    parser->ib->fence);
	else
		ttm_eu_backoff_reservation(&parser->validated);

	if (parser->relocs != NULL) {
		for (i = 0; i < parser->nrelocs; i++) {
			if (parser->relocs[i].gobj)
				drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
		}
	}
	kfree(parser->track);
	kfree(parser->relocs);
	kfree(parser->relocs_ptr);
	for (i = 0; i < parser->nchunks; i++) {
		kfree(parser->chunks[i].kdata);
		if ((parser->rdev->flags & RADEON_IS_AGP)) {
			kfree(parser->chunks[i].kpage[0]);
			kfree(parser->chunks[i].kpage[1]);
		}
	}
	kfree(parser->chunks);
	kfree(parser->chunks_array);
	radeon_ib_free(parser->rdev, &parser->ib);
}

static int radeon_cs_ib_chunk(struct radeon_device *rdev,
			      struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if (parser->cs_flags & RADEON_CS_USE_VM)
		return 0;

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	/* Copy the packet into the IB, the parser will read from the
	 * input memory (cached) and write to the IB (which can be
	 * uncached).
	 */
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib->length_dw = ib_chunk->length_dw;
	r = radeon_cs_parse(rdev, parser->ring, parser);
	if (r || parser->parser_error) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_finish_pages(parser);
	if (r) {
		DRM_ERROR("Invalid command stream !\n");
		return r;
	}
	r = radeon_cs_sync_rings(parser);
	if (r) {
		DRM_ERROR("Failed to synchronize rings !\n");
	}
	parser->ib->vm_id = 0;
	r = radeon_ib_schedule(rdev, parser->ib);
	if (r) {
		DRM_ERROR("Failed to schedule IB !\n");
	}
	return 0;
}

static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
				   struct radeon_vm *vm)
{
	struct radeon_bo_list *lobj;
	struct radeon_bo *bo;
	int r;

	list_for_each_entry(lobj, &parser->validated, tv.head) {
		bo = lobj->bo;
		r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
		if (r) {
			return r;
		}
	}
	return 0;
}

static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
				 struct radeon_cs_parser *parser)
{
	struct radeon_cs_chunk *ib_chunk;
	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	struct radeon_vm *vm = &fpriv->vm;
	int r;

	if (parser->chunk_ib_idx == -1)
		return 0;

	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
		return 0;

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
		if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
			DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
			return -EINVAL;
		}
		r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
				   ib_chunk->length_dw * 4);
		if (r) {
			DRM_ERROR("Failed to get const ib !\n");
			return r;
		}
		parser->const_ib->is_const_ib = true;
		parser->const_ib->length_dw = ib_chunk->length_dw;
		/* Copy the packet into the IB */
		if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
				       ib_chunk->length_dw * 4)) {
			return -EFAULT;
		}
		r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
		if (r) {
			return r;
		}
	}

	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
		DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
		return -EINVAL;
	}
	r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
			   ib_chunk->length_dw * 4);
	if (r) {
		DRM_ERROR("Failed to get ib !\n");
		return r;
	}
	parser->ib->length_dw = ib_chunk->length_dw;
	/* Copy the packet into the IB */
	if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
			       ib_chunk->length_dw * 4)) {
		return -EFAULT;
	}
	r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
	if (r) {
		return r;
	}

	mutex_lock(&vm->mutex);
	r = radeon_vm_bind(rdev, vm);
	if (r) {
		goto out;
	}
	r = radeon_bo_vm_update_pte(parser, vm);
	if (r) {
		goto out;
	}
	r = radeon_cs_sync_rings(parser);
	if (r) {
		DRM_ERROR("Failed to synchronize rings !\n");
	}

	if ((rdev->family >= CHIP_TAHITI) &&
	    (parser->chunk_const_ib_idx != -1)) {
		parser->const_ib->vm_id = vm->id;
		/* ib pool is bind at 0 in virtual address space to gpu_addr is the
		 * offset inside the pool bo
		 */
		parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
		r = radeon_ib_schedule(rdev, parser->const_ib);
		if (r)
			goto out;
	}

	parser->ib->vm_id = vm->id;
	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	 * offset inside the pool bo
	 */
	parser->ib->gpu_addr = parser->ib->sa_bo.offset;
	parser->ib->is_const_ib = false;
	r = radeon_ib_schedule(rdev, parser->ib);
out:
	if (!r) {
		if (vm->fence) {
			radeon_fence_unref(&vm->fence);
		}
		vm->fence = radeon_fence_ref(parser->ib->fence);
	}
	mutex_unlock(&fpriv->vm.mutex);
	return r;
}

int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
{
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_cs_parser parser;
	int r;

	radeon_mutex_lock(&rdev->cs_mutex);
	if (!rdev->accel_working) {
		radeon_mutex_unlock(&rdev->cs_mutex);
		return -EBUSY;
	}
	/* initialize parser */
	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	parser.filp = filp;
	parser.rdev = rdev;
	parser.dev = rdev->dev;
	parser.family = rdev->family;
	r = radeon_cs_parser_init(&parser, data);
	if (r) {
		DRM_ERROR("Failed to initialize parser !\n");
		radeon_cs_parser_fini(&parser, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_parser_relocs(&parser);
	if (r) {
		if (r != -ERESTARTSYS)
			DRM_ERROR("Failed to parse relocation %d!\n", r);
		radeon_cs_parser_fini(&parser, r);
		radeon_mutex_unlock(&rdev->cs_mutex);
		return r;
	}
	r = radeon_cs_ib_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
	r = radeon_cs_ib_vm_chunk(rdev, &parser);
	if (r) {
		goto out;
	}
out:
	radeon_cs_parser_fini(&parser, r);
	radeon_mutex_unlock(&rdev->cs_mutex);
	return r;
}

int radeon_cs_finish_pages(struct radeon_cs_parser *p)
{
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;

	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
		if (i == ibc->last_page_index) {
			size = (ibc->length_dw * 4) % PAGE_SIZE;
			if (size == 0)
				size = PAGE_SIZE;
		}
		
		if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       size))
			return -EFAULT;
	}
	return 0;
}

int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
{
	int new_page;
	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	int i;
	int size = PAGE_SIZE;
	bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;

	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
		if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
				       ibc->user_ptr + (i * PAGE_SIZE),
				       PAGE_SIZE)) {
			p->parser_error = -EFAULT;
			return 0;
		}
	}

	if (pg_idx == ibc->last_page_index) {
		size = (ibc->length_dw * 4) % PAGE_SIZE;
		if (size == 0)
			size = PAGE_SIZE;
	}

	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
	if (copy1)
		ibc->kpage[new_page] = p->ib->ptr + (pg_idx * (PAGE_SIZE / 4));

	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
			       ibc->user_ptr + (pg_idx * PAGE_SIZE),
			       size)) {
		p->parser_error = -EFAULT;
		return 0;
	}

	/* copy to IB for non single case */
	if (!copy1)
		memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);

	ibc->last_copied_page = pg_idx;
	ibc->kpage_idx[new_page] = pg_idx;

	return new_page;
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Jerome Glisse <glisse@freedesktop.org>
	26	*/
	27	#include "drmP.h"
	28	#include "radeon_drm.h"
	29	#include "radeon_reg.h"
	30	#include "radeon.h"
	31
	32	void r100_cs_dump_packet(struct radeon_cs_parser *p,
	33	struct radeon_cs_packet *pkt);
	34
	35	int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
	36	{
	37	struct drm_device *ddev = p->rdev->ddev;
	38	struct radeon_cs_chunk *chunk;
	39	unsigned i, j;
	40	bool duplicate;
	41
	42	if (p->chunk_relocs_idx == -1) {
	43	return 0;
	44	}
	45	chunk = &p->chunks[p->chunk_relocs_idx];
	46	/* FIXME: we assume that each relocs use 4 dwords */
	47	p->nrelocs = chunk->length_dw / 4;
	48	p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
	49	if (p->relocs_ptr == NULL) {
	50	return -ENOMEM;
	51	}
	52	p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
	53	if (p->relocs == NULL) {
	54	return -ENOMEM;
	55	}
	56	for (i = 0; i < p->nrelocs; i++) {
	57	struct drm_radeon_cs_reloc *r;
	58
	59	duplicate = false;
	60	r = (struct drm_radeon_cs_reloc )&chunk->kdata[i4];
16557f1e	61	for (j = 0; j < i; j++) {
771fe6b9 JG	62	if (r->handle == p->relocs[j].handle) {
	63	p->relocs_ptr[i] = &p->relocs[j];
	64	duplicate = true;
	65	break;
	66	}
	67	}
	68	if (!duplicate) {
	69	p->relocs[i].gobj = drm_gem_object_lookup(ddev,
	70	p->filp,
	71	r->handle);
	72	if (p->relocs[i].gobj == NULL) {
	73	DRM_ERROR("gem object lookup failed 0x%x\n",
	74	r->handle);
bf79cb91	75	return -ENOENT;
771fe6b9 JG	76	}
771fe6b9 JG	77	p->relocs_ptr[i] = &p->relocs[i];
7e4d15d9	78	p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
4c788679	79	p->relocs[i].lobj.bo = p->relocs[i].robj;
771fe6b9	80	p->relocs[i].lobj.wdomain = r->write_domain;
147666fb TH	81	p->relocs[i].lobj.rdomain = r->read_domains;
147666fb TH	82	p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
771fe6b9 JG	83	p->relocs[i].handle = r->handle;
771fe6b9 JG	84	p->relocs[i].flags = r->flags;
4c788679	85	radeon_bo_list_add_object(&p->relocs[i].lobj,
147666fb	86	&p->validated);
93504fce	87
16557f1e CK	88	} else
16557f1e CK	89	p->relocs[i].handle = 0;
771fe6b9	90	}
94429bb6	91	return radeon_bo_list_validate(&p->validated);
771fe6b9 JG	92	}
771fe6b9 JG	93
721604a1 JG	94	static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
	95	{
	96	p->priority = priority;
	97
	98	switch (ring) {
	99	default:
	100	DRM_ERROR("unknown ring id: %d\n", ring);
	101	return -EINVAL;
	102	case RADEON_CS_RING_GFX:
	103	p->ring = RADEON_RING_TYPE_GFX_INDEX;
	104	break;
	105	case RADEON_CS_RING_COMPUTE:
8d5ef7b1 AD	106	if (p->rdev->family >= CHIP_TAHITI) {
	107	if (p->priority > 0)
	108	p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
	109	else
	110	p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
	111	} else
	112	p->ring = RADEON_RING_TYPE_GFX_INDEX;
721604a1 JG	113	break;
	114	}
	115	return 0;
	116	}
	117
93504fce CK	118	static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
93504fce CK	119	{
cdac5504	120	bool sync_to_ring[RADEON_NUM_RINGS] = { };
93504fce CK	121	int i, r;
93504fce CK	122
cdac5504 CK	123	for (i = 0; i < p->nrelocs; i++) {
	124	if (!p->relocs[i].robj \|\| !p->relocs[i].robj->tbo.sync_obj)
	125	continue;
	126
	127	if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
	128	struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
	129	if (!radeon_fence_signaled(fence)) {
	130	sync_to_ring[fence->ring] = true;
	131	}
	132	}
	133	}
	134
93504fce CK	135	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
93504fce CK	136	/* no need to sync to our own or unused rings */
cdac5504	137	if (i == p->ring \|\| !sync_to_ring[i] \|\| !p->rdev->ring[i].ready)
93504fce CK	138	continue;
	139
	140	if (!p->ib->fence->semaphore) {
	141	r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
	142	if (r)
	143	return r;
	144	}
	145
	146	r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
	147	if (r)
	148	return r;
	149	radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
	150	radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);
	151
	152	r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
	153	if (r)
	154	return r;
	155	radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
	156	radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
	157	}
	158	return 0;
	159	}
	160
771fe6b9 JG	161	int radeon_cs_parser_init(struct radeon_cs_parser p, void data)
	162	{
	163	struct drm_radeon_cs *cs = data;
	164	uint64_t *chunk_array_ptr;
721604a1 JG	165	unsigned size, i;
	166	u32 ring = RADEON_CS_RING_GFX;
	167	s32 priority = 0;
771fe6b9 JG	168
	169	if (!cs->num_chunks) {
	170	return 0;
	171	}
	172	/* get chunks */
	173	INIT_LIST_HEAD(&p->validated);
	174	p->idx = 0;
	175	p->chunk_ib_idx = -1;
	176	p->chunk_relocs_idx = -1;
721604a1	177	p->chunk_flags_idx = -1;
dfcf5f36	178	p->chunk_const_ib_idx = -1;
771fe6b9 JG	179	p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
	180	if (p->chunks_array == NULL) {
	181	return -ENOMEM;
	182	}
	183	chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
	184	if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
	185	sizeof(uint64_t)*cs->num_chunks)) {
	186	return -EFAULT;
	187	}
721604a1	188	p->cs_flags = 0;
771fe6b9 JG	189	p->nchunks = cs->num_chunks;
	190	p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
	191	if (p->chunks == NULL) {
	192	return -ENOMEM;
	193	}
	194	for (i = 0; i < p->nchunks; i++) {
	195	struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
	196	struct drm_radeon_cs_chunk user_chunk;
	197	uint32_t __user *cdata;
	198
	199	chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
	200	if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
	201	sizeof(struct drm_radeon_cs_chunk))) {
	202	return -EFAULT;
	203	}
5176fdc4 DA	204	p->chunks[i].length_dw = user_chunk.length_dw;
5176fdc4 DA	205	p->chunks[i].kdata = NULL;
771fe6b9	206	p->chunks[i].chunk_id = user_chunk.chunk_id;
5176fdc4	207
771fe6b9 JG	208	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
	209	p->chunk_relocs_idx = i;
	210	}
	211	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
	212	p->chunk_ib_idx = i;
5176fdc4 DA	213	/* zero length IB isn't useful */
	214	if (p->chunks[i].length_dw == 0)
	215	return -EINVAL;
771fe6b9	216	}
dfcf5f36 AD	217	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
	218	p->chunk_const_ib_idx = i;
	219	/* zero length CONST IB isn't useful */
	220	if (p->chunks[i].length_dw == 0)
	221	return -EINVAL;
	222	}
721604a1 JG	223	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
	224	p->chunk_flags_idx = i;
	225	/* zero length flags aren't useful */
	226	if (p->chunks[i].length_dw == 0)
	227	return -EINVAL;
e70f224c	228	}
5176fdc4	229
771fe6b9	230	p->chunks[i].length_dw = user_chunk.length_dw;
513bcb46	231	p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
771fe6b9	232
513bcb46	233	cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
721604a1 JG	234	if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) \|\|
721604a1 JG	235	(p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
513bcb46 DA	236	size = p->chunks[i].length_dw * sizeof(uint32_t);
	237	p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
	238	if (p->chunks[i].kdata == NULL) {
	239	return -ENOMEM;
	240	}
	241	if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
	242	p->chunks[i].user_ptr, size)) {
	243	return -EFAULT;
	244	}
e70f224c	245	if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
721604a1 JG	246	p->cs_flags = p->chunks[i].kdata[0];
	247	if (p->chunks[i].length_dw > 1)
	248	ring = p->chunks[i].kdata[1];
	249	if (p->chunks[i].length_dw > 2)
	250	priority = (s32)p->chunks[i].kdata[2];
e70f224c	251	}
771fe6b9 JG	252	}
771fe6b9 JG	253	}
721604a1 JG	254
721604a1 JG	255	if ((p->cs_flags & RADEON_CS_USE_VM) &&
67e915e4 AD	256	!p->rdev->vm_manager.enabled) {
67e915e4 AD	257	DRM_ERROR("VM not active on asic!\n");
771fe6b9 JG	258	return -EINVAL;
771fe6b9 JG	259	}
e70f224c	260
1b5475db AD	261	/* we only support VM on SI+ */
	262	if ((p->rdev->family >= CHIP_TAHITI) &&
	263	((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
	264	DRM_ERROR("VM required on SI+!\n");
	265	return -EINVAL;
	266	}
	267
f48bb04a	268	if (radeon_cs_get_ring(p, ring, priority))
721604a1	269	return -EINVAL;
721604a1 JG	270
	271
	272	/* deal with non-vm */
	273	if ((p->chunk_ib_idx != -1) &&
	274	((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
	275	(p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
	276	if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
	277	DRM_ERROR("cs IB too big: %d\n",
	278	p->chunks[p->chunk_ib_idx].length_dw);
	279	return -EINVAL;
	280	}
6a7068b4 DA	281	if ((p->rdev->flags & RADEON_IS_AGP)) {
	282	p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	283	p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
	284	if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL \|\|
	285	p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
	286	kfree(p->chunks[i].kpage[0]);
	287	kfree(p->chunks[i].kpage[1]);
	288	return -ENOMEM;
	289	}
	290	}
721604a1 JG	291	p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
	292	p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
	293	p->chunks[p->chunk_ib_idx].last_copied_page = -1;
	294	p->chunks[p->chunk_ib_idx].last_page_index =
	295	((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
	296	}
	297
771fe6b9 JG	298	return 0;
	299	}
	300
	301	/**
	302	* cs_parser_fini() - clean parser states
	303	* @parser: parser structure holding parsing context.
	304	* @error: error number
	305	*
	306	* If error is set than unvalidate buffer, otherwise just free memory
	307	* used by parsing context.
	308	**/
	309	static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
	310	{
	311	unsigned i;
	312
147666fb TH	313
	314	if (!error && parser->ib)
	315	ttm_eu_fence_buffer_objects(&parser->validated,
	316	parser->ib->fence);
	317	else
	318	ttm_eu_backoff_reservation(&parser->validated);
	319
fcbc451b PN	320	if (parser->relocs != NULL) {
	321	for (i = 0; i < parser->nrelocs; i++) {
	322	if (parser->relocs[i].gobj)
	323	drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
	324	}
771fe6b9	325	}
48e113e5	326	kfree(parser->track);
771fe6b9 JG	327	kfree(parser->relocs);
	328	kfree(parser->relocs_ptr);
	329	for (i = 0; i < parser->nchunks; i++) {
	330	kfree(parser->chunks[i].kdata);
6a7068b4 DA	331	if ((parser->rdev->flags & RADEON_IS_AGP)) {
	332	kfree(parser->chunks[i].kpage[0]);
	333	kfree(parser->chunks[i].kpage[1]);
	334	}
771fe6b9 JG	335	}
	336	kfree(parser->chunks);
	337	kfree(parser->chunks_array);
	338	radeon_ib_free(parser->rdev, &parser->ib);
	339	}
	340
721604a1 JG	341	static int radeon_cs_ib_chunk(struct radeon_device *rdev,
	342	struct radeon_cs_parser *parser)
	343	{
	344	struct radeon_cs_chunk *ib_chunk;
	345	int r;
	346
	347	if (parser->chunk_ib_idx == -1)
	348	return 0;
	349
	350	if (parser->cs_flags & RADEON_CS_USE_VM)
	351	return 0;
	352
	353	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	354	/* Copy the packet into the IB, the parser will read from the
	355	* input memory (cached) and write to the IB (which can be
	356	* uncached).
	357	*/
	358	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	359	ib_chunk->length_dw * 4);
	360	if (r) {
	361	DRM_ERROR("Failed to get ib !\n");
	362	return r;
	363	}
	364	parser->ib->length_dw = ib_chunk->length_dw;
eb0c19c5	365	r = radeon_cs_parse(rdev, parser->ring, parser);
721604a1 JG	366	if (r \|\| parser->parser_error) {
	367	DRM_ERROR("Invalid command stream !\n");
	368	return r;
	369	}
	370	r = radeon_cs_finish_pages(parser);
	371	if (r) {
	372	DRM_ERROR("Invalid command stream !\n");
	373	return r;
	374	}
93504fce CK	375	r = radeon_cs_sync_rings(parser);
	376	if (r) {
	377	DRM_ERROR("Failed to synchronize rings !\n");
	378	}
721604a1 JG	379	parser->ib->vm_id = 0;
	380	r = radeon_ib_schedule(rdev, parser->ib);
	381	if (r) {
	382	DRM_ERROR("Failed to schedule IB !\n");
	383	}
	384	return 0;
	385	}
	386
	387	static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
	388	struct radeon_vm *vm)
	389	{
	390	struct radeon_bo_list *lobj;
	391	struct radeon_bo *bo;
	392	int r;
	393
	394	list_for_each_entry(lobj, &parser->validated, tv.head) {
	395	bo = lobj->bo;
	396	r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
	397	if (r) {
	398	return r;
	399	}
	400	}
	401	return 0;
	402	}
	403
	404	static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
	405	struct radeon_cs_parser *parser)
	406	{
	407	struct radeon_cs_chunk *ib_chunk;
	408	struct radeon_fpriv *fpriv = parser->filp->driver_priv;
	409	struct radeon_vm *vm = &fpriv->vm;
	410	int r;
	411
	412	if (parser->chunk_ib_idx == -1)
	413	return 0;
	414
	415	if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
	416	return 0;
	417
dfcf5f36 AD	418	if ((rdev->family >= CHIP_TAHITI) &&
	419	(parser->chunk_const_ib_idx != -1)) {
	420	ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
	421	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	422	DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
	423	return -EINVAL;
	424	}
	425	r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
	426	ib_chunk->length_dw * 4);
	427	if (r) {
	428	DRM_ERROR("Failed to get const ib !\n");
	429	return r;
	430	}
	431	parser->const_ib->is_const_ib = true;
	432	parser->const_ib->length_dw = ib_chunk->length_dw;
	433	/* Copy the packet into the IB */
	434	if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
	435	ib_chunk->length_dw * 4)) {
	436	return -EFAULT;
	437	}
	438	r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
	439	if (r) {
	440	return r;
	441	}
	442	}
	443
721604a1 JG	444	ib_chunk = &parser->chunks[parser->chunk_ib_idx];
	445	if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
	446	DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
	447	return -EINVAL;
	448	}
	449	r = radeon_ib_get(rdev, parser->ring, &parser->ib,
	450	ib_chunk->length_dw * 4);
	451	if (r) {
	452	DRM_ERROR("Failed to get ib !\n");
	453	return r;
	454	}
	455	parser->ib->length_dw = ib_chunk->length_dw;
	456	/* Copy the packet into the IB */
	457	if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
	458	ib_chunk->length_dw * 4)) {
	459	return -EFAULT;
	460	}
	461	r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
	462	if (r) {
	463	return r;
	464	}
	465
	466	mutex_lock(&vm->mutex);
	467	r = radeon_vm_bind(rdev, vm);
	468	if (r) {
	469	goto out;
	470	}
	471	r = radeon_bo_vm_update_pte(parser, vm);
	472	if (r) {
	473	goto out;
	474	}
93504fce CK	475	r = radeon_cs_sync_rings(parser);
	476	if (r) {
	477	DRM_ERROR("Failed to synchronize rings !\n");
	478	}
dfcf5f36 AD	479
	480	if ((rdev->family >= CHIP_TAHITI) &&
	481	(parser->chunk_const_ib_idx != -1)) {
	482	parser->const_ib->vm_id = vm->id;
	483	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	484	* offset inside the pool bo
	485	*/
	486	parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
	487	r = radeon_ib_schedule(rdev, parser->const_ib);
	488	if (r)
	489	goto out;
	490	}
	491
721604a1 JG	492	parser->ib->vm_id = vm->id;
	493	/* ib pool is bind at 0 in virtual address space to gpu_addr is the
	494	* offset inside the pool bo
	495	*/
	496	parser->ib->gpu_addr = parser->ib->sa_bo.offset;
dfcf5f36	497	parser->ib->is_const_ib = false;
721604a1 JG	498	r = radeon_ib_schedule(rdev, parser->ib);
	499	out:
	500	if (!r) {
	501	if (vm->fence) {
	502	radeon_fence_unref(&vm->fence);
	503	}
	504	vm->fence = radeon_fence_ref(parser->ib->fence);
	505	}
	506	mutex_unlock(&fpriv->vm.mutex);
	507	return r;
	508	}
	509
771fe6b9 JG	510	int radeon_cs_ioctl(struct drm_device dev, void data, struct drm_file *filp)
	511	{
	512	struct radeon_device *rdev = dev->dev_private;
	513	struct radeon_cs_parser parser;
771fe6b9 JG	514	int r;
771fe6b9 JG	515
7a1619b9	516	radeon_mutex_lock(&rdev->cs_mutex);
6b7746e8 JG	517	if (!rdev->accel_working) {
	518	radeon_mutex_unlock(&rdev->cs_mutex);
	519	return -EBUSY;
	520	}
771fe6b9 JG	521	/* initialize parser */
	522	memset(&parser, 0, sizeof(struct radeon_cs_parser));
	523	parser.filp = filp;
	524	parser.rdev = rdev;
c8c15ff1	525	parser.dev = rdev->dev;
428c6e36	526	parser.family = rdev->family;
771fe6b9 JG	527	r = radeon_cs_parser_init(&parser, data);
	528	if (r) {
	529	DRM_ERROR("Failed to initialize parser !\n");
	530	radeon_cs_parser_fini(&parser, r);
7a1619b9	531	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	532	return r;
771fe6b9 JG	533	}
771fe6b9 JG	534	r = radeon_cs_parser_relocs(&parser);
771fe6b9 JG	535	if (r) {
97f23b3d DA	536	if (r != -ERESTARTSYS)
97f23b3d DA	537	DRM_ERROR("Failed to parse relocation %d!\n", r);
771fe6b9	538	radeon_cs_parser_fini(&parser, r);
7a1619b9	539	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	540	return r;
771fe6b9 JG	541	}
721604a1	542	r = radeon_cs_ib_chunk(rdev, &parser);
771fe6b9	543	if (r) {
721604a1	544	goto out;
771fe6b9	545	}
721604a1	546	r = radeon_cs_ib_vm_chunk(rdev, &parser);
771fe6b9	547	if (r) {
721604a1	548	goto out;
771fe6b9	549	}
721604a1	550	out:
771fe6b9	551	radeon_cs_parser_fini(&parser, r);
7a1619b9	552	radeon_mutex_unlock(&rdev->cs_mutex);
771fe6b9 JG	553	return r;
771fe6b9 JG	554	}
513bcb46 DA	555
	556	int radeon_cs_finish_pages(struct radeon_cs_parser *p)
	557	{
	558	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	559	int i;
	560	int size = PAGE_SIZE;
	561
	562	for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
	563	if (i == ibc->last_page_index) {
	564	size = (ibc->length_dw * 4) % PAGE_SIZE;
	565	if (size == 0)
	566	size = PAGE_SIZE;
	567	}
	568
	569	if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
	570	ibc->user_ptr + (i * PAGE_SIZE),
	571	size))
	572	return -EFAULT;
	573	}
	574	return 0;
	575	}
	576
	577	int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
	578	{
	579	int new_page;
513bcb46 DA	580	struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
	581	int i;
	582	int size = PAGE_SIZE;
6a7068b4	583	bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
513bcb46	584
c5e617e2	585	for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
513bcb46 DA	586	if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
	587	ibc->user_ptr + (i * PAGE_SIZE),
	588	PAGE_SIZE)) {
	589	p->parser_error = -EFAULT;
	590	return 0;
	591	}
	592	}
	593
513bcb46 DA	594	if (pg_idx == ibc->last_page_index) {
513bcb46 DA	595	size = (ibc->length_dw * 4) % PAGE_SIZE;
6a7068b4 DA	596	if (size == 0)
6a7068b4 DA	597	size = PAGE_SIZE;
513bcb46 DA	598	}
513bcb46 DA	599
6a7068b4 DA	600	new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
	601	if (copy1)
	602	ibc->kpage[new_page] = p->ib->ptr + (pg_idx * (PAGE_SIZE / 4));
	603
513bcb46 DA	604	if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
	605	ibc->user_ptr + (pg_idx * PAGE_SIZE),
	606	size)) {
	607	p->parser_error = -EFAULT;
	608	return 0;
	609	}
	610
6a7068b4 DA	611	/* copy to IB for non single case */
	612	if (!copy1)
	613	memcpy((void )(p->ib->ptr+(pg_idx(PAGE_SIZE/4))), ibc->kpage[new_page], size);
513bcb46 DA	614
	615	ibc->last_copied_page = pg_idx;
	616	ibc->kpage_idx[new_page] = pg_idx;
	617
	618	return new_page;
	619	}