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drm/radeon/kms: DP fixes and cleanup from the ddx
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06
AD		 52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id);
771fe6b9
JG		 54
55/* from radeon_legacy_encoder.c */
56extern void
57radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
58 uint32_t supported_device);
59
60/* old legacy ATI BIOS routines */
61
62/* COMBIOS table offsets */
63enum radeon_combios_table_offset {
64 /* absolute offset tables */
65 COMBIOS_ASIC_INIT_1_TABLE,
66 COMBIOS_BIOS_SUPPORT_TABLE,
67 COMBIOS_DAC_PROGRAMMING_TABLE,
68 COMBIOS_MAX_COLOR_DEPTH_TABLE,
69 COMBIOS_CRTC_INFO_TABLE,
70 COMBIOS_PLL_INFO_TABLE,
71 COMBIOS_TV_INFO_TABLE,
72 COMBIOS_DFP_INFO_TABLE,
73 COMBIOS_HW_CONFIG_INFO_TABLE,
74 COMBIOS_MULTIMEDIA_INFO_TABLE,
75 COMBIOS_TV_STD_PATCH_TABLE,
76 COMBIOS_LCD_INFO_TABLE,
77 COMBIOS_MOBILE_INFO_TABLE,
78 COMBIOS_PLL_INIT_TABLE,
79 COMBIOS_MEM_CONFIG_TABLE,
80 COMBIOS_SAVE_MASK_TABLE,
81 COMBIOS_HARDCODED_EDID_TABLE,
82 COMBIOS_ASIC_INIT_2_TABLE,
83 COMBIOS_CONNECTOR_INFO_TABLE,
84 COMBIOS_DYN_CLK_1_TABLE,
85 COMBIOS_RESERVED_MEM_TABLE,
86 COMBIOS_EXT_TMDS_INFO_TABLE,
87 COMBIOS_MEM_CLK_INFO_TABLE,
88 COMBIOS_EXT_DAC_INFO_TABLE,
89 COMBIOS_MISC_INFO_TABLE,
90 COMBIOS_CRT_INFO_TABLE,
91 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
92 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
93 COMBIOS_FAN_SPEED_INFO_TABLE,
94 COMBIOS_OVERDRIVE_INFO_TABLE,
95 COMBIOS_OEM_INFO_TABLE,
96 COMBIOS_DYN_CLK_2_TABLE,
97 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
98 COMBIOS_I2C_INFO_TABLE,
99 /* relative offset tables */
100 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
101 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
102 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
103 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
104 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
105 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
106 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
110 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
111};
112
113enum radeon_combios_ddc {
114 DDC_NONE_DETECTED,
115 DDC_MONID,
116 DDC_DVI,
117 DDC_VGA,
118 DDC_CRT2,
119 DDC_LCD,
120 DDC_GPIO,
121};
122
123enum radeon_combios_connector {
124 CONNECTOR_NONE_LEGACY,
125 CONNECTOR_PROPRIETARY_LEGACY,
126 CONNECTOR_CRT_LEGACY,
127 CONNECTOR_DVI_I_LEGACY,
128 CONNECTOR_DVI_D_LEGACY,
129 CONNECTOR_CTV_LEGACY,
130 CONNECTOR_STV_LEGACY,
131 CONNECTOR_UNSUPPORTED_LEGACY
132};
133
134const int legacy_connector_convert[] = {
135 DRM_MODE_CONNECTOR_Unknown,
136 DRM_MODE_CONNECTOR_DVID,
137 DRM_MODE_CONNECTOR_VGA,
138 DRM_MODE_CONNECTOR_DVII,
139 DRM_MODE_CONNECTOR_DVID,
140 DRM_MODE_CONNECTOR_Composite,
141 DRM_MODE_CONNECTOR_SVIDEO,
142 DRM_MODE_CONNECTOR_Unknown,
143};
144
145static uint16_t combios_get_table_offset(struct drm_device *dev,
146 enum radeon_combios_table_offset table)
147{
148 struct radeon_device *rdev = dev->dev_private;
149 int rev;
150 uint16_t offset = 0, check_offset;
151
152 switch (table) {
153 /* absolute offset tables */
154 case COMBIOS_ASIC_INIT_1_TABLE:
155 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
156 if (check_offset)
157 offset = check_offset;
158 break;
159 case COMBIOS_BIOS_SUPPORT_TABLE:
160 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
161 if (check_offset)
162 offset = check_offset;
163 break;
164 case COMBIOS_DAC_PROGRAMMING_TABLE:
165 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
166 if (check_offset)
167 offset = check_offset;
168 break;
169 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
170 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
171 if (check_offset)
172 offset = check_offset;
173 break;
174 case COMBIOS_CRTC_INFO_TABLE:
175 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
176 if (check_offset)
177 offset = check_offset;
178 break;
179 case COMBIOS_PLL_INFO_TABLE:
180 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
181 if (check_offset)
182 offset = check_offset;
183 break;
184 case COMBIOS_TV_INFO_TABLE:
185 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
186 if (check_offset)
187 offset = check_offset;
188 break;
189 case COMBIOS_DFP_INFO_TABLE:
190 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
191 if (check_offset)
192 offset = check_offset;
193 break;
194 case COMBIOS_HW_CONFIG_INFO_TABLE:
195 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
196 if (check_offset)
197 offset = check_offset;
198 break;
199 case COMBIOS_MULTIMEDIA_INFO_TABLE:
200 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
201 if (check_offset)
202 offset = check_offset;
203 break;
204 case COMBIOS_TV_STD_PATCH_TABLE:
205 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
206 if (check_offset)
207 offset = check_offset;
208 break;
209 case COMBIOS_LCD_INFO_TABLE:
210 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
211 if (check_offset)
212 offset = check_offset;
213 break;
214 case COMBIOS_MOBILE_INFO_TABLE:
215 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
216 if (check_offset)
217 offset = check_offset;
218 break;
219 case COMBIOS_PLL_INIT_TABLE:
220 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
221 if (check_offset)
222 offset = check_offset;
223 break;
224 case COMBIOS_MEM_CONFIG_TABLE:
225 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
226 if (check_offset)
227 offset = check_offset;
228 break;
229 case COMBIOS_SAVE_MASK_TABLE:
230 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
231 if (check_offset)
232 offset = check_offset;
233 break;
234 case COMBIOS_HARDCODED_EDID_TABLE:
235 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
236 if (check_offset)
237 offset = check_offset;
238 break;
239 case COMBIOS_ASIC_INIT_2_TABLE:
240 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
241 if (check_offset)
242 offset = check_offset;
243 break;
244 case COMBIOS_CONNECTOR_INFO_TABLE:
245 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
246 if (check_offset)
247 offset = check_offset;
248 break;
249 case COMBIOS_DYN_CLK_1_TABLE:
250 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
251 if (check_offset)
252 offset = check_offset;
253 break;
254 case COMBIOS_RESERVED_MEM_TABLE:
255 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
256 if (check_offset)
257 offset = check_offset;
258 break;
259 case COMBIOS_EXT_TMDS_INFO_TABLE:
260 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
261 if (check_offset)
262 offset = check_offset;
263 break;
264 case COMBIOS_MEM_CLK_INFO_TABLE:
265 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
266 if (check_offset)
267 offset = check_offset;
268 break;
269 case COMBIOS_EXT_DAC_INFO_TABLE:
270 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
271 if (check_offset)
272 offset = check_offset;
273 break;
274 case COMBIOS_MISC_INFO_TABLE:
275 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
276 if (check_offset)
277 offset = check_offset;
278 break;
279 case COMBIOS_CRT_INFO_TABLE:
280 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
281 if (check_offset)
282 offset = check_offset;
283 break;
284 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
285 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
286 if (check_offset)
287 offset = check_offset;
288 break;
289 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
290 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
291 if (check_offset)
292 offset = check_offset;
293 break;
294 case COMBIOS_FAN_SPEED_INFO_TABLE:
295 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
296 if (check_offset)
297 offset = check_offset;
298 break;
299 case COMBIOS_OVERDRIVE_INFO_TABLE:
300 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
301 if (check_offset)
302 offset = check_offset;
303 break;
304 case COMBIOS_OEM_INFO_TABLE:
305 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
306 if (check_offset)
307 offset = check_offset;
308 break;
309 case COMBIOS_DYN_CLK_2_TABLE:
310 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
311 if (check_offset)
312 offset = check_offset;
313 break;
314 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
315 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
316 if (check_offset)
317 offset = check_offset;
318 break;
319 case COMBIOS_I2C_INFO_TABLE:
320 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
321 if (check_offset)
322 offset = check_offset;
323 break;
324 /* relative offset tables */
325 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
326 check_offset =
327 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
328 if (check_offset) {
329 rev = RBIOS8(check_offset);
330 if (rev > 0) {
331 check_offset = RBIOS16(check_offset + 0x3);
332 if (check_offset)
333 offset = check_offset;
334 }
335 }
336 break;
337 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
338 check_offset =
339 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
340 if (check_offset) {
341 rev = RBIOS8(check_offset);
342 if (rev > 0) {
343 check_offset = RBIOS16(check_offset + 0x5);
344 if (check_offset)
345 offset = check_offset;
346 }
347 }
348 break;
349 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
350 check_offset =
351 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
352 if (check_offset) {
353 rev = RBIOS8(check_offset);
354 if (rev > 0) {
355 check_offset = RBIOS16(check_offset + 0x7);
356 if (check_offset)
357 offset = check_offset;
358 }
359 }
360 break;
361 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
362 check_offset =
363 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
364 if (check_offset) {
365 rev = RBIOS8(check_offset);
366 if (rev == 2) {
367 check_offset = RBIOS16(check_offset + 0x9);
368 if (check_offset)
369 offset = check_offset;
370 }
371 }
372 break;
373 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
374 check_offset =
375 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
376 if (check_offset) {
377 while (RBIOS8(check_offset++));
378 check_offset += 2;
379 if (check_offset)
380 offset = check_offset;
381 }
382 break;
383 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
384 check_offset =
385 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
386 if (check_offset) {
387 check_offset = RBIOS16(check_offset + 0x11);
388 if (check_offset)
389 offset = check_offset;
390 }
391 break;
392 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
393 check_offset =
394 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
395 if (check_offset) {
396 check_offset = RBIOS16(check_offset + 0x13);
397 if (check_offset)
398 offset = check_offset;
399 }
400 break;
401 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
402 check_offset =
403 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
404 if (check_offset) {
405 check_offset = RBIOS16(check_offset + 0x15);
406 if (check_offset)
407 offset = check_offset;
408 }
409 break;
410 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
411 check_offset =
412 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
413 if (check_offset) {
414 check_offset = RBIOS16(check_offset + 0x17);
415 if (check_offset)
416 offset = check_offset;
417 }
418 break;
419 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
420 check_offset =
421 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
422 if (check_offset) {
423 check_offset = RBIOS16(check_offset + 0x2);
424 if (check_offset)
425 offset = check_offset;
426 }
427 break;
428 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
429 check_offset =
430 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
431 if (check_offset) {
432 check_offset = RBIOS16(check_offset + 0x4);
433 if (check_offset)
434 offset = check_offset;
435 }
436 break;
437 default:
438 break;
439 }
440
441 return offset;
442
443}
444
445struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
446{
447 struct radeon_i2c_bus_rec i2c;
448
449 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
450 i2c.mask_data_mask = RADEON_GPIO_EN_0;
451 i2c.a_clk_mask = RADEON_GPIO_A_1;
452 i2c.a_data_mask = RADEON_GPIO_A_0;
9b9fe724
AD		 453 i2c.en_clk_mask = RADEON_GPIO_EN_1;
454 i2c.en_data_mask = RADEON_GPIO_EN_0;
455 i2c.y_clk_mask = RADEON_GPIO_Y_1;
456 i2c.y_data_mask = RADEON_GPIO_Y_0;
771fe6b9
JG		 457 if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
458 (ddc_line == RADEON_MDGPIO_EN_REG)) {
459 i2c.mask_clk_reg = ddc_line;
460 i2c.mask_data_reg = ddc_line;
461 i2c.a_clk_reg = ddc_line;
462 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 463 i2c.en_clk_reg = ddc_line;
464 i2c.en_data_reg = ddc_line;
465 i2c.y_clk_reg = ddc_line + 4;
466 i2c.y_data_reg = ddc_line + 4;
771fe6b9
JG		 467 } else {
468 i2c.mask_clk_reg = ddc_line;
469 i2c.mask_data_reg = ddc_line;
470 i2c.a_clk_reg = ddc_line;
471 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 472 i2c.en_clk_reg = ddc_line;
473 i2c.en_data_reg = ddc_line;
474 i2c.y_clk_reg = ddc_line;
475 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 476 }
477
478 if (ddc_line)
479 i2c.valid = true;
480 else
481 i2c.valid = false;
482
483 return i2c;
484}
485
486bool radeon_combios_get_clock_info(struct drm_device *dev)
487{
488 struct radeon_device *rdev = dev->dev_private;
489 uint16_t pll_info;
490 struct radeon_pll *p1pll = &rdev->clock.p1pll;
491 struct radeon_pll *p2pll = &rdev->clock.p2pll;
492 struct radeon_pll *spll = &rdev->clock.spll;
493 struct radeon_pll *mpll = &rdev->clock.mpll;
494 int8_t rev;
495 uint16_t sclk, mclk;
496
497 if (rdev->bios == NULL)
4b30b870 498 return false;
771fe6b9
JG		 499
500 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
501 if (pll_info) {
502 rev = RBIOS8(pll_info);
503
504 /* pixel clocks */
505 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
506 p1pll->reference_div = RBIOS16(pll_info + 0x10);
507 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
508 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
509
510 if (rev > 9) {
511 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
512 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
513 } else {
514 p1pll->pll_in_min = 40;
515 p1pll->pll_in_max = 500;
516 }
517 *p2pll = *p1pll;
518
519 /* system clock */
520 spll->reference_freq = RBIOS16(pll_info + 0x1a);
521 spll->reference_div = RBIOS16(pll_info + 0x1c);
522 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
523 spll->pll_out_max = RBIOS32(pll_info + 0x22);
524
525 if (rev > 10) {
526 spll->pll_in_min = RBIOS32(pll_info + 0x48);
527 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
528 } else {
529 /* ??? */
530 spll->pll_in_min = 40;
531 spll->pll_in_max = 500;
532 }
533
534 /* memory clock */
535 mpll->reference_freq = RBIOS16(pll_info + 0x26);
536 mpll->reference_div = RBIOS16(pll_info + 0x28);
537 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
538 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
539
540 if (rev > 10) {
541 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
542 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
543 } else {
544 /* ??? */
545 mpll->pll_in_min = 40;
546 mpll->pll_in_max = 500;
547 }
548
549 /* default sclk/mclk */
550 sclk = RBIOS16(pll_info + 0xa);
551 mclk = RBIOS16(pll_info + 0x8);
552 if (sclk == 0)
553 sclk = 200 * 100;
554 if (mclk == 0)
555 mclk = 200 * 100;
556
557 rdev->clock.default_sclk = sclk;
558 rdev->clock.default_mclk = mclk;
559
560 return true;
561 }
562 return false;
563}
564
565struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
566 radeon_encoder
567 *encoder)
568{
569 struct drm_device *dev = encoder->base.dev;
570 struct radeon_device *rdev = dev->dev_private;
571 uint16_t dac_info;
572 uint8_t rev, bg, dac;
573 struct radeon_encoder_primary_dac *p_dac = NULL;
574
575 if (rdev->bios == NULL)
576 return NULL;
577
578 /* check CRT table */
579 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
580 if (dac_info) {
581 p_dac =
582 kzalloc(sizeof(struct radeon_encoder_primary_dac),
583 GFP_KERNEL);
584
585 if (!p_dac)
586 return NULL;
587
588 rev = RBIOS8(dac_info) & 0x3;
589 if (rev < 2) {
590 bg = RBIOS8(dac_info + 0x2) & 0xf;
591 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
592 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
593 } else {
594 bg = RBIOS8(dac_info + 0x2) & 0xf;
595 dac = RBIOS8(dac_info + 0x3) & 0xf;
596 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
597 }
598
599 }
600
601 return p_dac;
602}
603
604static enum radeon_tv_std
605radeon_combios_get_tv_info(struct radeon_encoder *encoder)
606{
607 struct drm_device *dev = encoder->base.dev;
608 struct radeon_device *rdev = dev->dev_private;
609 uint16_t tv_info;
610 enum radeon_tv_std tv_std = TV_STD_NTSC;
611
612 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
613 if (tv_info) {
614 if (RBIOS8(tv_info + 6) == 'T') {
615 switch (RBIOS8(tv_info + 7) & 0xf) {
616 case 1:
617 tv_std = TV_STD_NTSC;
618 DRM_INFO("Default TV standard: NTSC\n");
619 break;
620 case 2:
621 tv_std = TV_STD_PAL;
622 DRM_INFO("Default TV standard: PAL\n");
623 break;
624 case 3:
625 tv_std = TV_STD_PAL_M;
626 DRM_INFO("Default TV standard: PAL-M\n");
627 break;
628 case 4:
629 tv_std = TV_STD_PAL_60;
630 DRM_INFO("Default TV standard: PAL-60\n");
631 break;
632 case 5:
633 tv_std = TV_STD_NTSC_J;
634 DRM_INFO("Default TV standard: NTSC-J\n");
635 break;
636 case 6:
637 tv_std = TV_STD_SCART_PAL;
638 DRM_INFO("Default TV standard: SCART-PAL\n");
639 break;
640 default:
641 tv_std = TV_STD_NTSC;
642 DRM_INFO
643 ("Unknown TV standard; defaulting to NTSC\n");
644 break;
645 }
646
647 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
648 case 0:
649 DRM_INFO("29.498928713 MHz TV ref clk\n");
650 break;
651 case 1:
652 DRM_INFO("28.636360000 MHz TV ref clk\n");
653 break;
654 case 2:
655 DRM_INFO("14.318180000 MHz TV ref clk\n");
656 break;
657 case 3:
658 DRM_INFO("27.000000000 MHz TV ref clk\n");
659 break;
660 default:
661 break;
662 }
663 }
664 }
665 return tv_std;
666}
667
668static const uint32_t default_tvdac_adj[CHIP_LAST] = {
669 0x00000000, /* r100 */
670 0x00280000, /* rv100 */
671 0x00000000, /* rs100 */
672 0x00880000, /* rv200 */
673 0x00000000, /* rs200 */
674 0x00000000, /* r200 */
675 0x00770000, /* rv250 */
676 0x00290000, /* rs300 */
677 0x00560000, /* rv280 */
678 0x00780000, /* r300 */
679 0x00770000, /* r350 */
680 0x00780000, /* rv350 */
681 0x00780000, /* rv380 */
682 0x01080000, /* r420 */
683 0x01080000, /* r423 */
684 0x01080000, /* rv410 */
685 0x00780000, /* rs400 */
686 0x00780000, /* rs480 */
687};
688
6a719e05
DA		 689static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
690 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 691{
771fe6b9
JG		 692 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
693 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
694 tv_dac->ps2_tvdac_adj = 0x00880000;
695 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
696 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 697 return;
771fe6b9
JG		 698}
699
700struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
701 radeon_encoder
702 *encoder)
703{
704 struct drm_device *dev = encoder->base.dev;
705 struct radeon_device *rdev = dev->dev_private;
706 uint16_t dac_info;
707 uint8_t rev, bg, dac;
708 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 709 int found = 0;
710
711 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
712 if (!tv_dac)
713 return NULL;
771fe6b9
JG		 714
715 if (rdev->bios == NULL)
6a719e05 716 goto out;
771fe6b9
JG		 717
718 /* first check TV table */
719 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
720 if (dac_info) {
771fe6b9
JG		 721 rev = RBIOS8(dac_info + 0x3);
722 if (rev > 4) {
723 bg = RBIOS8(dac_info + 0xc) & 0xf;
724 dac = RBIOS8(dac_info + 0xd) & 0xf;
725 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
726
727 bg = RBIOS8(dac_info + 0xe) & 0xf;
728 dac = RBIOS8(dac_info + 0xf) & 0xf;
729 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
730
731 bg = RBIOS8(dac_info + 0x10) & 0xf;
732 dac = RBIOS8(dac_info + 0x11) & 0xf;
733 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 734 found = 1;
771fe6b9
JG		 735 } else if (rev > 1) {
736 bg = RBIOS8(dac_info + 0xc) & 0xf;
737 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
738 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
739
740 bg = RBIOS8(dac_info + 0xd) & 0xf;
741 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
742 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
743
744 bg = RBIOS8(dac_info + 0xe) & 0xf;
745 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
746 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 747 found = 1;
771fe6b9 748 }
771fe6b9 749 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
6a719e05
DA		 750 }
751 if (!found) {
771fe6b9
JG		 752 /* then check CRT table */
753 dac_info =
754 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
755 if (dac_info) {
771fe6b9
JG		 756 rev = RBIOS8(dac_info) & 0x3;
757 if (rev < 2) {
758 bg = RBIOS8(dac_info + 0x3) & 0xf;
759 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
760 tv_dac->ps2_tvdac_adj =
761 (bg << 16) | (dac << 20);
762 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
763 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 764 found = 1;
771fe6b9
JG		 765 } else {
766 bg = RBIOS8(dac_info + 0x4) & 0xf;
767 dac = RBIOS8(dac_info + 0x5) & 0xf;
768 tv_dac->ps2_tvdac_adj =
769 (bg << 16) | (dac << 20);
770 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
771 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 772 found = 1;
771fe6b9 773 }
6fe7ac3f
AD		 774 } else {
775 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 776 }
777 }
778
6a719e05
DA		 779out:
780 if (!found) /* fallback to defaults */
781 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
782
771fe6b9
JG		 783 return tv_dac;
784}
785
786static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
787 radeon_device
788 *rdev)
789{
790 struct radeon_encoder_lvds *lvds = NULL;
791 uint32_t fp_vert_stretch, fp_horz_stretch;
792 uint32_t ppll_div_sel, ppll_val;
8b5c7444 793 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 794
795 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
796
797 if (!lvds)
798 return NULL;
799
800 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
801 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
802
8b5c7444
MD		 803 /* These should be fail-safe defaults, fingers crossed */
804 lvds->panel_pwr_delay = 200;
805 lvds->panel_vcc_delay = 2000;
806
807 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
808 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
809 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
810
771fe6b9 811 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 812 lvds->native_mode.vdisplay =
771fe6b9
JG		 813 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
814 RADEON_VERT_PANEL_SHIFT) + 1;
815 else
de2103e4 816 lvds->native_mode.vdisplay =
771fe6b9
JG		 817 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
818
819 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 820 lvds->native_mode.hdisplay =
771fe6b9
JG		 821 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
822 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
823 else
de2103e4 824 lvds->native_mode.hdisplay =
771fe6b9
JG		 825 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
826
de2103e4
AD		 827 if ((lvds->native_mode.hdisplay < 640) ||
828 (lvds->native_mode.vdisplay < 480)) {
829 lvds->native_mode.hdisplay = 640;
830 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 831 }
832
833 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
834 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
835 if ((ppll_val & 0x000707ff) == 0x1bb)
836 lvds->use_bios_dividers = false;
837 else {
838 lvds->panel_ref_divider =
839 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
840 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
841 lvds->panel_fb_divider = ppll_val & 0x7ff;
842
843 if ((lvds->panel_ref_divider != 0) &&
844 (lvds->panel_fb_divider > 3))
845 lvds->use_bios_dividers = true;
846 }
847 lvds->panel_vcc_delay = 200;
848
849 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 850 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
851 lvds->native_mode.vdisplay);
771fe6b9
JG		 852
853 return lvds;
854}
855
856struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
857 *encoder)
858{
859 struct drm_device *dev = encoder->base.dev;
860 struct radeon_device *rdev = dev->dev_private;
861 uint16_t lcd_info;
862 uint32_t panel_setup;
863 char stmp[30];
864 int tmp, i;
865 struct radeon_encoder_lvds *lvds = NULL;
866
8dfaa8a7
MD		 867 if (rdev->bios == NULL) {
868 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
869 goto out;
870 }
771fe6b9
JG		 871
872 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
873
874 if (lcd_info) {
875 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
876
877 if (!lvds)
878 return NULL;
879
880 for (i = 0; i < 24; i++)
881 stmp[i] = RBIOS8(lcd_info + i + 1);
882 stmp[24] = 0;
883
884 DRM_INFO("Panel ID String: %s\n", stmp);
885
de2103e4
AD		 886 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
887 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 888
de2103e4
AD		 889 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
890 lvds->native_mode.vdisplay);
771fe6b9
JG		 891
892 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
893 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
894 lvds->panel_vcc_delay = 2000;
895
896 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
897 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
898 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
899
900 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
901 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
902 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
903 if ((lvds->panel_ref_divider != 0) &&
904 (lvds->panel_fb_divider > 3))
905 lvds->use_bios_dividers = true;
906
907 panel_setup = RBIOS32(lcd_info + 0x39);
908 lvds->lvds_gen_cntl = 0xff00;
909 if (panel_setup & 0x1)
910 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
911
912 if ((panel_setup >> 4) & 0x1)
913 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
914
915 switch ((panel_setup >> 8) & 0x7) {
916 case 0:
917 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
918 break;
919 case 1:
920 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
921 break;
922 case 2:
923 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
924 break;
925 default:
926 break;
927 }
928
929 if ((panel_setup >> 16) & 0x1)
930 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
931
932 if ((panel_setup >> 17) & 0x1)
933 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
934
935 if ((panel_setup >> 18) & 0x1)
936 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
937
938 if ((panel_setup >> 23) & 0x1)
939 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
940
941 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
942
943 for (i = 0; i < 32; i++) {
944 tmp = RBIOS16(lcd_info + 64 + i * 2);
945 if (tmp == 0)
946 break;
947
de2103e4 948 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
771fe6b9 949 (RBIOS16(tmp + 2) ==
de2103e4
AD		 950 lvds->native_mode.vdisplay)) {
951 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
952 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
953 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
954 RBIOS16(tmp + 21)) * 8;
955
956 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
957 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
958 lvds->native_mode.vsync_end =
959 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
960 (RBIOS16(tmp + 28) & 0x7ff);
961
962 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 963 lvds->native_mode.flags = 0;
de2103e4
AD		 964 /* set crtc values */
965 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
966
771fe6b9
JG		 967 }
968 }
6fe7ac3f 969 } else {
771fe6b9 970 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 971 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 972 }
8dfaa8a7
MD		 973out:
974 if (lvds)
975 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 976 return lvds;
977}
978
979static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
980 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
981 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
982 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
983 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
984 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
985 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
986 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
987 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
988 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
989 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
990 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
991 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
992 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
993 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
994 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
995 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 996 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
997 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 998};
999
445282db
DA		 1000bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1001 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1002{
445282db
DA		 1003 struct drm_device *dev = encoder->base.dev;
1004 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1005 int i;
771fe6b9
JG		 1006
1007 for (i = 0; i < 4; i++) {
1008 tmds->tmds_pll[i].value =
445282db 1009 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1010 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1011 }
1012
445282db 1013 return true;
771fe6b9
JG		 1014}
1015
445282db
DA		 1016bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1017 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1018{
1019 struct drm_device *dev = encoder->base.dev;
1020 struct radeon_device *rdev = dev->dev_private;
1021 uint16_t tmds_info;
1022 int i, n;
1023 uint8_t ver;
771fe6b9
JG		 1024
1025 if (rdev->bios == NULL)
445282db 1026 return false;
771fe6b9
JG		 1027
1028 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1029
1030 if (tmds_info) {
771fe6b9
JG		 1031 ver = RBIOS8(tmds_info);
1032 DRM_INFO("DFP table revision: %d\n", ver);
1033 if (ver == 3) {
1034 n = RBIOS8(tmds_info + 5) + 1;
1035 if (n > 4)
1036 n = 4;
1037 for (i = 0; i < n; i++) {
1038 tmds->tmds_pll[i].value =
1039 RBIOS32(tmds_info + i * 10 + 0x08);
1040 tmds->tmds_pll[i].freq =
1041 RBIOS16(tmds_info + i * 10 + 0x10);
1042 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1043 tmds->tmds_pll[i].freq,
1044 tmds->tmds_pll[i].value);
1045 }
1046 } else if (ver == 4) {
1047 int stride = 0;
1048 n = RBIOS8(tmds_info + 5) + 1;
1049 if (n > 4)
1050 n = 4;
1051 for (i = 0; i < n; i++) {
1052 tmds->tmds_pll[i].value =
1053 RBIOS32(tmds_info + stride + 0x08);
1054 tmds->tmds_pll[i].freq =
1055 RBIOS16(tmds_info + stride + 0x10);
1056 if (i == 0)
1057 stride += 10;
1058 else
1059 stride += 6;
1060 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1061 tmds->tmds_pll[i].freq,
1062 tmds->tmds_pll[i].value);
1063 }
1064 }
fcec570b 1065 } else {
771fe6b9 1066 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1067 return false;
1068 }
445282db
DA		 1069 return true;
1070}
1071
fcec570b
AD		 1072bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1073 struct radeon_encoder_ext_tmds *tmds)
445282db 1074{
fcec570b
AD		 1075 struct drm_device *dev = encoder->base.dev;
1076 struct radeon_device *rdev = dev->dev_private;
1077 struct radeon_i2c_bus_rec i2c_bus;
445282db 1078
fcec570b
AD		 1079 /* default for macs */
1080 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1081 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
445282db 1082
fcec570b
AD		 1083 /* XXX some macs have duallink chips */
1084 switch (rdev->mode_info.connector_table) {
1085 case CT_POWERBOOK_EXTERNAL:
1086 case CT_MINI_EXTERNAL:
1087 default:
1088 tmds->dvo_chip = DVO_SIL164;
1089 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1090 break;
1091 }
445282db 1092
fcec570b 1093 return true;
771fe6b9
JG		 1094}
1095
fcec570b
AD		 1096bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1097 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1098{
1099 struct drm_device *dev = encoder->base.dev;
1100 struct radeon_device *rdev = dev->dev_private;
fcec570b
AD		 1101 uint16_t offset;
1102 uint8_t ver, id, blocks, clk, data;
1103 int i;
1104 enum radeon_combios_ddc gpio;
1105 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9
JG		 1106
1107 if (rdev->bios == NULL)
fcec570b 1108 return false;
771fe6b9 1109
fcec570b
AD		 1110 tmds->i2c_bus = NULL;
1111 if (rdev->flags & RADEON_IS_IGP) {
1112 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1113 if (offset) {
1114 ver = RBIOS8(offset);
1115 DRM_INFO("GPIO Table revision: %d\n", ver);
1116 blocks = RBIOS8(offset + 2);
1117 for (i = 0; i < blocks; i++) {
1118 id = RBIOS8(offset + 3 + (i * 5) + 0);
1119 if (id == 136) {
1120 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1121 data = RBIOS8(offset + 3 + (i * 5) + 4);
1122 i2c_bus.valid = true;
1123 i2c_bus.mask_clk_mask = (1 << clk);
1124 i2c_bus.mask_data_mask = (1 << data);
1125 i2c_bus.a_clk_mask = (1 << clk);
1126 i2c_bus.a_data_mask = (1 << data);
1127 i2c_bus.en_clk_mask = (1 << clk);
1128 i2c_bus.en_data_mask = (1 << data);
1129 i2c_bus.y_clk_mask = (1 << clk);
1130 i2c_bus.y_data_mask = (1 << data);
1131 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1132 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1133 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1134 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1135 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1136 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1137 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1138 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1139 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1140 tmds->dvo_chip = DVO_SIL164;
1141 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1142 break;
1143 }
1144 }
1145 }
1146 } else {
1147 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1148 if (offset) {
1149 ver = RBIOS8(offset);
1150 DRM_INFO("External TMDS Table revision: %d\n", ver);
1151 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1152 tmds->slave_addr >>= 1; /* 7 bit addressing */
1153 gpio = RBIOS8(offset + 4 + 3);
1154 switch (gpio) {
1155 case DDC_MONID:
1156 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1157 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1158 break;
1159 case DDC_DVI:
1160 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1161 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1162 break;
1163 case DDC_VGA:
1164 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1165 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1166 break;
1167 case DDC_CRT2:
1168 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1169 if (rdev->family >= CHIP_R300)
1170 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1171 else
1172 i2c_bus = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1173 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1174 break;
1175 case DDC_LCD: /* MM i2c */
1176 DRM_ERROR("MM i2c requires hw i2c engine\n");
1177 break;
1178 default:
1179 DRM_ERROR("Unsupported gpio %d\n", gpio);
1180 break;
1181 }
1182 }
771fe6b9 1183 }
fcec570b
AD		 1184
1185 if (!tmds->i2c_bus) {
1186 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1187 return false;
1188 }
1189
1190 return true;
771fe6b9
JG		 1191}
1192
1193bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1194{
1195 struct radeon_device *rdev = dev->dev_private;
1196 struct radeon_i2c_bus_rec ddc_i2c;
1197
1198 rdev->mode_info.connector_table = radeon_connector_table;
1199 if (rdev->mode_info.connector_table == CT_NONE) {
1200#ifdef CONFIG_PPC_PMAC
1201 if (machine_is_compatible("PowerBook3,3")) {
1202 /* powerbook with VGA */
1203 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1204 } else if (machine_is_compatible("PowerBook3,4") ||
1205 machine_is_compatible("PowerBook3,5")) {
1206 /* powerbook with internal tmds */
1207 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1208 } else if (machine_is_compatible("PowerBook5,1") ||
1209 machine_is_compatible("PowerBook5,2") ||
1210 machine_is_compatible("PowerBook5,3") ||
1211 machine_is_compatible("PowerBook5,4") ||
1212 machine_is_compatible("PowerBook5,5")) {
1213 /* powerbook with external single link tmds (sil164) */
1214 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1215 } else if (machine_is_compatible("PowerBook5,6")) {
1216 /* powerbook with external dual or single link tmds */
1217 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1218 } else if (machine_is_compatible("PowerBook5,7") ||
1219 machine_is_compatible("PowerBook5,8") ||
1220 machine_is_compatible("PowerBook5,9")) {
1221 /* PowerBook6,2 ? */
1222 /* powerbook with external dual link tmds (sil1178?) */
1223 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1224 } else if (machine_is_compatible("PowerBook4,1") ||
1225 machine_is_compatible("PowerBook4,2") ||
1226 machine_is_compatible("PowerBook4,3") ||
1227 machine_is_compatible("PowerBook6,3") ||
1228 machine_is_compatible("PowerBook6,5") ||
1229 machine_is_compatible("PowerBook6,7")) {
1230 /* ibook */
1231 rdev->mode_info.connector_table = CT_IBOOK;
1232 } else if (machine_is_compatible("PowerMac4,4")) {
1233 /* emac */
1234 rdev->mode_info.connector_table = CT_EMAC;
1235 } else if (machine_is_compatible("PowerMac10,1")) {
1236 /* mini with internal tmds */
1237 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1238 } else if (machine_is_compatible("PowerMac10,2")) {
1239 /* mini with external tmds */
1240 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1241 } else if (machine_is_compatible("PowerMac12,1")) {
1242 /* PowerMac8,1 ? */
1243 /* imac g5 isight */
1244 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1245 } else
1246#endif /* CONFIG_PPC_PMAC */
1247 rdev->mode_info.connector_table = CT_GENERIC;
1248 }
1249
1250 switch (rdev->mode_info.connector_table) {
1251 case CT_GENERIC:
1252 DRM_INFO("Connector Table: %d (generic)\n",
1253 rdev->mode_info.connector_table);
1254 /* these are the most common settings */
1255 if (rdev->flags & RADEON_SINGLE_CRTC) {
1256 /* VGA - primary dac */
1257 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1258 radeon_add_legacy_encoder(dev,
1259 radeon_get_encoder_id(dev,
1260 ATOM_DEVICE_CRT1_SUPPORT,
1261 1),
1262 ATOM_DEVICE_CRT1_SUPPORT);
1263 radeon_add_legacy_connector(dev, 0,
1264 ATOM_DEVICE_CRT1_SUPPORT,
1265 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1266 &ddc_i2c,
1267 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1268 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1269 /* LVDS */
1270 ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
1271 radeon_add_legacy_encoder(dev,
1272 radeon_get_encoder_id(dev,
1273 ATOM_DEVICE_LCD1_SUPPORT,
1274 0),
1275 ATOM_DEVICE_LCD1_SUPPORT);
1276 radeon_add_legacy_connector(dev, 0,
1277 ATOM_DEVICE_LCD1_SUPPORT,
1278 DRM_MODE_CONNECTOR_LVDS,
b75fad06
AD		 1279 &ddc_i2c,
1280 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1281
1282 /* VGA - primary dac */
1283 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1284 radeon_add_legacy_encoder(dev,
1285 radeon_get_encoder_id(dev,
1286 ATOM_DEVICE_CRT1_SUPPORT,
1287 1),
1288 ATOM_DEVICE_CRT1_SUPPORT);
1289 radeon_add_legacy_connector(dev, 1,
1290 ATOM_DEVICE_CRT1_SUPPORT,
1291 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1292 &ddc_i2c,
1293 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1294 } else {
1295 /* DVI-I - tv dac, int tmds */
1296 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1297 radeon_add_legacy_encoder(dev,
1298 radeon_get_encoder_id(dev,
1299 ATOM_DEVICE_DFP1_SUPPORT,
1300 0),
1301 ATOM_DEVICE_DFP1_SUPPORT);
1302 radeon_add_legacy_encoder(dev,
1303 radeon_get_encoder_id(dev,
1304 ATOM_DEVICE_CRT2_SUPPORT,
1305 2),
1306 ATOM_DEVICE_CRT2_SUPPORT);
1307 radeon_add_legacy_connector(dev, 0,
1308 ATOM_DEVICE_DFP1_SUPPORT |
1309 ATOM_DEVICE_CRT2_SUPPORT,
1310 DRM_MODE_CONNECTOR_DVII,
b75fad06
AD		 1311 &ddc_i2c,
1312 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1313
1314 /* VGA - primary dac */
1315 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1316 radeon_add_legacy_encoder(dev,
1317 radeon_get_encoder_id(dev,
1318 ATOM_DEVICE_CRT1_SUPPORT,
1319 1),
1320 ATOM_DEVICE_CRT1_SUPPORT);
1321 radeon_add_legacy_connector(dev, 1,
1322 ATOM_DEVICE_CRT1_SUPPORT,
1323 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1324 &ddc_i2c,
1325 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1326 }
1327
1328 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1329 /* TV - tv dac */
1330 radeon_add_legacy_encoder(dev,
1331 radeon_get_encoder_id(dev,
1332 ATOM_DEVICE_TV1_SUPPORT,
1333 2),
1334 ATOM_DEVICE_TV1_SUPPORT);
1335 radeon_add_legacy_connector(dev, 2,
1336 ATOM_DEVICE_TV1_SUPPORT,
1337 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1338 &ddc_i2c,
1339 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1340 }
1341 break;
1342 case CT_IBOOK:
1343 DRM_INFO("Connector Table: %d (ibook)\n",
1344 rdev->mode_info.connector_table);
1345 /* LVDS */
1346 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1347 radeon_add_legacy_encoder(dev,
1348 radeon_get_encoder_id(dev,
1349 ATOM_DEVICE_LCD1_SUPPORT,
1350 0),
1351 ATOM_DEVICE_LCD1_SUPPORT);
1352 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1353 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1354 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1355 /* VGA - TV DAC */
1356 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1357 radeon_add_legacy_encoder(dev,
1358 radeon_get_encoder_id(dev,
1359 ATOM_DEVICE_CRT2_SUPPORT,
1360 2),
1361 ATOM_DEVICE_CRT2_SUPPORT);
1362 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1363 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1364 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1365 /* TV - TV DAC */
1366 radeon_add_legacy_encoder(dev,
1367 radeon_get_encoder_id(dev,
1368 ATOM_DEVICE_TV1_SUPPORT,
1369 2),
1370 ATOM_DEVICE_TV1_SUPPORT);
1371 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1372 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1373 &ddc_i2c,
1374 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1375 break;
1376 case CT_POWERBOOK_EXTERNAL:
1377 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1378 rdev->mode_info.connector_table);
1379 /* LVDS */
1380 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1381 radeon_add_legacy_encoder(dev,
1382 radeon_get_encoder_id(dev,
1383 ATOM_DEVICE_LCD1_SUPPORT,
1384 0),
1385 ATOM_DEVICE_LCD1_SUPPORT);
1386 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1387 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1388 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1389 /* DVI-I - primary dac, ext tmds */
1390 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1391 radeon_add_legacy_encoder(dev,
1392 radeon_get_encoder_id(dev,
1393 ATOM_DEVICE_DFP2_SUPPORT,
1394 0),
1395 ATOM_DEVICE_DFP2_SUPPORT);
1396 radeon_add_legacy_encoder(dev,
1397 radeon_get_encoder_id(dev,
1398 ATOM_DEVICE_CRT1_SUPPORT,
1399 1),
1400 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1401 /* XXX some are SL */
771fe6b9
JG		 1402 radeon_add_legacy_connector(dev, 1,
1403 ATOM_DEVICE_DFP2_SUPPORT |
1404 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1405 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1406 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I);
771fe6b9
JG		 1407 /* TV - TV DAC */
1408 radeon_add_legacy_encoder(dev,
1409 radeon_get_encoder_id(dev,
1410 ATOM_DEVICE_TV1_SUPPORT,
1411 2),
1412 ATOM_DEVICE_TV1_SUPPORT);
1413 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1414 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1415 &ddc_i2c,
1416 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1417 break;
1418 case CT_POWERBOOK_INTERNAL:
1419 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1420 rdev->mode_info.connector_table);
1421 /* LVDS */
1422 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1423 radeon_add_legacy_encoder(dev,
1424 radeon_get_encoder_id(dev,
1425 ATOM_DEVICE_LCD1_SUPPORT,
1426 0),
1427 ATOM_DEVICE_LCD1_SUPPORT);
1428 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1429 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1430 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1431 /* DVI-I - primary dac, int tmds */
1432 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1433 radeon_add_legacy_encoder(dev,
1434 radeon_get_encoder_id(dev,
1435 ATOM_DEVICE_DFP1_SUPPORT,
1436 0),
1437 ATOM_DEVICE_DFP1_SUPPORT);
1438 radeon_add_legacy_encoder(dev,
1439 radeon_get_encoder_id(dev,
1440 ATOM_DEVICE_CRT1_SUPPORT,
1441 1),
1442 ATOM_DEVICE_CRT1_SUPPORT);
1443 radeon_add_legacy_connector(dev, 1,
1444 ATOM_DEVICE_DFP1_SUPPORT |
1445 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1446 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1447 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1448 /* TV - TV DAC */
1449 radeon_add_legacy_encoder(dev,
1450 radeon_get_encoder_id(dev,
1451 ATOM_DEVICE_TV1_SUPPORT,
1452 2),
1453 ATOM_DEVICE_TV1_SUPPORT);
1454 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1455 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1456 &ddc_i2c,
1457 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1458 break;
1459 case CT_POWERBOOK_VGA:
1460 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1461 rdev->mode_info.connector_table);
1462 /* LVDS */
1463 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1464 radeon_add_legacy_encoder(dev,
1465 radeon_get_encoder_id(dev,
1466 ATOM_DEVICE_LCD1_SUPPORT,
1467 0),
1468 ATOM_DEVICE_LCD1_SUPPORT);
1469 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06
AD		 1470 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1471 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 1472 /* VGA - primary dac */
1473 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1474 radeon_add_legacy_encoder(dev,
1475 radeon_get_encoder_id(dev,
1476 ATOM_DEVICE_CRT1_SUPPORT,
1477 1),
1478 ATOM_DEVICE_CRT1_SUPPORT);
1479 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1480 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1481 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1482 /* TV - TV DAC */
1483 radeon_add_legacy_encoder(dev,
1484 radeon_get_encoder_id(dev,
1485 ATOM_DEVICE_TV1_SUPPORT,
1486 2),
1487 ATOM_DEVICE_TV1_SUPPORT);
1488 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1489 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1490 &ddc_i2c,
1491 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1492 break;
1493 case CT_MINI_EXTERNAL:
1494 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1495 rdev->mode_info.connector_table);
1496 /* DVI-I - tv dac, ext tmds */
1497 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1498 radeon_add_legacy_encoder(dev,
1499 radeon_get_encoder_id(dev,
1500 ATOM_DEVICE_DFP2_SUPPORT,
1501 0),
1502 ATOM_DEVICE_DFP2_SUPPORT);
1503 radeon_add_legacy_encoder(dev,
1504 radeon_get_encoder_id(dev,
1505 ATOM_DEVICE_CRT2_SUPPORT,
1506 2),
1507 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1508 /* XXX are any DL? */
771fe6b9
JG		 1509 radeon_add_legacy_connector(dev, 0,
1510 ATOM_DEVICE_DFP2_SUPPORT |
1511 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1512 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1513 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1514 /* TV - TV DAC */
1515 radeon_add_legacy_encoder(dev,
1516 radeon_get_encoder_id(dev,
1517 ATOM_DEVICE_TV1_SUPPORT,
1518 2),
1519 ATOM_DEVICE_TV1_SUPPORT);
1520 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1521 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1522 &ddc_i2c,
1523 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1524 break;
1525 case CT_MINI_INTERNAL:
1526 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1527 rdev->mode_info.connector_table);
1528 /* DVI-I - tv dac, int tmds */
1529 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1530 radeon_add_legacy_encoder(dev,
1531 radeon_get_encoder_id(dev,
1532 ATOM_DEVICE_DFP1_SUPPORT,
1533 0),
1534 ATOM_DEVICE_DFP1_SUPPORT);
1535 radeon_add_legacy_encoder(dev,
1536 radeon_get_encoder_id(dev,
1537 ATOM_DEVICE_CRT2_SUPPORT,
1538 2),
1539 ATOM_DEVICE_CRT2_SUPPORT);
1540 radeon_add_legacy_connector(dev, 0,
1541 ATOM_DEVICE_DFP1_SUPPORT |
1542 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1543 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1544 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9
JG		 1545 /* TV - TV DAC */
1546 radeon_add_legacy_encoder(dev,
1547 radeon_get_encoder_id(dev,
1548 ATOM_DEVICE_TV1_SUPPORT,
1549 2),
1550 ATOM_DEVICE_TV1_SUPPORT);
1551 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1552 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1553 &ddc_i2c,
1554 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1555 break;
1556 case CT_IMAC_G5_ISIGHT:
1557 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1558 rdev->mode_info.connector_table);
1559 /* DVI-D - int tmds */
1560 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1561 radeon_add_legacy_encoder(dev,
1562 radeon_get_encoder_id(dev,
1563 ATOM_DEVICE_DFP1_SUPPORT,
1564 0),
1565 ATOM_DEVICE_DFP1_SUPPORT);
1566 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06
AD		 1567 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1568 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
771fe6b9
JG		 1569 /* VGA - tv dac */
1570 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1571 radeon_add_legacy_encoder(dev,
1572 radeon_get_encoder_id(dev,
1573 ATOM_DEVICE_CRT2_SUPPORT,
1574 2),
1575 ATOM_DEVICE_CRT2_SUPPORT);
1576 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1577 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1578 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1579 /* TV - TV DAC */
1580 radeon_add_legacy_encoder(dev,
1581 radeon_get_encoder_id(dev,
1582 ATOM_DEVICE_TV1_SUPPORT,
1583 2),
1584 ATOM_DEVICE_TV1_SUPPORT);
1585 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1586 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1587 &ddc_i2c,
1588 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1589 break;
1590 case CT_EMAC:
1591 DRM_INFO("Connector Table: %d (emac)\n",
1592 rdev->mode_info.connector_table);
1593 /* VGA - primary dac */
1594 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1595 radeon_add_legacy_encoder(dev,
1596 radeon_get_encoder_id(dev,
1597 ATOM_DEVICE_CRT1_SUPPORT,
1598 1),
1599 ATOM_DEVICE_CRT1_SUPPORT);
1600 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06
AD		 1601 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1602 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1603 /* VGA - tv dac */
1604 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1605 radeon_add_legacy_encoder(dev,
1606 radeon_get_encoder_id(dev,
1607 ATOM_DEVICE_CRT2_SUPPORT,
1608 2),
1609 ATOM_DEVICE_CRT2_SUPPORT);
1610 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06
AD		 1611 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1612 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1613 /* TV - TV DAC */
1614 radeon_add_legacy_encoder(dev,
1615 radeon_get_encoder_id(dev,
1616 ATOM_DEVICE_TV1_SUPPORT,
1617 2),
1618 ATOM_DEVICE_TV1_SUPPORT);
1619 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1620 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 1621 &ddc_i2c,
1622 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1623 break;
1624 default:
1625 DRM_INFO("Connector table: %d (invalid)\n",
1626 rdev->mode_info.connector_table);
1627 return false;
1628 }
1629
1630 radeon_link_encoder_connector(dev);
1631
1632 return true;
1633}
1634
1635static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1636 int bios_index,
1637 enum radeon_combios_connector
1638 *legacy_connector,
1639 struct radeon_i2c_bus_rec *ddc_i2c)
1640{
1641 struct radeon_device *rdev = dev->dev_private;
1642
1643 /* XPRESS DDC quirks */
1644 if ((rdev->family == CHIP_RS400 ||
1645 rdev->family == CHIP_RS480) &&
1646 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1647 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1648 else if ((rdev->family == CHIP_RS400 ||
1649 rdev->family == CHIP_RS480) &&
1650 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1651 ddc_i2c->valid = true;
1652 ddc_i2c->mask_clk_mask = (0x20 << 8);
1653 ddc_i2c->mask_data_mask = 0x80;
1654 ddc_i2c->a_clk_mask = (0x20 << 8);
1655 ddc_i2c->a_data_mask = 0x80;
9b9fe724
AD		 1656 ddc_i2c->en_clk_mask = (0x20 << 8);
1657 ddc_i2c->en_data_mask = 0x80;
1658 ddc_i2c->y_clk_mask = (0x20 << 8);
1659 ddc_i2c->y_data_mask = 0x80;
771fe6b9
JG		 1660 ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
1661 ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
1662 ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
1663 ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
9b9fe724
AD		 1664 ddc_i2c->en_clk_reg = RADEON_GPIOPAD_EN;
1665 ddc_i2c->en_data_reg = RADEON_GPIOPAD_EN;
fcec570b
AD		 1666 ddc_i2c->y_clk_reg = RADEON_GPIOPAD_Y;
1667 ddc_i2c->y_data_reg = RADEON_GPIOPAD_Y;
771fe6b9
JG		 1668 }
1669
fcec570b
AD		 1670 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1671 if ((rdev->family >= CHIP_R300) &&
1672 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1673 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1674
771fe6b9
JG		 1675 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1676 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1677 if (dev->pdev->device == 0x515e &&
1678 dev->pdev->subsystem_vendor == 0x1014) {
1679 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1680 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1681 return false;
1682 }
1683
1684 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1685 if (dev->pdev->device == 0x5159 &&
1686 dev->pdev->subsystem_vendor == 0x1002 &&
1687 dev->pdev->subsystem_device == 0x013a) {
1688 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1689 *legacy_connector = CONNECTOR_CRT_LEGACY;
1690
1691 }
1692
1693 /* X300 card with extra non-existent DVI port */
1694 if (dev->pdev->device == 0x5B60 &&
1695 dev->pdev->subsystem_vendor == 0x17af &&
1696 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1697 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1698 return false;
1699 }
1700
1701 return true;
1702}
1703
790cfb34
AD		 1704static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1705{
1706 /* Acer 5102 has non-existent TV port */
1707 if (dev->pdev->device == 0x5975 &&
1708 dev->pdev->subsystem_vendor == 0x1025 &&
1709 dev->pdev->subsystem_device == 0x009f)
1710 return false;
1711
fc7f7119
AD		 1712 /* HP dc5750 has non-existent TV port */
1713 if (dev->pdev->device == 0x5974 &&
1714 dev->pdev->subsystem_vendor == 0x103c &&
1715 dev->pdev->subsystem_device == 0x280a)
1716 return false;
1717
fd874ad0
AD		 1718 /* MSI S270 has non-existent TV port */
1719 if (dev->pdev->device == 0x5955 &&
1720 dev->pdev->subsystem_vendor == 0x1462 &&
1721 dev->pdev->subsystem_device == 0x0131)
1722 return false;
1723
790cfb34
AD		 1724 return true;
1725}
1726
b75fad06
AD		 1727static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1728{
1729 struct radeon_device *rdev = dev->dev_private;
1730 uint32_t ext_tmds_info;
1731
1732 if (rdev->flags & RADEON_IS_IGP) {
1733 if (is_dvi_d)
1734 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1735 else
1736 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1737 }
1738 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1739 if (ext_tmds_info) {
1740 uint8_t rev = RBIOS8(ext_tmds_info);
1741 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1742 if (rev >= 3) {
1743 if (is_dvi_d)
1744 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1745 else
1746 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1747 } else {
1748 if (flags & 1) {
1749 if (is_dvi_d)
1750 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1751 else
1752 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1753 }
1754 }
1755 }
1756 if (is_dvi_d)
1757 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1758 else
1759 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1760}
1761
771fe6b9
JG		 1762bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1763{
1764 struct radeon_device *rdev = dev->dev_private;
1765 uint32_t conn_info, entry, devices;
b75fad06 1766 uint16_t tmp, connector_object_id;
771fe6b9
JG		 1767 enum radeon_combios_ddc ddc_type;
1768 enum radeon_combios_connector connector;
1769 int i = 0;
1770 struct radeon_i2c_bus_rec ddc_i2c;
1771
1772 if (rdev->bios == NULL)
1773 return false;
1774
1775 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1776 if (conn_info) {
1777 for (i = 0; i < 4; i++) {
1778 entry = conn_info + 2 + i * 2;
1779
1780 if (!RBIOS16(entry))
1781 break;
1782
1783 tmp = RBIOS16(entry);
1784
1785 connector = (tmp >> 12) & 0xf;
1786
1787 ddc_type = (tmp >> 8) & 0xf;
1788 switch (ddc_type) {
1789 case DDC_MONID:
1790 ddc_i2c =
1791 combios_setup_i2c_bus(RADEON_GPIO_MONID);
1792 break;
1793 case DDC_DVI:
1794 ddc_i2c =
1795 combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1796 break;
1797 case DDC_VGA:
1798 ddc_i2c =
1799 combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1800 break;
1801 case DDC_CRT2:
1802 ddc_i2c =
1803 combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1804 break;
1805 default:
1806 break;
1807 }
1808
2d152c6b
AD		 1809 if (!radeon_apply_legacy_quirks(dev, i, &connector,
1810 &ddc_i2c))
1811 continue;
771fe6b9
JG		 1812
1813 switch (connector) {
1814 case CONNECTOR_PROPRIETARY_LEGACY:
1815 if ((tmp >> 4) & 0x1)
1816 devices = ATOM_DEVICE_DFP2_SUPPORT;
1817 else
1818 devices = ATOM_DEVICE_DFP1_SUPPORT;
1819 radeon_add_legacy_encoder(dev,
1820 radeon_get_encoder_id
1821 (dev, devices, 0),
1822 devices);
1823 radeon_add_legacy_connector(dev, i, devices,
1824 legacy_connector_convert
1825 [connector],
b75fad06
AD		 1826 &ddc_i2c,
1827 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
771fe6b9
JG		 1828 break;
1829 case CONNECTOR_CRT_LEGACY:
1830 if (tmp & 0x1) {
1831 devices = ATOM_DEVICE_CRT2_SUPPORT;
1832 radeon_add_legacy_encoder(dev,
1833 radeon_get_encoder_id
1834 (dev,
1835 ATOM_DEVICE_CRT2_SUPPORT,
1836 2),
1837 ATOM_DEVICE_CRT2_SUPPORT);
1838 } else {
1839 devices = ATOM_DEVICE_CRT1_SUPPORT;
1840 radeon_add_legacy_encoder(dev,
1841 radeon_get_encoder_id
1842 (dev,
1843 ATOM_DEVICE_CRT1_SUPPORT,
1844 1),
1845 ATOM_DEVICE_CRT1_SUPPORT);
1846 }
1847 radeon_add_legacy_connector(dev,
1848 i,
1849 devices,
1850 legacy_connector_convert
1851 [connector],
b75fad06
AD		 1852 &ddc_i2c,
1853 CONNECTOR_OBJECT_ID_VGA);
771fe6b9
JG		 1854 break;
1855 case CONNECTOR_DVI_I_LEGACY:
1856 devices = 0;
1857 if (tmp & 0x1) {
1858 devices |= ATOM_DEVICE_CRT2_SUPPORT;
1859 radeon_add_legacy_encoder(dev,
1860 radeon_get_encoder_id
1861 (dev,
1862 ATOM_DEVICE_CRT2_SUPPORT,
1863 2),
1864 ATOM_DEVICE_CRT2_SUPPORT);
1865 } else {
1866 devices |= ATOM_DEVICE_CRT1_SUPPORT;
1867 radeon_add_legacy_encoder(dev,
1868 radeon_get_encoder_id
1869 (dev,
1870 ATOM_DEVICE_CRT1_SUPPORT,
1871 1),
1872 ATOM_DEVICE_CRT1_SUPPORT);
1873 }
1874 if ((tmp >> 4) & 0x1) {
1875 devices |= ATOM_DEVICE_DFP2_SUPPORT;
1876 radeon_add_legacy_encoder(dev,
1877 radeon_get_encoder_id
1878 (dev,
1879 ATOM_DEVICE_DFP2_SUPPORT,
1880 0),
1881 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 1882 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 1883 } else {
1884 devices |= ATOM_DEVICE_DFP1_SUPPORT;
1885 radeon_add_legacy_encoder(dev,
1886 radeon_get_encoder_id
1887 (dev,
1888 ATOM_DEVICE_DFP1_SUPPORT,
1889 0),
1890 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 1891 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 1892 }
1893 radeon_add_legacy_connector(dev,
1894 i,
1895 devices,
1896 legacy_connector_convert
1897 [connector],
b75fad06
AD		 1898 &ddc_i2c,
1899 connector_object_id);
771fe6b9
JG		 1900 break;
1901 case CONNECTOR_DVI_D_LEGACY:
b75fad06 1902 if ((tmp >> 4) & 0x1) {
771fe6b9 1903 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 1904 connector_object_id = combios_check_dl_dvi(dev, 1);
1905 } else {
771fe6b9 1906 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 1907 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1908 }
771fe6b9
JG		 1909 radeon_add_legacy_encoder(dev,
1910 radeon_get_encoder_id
1911 (dev, devices, 0),
1912 devices);
1913 radeon_add_legacy_connector(dev, i, devices,
1914 legacy_connector_convert
1915 [connector],
b75fad06
AD		 1916 &ddc_i2c,
1917 connector_object_id);
771fe6b9
JG		 1918 break;
1919 case CONNECTOR_CTV_LEGACY:
1920 case CONNECTOR_STV_LEGACY:
1921 radeon_add_legacy_encoder(dev,
1922 radeon_get_encoder_id
1923 (dev,
1924 ATOM_DEVICE_TV1_SUPPORT,
1925 2),
1926 ATOM_DEVICE_TV1_SUPPORT);
1927 radeon_add_legacy_connector(dev, i,
1928 ATOM_DEVICE_TV1_SUPPORT,
1929 legacy_connector_convert
1930 [connector],
b75fad06
AD		 1931 &ddc_i2c,
1932 CONNECTOR_OBJECT_ID_SVIDEO);
771fe6b9
JG		 1933 break;
1934 default:
1935 DRM_ERROR("Unknown connector type: %d\n",
1936 connector);
1937 continue;
1938 }
1939
1940 }
1941 } else {
1942 uint16_t tmds_info =
1943 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1944 if (tmds_info) {
1945 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
1946
1947 radeon_add_legacy_encoder(dev,
1948 radeon_get_encoder_id(dev,
1949 ATOM_DEVICE_CRT1_SUPPORT,
1950 1),
1951 ATOM_DEVICE_CRT1_SUPPORT);
1952 radeon_add_legacy_encoder(dev,
1953 radeon_get_encoder_id(dev,
1954 ATOM_DEVICE_DFP1_SUPPORT,
1955 0),
1956 ATOM_DEVICE_DFP1_SUPPORT);
1957
1958 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1959 radeon_add_legacy_connector(dev,
1960 0,
1961 ATOM_DEVICE_CRT1_SUPPORT |
1962 ATOM_DEVICE_DFP1_SUPPORT,
1963 DRM_MODE_CONNECTOR_DVII,
b75fad06
AD		 1964 &ddc_i2c,
1965 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
771fe6b9 1966 } else {
d0c403e9
AD		 1967 uint16_t crt_info =
1968 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1969 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
1970 if (crt_info) {
1971 radeon_add_legacy_encoder(dev,
1972 radeon_get_encoder_id(dev,
1973 ATOM_DEVICE_CRT1_SUPPORT,
1974 1),
1975 ATOM_DEVICE_CRT1_SUPPORT);
1976 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1977 radeon_add_legacy_connector(dev,
1978 0,
1979 ATOM_DEVICE_CRT1_SUPPORT,
1980 DRM_MODE_CONNECTOR_VGA,
b75fad06
AD		 1981 &ddc_i2c,
1982 CONNECTOR_OBJECT_ID_VGA);
d0c403e9
AD		 1983 } else {
1984 DRM_DEBUG("No connector info found\n");
1985 return false;
1986 }
771fe6b9
JG		 1987 }
1988 }
1989
1990 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
1991 uint16_t lcd_info =
1992 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1993 if (lcd_info) {
1994 uint16_t lcd_ddc_info =
1995 combios_get_table_offset(dev,
1996 COMBIOS_LCD_DDC_INFO_TABLE);
1997
1998 radeon_add_legacy_encoder(dev,
1999 radeon_get_encoder_id(dev,
2000 ATOM_DEVICE_LCD1_SUPPORT,
2001 0),
2002 ATOM_DEVICE_LCD1_SUPPORT);
2003
2004 if (lcd_ddc_info) {
2005 ddc_type = RBIOS8(lcd_ddc_info + 2);
2006 switch (ddc_type) {
2007 case DDC_MONID:
2008 ddc_i2c =
2009 combios_setup_i2c_bus
2010 (RADEON_GPIO_MONID);
2011 break;
2012 case DDC_DVI:
2013 ddc_i2c =
2014 combios_setup_i2c_bus
2015 (RADEON_GPIO_DVI_DDC);
2016 break;
2017 case DDC_VGA:
2018 ddc_i2c =
2019 combios_setup_i2c_bus
2020 (RADEON_GPIO_VGA_DDC);
2021 break;
2022 case DDC_CRT2:
2023 ddc_i2c =
2024 combios_setup_i2c_bus
2025 (RADEON_GPIO_CRT2_DDC);
2026 break;
2027 case DDC_LCD:
2028 ddc_i2c =
2029 combios_setup_i2c_bus
2030 (RADEON_LCD_GPIO_MASK);
2031 ddc_i2c.mask_clk_mask =
2032 RBIOS32(lcd_ddc_info + 3);
2033 ddc_i2c.mask_data_mask =
2034 RBIOS32(lcd_ddc_info + 7);
2035 ddc_i2c.a_clk_mask =
2036 RBIOS32(lcd_ddc_info + 3);
2037 ddc_i2c.a_data_mask =
2038 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2039 ddc_i2c.en_clk_mask =
771fe6b9 2040 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2041 ddc_i2c.en_data_mask =
771fe6b9 2042 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2043 ddc_i2c.y_clk_mask =
771fe6b9 2044 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2045 ddc_i2c.y_data_mask =
771fe6b9
JG		 2046 RBIOS32(lcd_ddc_info + 7);
2047 break;
2048 case DDC_GPIO:
2049 ddc_i2c =
2050 combios_setup_i2c_bus
2051 (RADEON_MDGPIO_EN_REG);
2052 ddc_i2c.mask_clk_mask =
2053 RBIOS32(lcd_ddc_info + 3);
2054 ddc_i2c.mask_data_mask =
2055 RBIOS32(lcd_ddc_info + 7);
2056 ddc_i2c.a_clk_mask =
2057 RBIOS32(lcd_ddc_info + 3);
2058 ddc_i2c.a_data_mask =
2059 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2060 ddc_i2c.en_clk_mask =
771fe6b9 2061 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2062 ddc_i2c.en_data_mask =
771fe6b9 2063 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2064 ddc_i2c.y_clk_mask =
771fe6b9 2065 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2066 ddc_i2c.y_data_mask =
771fe6b9
JG		 2067 RBIOS32(lcd_ddc_info + 7);
2068 break;
2069 default:
2070 ddc_i2c.valid = false;
2071 break;
2072 }
2073 DRM_DEBUG("LCD DDC Info Table found!\n");
2074 } else
2075 ddc_i2c.valid = false;
2076
2077 radeon_add_legacy_connector(dev,
2078 5,
2079 ATOM_DEVICE_LCD1_SUPPORT,
2080 DRM_MODE_CONNECTOR_LVDS,
b75fad06
AD		 2081 &ddc_i2c,
2082 CONNECTOR_OBJECT_ID_LVDS);
771fe6b9
JG		 2083 }
2084 }
2085
2086 /* check TV table */
2087 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2088 uint32_t tv_info =
2089 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2090 if (tv_info) {
2091 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34
AD		 2092 if (radeon_apply_legacy_tv_quirks(dev)) {
2093 radeon_add_legacy_encoder(dev,
2094 radeon_get_encoder_id
2095 (dev,
2096 ATOM_DEVICE_TV1_SUPPORT,
2097 2),
2098 ATOM_DEVICE_TV1_SUPPORT);
2099 radeon_add_legacy_connector(dev, 6,
2100 ATOM_DEVICE_TV1_SUPPORT,
2101 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06
AD		 2102 &ddc_i2c,
2103 CONNECTOR_OBJECT_ID_SVIDEO);
790cfb34 2104 }
771fe6b9
JG		 2105 }
2106 }
2107 }
2108
2109 radeon_link_encoder_connector(dev);
2110
2111 return true;
2112}
2113
fcec570b
AD		 2114void radeon_external_tmds_setup(struct drm_encoder *encoder)
2115{
2116 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2117 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2118
2119 if (!tmds)
2120 return;
2121
2122 switch (tmds->dvo_chip) {
2123 case DVO_SIL164:
2124 /* sil 164 */
2125 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2126 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2127 tmds->slave_addr,
2128 0x08, 0x30);
2129 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2130 tmds->slave_addr,
2131 0x09, 0x00);
2132 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2133 tmds->slave_addr,
2134 0x0a, 0x90);
2135 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2136 tmds->slave_addr,
2137 0x0c, 0x89);
2138 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2139 tmds->slave_addr,
2140 0x08, 0x3b);
2141 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2142 break;
2143 case DVO_SIL1178:
2144 /* sil 1178 - untested */
2145 /*
2146 * 0x0f, 0x44
2147 * 0x0f, 0x4c
2148 * 0x0e, 0x01
2149 * 0x0a, 0x80
2150 * 0x09, 0x30
2151 * 0x0c, 0xc9
2152 * 0x0d, 0x70
2153 * 0x08, 0x32
2154 * 0x08, 0x33
2155 */
2156 break;
2157 default:
2158 break;
2159 }
2160
2161}
2162
2163bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2164{
2165 struct drm_device *dev = encoder->dev;
2166 struct radeon_device *rdev = dev->dev_private;
2167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2168 uint16_t offset;
2169 uint8_t blocks, slave_addr, rev;
2170 uint32_t index, id;
2171 uint32_t reg, val, and_mask, or_mask;
2172 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2173
2174 if (rdev->bios == NULL)
2175 return false;
2176
2177 if (!tmds)
2178 return false;
2179
2180 if (rdev->flags & RADEON_IS_IGP) {
2181 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2182 rev = RBIOS8(offset);
2183 if (offset) {
2184 rev = RBIOS8(offset);
2185 if (rev > 1) {
2186 blocks = RBIOS8(offset + 3);
2187 index = offset + 4;
2188 while (blocks > 0) {
2189 id = RBIOS16(index);
2190 index += 2;
2191 switch (id >> 13) {
2192 case 0:
2193 reg = (id & 0x1fff) * 4;
2194 val = RBIOS32(index);
2195 index += 4;
2196 WREG32(reg, val);
2197 break;
2198 case 2:
2199 reg = (id & 0x1fff) * 4;
2200 and_mask = RBIOS32(index);
2201 index += 4;
2202 or_mask = RBIOS32(index);
2203 index += 4;
2204 val = RREG32(reg);
2205 val = (val & and_mask) | or_mask;
2206 WREG32(reg, val);
2207 break;
2208 case 3:
2209 val = RBIOS16(index);
2210 index += 2;
2211 udelay(val);
2212 break;
2213 case 4:
2214 val = RBIOS16(index);
2215 index += 2;
2216 udelay(val * 1000);
2217 break;
2218 case 6:
2219 slave_addr = id & 0xff;
2220 slave_addr >>= 1; /* 7 bit addressing */
2221 index++;
2222 reg = RBIOS8(index);
2223 index++;
2224 val = RBIOS8(index);
2225 index++;
2226 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2227 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2228 slave_addr,
2229 reg, val);
2230 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2231 break;
2232 default:
2233 DRM_ERROR("Unknown id %d\n", id >> 13);
2234 break;
2235 }
2236 blocks--;
2237 }
2238 return true;
2239 }
2240 }
2241 } else {
2242 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2243 if (offset) {
2244 index = offset + 10;
2245 id = RBIOS16(index);
2246 while (id != 0xffff) {
2247 index += 2;
2248 switch (id >> 13) {
2249 case 0:
2250 reg = (id & 0x1fff) * 4;
2251 val = RBIOS32(index);
2252 WREG32(reg, val);
2253 break;
2254 case 2:
2255 reg = (id & 0x1fff) * 4;
2256 and_mask = RBIOS32(index);
2257 index += 4;
2258 or_mask = RBIOS32(index);
2259 index += 4;
2260 val = RREG32(reg);
2261 val = (val & and_mask) | or_mask;
2262 WREG32(reg, val);
2263 break;
2264 case 4:
2265 val = RBIOS16(index);
2266 index += 2;
2267 udelay(val);
2268 break;
2269 case 5:
2270 reg = id & 0x1fff;
2271 and_mask = RBIOS32(index);
2272 index += 4;
2273 or_mask = RBIOS32(index);
2274 index += 4;
2275 val = RREG32_PLL(reg);
2276 val = (val & and_mask) | or_mask;
2277 WREG32_PLL(reg, val);
2278 break;
2279 case 6:
2280 reg = id & 0x1fff;
2281 val = RBIOS8(index);
2282 index += 1;
2283 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2284 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2285 tmds->slave_addr,
2286 reg, val);
2287 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2288 break;
2289 default:
2290 DRM_ERROR("Unknown id %d\n", id >> 13);
2291 break;
2292 }
2293 id = RBIOS16(index);
2294 }
2295 return true;
2296 }
2297 }
2298 return false;
2299}
2300
771fe6b9
JG		 2301static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2302{
2303 struct radeon_device *rdev = dev->dev_private;
2304
2305 if (offset) {
2306 while (RBIOS16(offset)) {
2307 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2308 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2309 uint32_t val, and_mask, or_mask;
2310 uint32_t tmp;
2311
2312 offset += 2;
2313 switch (cmd) {
2314 case 0:
2315 val = RBIOS32(offset);
2316 offset += 4;
2317 WREG32(addr, val);
2318 break;
2319 case 1:
2320 val = RBIOS32(offset);
2321 offset += 4;
2322 WREG32(addr, val);
2323 break;
2324 case 2:
2325 and_mask = RBIOS32(offset);
2326 offset += 4;
2327 or_mask = RBIOS32(offset);
2328 offset += 4;
2329 tmp = RREG32(addr);
2330 tmp &= and_mask;
2331 tmp |= or_mask;
2332 WREG32(addr, tmp);
2333 break;
2334 case 3:
2335 and_mask = RBIOS32(offset);
2336 offset += 4;
2337 or_mask = RBIOS32(offset);
2338 offset += 4;
2339 tmp = RREG32(addr);
2340 tmp &= and_mask;
2341 tmp |= or_mask;
2342 WREG32(addr, tmp);
2343 break;
2344 case 4:
2345 val = RBIOS16(offset);
2346 offset += 2;
2347 udelay(val);
2348 break;
2349 case 5:
2350 val = RBIOS16(offset);
2351 offset += 2;
2352 switch (addr) {
2353 case 8:
2354 while (val--) {
2355 if (!
2356 (RREG32_PLL
2357 (RADEON_CLK_PWRMGT_CNTL) &
2358 RADEON_MC_BUSY))
2359 break;
2360 }
2361 break;
2362 case 9:
2363 while (val--) {
2364 if ((RREG32(RADEON_MC_STATUS) &
2365 RADEON_MC_IDLE))
2366 break;
2367 }
2368 break;
2369 default:
2370 break;
2371 }
2372 break;
2373 default:
2374 break;
2375 }
2376 }
2377 }
2378}
2379
2380static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2381{
2382 struct radeon_device *rdev = dev->dev_private;
2383
2384 if (offset) {
2385 while (RBIOS8(offset)) {
2386 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2387 uint8_t addr = (RBIOS8(offset) & 0x3f);
2388 uint32_t val, shift, tmp;
2389 uint32_t and_mask, or_mask;
2390
2391 offset++;
2392 switch (cmd) {
2393 case 0:
2394 val = RBIOS32(offset);
2395 offset += 4;
2396 WREG32_PLL(addr, val);
2397 break;
2398 case 1:
2399 shift = RBIOS8(offset) * 8;
2400 offset++;
2401 and_mask = RBIOS8(offset) << shift;
2402 and_mask |= ~(0xff << shift);
2403 offset++;
2404 or_mask = RBIOS8(offset) << shift;
2405 offset++;
2406 tmp = RREG32_PLL(addr);
2407 tmp &= and_mask;
2408 tmp |= or_mask;
2409 WREG32_PLL(addr, tmp);
2410 break;
2411 case 2:
2412 case 3:
2413 tmp = 1000;
2414 switch (addr) {
2415 case 1:
2416 udelay(150);
2417 break;
2418 case 2:
2419 udelay(1000);
2420 break;
2421 case 3:
2422 while (tmp--) {
2423 if (!
2424 (RREG32_PLL
2425 (RADEON_CLK_PWRMGT_CNTL) &
2426 RADEON_MC_BUSY))
2427 break;
2428 }
2429 break;
2430 case 4:
2431 while (tmp--) {
2432 if (RREG32_PLL
2433 (RADEON_CLK_PWRMGT_CNTL) &
2434 RADEON_DLL_READY)
2435 break;
2436 }
2437 break;
2438 case 5:
2439 tmp =
2440 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2441 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2442#if 0
2443 uint32_t mclk_cntl =
2444 RREG32_PLL
2445 (RADEON_MCLK_CNTL);
2446 mclk_cntl &= 0xffff0000;
2447 /*mclk_cntl |= 0x00001111;*//* ??? */
2448 WREG32_PLL(RADEON_MCLK_CNTL,
2449 mclk_cntl);
2450 udelay(10000);
2451#endif
2452 WREG32_PLL
2453 (RADEON_CLK_PWRMGT_CNTL,
2454 tmp &
2455 ~RADEON_CG_NO1_DEBUG_0);
2456 udelay(10000);
2457 }
2458 break;
2459 default:
2460 break;
2461 }
2462 break;
2463 default:
2464 break;
2465 }
2466 }
2467 }
2468}
2469
2470static void combios_parse_ram_reset_table(struct drm_device *dev,
2471 uint16_t offset)
2472{
2473 struct radeon_device *rdev = dev->dev_private;
2474 uint32_t tmp;
2475
2476 if (offset) {
2477 uint8_t val = RBIOS8(offset);
2478 while (val != 0xff) {
2479 offset++;
2480
2481 if (val == 0x0f) {
2482 uint32_t channel_complete_mask;
2483
2484 if (ASIC_IS_R300(rdev))
2485 channel_complete_mask =
2486 R300_MEM_PWRUP_COMPLETE;
2487 else
2488 channel_complete_mask =
2489 RADEON_MEM_PWRUP_COMPLETE;
2490 tmp = 20000;
2491 while (tmp--) {
2492 if ((RREG32(RADEON_MEM_STR_CNTL) &
2493 channel_complete_mask) ==
2494 channel_complete_mask)
2495 break;
2496 }
2497 } else {
2498 uint32_t or_mask = RBIOS16(offset);
2499 offset += 2;
2500
2501 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2502 tmp &= RADEON_SDRAM_MODE_MASK;
2503 tmp |= or_mask;
2504 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2505
2506 or_mask = val << 24;
2507 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2508 tmp &= RADEON_B3MEM_RESET_MASK;
2509 tmp |= or_mask;
2510 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2511 }
2512 val = RBIOS8(offset);
2513 }
2514 }
2515}
2516
2517static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2518 int mem_addr_mapping)
2519{
2520 struct radeon_device *rdev = dev->dev_private;
2521 uint32_t mem_cntl;
2522 uint32_t mem_size;
2523 uint32_t addr = 0;
2524
2525 mem_cntl = RREG32(RADEON_MEM_CNTL);
2526 if (mem_cntl & RV100_HALF_MODE)
2527 ram /= 2;
2528 mem_size = ram;
2529 mem_cntl &= ~(0xff << 8);
2530 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2531 WREG32(RADEON_MEM_CNTL, mem_cntl);
2532 RREG32(RADEON_MEM_CNTL);
2533
2534 /* sdram reset ? */
2535
2536 /* something like this???? */
2537 while (ram--) {
2538 addr = ram * 1024 * 1024;
2539 /* write to each page */
2540 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2541 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2542 /* read back and verify */
2543 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2544 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2545 return 0;
2546 }
2547
2548 return mem_size;
2549}
2550
2551static void combios_write_ram_size(struct drm_device *dev)
2552{
2553 struct radeon_device *rdev = dev->dev_private;
2554 uint8_t rev;
2555 uint16_t offset;
2556 uint32_t mem_size = 0;
2557 uint32_t mem_cntl = 0;
2558
2559 /* should do something smarter here I guess... */
2560 if (rdev->flags & RADEON_IS_IGP)
2561 return;
2562
2563 /* first check detected mem table */
2564 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2565 if (offset) {
2566 rev = RBIOS8(offset);
2567 if (rev < 3) {
2568 mem_cntl = RBIOS32(offset + 1);
2569 mem_size = RBIOS16(offset + 5);
2570 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2571 ((dev->pdev->device != 0x515e)
2572 && (dev->pdev->device != 0x5969)))
2573 WREG32(RADEON_MEM_CNTL, mem_cntl);
2574 }
2575 }
2576
2577 if (!mem_size) {
2578 offset =
2579 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2580 if (offset) {
2581 rev = RBIOS8(offset - 1);
2582 if (rev < 1) {
2583 if (((rdev->flags & RADEON_FAMILY_MASK) <
2584 CHIP_R200)
2585 && ((dev->pdev->device != 0x515e)
2586 && (dev->pdev->device != 0x5969))) {
2587 int ram = 0;
2588 int mem_addr_mapping = 0;
2589
2590 while (RBIOS8(offset)) {
2591 ram = RBIOS8(offset);
2592 mem_addr_mapping =
2593 RBIOS8(offset + 1);
2594 if (mem_addr_mapping != 0x25)
2595 ram *= 2;
2596 mem_size =
2597 combios_detect_ram(dev, ram,
2598 mem_addr_mapping);
2599 if (mem_size)
2600 break;
2601 offset += 2;
2602 }
2603 } else
2604 mem_size = RBIOS8(offset);
2605 } else {
2606 mem_size = RBIOS8(offset);
2607 mem_size *= 2; /* convert to MB */
2608 }
2609 }
2610 }
2611
2612 mem_size *= (1024 * 1024); /* convert to bytes */
2613 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2614}
2615
2616void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2617{
2618 uint16_t dyn_clk_info =
2619 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2620
2621 if (dyn_clk_info)
2622 combios_parse_pll_table(dev, dyn_clk_info);
2623}
2624
2625void radeon_combios_asic_init(struct drm_device *dev)
2626{
2627 struct radeon_device *rdev = dev->dev_private;
2628 uint16_t table;
2629
2630 /* port hardcoded mac stuff from radeonfb */
2631 if (rdev->bios == NULL)
2632 return;
2633
2634 /* ASIC INIT 1 */
2635 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2636 if (table)
2637 combios_parse_mmio_table(dev, table);
2638
2639 /* PLL INIT */
2640 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2641 if (table)
2642 combios_parse_pll_table(dev, table);
2643
2644 /* ASIC INIT 2 */
2645 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2646 if (table)
2647 combios_parse_mmio_table(dev, table);
2648
2649 if (!(rdev->flags & RADEON_IS_IGP)) {
2650 /* ASIC INIT 4 */
2651 table =
2652 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2653 if (table)
2654 combios_parse_mmio_table(dev, table);
2655
2656 /* RAM RESET */
2657 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2658 if (table)
2659 combios_parse_ram_reset_table(dev, table);
2660
2661 /* ASIC INIT 3 */
2662 table =
2663 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2664 if (table)
2665 combios_parse_mmio_table(dev, table);
2666
2667 /* write CONFIG_MEMSIZE */
2668 combios_write_ram_size(dev);
2669 }
2670
2671 /* DYN CLK 1 */
2672 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2673 if (table)
2674 combios_parse_pll_table(dev, table);
2675
2676}
2677
2678void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2679{
2680 struct radeon_device *rdev = dev->dev_private;
2681 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2682
2683 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2684 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2685 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2686
2687 /* let the bios control the backlight */
2688 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2689
2690 /* tell the bios not to handle mode switching */
2691 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2692 RADEON_ACC_MODE_CHANGE);
2693
2694 /* tell the bios a driver is loaded */
2695 bios_7_scratch |= RADEON_DRV_LOADED;
2696
2697 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2698 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2699 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2700}
2701
2702void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2703{
2704 struct drm_device *dev = encoder->dev;
2705 struct radeon_device *rdev = dev->dev_private;
2706 uint32_t bios_6_scratch;
2707
2708 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2709
2710 if (lock)
2711 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2712 else
2713 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2714
2715 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2716}
2717
2718void
2719radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2720 struct drm_encoder *encoder,
2721 bool connected)
2722{
2723 struct drm_device *dev = connector->dev;
2724 struct radeon_device *rdev = dev->dev_private;
2725 struct radeon_connector *radeon_connector =
2726 to_radeon_connector(connector);
2727 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2728 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2729 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2730
2731 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2732 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2733 if (connected) {
2734 DRM_DEBUG("TV1 connected\n");
2735 /* fix me */
2736 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2737 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2738 bios_5_scratch |= RADEON_TV1_ON;
2739 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2740 } else {
2741 DRM_DEBUG("TV1 disconnected\n");
2742 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2743 bios_5_scratch &= ~RADEON_TV1_ON;
2744 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2745 }
2746 }
2747 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2748 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2749 if (connected) {
2750 DRM_DEBUG("LCD1 connected\n");
2751 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2752 bios_5_scratch |= RADEON_LCD1_ON;
2753 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2754 } else {
2755 DRM_DEBUG("LCD1 disconnected\n");
2756 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2757 bios_5_scratch &= ~RADEON_LCD1_ON;
2758 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2759 }
2760 }
2761 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2762 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2763 if (connected) {
2764 DRM_DEBUG("CRT1 connected\n");
2765 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2766 bios_5_scratch |= RADEON_CRT1_ON;
2767 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2768 } else {
2769 DRM_DEBUG("CRT1 disconnected\n");
2770 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2771 bios_5_scratch &= ~RADEON_CRT1_ON;
2772 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2773 }
2774 }
2775 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2776 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2777 if (connected) {
2778 DRM_DEBUG("CRT2 connected\n");
2779 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2780 bios_5_scratch |= RADEON_CRT2_ON;
2781 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2782 } else {
2783 DRM_DEBUG("CRT2 disconnected\n");
2784 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2785 bios_5_scratch &= ~RADEON_CRT2_ON;
2786 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2787 }
2788 }
2789 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2790 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2791 if (connected) {
2792 DRM_DEBUG("DFP1 connected\n");
2793 bios_4_scratch |= RADEON_DFP1_ATTACHED;
2794 bios_5_scratch |= RADEON_DFP1_ON;
2795 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2796 } else {
2797 DRM_DEBUG("DFP1 disconnected\n");
2798 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2799 bios_5_scratch &= ~RADEON_DFP1_ON;
2800 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2801 }
2802 }
2803 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2804 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2805 if (connected) {
2806 DRM_DEBUG("DFP2 connected\n");
2807 bios_4_scratch |= RADEON_DFP2_ATTACHED;
2808 bios_5_scratch |= RADEON_DFP2_ON;
2809 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2810 } else {
2811 DRM_DEBUG("DFP2 disconnected\n");
2812 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2813 bios_5_scratch &= ~RADEON_DFP2_ON;
2814 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2815 }
2816 }
2817 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2818 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2819}
2820
2821void
2822radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2823{
2824 struct drm_device *dev = encoder->dev;
2825 struct radeon_device *rdev = dev->dev_private;
2826 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2827 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2828
2829 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2830 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2831 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2832 }
2833 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2834 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2835 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2836 }
2837 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2838 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2839 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2840 }
2841 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2842 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2843 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2844 }
2845 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2846 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2847 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2848 }
2849 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2850 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2851 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2852 }
2853 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2854}
2855
2856void
2857radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2858{
2859 struct drm_device *dev = encoder->dev;
2860 struct radeon_device *rdev = dev->dev_private;
2861 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2862 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2863
2864 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2865 if (on)
2866 bios_6_scratch |= RADEON_TV_DPMS_ON;
2867 else
2868 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2869 }
2870 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2871 if (on)
2872 bios_6_scratch |= RADEON_CRT_DPMS_ON;
2873 else
2874 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2875 }
2876 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2877 if (on)
2878 bios_6_scratch |= RADEON_LCD_DPMS_ON;
2879 else
2880 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
2881 }
2882 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
2883 if (on)
2884 bios_6_scratch |= RADEON_DFP_DPMS_ON;
2885 else
2886 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
2887 }
2888 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2889}
kernel source for telekom puls (alcatel/mediatek)