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drm/radeon/kms: IB locking dumps out a lockdep ordering issue
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info);
50
51/* from radeon_legacy_encoder.c */
52extern void
53radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
54 uint32_t supported_device);
55
56union atom_supported_devices {
57 struct _ATOM_SUPPORTED_DEVICES_INFO info;
58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
60};
61
62static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
63 *dev, uint8_t id)
64{
65 struct radeon_device *rdev = dev->dev_private;
66 struct atom_context *ctx = rdev->mode_info.atom_context;
67 ATOM_GPIO_I2C_ASSIGMENT gpio;
68 struct radeon_i2c_bus_rec i2c;
69 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
70 struct _ATOM_GPIO_I2C_INFO *i2c_info;
71 uint16_t data_offset;
72
73 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
74 i2c.valid = false;
75
76 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
77
78 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
79
80 gpio = i2c_info->asGPIO_Info[id];
81
82 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
83 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
84 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
85 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
86 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
87 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
88 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
89 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
90 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
91 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
92 i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
93 i2c.put_data_mask = (1 << gpio.ucDataEnShift);
94 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
95 i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
96 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
97 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
98 i2c.valid = true;
99
100 return i2c;
101}
102
103static bool radeon_atom_apply_quirks(struct drm_device *dev,
104 uint32_t supported_device,
105 int *connector_type,
848577ee 106 struct radeon_i2c_bus_rec *i2c_bus,
705af9c7 107 uint16_t *line_mux)
771fe6b9
JG		 108{
109
110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
111 if ((dev->pdev->device == 0x791e) &&
112 (dev->pdev->subsystem_vendor == 0x1043) &&
113 (dev->pdev->subsystem_device == 0x826d)) {
114 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
115 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
116 *connector_type = DRM_MODE_CONNECTOR_DVID;
117 }
118
119 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
120 if ((dev->pdev->device == 0x7941) &&
121 (dev->pdev->subsystem_vendor == 0x147b) &&
122 (dev->pdev->subsystem_device == 0x2412)) {
123 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
124 return false;
125 }
126
127 /* Falcon NW laptop lists vga ddc line for LVDS */
128 if ((dev->pdev->device == 0x5653) &&
129 (dev->pdev->subsystem_vendor == 0x1462) &&
130 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 131 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 132 i2c_bus->valid = false;
848577ee
AD		 133 *line_mux = 53;
134 }
771fe6b9
JG		 135 }
136
137 /* Funky macbooks */
138 if ((dev->pdev->device == 0x71C5) &&
139 (dev->pdev->subsystem_vendor == 0x106b) &&
140 (dev->pdev->subsystem_device == 0x0080)) {
141 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
142 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
143 return false;
144 }
145
771fe6b9
JG		 146 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
147 if ((dev->pdev->device == 0x9598) &&
148 (dev->pdev->subsystem_vendor == 0x1043) &&
149 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 150 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 151 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 152 }
153 }
154
155 /* ASUS HD 3450 board lists the DVI port as HDMI */
156 if ((dev->pdev->device == 0x95C5) &&
157 (dev->pdev->subsystem_vendor == 0x1043) &&
158 (dev->pdev->subsystem_device == 0x01e2)) {
159 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 160 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 161 }
162 }
163
705af9c7
AD		 164 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
165 * HDMI + VGA reporting as HDMI
166 */
167 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
168 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
169 *connector_type = DRM_MODE_CONNECTOR_VGA;
170 *line_mux = 0;
171 }
172 }
173
771fe6b9
JG		 174 return true;
175}
176
177const int supported_devices_connector_convert[] = {
178 DRM_MODE_CONNECTOR_Unknown,
179 DRM_MODE_CONNECTOR_VGA,
180 DRM_MODE_CONNECTOR_DVII,
181 DRM_MODE_CONNECTOR_DVID,
182 DRM_MODE_CONNECTOR_DVIA,
183 DRM_MODE_CONNECTOR_SVIDEO,
184 DRM_MODE_CONNECTOR_Composite,
185 DRM_MODE_CONNECTOR_LVDS,
186 DRM_MODE_CONNECTOR_Unknown,
187 DRM_MODE_CONNECTOR_Unknown,
188 DRM_MODE_CONNECTOR_HDMIA,
189 DRM_MODE_CONNECTOR_HDMIB,
190 DRM_MODE_CONNECTOR_Unknown,
191 DRM_MODE_CONNECTOR_Unknown,
192 DRM_MODE_CONNECTOR_9PinDIN,
193 DRM_MODE_CONNECTOR_DisplayPort
194};
195
196const int object_connector_convert[] = {
197 DRM_MODE_CONNECTOR_Unknown,
198 DRM_MODE_CONNECTOR_DVII,
199 DRM_MODE_CONNECTOR_DVII,
200 DRM_MODE_CONNECTOR_DVID,
201 DRM_MODE_CONNECTOR_DVID,
202 DRM_MODE_CONNECTOR_VGA,
203 DRM_MODE_CONNECTOR_Composite,
204 DRM_MODE_CONNECTOR_SVIDEO,
205 DRM_MODE_CONNECTOR_Unknown,
705af9c7 206 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 207 DRM_MODE_CONNECTOR_9PinDIN,
208 DRM_MODE_CONNECTOR_Unknown,
209 DRM_MODE_CONNECTOR_HDMIA,
210 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 211 DRM_MODE_CONNECTOR_LVDS,
212 DRM_MODE_CONNECTOR_9PinDIN,
213 DRM_MODE_CONNECTOR_Unknown,
214 DRM_MODE_CONNECTOR_Unknown,
215 DRM_MODE_CONNECTOR_Unknown,
216 DRM_MODE_CONNECTOR_DisplayPort
217};
218
219bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
220{
221 struct radeon_device *rdev = dev->dev_private;
222 struct radeon_mode_info *mode_info = &rdev->mode_info;
223 struct atom_context *ctx = mode_info->atom_context;
224 int index = GetIndexIntoMasterTable(DATA, Object_Header);
225 uint16_t size, data_offset;
226 uint8_t frev, crev, line_mux = 0;
227 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
228 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
229 ATOM_OBJECT_HEADER *obj_header;
230 int i, j, path_size, device_support;
231 int connector_type;
705af9c7 232 uint16_t igp_lane_info, conn_id;
771fe6b9
JG		 233 bool linkb;
234 struct radeon_i2c_bus_rec ddc_bus;
235
236 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
237
238 if (data_offset == 0)
239 return false;
240
241 if (crev < 2)
242 return false;
243
244 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
245 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
246 (ctx->bios + data_offset +
247 le16_to_cpu(obj_header->usDisplayPathTableOffset));
248 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
249 (ctx->bios + data_offset +
250 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
251 device_support = le16_to_cpu(obj_header->usDeviceSupport);
252
253 path_size = 0;
254 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
255 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
256 ATOM_DISPLAY_OBJECT_PATH *path;
257 addr += path_size;
258 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
259 path_size += le16_to_cpu(path->usSize);
260 linkb = false;
261
262 if (device_support & le16_to_cpu(path->usDeviceTag)) {
263 uint8_t con_obj_id, con_obj_num, con_obj_type;
264
265 con_obj_id =
266 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
267 >> OBJECT_ID_SHIFT;
268 con_obj_num =
269 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
270 >> ENUM_ID_SHIFT;
271 con_obj_type =
272 (le16_to_cpu(path->usConnObjectId) &
273 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
274
275 if ((le16_to_cpu(path->usDeviceTag) ==
276 ATOM_DEVICE_TV1_SUPPORT)
277 || (le16_to_cpu(path->usDeviceTag) ==
278 ATOM_DEVICE_TV2_SUPPORT)
279 || (le16_to_cpu(path->usDeviceTag) ==
280 ATOM_DEVICE_CV_SUPPORT))
281 continue;
282
283 if ((rdev->family == CHIP_RS780) &&
284 (con_obj_id ==
285 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
286 uint16_t igp_offset = 0;
287 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
288
289 index =
290 GetIndexIntoMasterTable(DATA,
291 IntegratedSystemInfo);
292
293 atom_parse_data_header(ctx, index, &size, &frev,
294 &crev, &igp_offset);
295
296 if (crev >= 2) {
297 igp_obj =
298 (ATOM_INTEGRATED_SYSTEM_INFO_V2
299 *) (ctx->bios + igp_offset);
300
301 if (igp_obj) {
302 uint32_t slot_config, ct;
303
304 if (con_obj_num == 1)
305 slot_config =
306 igp_obj->
307 ulDDISlot1Config;
308 else
309 slot_config =
310 igp_obj->
311 ulDDISlot2Config;
312
313 ct = (slot_config >> 16) & 0xff;
314 connector_type =
315 object_connector_convert
316 [ct];
317 igp_lane_info =
318 slot_config & 0xffff;
319 } else
320 continue;
321 } else
322 continue;
323 } else {
324 igp_lane_info = 0;
325 connector_type =
326 object_connector_convert[con_obj_id];
327 }
328
329 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
330 continue;
331
332 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
333 j++) {
334 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
335
336 enc_obj_id =
337 (le16_to_cpu(path->usGraphicObjIds[j]) &
338 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
339 enc_obj_num =
340 (le16_to_cpu(path->usGraphicObjIds[j]) &
341 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
342 enc_obj_type =
343 (le16_to_cpu(path->usGraphicObjIds[j]) &
344 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
345
346 /* FIXME: add support for router objects */
347 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
348 if (enc_obj_num == 2)
349 linkb = true;
350 else
351 linkb = false;
352
353 radeon_add_atom_encoder(dev,
354 enc_obj_id,
355 le16_to_cpu
356 (path->
357 usDeviceTag));
358
359 }
360 }
361
362 /* look up gpio for ddc */
363 if ((le16_to_cpu(path->usDeviceTag) &
364 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
365 == 0) {
366 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
367 if (le16_to_cpu(path->usConnObjectId) ==
368 le16_to_cpu(con_obj->asObjects[j].
369 usObjectID)) {
370 ATOM_COMMON_RECORD_HEADER
371 *record =
372 (ATOM_COMMON_RECORD_HEADER
373 *)
374 (ctx->bios + data_offset +
375 le16_to_cpu(con_obj->
376 asObjects[j].
377 usRecordOffset));
378 ATOM_I2C_RECORD *i2c_record;
379
380 while (record->ucRecordType > 0
381 && record->
382 ucRecordType <=
383 ATOM_MAX_OBJECT_RECORD_NUMBER) {
771fe6b9
JG		 384 switch (record->
385 ucRecordType) {
386 case ATOM_I2C_RECORD_TYPE:
387 i2c_record =
388 (ATOM_I2C_RECORD
389 *) record;
390 line_mux =
391 i2c_record->
392 sucI2cId.
393 bfI2C_LineMux;
394 break;
395 }
396 record =
397 (ATOM_COMMON_RECORD_HEADER
398 *) ((char *)record
399 +
400 record->
401 ucRecordSize);
402 }
403 break;
404 }
405 }
406 } else
407 line_mux = 0;
408
409 if ((le16_to_cpu(path->usDeviceTag) ==
410 ATOM_DEVICE_TV1_SUPPORT)
411 || (le16_to_cpu(path->usDeviceTag) ==
412 ATOM_DEVICE_TV2_SUPPORT)
413 || (le16_to_cpu(path->usDeviceTag) ==
414 ATOM_DEVICE_CV_SUPPORT))
415 ddc_bus.valid = false;
416 else
417 ddc_bus = radeon_lookup_gpio(dev, line_mux);
418
705af9c7
AD		 419 conn_id = le16_to_cpu(path->usConnObjectId);
420
421 if (!radeon_atom_apply_quirks
422 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
423 &ddc_bus, &conn_id))
424 continue;
425
771fe6b9 426 radeon_add_atom_connector(dev,
705af9c7 427 conn_id,
771fe6b9
JG		 428 le16_to_cpu(path->
429 usDeviceTag),
430 connector_type, &ddc_bus,
431 linkb, igp_lane_info);
432
433 }
434 }
435
436 radeon_link_encoder_connector(dev);
437
438 return true;
439}
440
441struct bios_connector {
442 bool valid;
705af9c7 443 uint16_t line_mux;
771fe6b9
JG		 444 uint16_t devices;
445 int connector_type;
446 struct radeon_i2c_bus_rec ddc_bus;
447};
448
449bool radeon_get_atom_connector_info_from_supported_devices_table(struct
450 drm_device
451 *dev)
452{
453 struct radeon_device *rdev = dev->dev_private;
454 struct radeon_mode_info *mode_info = &rdev->mode_info;
455 struct atom_context *ctx = mode_info->atom_context;
456 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
457 uint16_t size, data_offset;
458 uint8_t frev, crev;
459 uint16_t device_support;
460 uint8_t dac;
461 union atom_supported_devices *supported_devices;
462 int i, j;
463 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
464
465 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
466
467 supported_devices =
468 (union atom_supported_devices *)(ctx->bios + data_offset);
469
470 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
471
472 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
473 ATOM_CONNECTOR_INFO_I2C ci =
474 supported_devices->info.asConnInfo[i];
475
476 bios_connectors[i].valid = false;
477
478 if (!(device_support & (1 << i))) {
479 continue;
480 }
481
482 if (i == ATOM_DEVICE_CV_INDEX) {
483 DRM_DEBUG("Skipping Component Video\n");
484 continue;
485 }
486
771fe6b9
JG		 487 bios_connectors[i].connector_type =
488 supported_devices_connector_convert[ci.sucConnectorInfo.
489 sbfAccess.
490 bfConnectorType];
491
492 if (bios_connectors[i].connector_type ==
493 DRM_MODE_CONNECTOR_Unknown)
494 continue;
495
496 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
497
498 if ((rdev->family == CHIP_RS690) ||
499 (rdev->family == CHIP_RS740)) {
500 if ((i == ATOM_DEVICE_DFP2_INDEX)
501 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
502 bios_connectors[i].line_mux =
503 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
504 else if ((i == ATOM_DEVICE_DFP3_INDEX)
505 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
506 bios_connectors[i].line_mux =
507 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
508 else
509 bios_connectors[i].line_mux =
510 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
511 } else
512 bios_connectors[i].line_mux =
513 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
514
515 /* give tv unique connector ids */
516 if (i == ATOM_DEVICE_TV1_INDEX) {
517 bios_connectors[i].ddc_bus.valid = false;
518 bios_connectors[i].line_mux = 50;
519 } else if (i == ATOM_DEVICE_TV2_INDEX) {
520 bios_connectors[i].ddc_bus.valid = false;
521 bios_connectors[i].line_mux = 51;
522 } else if (i == ATOM_DEVICE_CV_INDEX) {
523 bios_connectors[i].ddc_bus.valid = false;
524 bios_connectors[i].line_mux = 52;
525 } else
526 bios_connectors[i].ddc_bus =
527 radeon_lookup_gpio(dev,
528 bios_connectors[i].line_mux);
529
530 /* Always set the connector type to VGA for CRT1/CRT2. if they are
531 * shared with a DVI port, we'll pick up the DVI connector when we
532 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
533 */
534 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
535 bios_connectors[i].connector_type =
536 DRM_MODE_CONNECTOR_VGA;
537
538 if (!radeon_atom_apply_quirks
539 (dev, (1 << i), &bios_connectors[i].connector_type,
848577ee 540 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
771fe6b9
JG		 541 continue;
542
543 bios_connectors[i].valid = true;
544 bios_connectors[i].devices = (1 << i);
545
546 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
547 radeon_add_atom_encoder(dev,
548 radeon_get_encoder_id(dev,
549 (1 << i),
550 dac),
551 (1 << i));
552 else
553 radeon_add_legacy_encoder(dev,
554 radeon_get_encoder_id(dev,
555 (1 <<
556 i),
557 dac),
558 (1 << i));
559 }
560
561 /* combine shared connectors */
562 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
563 if (bios_connectors[i].valid) {
564 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
565 if (bios_connectors[j].valid && (i != j)) {
566 if (bios_connectors[i].line_mux ==
567 bios_connectors[j].line_mux) {
568 if (((bios_connectors[i].
569 devices &
570 (ATOM_DEVICE_DFP_SUPPORT))
571 && (bios_connectors[j].
572 devices &
573 (ATOM_DEVICE_CRT_SUPPORT)))
574 ||
575 ((bios_connectors[j].
576 devices &
577 (ATOM_DEVICE_DFP_SUPPORT))
578 && (bios_connectors[i].
579 devices &
580 (ATOM_DEVICE_CRT_SUPPORT)))) {
581 bios_connectors[i].
582 devices |=
583 bios_connectors[j].
584 devices;
585 bios_connectors[i].
586 connector_type =
587 DRM_MODE_CONNECTOR_DVII;
588 bios_connectors[j].
589 valid = false;
590 }
591 }
592 }
593 }
594 }
595 }
596
597 /* add the connectors */
598 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
599 if (bios_connectors[i].valid)
600 radeon_add_atom_connector(dev,
601 bios_connectors[i].line_mux,
602 bios_connectors[i].devices,
603 bios_connectors[i].
604 connector_type,
605 &bios_connectors[i].ddc_bus,
606 false, 0);
607 }
608
609 radeon_link_encoder_connector(dev);
610
611 return true;
612}
613
614union firmware_info {
615 ATOM_FIRMWARE_INFO info;
616 ATOM_FIRMWARE_INFO_V1_2 info_12;
617 ATOM_FIRMWARE_INFO_V1_3 info_13;
618 ATOM_FIRMWARE_INFO_V1_4 info_14;
619};
620
621bool radeon_atom_get_clock_info(struct drm_device *dev)
622{
623 struct radeon_device *rdev = dev->dev_private;
624 struct radeon_mode_info *mode_info = &rdev->mode_info;
625 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
626 union firmware_info *firmware_info;
627 uint8_t frev, crev;
628 struct radeon_pll *p1pll = &rdev->clock.p1pll;
629 struct radeon_pll *p2pll = &rdev->clock.p2pll;
630 struct radeon_pll *spll = &rdev->clock.spll;
631 struct radeon_pll *mpll = &rdev->clock.mpll;
632 uint16_t data_offset;
633
634 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
635 &crev, &data_offset);
636
637 firmware_info =
638 (union firmware_info *)(mode_info->atom_context->bios +
639 data_offset);
640
641 if (firmware_info) {
642 /* pixel clocks */
643 p1pll->reference_freq =
644 le16_to_cpu(firmware_info->info.usReferenceClock);
645 p1pll->reference_div = 0;
646
647 p1pll->pll_out_min =
648 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
649 p1pll->pll_out_max =
650 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
651
652 if (p1pll->pll_out_min == 0) {
653 if (ASIC_IS_AVIVO(rdev))
654 p1pll->pll_out_min = 64800;
655 else
656 p1pll->pll_out_min = 20000;
657 }
658
659 p1pll->pll_in_min =
660 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
661 p1pll->pll_in_max =
662 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
663
664 *p2pll = *p1pll;
665
666 /* system clock */
667 spll->reference_freq =
668 le16_to_cpu(firmware_info->info.usReferenceClock);
669 spll->reference_div = 0;
670
671 spll->pll_out_min =
672 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
673 spll->pll_out_max =
674 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
675
676 /* ??? */
677 if (spll->pll_out_min == 0) {
678 if (ASIC_IS_AVIVO(rdev))
679 spll->pll_out_min = 64800;
680 else
681 spll->pll_out_min = 20000;
682 }
683
684 spll->pll_in_min =
685 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
686 spll->pll_in_max =
687 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
688
689 /* memory clock */
690 mpll->reference_freq =
691 le16_to_cpu(firmware_info->info.usReferenceClock);
692 mpll->reference_div = 0;
693
694 mpll->pll_out_min =
695 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
696 mpll->pll_out_max =
697 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
698
699 /* ??? */
700 if (mpll->pll_out_min == 0) {
701 if (ASIC_IS_AVIVO(rdev))
702 mpll->pll_out_min = 64800;
703 else
704 mpll->pll_out_min = 20000;
705 }
706
707 mpll->pll_in_min =
708 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
709 mpll->pll_in_max =
710 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
711
712 rdev->clock.default_sclk =
713 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
714 rdev->clock.default_mclk =
715 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
716
717 return true;
718 }
719 return false;
720}
721
722struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
723 radeon_encoder
724 *encoder)
725{
726 struct drm_device *dev = encoder->base.dev;
727 struct radeon_device *rdev = dev->dev_private;
728 struct radeon_mode_info *mode_info = &rdev->mode_info;
729 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
730 uint16_t data_offset;
731 struct _ATOM_TMDS_INFO *tmds_info;
732 uint8_t frev, crev;
733 uint16_t maxfreq;
734 int i;
735 struct radeon_encoder_int_tmds *tmds = NULL;
736
737 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
738 &crev, &data_offset);
739
740 tmds_info =
741 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
742 data_offset);
743
744 if (tmds_info) {
745 tmds =
746 kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
747
748 if (!tmds)
749 return NULL;
750
751 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
752 for (i = 0; i < 4; i++) {
753 tmds->tmds_pll[i].freq =
754 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
755 tmds->tmds_pll[i].value =
756 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
757 tmds->tmds_pll[i].value |=
758 (tmds_info->asMiscInfo[i].
759 ucPLL_VCO_Gain & 0x3f) << 6;
760 tmds->tmds_pll[i].value |=
761 (tmds_info->asMiscInfo[i].
762 ucPLL_DutyCycle & 0xf) << 12;
763 tmds->tmds_pll[i].value |=
764 (tmds_info->asMiscInfo[i].
765 ucPLL_VoltageSwing & 0xf) << 16;
766
767 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
768 tmds->tmds_pll[i].freq,
769 tmds->tmds_pll[i].value);
770
771 if (maxfreq == tmds->tmds_pll[i].freq) {
772 tmds->tmds_pll[i].freq = 0xffffffff;
773 break;
774 }
775 }
776 }
777 return tmds;
778}
779
780union lvds_info {
781 struct _ATOM_LVDS_INFO info;
782 struct _ATOM_LVDS_INFO_V12 info_12;
783};
784
785struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
786 radeon_encoder
787 *encoder)
788{
789 struct drm_device *dev = encoder->base.dev;
790 struct radeon_device *rdev = dev->dev_private;
791 struct radeon_mode_info *mode_info = &rdev->mode_info;
792 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
793 uint16_t data_offset;
794 union lvds_info *lvds_info;
795 uint8_t frev, crev;
796 struct radeon_encoder_atom_dig *lvds = NULL;
797
798 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
799 &crev, &data_offset);
800
801 lvds_info =
802 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
803
804 if (lvds_info) {
805 lvds =
806 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
807
808 if (!lvds)
809 return NULL;
810
811 lvds->native_mode.dotclock =
812 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
813 lvds->native_mode.panel_xres =
814 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
815 lvds->native_mode.panel_yres =
816 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
817 lvds->native_mode.hblank =
818 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
819 lvds->native_mode.hoverplus =
820 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
821 lvds->native_mode.hsync_width =
822 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
823 lvds->native_mode.vblank =
824 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
825 lvds->native_mode.voverplus =
826 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
827 lvds->native_mode.vsync_width =
828 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
829 lvds->panel_pwr_delay =
830 le16_to_cpu(lvds_info->info.usOffDelayInMs);
831 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
832
833 encoder->native_mode = lvds->native_mode;
834 }
835 return lvds;
836}
837
6fe7ac3f
AD		 838struct radeon_encoder_primary_dac *
839radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
840{
841 struct drm_device *dev = encoder->base.dev;
842 struct radeon_device *rdev = dev->dev_private;
843 struct radeon_mode_info *mode_info = &rdev->mode_info;
844 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
845 uint16_t data_offset;
846 struct _COMPASSIONATE_DATA *dac_info;
847 uint8_t frev, crev;
848 uint8_t bg, dac;
6fe7ac3f
AD		 849 struct radeon_encoder_primary_dac *p_dac = NULL;
850
851 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
852
853 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
854
855 if (dac_info) {
856 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
857
858 if (!p_dac)
859 return NULL;
860
861 bg = dac_info->ucDAC1_BG_Adjustment;
862 dac = dac_info->ucDAC1_DAC_Adjustment;
863 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
864
865 }
866 return p_dac;
867}
868
4ce001ab
DA		 869bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
870 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
871 int32_t *pixel_clock)
872{
873 struct radeon_mode_info *mode_info = &rdev->mode_info;
874 ATOM_ANALOG_TV_INFO *tv_info;
875 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
876 ATOM_DTD_FORMAT *dtd_timings;
877 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
878 u8 frev, crev;
879 uint16_t data_offset;
880
881 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
882
883 switch (crev) {
884 case 1:
885 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
886 if (index > MAX_SUPPORTED_TV_TIMING)
887 return false;
888
889 crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
890 crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
891 crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
892 crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
893
894 crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
895 crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
896 crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
897 crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
898
899 crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
900
901 crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
902 crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
903 crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
904 crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
905 *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
906
907 if (index == 1) {
908 /* PAL timings appear to have wrong values for totals */
909 crtc_timing->usH_Total -= 1;
910 crtc_timing->usV_Total -= 1;
911 }
912 break;
913 case 2:
914 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
915 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
916 return false;
917
918 dtd_timings = &tv_info_v1_2->aModeTimings[index];
919 crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
920 crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
921 crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
922 crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
923 crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
924 crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
925 crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
926 crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
927
928 crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
929 *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
930 break;
931 }
932 return true;
933}
934
6fe7ac3f
AD		 935struct radeon_encoder_tv_dac *
936radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
937{
938 struct drm_device *dev = encoder->base.dev;
939 struct radeon_device *rdev = dev->dev_private;
940 struct radeon_mode_info *mode_info = &rdev->mode_info;
941 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
942 uint16_t data_offset;
943 struct _COMPASSIONATE_DATA *dac_info;
944 uint8_t frev, crev;
945 uint8_t bg, dac;
6fe7ac3f
AD		 946 struct radeon_encoder_tv_dac *tv_dac = NULL;
947
948 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
949
950 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
951
952 if (dac_info) {
953 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
954
955 if (!tv_dac)
956 return NULL;
957
958 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
959 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
960 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
961
962 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
963 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
964 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
965
966 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
967 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
968 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
969
970 }
971 return tv_dac;
972}
973
771fe6b9
JG		 974void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
975{
976 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
977 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
978
979 args.ucEnable = enable;
980
981 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
982}
983
984void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
985{
986 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
987 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
988
989 args.ucEnable = enable;
990
991 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
992}
993
994void radeon_atom_set_engine_clock(struct radeon_device *rdev,
995 uint32_t eng_clock)
996{
997 SET_ENGINE_CLOCK_PS_ALLOCATION args;
998 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
999
1000 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1001
1002 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1003}
1004
1005void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1006 uint32_t mem_clock)
1007{
1008 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1009 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1010
1011 if (rdev->flags & RADEON_IS_IGP)
1012 return;
1013
1014 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1015
1016 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1017}
1018
1019void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1020{
1021 struct radeon_device *rdev = dev->dev_private;
1022 uint32_t bios_2_scratch, bios_6_scratch;
1023
1024 if (rdev->family >= CHIP_R600) {
4ce001ab 1025 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 1026 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1027 } else {
4ce001ab 1028 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 1029 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1030 }
1031
1032 /* let the bios control the backlight */
1033 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1034
1035 /* tell the bios not to handle mode switching */
1036 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1037
1038 if (rdev->family >= CHIP_R600) {
1039 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1040 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1041 } else {
1042 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1043 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1044 }
1045
1046}
1047
1048void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1049{
1050 struct drm_device *dev = encoder->dev;
1051 struct radeon_device *rdev = dev->dev_private;
1052 uint32_t bios_6_scratch;
1053
1054 if (rdev->family >= CHIP_R600)
1055 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1056 else
1057 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1058
1059 if (lock)
1060 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1061 else
1062 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1063
1064 if (rdev->family >= CHIP_R600)
1065 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1066 else
1067 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1068}
1069
1070/* at some point we may want to break this out into individual functions */
1071void
1072radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1073 struct drm_encoder *encoder,
1074 bool connected)
1075{
1076 struct drm_device *dev = connector->dev;
1077 struct radeon_device *rdev = dev->dev_private;
1078 struct radeon_connector *radeon_connector =
1079 to_radeon_connector(connector);
1080 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1081 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1082
1083 if (rdev->family >= CHIP_R600) {
1084 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1085 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1086 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1087 } else {
1088 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1089 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1090 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1091 }
1092
1093 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1094 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1095 if (connected) {
1096 DRM_DEBUG("TV1 connected\n");
1097 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1098 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1099 } else {
1100 DRM_DEBUG("TV1 disconnected\n");
1101 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1102 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1103 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1104 }
1105 }
1106 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1107 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1108 if (connected) {
1109 DRM_DEBUG("CV connected\n");
1110 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1111 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1112 } else {
1113 DRM_DEBUG("CV disconnected\n");
1114 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1115 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1116 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1117 }
1118 }
1119 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1120 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1121 if (connected) {
1122 DRM_DEBUG("LCD1 connected\n");
1123 bios_0_scratch |= ATOM_S0_LCD1;
1124 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1125 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1126 } else {
1127 DRM_DEBUG("LCD1 disconnected\n");
1128 bios_0_scratch &= ~ATOM_S0_LCD1;
1129 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1130 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1131 }
1132 }
1133 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1134 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1135 if (connected) {
1136 DRM_DEBUG("CRT1 connected\n");
1137 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1138 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1139 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1140 } else {
1141 DRM_DEBUG("CRT1 disconnected\n");
1142 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1143 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1144 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1145 }
1146 }
1147 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1148 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1149 if (connected) {
1150 DRM_DEBUG("CRT2 connected\n");
1151 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1152 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1153 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1154 } else {
1155 DRM_DEBUG("CRT2 disconnected\n");
1156 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1157 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1158 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1159 }
1160 }
1161 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1162 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1163 if (connected) {
1164 DRM_DEBUG("DFP1 connected\n");
1165 bios_0_scratch |= ATOM_S0_DFP1;
1166 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1167 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1168 } else {
1169 DRM_DEBUG("DFP1 disconnected\n");
1170 bios_0_scratch &= ~ATOM_S0_DFP1;
1171 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1172 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1173 }
1174 }
1175 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1176 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1177 if (connected) {
1178 DRM_DEBUG("DFP2 connected\n");
1179 bios_0_scratch |= ATOM_S0_DFP2;
1180 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1181 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1182 } else {
1183 DRM_DEBUG("DFP2 disconnected\n");
1184 bios_0_scratch &= ~ATOM_S0_DFP2;
1185 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1186 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1187 }
1188 }
1189 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1190 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1191 if (connected) {
1192 DRM_DEBUG("DFP3 connected\n");
1193 bios_0_scratch |= ATOM_S0_DFP3;
1194 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1195 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1196 } else {
1197 DRM_DEBUG("DFP3 disconnected\n");
1198 bios_0_scratch &= ~ATOM_S0_DFP3;
1199 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1200 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1201 }
1202 }
1203 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1204 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1205 if (connected) {
1206 DRM_DEBUG("DFP4 connected\n");
1207 bios_0_scratch |= ATOM_S0_DFP4;
1208 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1209 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1210 } else {
1211 DRM_DEBUG("DFP4 disconnected\n");
1212 bios_0_scratch &= ~ATOM_S0_DFP4;
1213 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1214 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1215 }
1216 }
1217 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1218 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1219 if (connected) {
1220 DRM_DEBUG("DFP5 connected\n");
1221 bios_0_scratch |= ATOM_S0_DFP5;
1222 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1223 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1224 } else {
1225 DRM_DEBUG("DFP5 disconnected\n");
1226 bios_0_scratch &= ~ATOM_S0_DFP5;
1227 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1228 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1229 }
1230 }
1231
1232 if (rdev->family >= CHIP_R600) {
1233 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1234 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1235 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1236 } else {
1237 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1238 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1239 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1240 }
1241}
1242
1243void
1244radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1245{
1246 struct drm_device *dev = encoder->dev;
1247 struct radeon_device *rdev = dev->dev_private;
1248 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1249 uint32_t bios_3_scratch;
1250
1251 if (rdev->family >= CHIP_R600)
1252 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1253 else
1254 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1255
1256 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1257 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1258 bios_3_scratch |= (crtc << 18);
1259 }
1260 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1261 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1262 bios_3_scratch |= (crtc << 24);
1263 }
1264 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1265 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1266 bios_3_scratch |= (crtc << 16);
1267 }
1268 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1269 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1270 bios_3_scratch |= (crtc << 20);
1271 }
1272 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1273 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1274 bios_3_scratch |= (crtc << 17);
1275 }
1276 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1277 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1278 bios_3_scratch |= (crtc << 19);
1279 }
1280 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1281 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1282 bios_3_scratch |= (crtc << 23);
1283 }
1284 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1285 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1286 bios_3_scratch |= (crtc << 25);
1287 }
1288
1289 if (rdev->family >= CHIP_R600)
1290 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1291 else
1292 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1293}
1294
1295void
1296radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1297{
1298 struct drm_device *dev = encoder->dev;
1299 struct radeon_device *rdev = dev->dev_private;
1300 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1301 uint32_t bios_2_scratch;
1302
1303 if (rdev->family >= CHIP_R600)
1304 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1305 else
1306 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1307
1308 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1309 if (on)
1310 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1311 else
1312 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1313 }
1314 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1315 if (on)
1316 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1317 else
1318 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1319 }
1320 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1321 if (on)
1322 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1323 else
1324 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1325 }
1326 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1327 if (on)
1328 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1329 else
1330 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1331 }
1332 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1333 if (on)
1334 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1335 else
1336 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1337 }
1338 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1339 if (on)
1340 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1341 else
1342 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1343 }
1344 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1345 if (on)
1346 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1347 else
1348 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1349 }
1350 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1351 if (on)
1352 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1353 else
1354 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1355 }
1356 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1357 if (on)
1358 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1359 else
1360 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1361 }
1362 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1363 if (on)
1364 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1365 else
1366 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1367 }
1368
1369 if (rdev->family >= CHIP_R600)
1370 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1371 else
1372 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1373}
kernel source for telekom puls (alcatel/mediatek)