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drm/radeon/kms: add some new pci ids
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
5137ee94
AD		 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
771fe6b9
JG		 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
5137ee94 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
36868bda 40 uint32_t supported_device, u16 caps);
771fe6b9
JG		 41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
5137ee94 49 uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
5137ee94 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
eed45b30
AD		 65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
771fe6b9 67{
771fe6b9 68 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 73 uint16_t data_offset, size;
74 int i, num_indices;
771fe6b9
JG		 75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
95beb690 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
95beb690
AD		 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 86 gpio = &i2c_info->asGPIO_Info[i];
87
ea39302b
AD		 88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
4589433c 91 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
ea39302b
AD		 92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
3074adc8
AD		 101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
103 if ((i == 4) &&
4589433c 104 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
3074adc8
AD		 105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
107 }
108
a084e6ee
AD		 109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
126
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
129 else
130 i2c.hw_capable = false;
131
132 if (gpio->sucI2cId.ucAccess == 0xa0)
133 i2c.mm_i2c = true;
134 else
135 i2c.mm_i2c = false;
136
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
138
f376b94f
AD		 139 if (i2c.mask_clk_reg)
140 i2c.valid = true;
a084e6ee
AD		 141 break;
142 }
d3f420d1
AD		 143 }
144 }
771fe6b9
JG		 145
146 return i2c;
147}
148
f376b94f
AD		 149void radeon_atombios_i2c_init(struct radeon_device *rdev)
150{
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
157 int i, num_indices;
158 char stmp[32];
159
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
161
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
164
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
167
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
170 i2c.valid = false;
ea39302b
AD		 171
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev)) {
174 if ((i == 7) &&
4589433c 175 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
ea39302b
AD		 176 (gpio->sucI2cId.ucAccess == 0)) {
177 gpio->sucI2cId.ucAccess = 0x97;
178 gpio->ucDataMaskShift = 8;
179 gpio->ucDataEnShift = 8;
180 gpio->ucDataY_Shift = 8;
181 gpio->ucDataA_Shift = 8;
182 }
183 }
184
3074adc8
AD		 185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
187 if ((i == 4) &&
4589433c 188 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
3074adc8
AD		 189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
191 }
192
f376b94f
AD		 193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
204 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
209
210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
211 i2c.hw_capable = true;
212 else
213 i2c.hw_capable = false;
214
215 if (gpio->sucI2cId.ucAccess == 0xa0)
216 i2c.mm_i2c = true;
217 else
218 i2c.mm_i2c = false;
219
220 i2c.i2c_id = gpio->sucI2cId.ucAccess;
221
222 if (i2c.mask_clk_reg) {
223 i2c.valid = true;
224 sprintf(stmp, "0x%x", i2c.i2c_id);
225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
226 }
227 }
228 }
229}
230
eed45b30
AD		 231static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
232 u8 id)
233{
234 struct atom_context *ctx = rdev->mode_info.atom_context;
235 struct radeon_gpio_rec gpio;
236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
237 struct _ATOM_GPIO_PIN_LUT *gpio_info;
238 ATOM_GPIO_PIN_ASSIGNMENT *pin;
239 u16 data_offset, size;
240 int i, num_indices;
241
242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
243 gpio.valid = false;
244
a084e6ee
AD		 245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 247
a084e6ee
AD		 248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 250
a084e6ee
AD		 251 for (i = 0; i < num_indices; i++) {
252 pin = &gpio_info->asGPIO_Pin[i];
253 if (id == pin->ucGPIO_ID) {
254 gpio.id = pin->ucGPIO_ID;
4589433c 255 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
a084e6ee
AD		 256 gpio.mask = (1 << pin->ucGpioPinBitShift);
257 gpio.valid = true;
258 break;
259 }
eed45b30
AD		 260 }
261 }
262
263 return gpio;
264}
265
266static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
267 struct radeon_gpio_rec *gpio)
268{
269 struct radeon_hpd hpd;
bcc1c2a1
AD		 270 u32 reg;
271
1d978dac
JD		 272 memset(&hpd, 0, sizeof(struct radeon_hpd));
273
bcc1c2a1
AD		 274 if (ASIC_IS_DCE4(rdev))
275 reg = EVERGREEN_DC_GPIO_HPD_A;
276 else
277 reg = AVIVO_DC_GPIO_HPD_A;
278
eed45b30 279 hpd.gpio = *gpio;
bcc1c2a1 280 if (gpio->reg == reg) {
eed45b30
AD		 281 switch(gpio->mask) {
282 case (1 << 0):
283 hpd.hpd = RADEON_HPD_1;
284 break;
285 case (1 << 8):
286 hpd.hpd = RADEON_HPD_2;
287 break;
288 case (1 << 16):
289 hpd.hpd = RADEON_HPD_3;
290 break;
291 case (1 << 24):
292 hpd.hpd = RADEON_HPD_4;
293 break;
294 case (1 << 26):
295 hpd.hpd = RADEON_HPD_5;
296 break;
297 case (1 << 28):
298 hpd.hpd = RADEON_HPD_6;
299 break;
300 default:
301 hpd.hpd = RADEON_HPD_NONE;
302 break;
303 }
304 } else
305 hpd.hpd = RADEON_HPD_NONE;
306 return hpd;
307}
308
771fe6b9
JG		 309static bool radeon_atom_apply_quirks(struct drm_device *dev,
310 uint32_t supported_device,
311 int *connector_type,
848577ee 312 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 313 uint16_t *line_mux,
314 struct radeon_hpd *hpd)
771fe6b9
JG		 315{
316
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev->pdev->device == 0x791e) &&
319 (dev->pdev->subsystem_vendor == 0x1043) &&
320 (dev->pdev->subsystem_device == 0x826d)) {
321 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
323 *connector_type = DRM_MODE_CONNECTOR_DVID;
324 }
325
c86a9038
AD		 326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x1849) &&
329 (dev->pdev->subsystem_device == 0x7941)) {
330 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
331 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
332 *connector_type = DRM_MODE_CONNECTOR_DVID;
333 }
334
f36fce0f
AD		 335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev->pdev->device == 0x796e) &&
337 (dev->pdev->subsystem_vendor == 0x1462) &&
338 (dev->pdev->subsystem_device == 0x7302)) {
339 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
340 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
341 return false;
342 }
343
771fe6b9
JG		 344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev->pdev->device == 0x7941) &&
346 (dev->pdev->subsystem_vendor == 0x147b) &&
347 (dev->pdev->subsystem_device == 0x2412)) {
348 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
349 return false;
350 }
351
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev->pdev->device == 0x5653) &&
354 (dev->pdev->subsystem_vendor == 0x1462) &&
355 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 356 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 357 i2c_bus->valid = false;
848577ee
AD		 358 *line_mux = 53;
359 }
771fe6b9
JG		 360 }
361
4e3f9b78
AD		 362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev->pdev->device == 0x7146) &&
364 (dev->pdev->subsystem_vendor == 0x17af) &&
365 (dev->pdev->subsystem_device == 0x2058)) {
366 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
367 return false;
368 }
369
aa1a750e
DA		 370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev->pdev->device == 0x7142) &&
372 (dev->pdev->subsystem_vendor == 0x1458) &&
373 (dev->pdev->subsystem_device == 0x2134)) {
374 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
375 return false;
376 }
377
378
771fe6b9
JG		 379 /* Funky macbooks */
380 if ((dev->pdev->device == 0x71C5) &&
381 (dev->pdev->subsystem_vendor == 0x106b) &&
382 (dev->pdev->subsystem_device == 0x0080)) {
383 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
384 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
385 return false;
e1e8a5dd
AD		 386 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
387 *line_mux = 0x90;
771fe6b9
JG		 388 }
389
be23da8a
AD		 390 /* mac rv630, rv730, others */
391 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
392 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
393 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
394 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
f598aa75
AD		 395 }
396
771fe6b9
JG		 397 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
398 if ((dev->pdev->device == 0x9598) &&
399 (dev->pdev->subsystem_vendor == 0x1043) &&
400 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 402 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 403 }
404 }
405
e153b70b
AD		 406 /* ASUS HD 3600 board lists the DVI port as HDMI */
407 if ((dev->pdev->device == 0x9598) &&
408 (dev->pdev->subsystem_vendor == 0x1043) &&
409 (dev->pdev->subsystem_device == 0x01e4)) {
410 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
411 *connector_type = DRM_MODE_CONNECTOR_DVII;
412 }
413 }
414
705af9c7
AD		 415 /* ASUS HD 3450 board lists the DVI port as HDMI */
416 if ((dev->pdev->device == 0x95C5) &&
417 (dev->pdev->subsystem_vendor == 0x1043) &&
418 (dev->pdev->subsystem_device == 0x01e2)) {
419 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 420 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 421 }
422 }
423
705af9c7
AD		 424 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
425 * HDMI + VGA reporting as HDMI
426 */
427 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
428 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
429 *connector_type = DRM_MODE_CONNECTOR_VGA;
430 *line_mux = 0;
431 }
432 }
433
2f299d5d
AD		 434 /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
435 * on the laptop and a DVI port on the docking station and
436 * both share the same encoder, hpd pin, and ddc line.
437 * So while the bios table is technically correct,
438 * we drop the DVI port here since xrandr has no concept of
439 * encoders and will try and drive both connectors
440 * with different crtcs which isn't possible on the hardware
441 * side and leaves no crtcs for LVDS or VGA.
442 */
3e5f8ff3
AD		 443 if ((dev->pdev->device == 0x95c4) &&
444 (dev->pdev->subsystem_vendor == 0x1025) &&
445 (dev->pdev->subsystem_device == 0x013c)) {
446 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be 447 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
2f299d5d 448 /* actually it's a DVI-D port not DVI-I */
3e5f8ff3 449 *connector_type = DRM_MODE_CONNECTOR_DVID;
2f299d5d 450 return false;
9ea2c4be 451 }
3e5f8ff3
AD		 452 }
453
efa8450f
DA		 454 /* XFX Pine Group device rv730 reports no VGA DDC lines
455 * even though they are wired up to record 0x93
456 */
457 if ((dev->pdev->device == 0x9498) &&
458 (dev->pdev->subsystem_vendor == 0x1682) &&
459 (dev->pdev->subsystem_device == 0x2452)) {
460 struct radeon_device *rdev = dev->dev_private;
461 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
462 }
771fe6b9
JG		 463 return true;
464}
465
466const int supported_devices_connector_convert[] = {
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_VGA,
469 DRM_MODE_CONNECTOR_DVII,
470 DRM_MODE_CONNECTOR_DVID,
471 DRM_MODE_CONNECTOR_DVIA,
472 DRM_MODE_CONNECTOR_SVIDEO,
473 DRM_MODE_CONNECTOR_Composite,
474 DRM_MODE_CONNECTOR_LVDS,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_HDMIA,
478 DRM_MODE_CONNECTOR_HDMIB,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_9PinDIN,
482 DRM_MODE_CONNECTOR_DisplayPort
483};
484
b75fad06
AD		 485const uint16_t supported_devices_connector_object_id_convert[] = {
486 CONNECTOR_OBJECT_ID_NONE,
487 CONNECTOR_OBJECT_ID_VGA,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE,
492 CONNECTOR_OBJECT_ID_SVIDEO,
493 CONNECTOR_OBJECT_ID_LVDS,
494 CONNECTOR_OBJECT_ID_9PIN_DIN,
495 CONNECTOR_OBJECT_ID_9PIN_DIN,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
499 CONNECTOR_OBJECT_ID_SVIDEO
500};
501
771fe6b9
JG		 502const int object_connector_convert[] = {
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DVII,
505 DRM_MODE_CONNECTOR_DVII,
506 DRM_MODE_CONNECTOR_DVID,
507 DRM_MODE_CONNECTOR_DVID,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_Composite,
510 DRM_MODE_CONNECTOR_SVIDEO,
511 DRM_MODE_CONNECTOR_Unknown,
705af9c7 512 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 513 DRM_MODE_CONNECTOR_9PinDIN,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_HDMIA,
516 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 517 DRM_MODE_CONNECTOR_LVDS,
518 DRM_MODE_CONNECTOR_9PinDIN,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 522 DRM_MODE_CONNECTOR_DisplayPort,
523 DRM_MODE_CONNECTOR_eDP,
524 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 525};
526
527bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
528{
529 struct radeon_device *rdev = dev->dev_private;
530 struct radeon_mode_info *mode_info = &rdev->mode_info;
531 struct atom_context *ctx = mode_info->atom_context;
532 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 533 u16 size, data_offset;
534 u8 frev, crev;
771fe6b9 535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
36868bda 536 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
26b5bc98 537 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
539 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 540 int i, j, k, path_size, device_support;
771fe6b9 541 int connector_type;
eed45b30 542 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9 543 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 544 struct radeon_router router;
eed45b30
AD		 545 struct radeon_gpio_rec gpio;
546 struct radeon_hpd hpd;
547
a084e6ee 548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 549 return false;
550
551 if (crev < 2)
552 return false;
553
554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usDisplayPathTableOffset));
558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
36868bda
AD		 561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
562 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
26b5bc98
AD		 564 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 567 device_support = le16_to_cpu(obj_header->usDeviceSupport);
568
569 path_size = 0;
570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
571 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
572 ATOM_DISPLAY_OBJECT_PATH *path;
573 addr += path_size;
574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
575 path_size += le16_to_cpu(path->usSize);
5137ee94 576
771fe6b9
JG		 577 if (device_support & le16_to_cpu(path->usDeviceTag)) {
578 uint8_t con_obj_id, con_obj_num, con_obj_type;
579
580 con_obj_id =
581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
582 >> OBJECT_ID_SHIFT;
583 con_obj_num =
584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
585 >> ENUM_ID_SHIFT;
586 con_obj_type =
587 (le16_to_cpu(path->usConnObjectId) &
588 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
589
4bbd4973
DA		 590 /* TODO CV support */
591 if (le16_to_cpu(path->usDeviceTag) ==
592 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 593 continue;
594
ee59f2b4
AD		 595 /* IGP chips */
596 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 597 (con_obj_id ==
598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
599 uint16_t igp_offset = 0;
600 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
601
602 index =
603 GetIndexIntoMasterTable(DATA,
604 IntegratedSystemInfo);
605
a084e6ee
AD		 606 if (atom_parse_data_header(ctx, index, &size, &frev,
607 &crev, &igp_offset)) {
608
609 if (crev >= 2) {
610 igp_obj =
611 (ATOM_INTEGRATED_SYSTEM_INFO_V2
612 *) (ctx->bios + igp_offset);
613
614 if (igp_obj) {
615 uint32_t slot_config, ct;
616
617 if (con_obj_num == 1)
618 slot_config =
619 igp_obj->
620 ulDDISlot1Config;
621 else
622 slot_config =
623 igp_obj->
624 ulDDISlot2Config;
625
626 ct = (slot_config >> 16) & 0xff;
627 connector_type =
628 object_connector_convert
629 [ct];
630 connector_object_id = ct;
631 igp_lane_info =
632 slot_config & 0xffff;
633 } else
634 continue;
771fe6b9
JG		 635 } else
636 continue;
a084e6ee
AD		 637 } else {
638 igp_lane_info = 0;
639 connector_type =
640 object_connector_convert[con_obj_id];
641 connector_object_id = con_obj_id;
642 }
771fe6b9
JG		 643 } else {
644 igp_lane_info = 0;
645 connector_type =
646 object_connector_convert[con_obj_id];
b75fad06 647 connector_object_id = con_obj_id;
771fe6b9
JG		 648 }
649
650 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
651 continue;
652
bdd91b2b
TW		 653 router.ddc_valid = false;
654 router.cd_valid = false;
26b5bc98
AD		 655 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
656 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 657
26b5bc98 658 grph_obj_id =
771fe6b9
JG		 659 (le16_to_cpu(path->usGraphicObjIds[j]) &
660 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 661 grph_obj_num =
771fe6b9
JG		 662 (le16_to_cpu(path->usGraphicObjIds[j]) &
663 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 664 grph_obj_type =
771fe6b9
JG		 665 (le16_to_cpu(path->usGraphicObjIds[j]) &
666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
667
26b5bc98 668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
36868bda
AD		 669 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
670 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
671 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
672 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
673 (ctx->bios + data_offset +
674 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
675 ATOM_ENCODER_CAP_RECORD *cap_record;
676 u16 caps = 0;
771fe6b9 677
97ea530f
JL		 678 while (record->ucRecordSize > 0 &&
679 record->ucRecordType > 0 &&
36868bda
AD		 680 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
681 switch (record->ucRecordType) {
682 case ATOM_ENCODER_CAP_RECORD_TYPE:
683 cap_record =(ATOM_ENCODER_CAP_RECORD *)
684 record;
685 caps = le16_to_cpu(cap_record->usEncoderCap);
686 break;
687 }
688 record = (ATOM_COMMON_RECORD_HEADER *)
689 ((char *)record + record->ucRecordSize);
690 }
691 radeon_add_atom_encoder(dev,
692 encoder_obj,
693 le16_to_cpu
694 (path->
695 usDeviceTag),
696 caps);
697 }
698 }
26b5bc98 699 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
26b5bc98 700 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
bdd91b2b 701 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
26b5bc98
AD		 702 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
703 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
704 (ctx->bios + data_offset +
705 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
706 ATOM_I2C_RECORD *i2c_record;
707 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
708 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
fb939dfc 709 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
26b5bc98
AD		 710 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
711 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
712 (ctx->bios + data_offset +
713 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
714 int enum_id;
715
716 router.router_id = router_obj_id;
717 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
718 enum_id++) {
719 if (le16_to_cpu(path->usConnObjectId) ==
720 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
721 break;
722 }
723
97ea530f
JL		 724 while (record->ucRecordSize > 0 &&
725 record->ucRecordType > 0 &&
26b5bc98
AD		 726 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
727 switch (record->ucRecordType) {
728 case ATOM_I2C_RECORD_TYPE:
729 i2c_record =
730 (ATOM_I2C_RECORD *)
731 record;
732 i2c_config =
733 (ATOM_I2C_ID_CONFIG_ACCESS *)
734 &i2c_record->sucI2cId;
735 router.i2c_info =
736 radeon_lookup_i2c_gpio(rdev,
737 i2c_config->
738 ucAccess);
739 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
740 break;
741 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
742 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
743 record;
fb939dfc
AD		 744 router.ddc_valid = true;
745 router.ddc_mux_type = ddc_path->ucMuxType;
746 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
747 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
748 break;
749 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
750 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
751 record;
752 router.cd_valid = true;
753 router.cd_mux_type = cd_path->ucMuxType;
754 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
755 router.cd_mux_state = cd_path->ucMuxState[enum_id];
26b5bc98
AD		 756 break;
757 }
758 record = (ATOM_COMMON_RECORD_HEADER *)
759 ((char *)record + record->ucRecordSize);
760 }
761 }
762 }
771fe6b9
JG		 763 }
764 }
765
eed45b30 766 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 767 ddc_bus.valid = false;
768 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 769 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 770 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 771 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
772 if (le16_to_cpu(path->usConnObjectId) ==
773 le16_to_cpu(con_obj->asObjects[j].
774 usObjectID)) {
775 ATOM_COMMON_RECORD_HEADER
776 *record =
777 (ATOM_COMMON_RECORD_HEADER
778 *)
779 (ctx->bios + data_offset +
780 le16_to_cpu(con_obj->
781 asObjects[j].
782 usRecordOffset));
783 ATOM_I2C_RECORD *i2c_record;
eed45b30 784 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 785 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 786
97ea530f
JL		 787 while (record->ucRecordSize > 0 &&
788 record->ucRecordType > 0 &&
789 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 790 switch (record->ucRecordType) {
771fe6b9
JG		 791 case ATOM_I2C_RECORD_TYPE:
792 i2c_record =
eed45b30
AD		 793 (ATOM_I2C_RECORD *)
794 record;
d3f420d1
AD		 795 i2c_config =
796 (ATOM_I2C_ID_CONFIG_ACCESS *)
797 &i2c_record->sucI2cId;
eed45b30 798 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 799 i2c_config->
800 ucAccess);
eed45b30
AD		 801 break;
802 case ATOM_HPD_INT_RECORD_TYPE:
803 hpd_record =
804 (ATOM_HPD_INT_RECORD *)
805 record;
806 gpio = radeon_lookup_gpio(rdev,
807 hpd_record->ucHPDIntGPIOID);
808 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
809 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 810 break;
811 }
812 record =
813 (ATOM_COMMON_RECORD_HEADER
814 *) ((char *)record
815 +
816 record->
817 ucRecordSize);
818 }
819 break;
820 }
821 }
eed45b30 822 }
771fe6b9 823
bcc1c2a1 824 /* needed for aux chan transactions */
8e36ed00 825 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 826
705af9c7
AD		 827 conn_id = le16_to_cpu(path->usConnObjectId);
828
829 if (!radeon_atom_apply_quirks
830 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 831 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 832 continue;
833
771fe6b9 834 radeon_add_atom_connector(dev,
705af9c7 835 conn_id,
771fe6b9
JG		 836 le16_to_cpu(path->
837 usDeviceTag),
838 connector_type, &ddc_bus,
5137ee94 839 igp_lane_info,
eed45b30 840 connector_object_id,
26b5bc98
AD		 841 &hpd,
842 &router);
771fe6b9
JG		 843
844 }
845 }
846
847 radeon_link_encoder_connector(dev);
848
849 return true;
850}
851
b75fad06
AD		 852static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
853 int connector_type,
854 uint16_t devices)
855{
856 struct radeon_device *rdev = dev->dev_private;
857
858 if (rdev->flags & RADEON_IS_IGP) {
859 return supported_devices_connector_object_id_convert
860 [connector_type];
861 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
862 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
863 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
864 struct radeon_mode_info *mode_info = &rdev->mode_info;
865 struct atom_context *ctx = mode_info->atom_context;
866 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
867 uint16_t size, data_offset;
868 uint8_t frev, crev;
869 ATOM_XTMDS_INFO *xtmds;
870
a084e6ee
AD		 871 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
872 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 873
a084e6ee
AD		 874 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
879 } else {
880 if (connector_type == DRM_MODE_CONNECTOR_DVII)
881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
882 else
883 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
884 }
885 } else
886 return supported_devices_connector_object_id_convert
887 [connector_type];
b75fad06
AD		 888 } else {
889 return supported_devices_connector_object_id_convert
890 [connector_type];
891 }
892}
893
771fe6b9
JG		 894struct bios_connector {
895 bool valid;
705af9c7 896 uint16_t line_mux;
771fe6b9
JG		 897 uint16_t devices;
898 int connector_type;
899 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 900 struct radeon_hpd hpd;
771fe6b9
JG		 901};
902
903bool radeon_get_atom_connector_info_from_supported_devices_table(struct
904 drm_device
905 *dev)
906{
907 struct radeon_device *rdev = dev->dev_private;
908 struct radeon_mode_info *mode_info = &rdev->mode_info;
909 struct atom_context *ctx = mode_info->atom_context;
910 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
911 uint16_t size, data_offset;
912 uint8_t frev, crev;
913 uint16_t device_support;
914 uint8_t dac;
915 union atom_supported_devices *supported_devices;
eed45b30 916 int i, j, max_device;
f49d273d
PB		 917 struct bios_connector *bios_connectors;
918 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 919 struct radeon_router router;
920
fb939dfc
AD		 921 router.ddc_valid = false;
922 router.cd_valid = false;
771fe6b9 923
f49d273d
PB		 924 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
925 if (!bios_connectors)
926 return false;
927
928 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
929 &data_offset)) {
930 kfree(bios_connectors);
a084e6ee 931 return false;
f49d273d 932 }
771fe6b9
JG		 933
934 supported_devices =
935 (union atom_supported_devices *)(ctx->bios + data_offset);
936
937 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
938
eed45b30
AD		 939 if (frev > 1)
940 max_device = ATOM_MAX_SUPPORTED_DEVICE;
941 else
942 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
943
944 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 945 ATOM_CONNECTOR_INFO_I2C ci =
946 supported_devices->info.asConnInfo[i];
947
948 bios_connectors[i].valid = false;
949
950 if (!(device_support & (1 << i))) {
951 continue;
952 }
953
954 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 955 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 956 continue;
957 }
958
771fe6b9
JG		 959 bios_connectors[i].connector_type =
960 supported_devices_connector_convert[ci.sucConnectorInfo.
961 sbfAccess.
962 bfConnectorType];
963
964 if (bios_connectors[i].connector_type ==
965 DRM_MODE_CONNECTOR_Unknown)
966 continue;
967
968 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
969
d3f420d1
AD		 970 bios_connectors[i].line_mux =
971 ci.sucI2cId.ucAccess;
771fe6b9
JG		 972
973 /* give tv unique connector ids */
974 if (i == ATOM_DEVICE_TV1_INDEX) {
975 bios_connectors[i].ddc_bus.valid = false;
976 bios_connectors[i].line_mux = 50;
977 } else if (i == ATOM_DEVICE_TV2_INDEX) {
978 bios_connectors[i].ddc_bus.valid = false;
979 bios_connectors[i].line_mux = 51;
980 } else if (i == ATOM_DEVICE_CV_INDEX) {
981 bios_connectors[i].ddc_bus.valid = false;
982 bios_connectors[i].line_mux = 52;
983 } else
984 bios_connectors[i].ddc_bus =
eed45b30
AD		 985 radeon_lookup_i2c_gpio(rdev,
986 bios_connectors[i].line_mux);
987
988 if ((crev > 1) && (frev > 1)) {
989 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
990 switch (isb) {
991 case 0x4:
992 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
993 break;
994 case 0xa:
995 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
996 break;
997 default:
998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
999 break;
1000 }
1001 } else {
1002 if (i == ATOM_DEVICE_DFP1_INDEX)
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004 else if (i == ATOM_DEVICE_DFP2_INDEX)
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1006 else
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1008 }
771fe6b9
JG		 1009
1010 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1011 * shared with a DVI port, we'll pick up the DVI connector when we
1012 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1013 */
1014 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1015 bios_connectors[i].connector_type =
1016 DRM_MODE_CONNECTOR_VGA;
1017
1018 if (!radeon_atom_apply_quirks
1019 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 1020 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1021 &bios_connectors[i].hpd))
771fe6b9
JG		 1022 continue;
1023
1024 bios_connectors[i].valid = true;
1025 bios_connectors[i].devices = (1 << i);
1026
1027 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1028 radeon_add_atom_encoder(dev,
5137ee94 1029 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1030 (1 << i),
1031 dac),
36868bda
AD		 1032 (1 << i),
1033 0);
771fe6b9
JG		 1034 else
1035 radeon_add_legacy_encoder(dev,
5137ee94 1036 radeon_get_encoder_enum(dev,
f56cd64f 1037 (1 << i),
771fe6b9
JG		 1038 dac),
1039 (1 << i));
1040 }
1041
1042 /* combine shared connectors */
eed45b30 1043 for (i = 0; i < max_device; i++) {
771fe6b9 1044 if (bios_connectors[i].valid) {
eed45b30 1045 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 1046 if (bios_connectors[j].valid && (i != j)) {
1047 if (bios_connectors[i].line_mux ==
1048 bios_connectors[j].line_mux) {
f56cd64f
AD		 1049 /* make sure not to combine LVDS */
1050 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[i].line_mux = 53;
1052 bios_connectors[i].ddc_bus.valid = false;
1053 continue;
1054 }
1055 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1056 bios_connectors[j].line_mux = 53;
1057 bios_connectors[j].ddc_bus.valid = false;
1058 continue;
1059 }
1060 /* combine analog and digital for DVI-I */
1061 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1063 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1065 bios_connectors[i].devices |=
1066 bios_connectors[j].devices;
1067 bios_connectors[i].connector_type =
1068 DRM_MODE_CONNECTOR_DVII;
1069 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 1070 bios_connectors[i].hpd =
1071 bios_connectors[j].hpd;
f56cd64f 1072 bios_connectors[j].valid = false;
771fe6b9
JG		 1073 }
1074 }
1075 }
1076 }
1077 }
1078 }
1079
1080 /* add the connectors */
eed45b30 1081 for (i = 0; i < max_device; i++) {
b75fad06
AD		 1082 if (bios_connectors[i].valid) {
1083 uint16_t connector_object_id =
1084 atombios_get_connector_object_id(dev,
1085 bios_connectors[i].connector_type,
1086 bios_connectors[i].devices);
771fe6b9
JG		 1087 radeon_add_atom_connector(dev,
1088 bios_connectors[i].line_mux,
1089 bios_connectors[i].devices,
1090 bios_connectors[i].
1091 connector_type,
1092 &bios_connectors[i].ddc_bus,
5137ee94 1093 0,
eed45b30 1094 connector_object_id,
26b5bc98
AD		 1095 &bios_connectors[i].hpd,
1096 &router);
b75fad06 1097 }
771fe6b9
JG		 1098 }
1099
1100 radeon_link_encoder_connector(dev);
1101
f49d273d 1102 kfree(bios_connectors);
771fe6b9
JG		 1103 return true;
1104}
1105
1106union firmware_info {
1107 ATOM_FIRMWARE_INFO info;
1108 ATOM_FIRMWARE_INFO_V1_2 info_12;
1109 ATOM_FIRMWARE_INFO_V1_3 info_13;
1110 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1111 ATOM_FIRMWARE_INFO_V2_1 info_21;
f82b3ddc 1112 ATOM_FIRMWARE_INFO_V2_2 info_22;
771fe6b9
JG		 1113};
1114
1115bool radeon_atom_get_clock_info(struct drm_device *dev)
1116{
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1120 union firmware_info *firmware_info;
1121 uint8_t frev, crev;
1122 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1123 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1124 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1125 struct radeon_pll *spll = &rdev->clock.spll;
1126 struct radeon_pll *mpll = &rdev->clock.mpll;
1127 uint16_t data_offset;
1128
a084e6ee
AD		 1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 firmware_info =
1132 (union firmware_info *)(mode_info->atom_context->bios +
1133 data_offset);
771fe6b9
JG		 1134 /* pixel clocks */
1135 p1pll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 p1pll->reference_div = 0;
1138
bc293e58
MF		 1139 if (crev < 2)
1140 p1pll->pll_out_min =
1141 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1142 else
1143 p1pll->pll_out_min =
1144 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1145 p1pll->pll_out_max =
1146 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1147
86cb2bbf
AD		 1148 if (crev >= 4) {
1149 p1pll->lcd_pll_out_min =
1150 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1151 if (p1pll->lcd_pll_out_min == 0)
1152 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1153 p1pll->lcd_pll_out_max =
1154 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_max == 0)
1156 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1157 } else {
1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160 }
1161
771fe6b9
JG		 1162 if (p1pll->pll_out_min == 0) {
1163 if (ASIC_IS_AVIVO(rdev))
1164 p1pll->pll_out_min = 64800;
1165 else
1166 p1pll->pll_out_min = 20000;
1167 }
1168
1169 p1pll->pll_in_min =
1170 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1171 p1pll->pll_in_max =
1172 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1173
1174 *p2pll = *p1pll;
1175
1176 /* system clock */
f82b3ddc
AD		 1177 if (ASIC_IS_DCE4(rdev))
1178 spll->reference_freq =
1179 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1180 else
1181 spll->reference_freq =
1182 le16_to_cpu(firmware_info->info.usReferenceClock);
771fe6b9
JG		 1183 spll->reference_div = 0;
1184
1185 spll->pll_out_min =
1186 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1187 spll->pll_out_max =
1188 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1189
1190 /* ??? */
1191 if (spll->pll_out_min == 0) {
1192 if (ASIC_IS_AVIVO(rdev))
1193 spll->pll_out_min = 64800;
1194 else
1195 spll->pll_out_min = 20000;
1196 }
1197
1198 spll->pll_in_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1200 spll->pll_in_max =
1201 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1202
1203 /* memory clock */
f82b3ddc
AD		 1204 if (ASIC_IS_DCE4(rdev))
1205 mpll->reference_freq =
1206 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1207 else
1208 mpll->reference_freq =
1209 le16_to_cpu(firmware_info->info.usReferenceClock);
771fe6b9
JG		 1210 mpll->reference_div = 0;
1211
1212 mpll->pll_out_min =
1213 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1214 mpll->pll_out_max =
1215 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1216
1217 /* ??? */
1218 if (mpll->pll_out_min == 0) {
1219 if (ASIC_IS_AVIVO(rdev))
1220 mpll->pll_out_min = 64800;
1221 else
1222 mpll->pll_out_min = 20000;
1223 }
1224
1225 mpll->pll_in_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1227 mpll->pll_in_max =
1228 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1229
1230 rdev->clock.default_sclk =
1231 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1232 rdev->clock.default_mclk =
1233 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1234
bcc1c2a1
AD		 1235 if (ASIC_IS_DCE4(rdev)) {
1236 rdev->clock.default_dispclk =
1237 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
f82b3ddc
AD		 1238 if (rdev->clock.default_dispclk == 0) {
1239 if (ASIC_IS_DCE5(rdev))
1240 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1241 else
1242 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1243 }
bcc1c2a1
AD		 1244 rdev->clock.dp_extclk =
1245 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1246 }
1247 *dcpll = *p1pll;
1248
771fe6b9
JG		 1249 return true;
1250 }
bcc1c2a1 1251
771fe6b9
JG		 1252 return false;
1253}
1254
06b6476d
AD		 1255union igp_info {
1256 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1257 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1258};
1259
1260bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1261{
1262 struct radeon_mode_info *mode_info = &rdev->mode_info;
1263 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1264 union igp_info *igp_info;
1265 u8 frev, crev;
1266 u16 data_offset;
1267
4c70b2ea
AD		 1268 /* sideport is AMD only */
1269 if (rdev->family == CHIP_RS600)
1270 return false;
1271
a084e6ee
AD		 1272 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1273 &frev, &crev, &data_offset)) {
1274 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1275 data_offset);
06b6476d
AD		 1276 switch (crev) {
1277 case 1:
4589433c 1278 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
4c70b2ea 1279 return true;
06b6476d
AD		 1280 break;
1281 case 2:
4589433c 1282 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
06b6476d
AD		 1283 return true;
1284 break;
1285 default:
1286 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1287 break;
1288 }
1289 }
1290 return false;
1291}
1292
445282db
DA		 1293bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1294 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1295{
1296 struct drm_device *dev = encoder->base.dev;
1297 struct radeon_device *rdev = dev->dev_private;
1298 struct radeon_mode_info *mode_info = &rdev->mode_info;
1299 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1300 uint16_t data_offset;
1301 struct _ATOM_TMDS_INFO *tmds_info;
1302 uint8_t frev, crev;
1303 uint16_t maxfreq;
1304 int i;
771fe6b9 1305
a084e6ee
AD		 1306 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1307 &frev, &crev, &data_offset)) {
1308 tmds_info =
1309 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1310 data_offset);
771fe6b9 1311
771fe6b9
JG		 1312 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1313 for (i = 0; i < 4; i++) {
1314 tmds->tmds_pll[i].freq =
1315 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1316 tmds->tmds_pll[i].value =
1317 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1318 tmds->tmds_pll[i].value |=
1319 (tmds_info->asMiscInfo[i].
1320 ucPLL_VCO_Gain & 0x3f) << 6;
1321 tmds->tmds_pll[i].value |=
1322 (tmds_info->asMiscInfo[i].
1323 ucPLL_DutyCycle & 0xf) << 12;
1324 tmds->tmds_pll[i].value |=
1325 (tmds_info->asMiscInfo[i].
1326 ucPLL_VoltageSwing & 0xf) << 16;
1327
d9fdaafb 1328 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1329 tmds->tmds_pll[i].freq,
1330 tmds->tmds_pll[i].value);
1331
1332 if (maxfreq == tmds->tmds_pll[i].freq) {
1333 tmds->tmds_pll[i].freq = 0xffffffff;
1334 break;
1335 }
1336 }
445282db 1337 return true;
771fe6b9 1338 }
445282db 1339 return false;
771fe6b9
JG		 1340}
1341
ba032a58
AD		 1342bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1343 struct radeon_atom_ss *ss,
1344 int id)
ebbe1cb9 1345{
ebbe1cb9
AD		 1346 struct radeon_mode_info *mode_info = &rdev->mode_info;
1347 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
ba032a58 1348 uint16_t data_offset, size;
ebbe1cb9
AD		 1349 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1350 uint8_t frev, crev;
ba032a58 1351 int i, num_indices;
ebbe1cb9 1352
ba032a58
AD		 1353 memset(ss, 0, sizeof(struct radeon_atom_ss));
1354 if (atom_parse_data_header(mode_info->atom_context, index, &size,
a084e6ee
AD		 1355 &frev, &crev, &data_offset)) {
1356 ss_info =
1357 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1358
ba032a58
AD		 1359 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1360 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
ebbe1cb9 1361
ba032a58 1362 for (i = 0; i < num_indices; i++) {
279b215e
AD		 1363 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1364 ss->percentage =
1365 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1366 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1367 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1368 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1369 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1370 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
ba032a58
AD		 1371 return true;
1372 }
1373 }
1374 }
1375 return false;
1376}
1377
4339c442
AD		 1378static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1379 struct radeon_atom_ss *ss,
1380 int id)
1381{
1382 struct radeon_mode_info *mode_info = &rdev->mode_info;
1383 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1384 u16 data_offset, size;
1385 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1386 u8 frev, crev;
1387 u16 percentage = 0, rate = 0;
1388
1389 /* get any igp specific overrides */
1390 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1391 &frev, &crev, &data_offset)) {
1392 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1393 (mode_info->atom_context->bios + data_offset);
1394 switch (id) {
1395 case ASIC_INTERNAL_SS_ON_TMDS:
1396 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1397 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1398 break;
1399 case ASIC_INTERNAL_SS_ON_HDMI:
1400 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1401 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1402 break;
1403 case ASIC_INTERNAL_SS_ON_LVDS:
1404 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1405 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1406 break;
1407 }
1408 if (percentage)
1409 ss->percentage = percentage;
1410 if (rate)
1411 ss->rate = rate;
1412 }
1413}
1414
ba032a58
AD		 1415union asic_ss_info {
1416 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1417 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1418 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1419};
1420
1421bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1422 struct radeon_atom_ss *ss,
1423 int id, u32 clock)
1424{
1425 struct radeon_mode_info *mode_info = &rdev->mode_info;
1426 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1427 uint16_t data_offset, size;
1428 union asic_ss_info *ss_info;
1429 uint8_t frev, crev;
1430 int i, num_indices;
1431
1432 memset(ss, 0, sizeof(struct radeon_atom_ss));
1433 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1434 &frev, &crev, &data_offset)) {
1435
1436 ss_info =
1437 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1438
1439 switch (frev) {
1440 case 1:
1441 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1442 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1443
1444 for (i = 0; i < num_indices; i++) {
1445 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
4589433c 1446 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
ba032a58
AD		 1447 ss->percentage =
1448 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1449 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1450 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1451 return true;
1452 }
279b215e 1453 }
ba032a58
AD		 1454 break;
1455 case 2:
1456 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1457 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1458 for (i = 0; i < num_indices; i++) {
1459 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
4589433c 1460 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
ba032a58
AD		 1461 ss->percentage =
1462 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1463 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1464 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1465 return true;
1466 }
1467 }
1468 break;
1469 case 3:
1470 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1471 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1472 for (i = 0; i < num_indices; i++) {
1473 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
4589433c 1474 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
ba032a58
AD		 1475 ss->percentage =
1476 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1477 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1478 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
4339c442
AD		 1479 if (rdev->flags & RADEON_IS_IGP)
1480 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
ba032a58
AD		 1481 return true;
1482 }
1483 }
1484 break;
1485 default:
1486 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1487 break;
279b215e 1488 }
ba032a58 1489
ebbe1cb9 1490 }
ba032a58 1491 return false;
ebbe1cb9
AD		 1492}
1493
771fe6b9
JG		 1494union lvds_info {
1495 struct _ATOM_LVDS_INFO info;
1496 struct _ATOM_LVDS_INFO_V12 info_12;
1497};
1498
1499struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1500 radeon_encoder
1501 *encoder)
1502{
1503 struct drm_device *dev = encoder->base.dev;
1504 struct radeon_device *rdev = dev->dev_private;
1505 struct radeon_mode_info *mode_info = &rdev->mode_info;
1506 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1507 uint16_t data_offset, misc;
771fe6b9
JG		 1508 union lvds_info *lvds_info;
1509 uint8_t frev, crev;
1510 struct radeon_encoder_atom_dig *lvds = NULL;
5137ee94 1511 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9 1512
a084e6ee
AD		 1513 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1514 &frev, &crev, &data_offset)) {
1515 lvds_info =
1516 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1517 lvds =
1518 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1519
1520 if (!lvds)
1521 return NULL;
1522
de2103e4 1523 lvds->native_mode.clock =
771fe6b9 1524 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1525 lvds->native_mode.hdisplay =
771fe6b9 1526 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1527 lvds->native_mode.vdisplay =
771fe6b9 1528 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1529 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1530 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1531 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1532 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1533 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1534 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1535 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1536 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1537 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1538 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1539 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1540 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1541 lvds->panel_pwr_delay =
1542 le16_to_cpu(lvds_info->info.usOffDelayInMs);
ba032a58 1543 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1544
1545 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1546 if (misc & ATOM_VSYNC_POLARITY)
1547 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1548 if (misc & ATOM_HSYNC_POLARITY)
1549 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1550 if (misc & ATOM_COMPOSITESYNC)
1551 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1552 if (misc & ATOM_INTERLACE)
1553 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1554 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1555 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1556
4589433c
CC		 1557 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1558 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
7a868e18 1559
de2103e4
AD		 1560 /* set crtc values */
1561 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1562
ba032a58 1563 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
ebbe1cb9 1564
771fe6b9 1565 encoder->native_mode = lvds->native_mode;
5137ee94
AD		 1566
1567 if (encoder_enum == 2)
1568 lvds->linkb = true;
1569 else
1570 lvds->linkb = false;
1571
c324acd5 1572 /* parse the lcd record table */
4589433c 1573 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
c324acd5
AD		 1574 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1575 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1576 bool bad_record = false;
1577 u8 *record = (u8 *)(mode_info->atom_context->bios +
1578 data_offset +
4589433c 1579 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
c324acd5
AD		 1580 while (*record != ATOM_RECORD_END_TYPE) {
1581 switch (*record) {
1582 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1583 record += sizeof(ATOM_PATCH_RECORD_MODE);
1584 break;
1585 case LCD_RTS_RECORD_TYPE:
1586 record += sizeof(ATOM_LCD_RTS_RECORD);
1587 break;
1588 case LCD_CAP_RECORD_TYPE:
1589 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1590 break;
1591 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1592 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1593 if (fake_edid_record->ucFakeEDIDLength) {
1594 struct edid *edid;
1595 int edid_size =
1596 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1597 edid = kmalloc(edid_size, GFP_KERNEL);
1598 if (edid) {
1599 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1600 fake_edid_record->ucFakeEDIDLength);
1601
1602 if (drm_edid_is_valid(edid))
1603 rdev->mode_info.bios_hardcoded_edid = edid;
1604 else
1605 kfree(edid);
1606 }
1607 }
1608 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1609 break;
1610 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1611 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1612 lvds->native_mode.width_mm = panel_res_record->usHSize;
1613 lvds->native_mode.height_mm = panel_res_record->usVSize;
1614 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1615 break;
1616 default:
1617 DRM_ERROR("Bad LCD record %d\n", *record);
1618 bad_record = true;
1619 break;
1620 }
1621 if (bad_record)
1622 break;
1623 }
1624 }
771fe6b9
JG		 1625 }
1626 return lvds;
1627}
1628
6fe7ac3f
AD		 1629struct radeon_encoder_primary_dac *
1630radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1631{
1632 struct drm_device *dev = encoder->base.dev;
1633 struct radeon_device *rdev = dev->dev_private;
1634 struct radeon_mode_info *mode_info = &rdev->mode_info;
1635 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1636 uint16_t data_offset;
1637 struct _COMPASSIONATE_DATA *dac_info;
1638 uint8_t frev, crev;
1639 uint8_t bg, dac;
6fe7ac3f
AD		 1640 struct radeon_encoder_primary_dac *p_dac = NULL;
1641
a084e6ee
AD		 1642 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1643 &frev, &crev, &data_offset)) {
1644 dac_info = (struct _COMPASSIONATE_DATA *)
1645 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1646
6fe7ac3f
AD		 1647 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1648
1649 if (!p_dac)
1650 return NULL;
1651
1652 bg = dac_info->ucDAC1_BG_Adjustment;
1653 dac = dac_info->ucDAC1_DAC_Adjustment;
1654 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1655
1656 }
1657 return p_dac;
1658}
1659
4ce001ab 1660bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1661 struct drm_display_mode *mode)
4ce001ab
DA		 1662{
1663 struct radeon_mode_info *mode_info = &rdev->mode_info;
1664 ATOM_ANALOG_TV_INFO *tv_info;
1665 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1666 ATOM_DTD_FORMAT *dtd_timings;
1667 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1668 u8 frev, crev;
5a9bcacc 1669 u16 data_offset, misc;
4ce001ab 1670
a084e6ee
AD		 1671 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1672 &frev, &crev, &data_offset))
1673 return false;
4ce001ab
DA		 1674
1675 switch (crev) {
1676 case 1:
1677 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1678 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1679 return false;
1680
5a9bcacc
AD		 1681 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1682 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1683 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1684 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1685 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1686
1687 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1688 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1689 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1690 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1691 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1692
1693 mode->flags = 0;
1694 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1695 if (misc & ATOM_VSYNC_POLARITY)
1696 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1697 if (misc & ATOM_HSYNC_POLARITY)
1698 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1699 if (misc & ATOM_COMPOSITESYNC)
1700 mode->flags |= DRM_MODE_FLAG_CSYNC;
1701 if (misc & ATOM_INTERLACE)
1702 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1703 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1704 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1705
1706 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1707
1708 if (index == 1) {
1709 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1710 mode->crtc_htotal -= 1;
1711 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1712 }
1713 break;
1714 case 2:
1715 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1716 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1717 return false;
1718
1719 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1720 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1721 le16_to_cpu(dtd_timings->usHBlanking_Time);
1722 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1723 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1724 le16_to_cpu(dtd_timings->usHSyncOffset);
1725 mode->crtc_hsync_end = mode->crtc_hsync_start +
1726 le16_to_cpu(dtd_timings->usHSyncWidth);
1727
1728 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1729 le16_to_cpu(dtd_timings->usVBlanking_Time);
1730 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1731 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1732 le16_to_cpu(dtd_timings->usVSyncOffset);
1733 mode->crtc_vsync_end = mode->crtc_vsync_start +
1734 le16_to_cpu(dtd_timings->usVSyncWidth);
1735
1736 mode->flags = 0;
1737 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1738 if (misc & ATOM_VSYNC_POLARITY)
1739 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1740 if (misc & ATOM_HSYNC_POLARITY)
1741 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1742 if (misc & ATOM_COMPOSITESYNC)
1743 mode->flags |= DRM_MODE_FLAG_CSYNC;
1744 if (misc & ATOM_INTERLACE)
1745 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1746 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1747 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1748
1749 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1750 break;
1751 }
1752 return true;
1753}
1754
d79766fa
AD		 1755enum radeon_tv_std
1756radeon_atombios_get_tv_info(struct radeon_device *rdev)
1757{
1758 struct radeon_mode_info *mode_info = &rdev->mode_info;
1759 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1760 uint16_t data_offset;
1761 uint8_t frev, crev;
1762 struct _ATOM_ANALOG_TV_INFO *tv_info;
1763 enum radeon_tv_std tv_std = TV_STD_NTSC;
1764
a084e6ee
AD		 1765 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1766 &frev, &crev, &data_offset)) {
d79766fa 1767
a084e6ee
AD		 1768 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1769 (mode_info->atom_context->bios + data_offset);
d79766fa 1770
a084e6ee
AD		 1771 switch (tv_info->ucTV_BootUpDefaultStandard) {
1772 case ATOM_TV_NTSC:
1773 tv_std = TV_STD_NTSC;
40f76d81 1774 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
a084e6ee
AD		 1775 break;
1776 case ATOM_TV_NTSCJ:
1777 tv_std = TV_STD_NTSC_J;
40f76d81 1778 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
a084e6ee
AD		 1779 break;
1780 case ATOM_TV_PAL:
1781 tv_std = TV_STD_PAL;
40f76d81 1782 DRM_DEBUG_KMS("Default TV standard: PAL\n");
a084e6ee
AD		 1783 break;
1784 case ATOM_TV_PALM:
1785 tv_std = TV_STD_PAL_M;
40f76d81 1786 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
a084e6ee
AD		 1787 break;
1788 case ATOM_TV_PALN:
1789 tv_std = TV_STD_PAL_N;
40f76d81 1790 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
a084e6ee
AD		 1791 break;
1792 case ATOM_TV_PALCN:
1793 tv_std = TV_STD_PAL_CN;
40f76d81 1794 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
a084e6ee
AD		 1795 break;
1796 case ATOM_TV_PAL60:
1797 tv_std = TV_STD_PAL_60;
40f76d81 1798 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
a084e6ee
AD		 1799 break;
1800 case ATOM_TV_SECAM:
1801 tv_std = TV_STD_SECAM;
40f76d81 1802 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
a084e6ee
AD		 1803 break;
1804 default:
1805 tv_std = TV_STD_NTSC;
40f76d81 1806 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
a084e6ee
AD		 1807 break;
1808 }
d79766fa
AD		 1809 }
1810 return tv_std;
1811}
1812
6fe7ac3f
AD		 1813struct radeon_encoder_tv_dac *
1814radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1815{
1816 struct drm_device *dev = encoder->base.dev;
1817 struct radeon_device *rdev = dev->dev_private;
1818 struct radeon_mode_info *mode_info = &rdev->mode_info;
1819 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1820 uint16_t data_offset;
1821 struct _COMPASSIONATE_DATA *dac_info;
1822 uint8_t frev, crev;
1823 uint8_t bg, dac;
6fe7ac3f
AD		 1824 struct radeon_encoder_tv_dac *tv_dac = NULL;
1825
a084e6ee
AD		 1826 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1827 &frev, &crev, &data_offset)) {
6fe7ac3f 1828
a084e6ee
AD		 1829 dac_info = (struct _COMPASSIONATE_DATA *)
1830 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1831
6fe7ac3f
AD		 1832 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1833
1834 if (!tv_dac)
1835 return NULL;
1836
1837 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1838 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1839 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1840
1841 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1842 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1843 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1844
1845 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1846 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1847 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1848
d79766fa 1849 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1850 }
1851 return tv_dac;
1852}
1853
29fb52ca
AD		 1854static const char *thermal_controller_names[] = {
1855 "NONE",
678e7dfa
AD		 1856 "lm63",
1857 "adm1032",
1858 "adm1030",
1859 "max6649",
1860 "lm64",
1861 "f75375",
1862 "asc7xxx",
29fb52ca
AD		 1863};
1864
1865static const char *pp_lib_thermal_controller_names[] = {
1866 "NONE",
678e7dfa
AD		 1867 "lm63",
1868 "adm1032",
1869 "adm1030",
1870 "max6649",
1871 "lm64",
1872 "f75375",
29fb52ca
AD		 1873 "RV6xx",
1874 "RV770",
678e7dfa 1875 "adt7473",
560154e9 1876 "NONE",
49f65982
AD		 1877 "External GPIO",
1878 "Evergreen",
b0e66414
AD		 1879 "emc2103",
1880 "Sumo",
4fddba1f 1881 "Northern Islands",
29fb52ca
AD		 1882};
1883
56278a8e
AD		 1884union power_info {
1885 struct _ATOM_POWERPLAY_INFO info;
1886 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1887 struct _ATOM_POWERPLAY_INFO_V3 info_3;
560154e9 1888 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
b0e66414
AD		 1889 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1890 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
56278a8e
AD		 1891};
1892
560154e9
AD		 1893union pplib_clock_info {
1894 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1895 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1896 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
b0e66414 1897 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
560154e9
AD		 1898};
1899
1900union pplib_power_state {
1901 struct _ATOM_PPLIB_STATE v1;
1902 struct _ATOM_PPLIB_STATE_V2 v2;
1903};
1904
1905static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1906 int state_index,
1907 u32 misc, u32 misc2)
1908{
1909 rdev->pm.power_state[state_index].misc = misc;
1910 rdev->pm.power_state[state_index].misc2 = misc2;
1911 /* order matters! */
1912 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1913 rdev->pm.power_state[state_index].type =
1914 POWER_STATE_TYPE_POWERSAVE;
1915 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1916 rdev->pm.power_state[state_index].type =
1917 POWER_STATE_TYPE_BATTERY;
1918 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1919 rdev->pm.power_state[state_index].type =
1920 POWER_STATE_TYPE_BATTERY;
1921 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1922 rdev->pm.power_state[state_index].type =
1923 POWER_STATE_TYPE_BALANCED;
1924 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1925 rdev->pm.power_state[state_index].type =
1926 POWER_STATE_TYPE_PERFORMANCE;
1927 rdev->pm.power_state[state_index].flags &=
1928 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1929 }
1930 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1931 rdev->pm.power_state[state_index].type =
1932 POWER_STATE_TYPE_BALANCED;
1933 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1934 rdev->pm.power_state[state_index].type =
1935 POWER_STATE_TYPE_DEFAULT;
1936 rdev->pm.default_power_state_index = state_index;
1937 rdev->pm.power_state[state_index].default_clock_mode =
1938 &rdev->pm.power_state[state_index].clock_info[0];
1939 } else if (state_index == 0) {
1940 rdev->pm.power_state[state_index].clock_info[0].flags |=
1941 RADEON_PM_MODE_NO_DISPLAY;
1942 }
1943}
1944
1945static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
771fe6b9 1946{
56278a8e 1947 struct radeon_mode_info *mode_info = &rdev->mode_info;
560154e9
AD		 1948 u32 misc, misc2 = 0;
1949 int num_modes = 0, i;
1950 int state_index = 0;
1951 struct radeon_i2c_bus_rec i2c_bus;
1952 union power_info *power_info;
56278a8e 1953 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
560154e9 1954 u16 data_offset;
56278a8e 1955 u8 frev, crev;
771fe6b9 1956
560154e9
AD		 1957 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1958 &frev, &crev, &data_offset))
1959 return state_index;
1960 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1961
1962 /* add the i2c bus for thermal/fan chip */
1963 if (power_info->info.ucOverdriveThermalController > 0) {
1964 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1965 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1966 power_info->info.ucOverdriveControllerAddress >> 1);
1967 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1968 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1969 if (rdev->pm.i2c_bus) {
1970 struct i2c_board_info info = { };
1971 const char *name = thermal_controller_names[power_info->info.
1972 ucOverdriveThermalController];
1973 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1974 strlcpy(info.type, name, sizeof(info.type));
1975 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1976 }
1977 }
1978 num_modes = power_info->info.ucNumOfPowerModeEntries;
1979 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1980 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
0975b162
AD		 1981 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
1982 if (!rdev->pm.power_state)
1983 return state_index;
560154e9
AD		 1984 /* last mode is usually default, array is low to high */
1985 for (i = 0; i < num_modes; i++) {
1986 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1987 switch (frev) {
1988 case 1:
1989 rdev->pm.power_state[state_index].num_clock_modes = 1;
1990 rdev->pm.power_state[state_index].clock_info[0].mclk =
1991 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1992 rdev->pm.power_state[state_index].clock_info[0].sclk =
1993 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1994 /* skip invalid modes */
1995 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1996 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1997 continue;
1998 rdev->pm.power_state[state_index].pcie_lanes =
1999 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2000 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2001 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2002 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2003 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2004 VOLTAGE_GPIO;
2005 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2006 radeon_lookup_gpio(rdev,
2007 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2008 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2009 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2010 true;
2011 else
2012 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2013 false;
2014 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2015 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2016 VOLTAGE_VDDC;
2017 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2018 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
29fb52ca 2019 }
560154e9
AD		 2020 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2021 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2022 state_index++;
2023 break;
2024 case 2:
2025 rdev->pm.power_state[state_index].num_clock_modes = 1;
2026 rdev->pm.power_state[state_index].clock_info[0].mclk =
2027 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2028 rdev->pm.power_state[state_index].clock_info[0].sclk =
2029 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2030 /* skip invalid modes */
2031 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2032 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2033 continue;
2034 rdev->pm.power_state[state_index].pcie_lanes =
2035 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2036 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2037 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2038 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2039 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2040 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2041 VOLTAGE_GPIO;
2042 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2043 radeon_lookup_gpio(rdev,
2044 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2045 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2046 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2047 true;
2048 else
2049 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2050 false;
2051 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2052 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2053 VOLTAGE_VDDC;
2054 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2055 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
56278a8e 2056 }
560154e9
AD		 2057 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2058 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2059 state_index++;
2060 break;
2061 case 3:
2062 rdev->pm.power_state[state_index].num_clock_modes = 1;
2063 rdev->pm.power_state[state_index].clock_info[0].mclk =
2064 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2065 rdev->pm.power_state[state_index].clock_info[0].sclk =
2066 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2067 /* skip invalid modes */
2068 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2069 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2070 continue;
2071 rdev->pm.power_state[state_index].pcie_lanes =
2072 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2073 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2074 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2075 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2076 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2077 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2078 VOLTAGE_GPIO;
2079 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2080 radeon_lookup_gpio(rdev,
2081 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2082 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2083 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2084 true;
2085 else
2086 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2087 false;
2088 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2089 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2090 VOLTAGE_VDDC;
2091 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2092 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2093 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2094 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2095 true;
2096 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2097 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2098 }
02b17cc0 2099 }
560154e9
AD		 2100 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2101 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2102 state_index++;
2103 break;
2104 }
2105 }
2106 /* last mode is usually default */
2107 if (rdev->pm.default_power_state_index == -1) {
2108 rdev->pm.power_state[state_index - 1].type =
2109 POWER_STATE_TYPE_DEFAULT;
2110 rdev->pm.default_power_state_index = state_index - 1;
2111 rdev->pm.power_state[state_index - 1].default_clock_mode =
2112 &rdev->pm.power_state[state_index - 1].clock_info[0];
2113 rdev->pm.power_state[state_index].flags &=
2114 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2115 rdev->pm.power_state[state_index].misc = 0;
2116 rdev->pm.power_state[state_index].misc2 = 0;
2117 }
2118 return state_index;
2119}
2120
2121static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2122 ATOM_PPLIB_THERMALCONTROLLER *controller)
2123{
2124 struct radeon_i2c_bus_rec i2c_bus;
2125
2126 /* add the i2c bus for thermal/fan chip */
2127 if (controller->ucType > 0) {
2128 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2129 DRM_INFO("Internal thermal controller %s fan control\n",
2130 (controller->ucFanParameters &
2131 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2132 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2133 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2134 DRM_INFO("Internal thermal controller %s fan control\n",
2135 (controller->ucFanParameters &
2136 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2137 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2138 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2139 DRM_INFO("Internal thermal controller %s fan control\n",
2140 (controller->ucFanParameters &
2141 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2142 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
b0e66414
AD		 2143 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2144 DRM_INFO("Internal thermal controller %s fan control\n",
2145 (controller->ucFanParameters &
2146 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2147 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
4fddba1f
AD		 2148 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2149 DRM_INFO("Internal thermal controller %s fan control\n",
2150 (controller->ucFanParameters &
2151 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2152 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
560154e9
AD		 2153 } else if ((controller->ucType ==
2154 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2155 (controller->ucType ==
b0e66414
AD		 2156 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2157 (controller->ucType ==
2158 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
560154e9 2159 DRM_INFO("Special thermal controller config\n");
49f65982 2160 } else {
560154e9
AD		 2161 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2162 pp_lib_thermal_controller_names[controller->ucType],
2163 controller->ucI2cAddress >> 1,
2164 (controller->ucFanParameters &
2165 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2166 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2167 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2168 if (rdev->pm.i2c_bus) {
2169 struct i2c_board_info info = { };
2170 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2171 info.addr = controller->ucI2cAddress >> 1;
2172 strlcpy(info.type, name, sizeof(info.type));
2173 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
c5e8ce61 2174 }
560154e9
AD		 2175 }
2176 }
2177}
c5e8ce61 2178
2feea49a
AD		 2179static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2180 u16 *vddc, u16 *vddci)
560154e9
AD		 2181{
2182 struct radeon_mode_info *mode_info = &rdev->mode_info;
2183 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2184 u8 frev, crev;
2185 u16 data_offset;
2186 union firmware_info *firmware_info;
2feea49a
AD		 2187
2188 *vddc = 0;
2189 *vddci = 0;
678e7dfa 2190
560154e9
AD		 2191 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2192 &frev, &crev, &data_offset)) {
2193 firmware_info =
2194 (union firmware_info *)(mode_info->atom_context->bios +
2195 data_offset);
2feea49a
AD		 2196 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2197 if ((frev == 2) && (crev >= 2))
2198 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
560154e9 2199 }
560154e9
AD		 2200}
2201
2202static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2203 int state_index, int mode_index,
2204 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2205{
2206 int j;
2207 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2208 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2feea49a
AD		 2209 u16 vddc, vddci;
2210
2211 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
560154e9
AD		 2212
2213 rdev->pm.power_state[state_index].misc = misc;
2214 rdev->pm.power_state[state_index].misc2 = misc2;
2215 rdev->pm.power_state[state_index].pcie_lanes =
2216 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2217 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2218 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2219 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2220 rdev->pm.power_state[state_index].type =
2221 POWER_STATE_TYPE_BATTERY;
2222 break;
2223 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2224 rdev->pm.power_state[state_index].type =
2225 POWER_STATE_TYPE_BALANCED;
2226 break;
2227 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2228 rdev->pm.power_state[state_index].type =
2229 POWER_STATE_TYPE_PERFORMANCE;
2230 break;
2231 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2232 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2233 rdev->pm.power_state[state_index].type =
2234 POWER_STATE_TYPE_PERFORMANCE;
2235 break;
2236 }
2237 rdev->pm.power_state[state_index].flags = 0;
2238 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2239 rdev->pm.power_state[state_index].flags |=
2240 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2241 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2242 rdev->pm.power_state[state_index].type =
2243 POWER_STATE_TYPE_DEFAULT;
2244 rdev->pm.default_power_state_index = state_index;
2245 rdev->pm.power_state[state_index].default_clock_mode =
2246 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
9ace9f7b
AD		 2247 if (ASIC_IS_DCE5(rdev)) {
2248 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2249 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2250 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2251 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2feea49a 2252 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
9ace9f7b
AD		 2253 } else {
2254 /* patch the table values with the default slck/mclk from firmware info */
2255 for (j = 0; j < mode_index; j++) {
2256 rdev->pm.power_state[state_index].clock_info[j].mclk =
2257 rdev->clock.default_mclk;
2258 rdev->pm.power_state[state_index].clock_info[j].sclk =
2259 rdev->clock.default_sclk;
2260 if (vddc)
2261 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2262 vddc;
2263 }
560154e9
AD		 2264 }
2265 }
2266}
2267
2268static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2269 int state_index, int mode_index,
2270 union pplib_clock_info *clock_info)
2271{
2272 u32 sclk, mclk;
2273
2274 if (rdev->flags & RADEON_IS_IGP) {
b0e66414
AD		 2275 if (rdev->family >= CHIP_PALM) {
2276 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2277 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2278 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2279 } else {
2280 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2281 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2282 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2283 }
560154e9
AD		 2284 } else if (ASIC_IS_DCE4(rdev)) {
2285 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2286 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2287 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2288 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2289 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2290 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2291 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2292 VOLTAGE_SW;
2293 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
4589433c 2294 le16_to_cpu(clock_info->evergreen.usVDDC);
2feea49a
AD		 2295 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2296 le16_to_cpu(clock_info->evergreen.usVDDCI);
560154e9
AD		 2297 } else {
2298 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2299 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2300 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2301 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2302 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2303 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2304 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2305 VOLTAGE_SW;
2306 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
4589433c 2307 le16_to_cpu(clock_info->r600.usVDDC);
560154e9
AD		 2308 }
2309
2310 if (rdev->flags & RADEON_IS_IGP) {
2311 /* skip invalid modes */
2312 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2313 return false;
2314 } else {
2315 /* skip invalid modes */
2316 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2317 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2318 return false;
2319 }
2320 return true;
2321}
2322
2323static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2324{
2325 struct radeon_mode_info *mode_info = &rdev->mode_info;
2326 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2327 union pplib_power_state *power_state;
2328 int i, j;
2329 int state_index = 0, mode_index = 0;
2330 union pplib_clock_info *clock_info;
2331 bool valid;
2332 union power_info *power_info;
2333 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2334 u16 data_offset;
2335 u8 frev, crev;
2336
2337 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2338 &frev, &crev, &data_offset))
2339 return state_index;
2340 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2341
2342 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
0975b162
AD		 2343 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2344 power_info->pplib.ucNumStates, GFP_KERNEL);
2345 if (!rdev->pm.power_state)
2346 return state_index;
560154e9
AD		 2347 /* first mode is usually default, followed by low to high */
2348 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2349 mode_index = 0;
2350 power_state = (union pplib_power_state *)
2351 (mode_info->atom_context->bios + data_offset +
2352 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2353 i * power_info->pplib.ucStateEntrySize);
2354 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2355 (mode_info->atom_context->bios + data_offset +
2356 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2357 (power_state->v1.ucNonClockStateIndex *
2358 power_info->pplib.ucNonClockSize));
2359 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2360 clock_info = (union pplib_clock_info *)
2361 (mode_info->atom_context->bios + data_offset +
2362 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2363 (power_state->v1.ucClockStateIndices[j] *
2364 power_info->pplib.ucClockInfoSize));
2365 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2366 state_index, mode_index,
2367 clock_info);
2368 if (valid)
2369 mode_index++;
2370 }
2371 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2372 if (mode_index) {
2373 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2374 non_clock_info);
2375 state_index++;
2376 }
2377 }
2378 /* if multiple clock modes, mark the lowest as no display */
2379 for (i = 0; i < state_index; i++) {
2380 if (rdev->pm.power_state[i].num_clock_modes > 1)
2381 rdev->pm.power_state[i].clock_info[0].flags |=
2382 RADEON_PM_MODE_NO_DISPLAY;
2383 }
2384 /* first mode is usually default */
2385 if (rdev->pm.default_power_state_index == -1) {
2386 rdev->pm.power_state[0].type =
2387 POWER_STATE_TYPE_DEFAULT;
2388 rdev->pm.default_power_state_index = 0;
2389 rdev->pm.power_state[0].default_clock_mode =
2390 &rdev->pm.power_state[0].clock_info[0];
2391 }
2392 return state_index;
2393}
2394
b0e66414
AD		 2395static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2396{
2397 struct radeon_mode_info *mode_info = &rdev->mode_info;
2398 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2399 union pplib_power_state *power_state;
2400 int i, j, non_clock_array_index, clock_array_index;
2401 int state_index = 0, mode_index = 0;
2402 union pplib_clock_info *clock_info;
2403 struct StateArray *state_array;
2404 struct ClockInfoArray *clock_info_array;
2405 struct NonClockInfoArray *non_clock_info_array;
2406 bool valid;
2407 union power_info *power_info;
2408 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2409 u16 data_offset;
2410 u8 frev, crev;
2411
2412 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2413 &frev, &crev, &data_offset))
2414 return state_index;
2415 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2416
2417 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2418 state_array = (struct StateArray *)
2419 (mode_info->atom_context->bios + data_offset +
4589433c 2420 le16_to_cpu(power_info->pplib.usStateArrayOffset));
b0e66414
AD		 2421 clock_info_array = (struct ClockInfoArray *)
2422 (mode_info->atom_context->bios + data_offset +
4589433c 2423 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
b0e66414
AD		 2424 non_clock_info_array = (struct NonClockInfoArray *)
2425 (mode_info->atom_context->bios + data_offset +
4589433c 2426 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
0975b162
AD		 2427 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2428 state_array->ucNumEntries, GFP_KERNEL);
2429 if (!rdev->pm.power_state)
2430 return state_index;
b0e66414
AD		 2431 for (i = 0; i < state_array->ucNumEntries; i++) {
2432 mode_index = 0;
2433 power_state = (union pplib_power_state *)&state_array->states[i];
2434 /* XXX this might be an inagua bug... */
2435 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2436 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2437 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2438 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2439 clock_array_index = power_state->v2.clockInfoIndex[j];
2440 /* XXX this might be an inagua bug... */
2441 if (clock_array_index >= clock_info_array->ucNumEntries)
2442 continue;
2443 clock_info = (union pplib_clock_info *)
2444 &clock_info_array->clockInfo[clock_array_index];
2445 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2446 state_index, mode_index,
2447 clock_info);
2448 if (valid)
2449 mode_index++;
2450 }
2451 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2452 if (mode_index) {
2453 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2454 non_clock_info);
2455 state_index++;
2456 }
2457 }
2458 /* if multiple clock modes, mark the lowest as no display */
2459 for (i = 0; i < state_index; i++) {
2460 if (rdev->pm.power_state[i].num_clock_modes > 1)
2461 rdev->pm.power_state[i].clock_info[0].flags |=
2462 RADEON_PM_MODE_NO_DISPLAY;
2463 }
2464 /* first mode is usually default */
2465 if (rdev->pm.default_power_state_index == -1) {
2466 rdev->pm.power_state[0].type =
2467 POWER_STATE_TYPE_DEFAULT;
2468 rdev->pm.default_power_state_index = 0;
2469 rdev->pm.power_state[0].default_clock_mode =
2470 &rdev->pm.power_state[0].clock_info[0];
2471 }
2472 return state_index;
2473}
2474
560154e9
AD		 2475void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2476{
2477 struct radeon_mode_info *mode_info = &rdev->mode_info;
2478 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2479 u16 data_offset;
2480 u8 frev, crev;
2481 int state_index = 0;
2482
2483 rdev->pm.default_power_state_index = -1;
2484
2485 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2486 &frev, &crev, &data_offset)) {
2487 switch (frev) {
2488 case 1:
2489 case 2:
2490 case 3:
2491 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2492 break;
2493 case 4:
2494 case 5:
2495 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2496 break;
b0e66414
AD		 2497 case 6:
2498 state_index = radeon_atombios_parse_power_table_6(rdev);
2499 break;
560154e9
AD		 2500 default:
2501 break;
56278a8e
AD		 2502 }
2503 } else {
0975b162
AD		 2504 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2505 if (rdev->pm.power_state) {
2506 /* add the default mode */
2507 rdev->pm.power_state[state_index].type =
2508 POWER_STATE_TYPE_DEFAULT;
2509 rdev->pm.power_state[state_index].num_clock_modes = 1;
2510 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2511 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2512 rdev->pm.power_state[state_index].default_clock_mode =
2513 &rdev->pm.power_state[state_index].clock_info[0];
2514 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2515 rdev->pm.power_state[state_index].pcie_lanes = 16;
2516 rdev->pm.default_power_state_index = state_index;
2517 rdev->pm.power_state[state_index].flags = 0;
2518 state_index++;
2519 }
56278a8e 2520 }
02b17cc0 2521
56278a8e 2522 rdev->pm.num_power_states = state_index;
9038dfdf 2523
a48b9b4e
AD		 2524 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2525 rdev->pm.current_clock_mode_index = 0;
4d60173f 2526 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 2527}
2528
771fe6b9 2529void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2530{
771fe6b9
JG		 2531 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2532 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2533
2534 args.ucEnable = enable;
2535
2536 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2537}
2538
7433874e
RM		 2539uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2540{
2541 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2542 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2543
2544 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4589433c 2545 return le32_to_cpu(args.ulReturnEngineClock);
7433874e
RM		 2546}
2547
2548uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2549{
2550 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2551 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2552
2553 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4589433c 2554 return le32_to_cpu(args.ulReturnMemoryClock);
7433874e
RM		 2555}
2556
771fe6b9
JG		 2557void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2558 uint32_t eng_clock)
2559{
2560 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2561 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2562
4589433c 2563 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
771fe6b9
JG		 2564
2565 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2566}
2567
2568void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2569 uint32_t mem_clock)
2570{
2571 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2572 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2573
2574 if (rdev->flags & RADEON_IS_IGP)
2575 return;
2576
4589433c 2577 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
771fe6b9
JG		 2578
2579 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2580}
2581
7ac9aa5a
AD		 2582union set_voltage {
2583 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2584 struct _SET_VOLTAGE_PARAMETERS v1;
2585 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2586};
2587
8a83ec5e 2588void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
7ac9aa5a
AD		 2589{
2590 union set_voltage args;
2591 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
8a83ec5e 2592 u8 frev, crev, volt_index = voltage_level;
7ac9aa5a
AD		 2593
2594 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2595 return;
2596
2597 switch (crev) {
2598 case 1:
8a83ec5e 2599 args.v1.ucVoltageType = voltage_type;
7ac9aa5a
AD		 2600 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2601 args.v1.ucVoltageIndex = volt_index;
2602 break;
2603 case 2:
8a83ec5e 2604 args.v2.ucVoltageType = voltage_type;
7ac9aa5a 2605 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
8a83ec5e 2606 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
7ac9aa5a
AD		 2607 break;
2608 default:
2609 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2610 return;
2611 }
2612
2613 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2614}
2615
2616
2617
771fe6b9
JG		 2618void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2619{
2620 struct radeon_device *rdev = dev->dev_private;
2621 uint32_t bios_2_scratch, bios_6_scratch;
2622
2623 if (rdev->family >= CHIP_R600) {
4ce001ab 2624 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2625 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2626 } else {
4ce001ab 2627 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2628 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2629 }
2630
2631 /* let the bios control the backlight */
2632 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2633
2634 /* tell the bios not to handle mode switching */
87364760 2635 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
771fe6b9
JG		 2636
2637 if (rdev->family >= CHIP_R600) {
2638 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2639 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2640 } else {
2641 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2642 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2643 }
2644
2645}
2646
f657c2a7
YZ		 2647void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2648{
2649 uint32_t scratch_reg;
2650 int i;
2651
2652 if (rdev->family >= CHIP_R600)
2653 scratch_reg = R600_BIOS_0_SCRATCH;
2654 else
2655 scratch_reg = RADEON_BIOS_0_SCRATCH;
2656
2657 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2658 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2659}
2660
2661void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2662{
2663 uint32_t scratch_reg;
2664 int i;
2665
2666 if (rdev->family >= CHIP_R600)
2667 scratch_reg = R600_BIOS_0_SCRATCH;
2668 else
2669 scratch_reg = RADEON_BIOS_0_SCRATCH;
2670
2671 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2672 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2673}
2674
771fe6b9
JG		 2675void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2676{
2677 struct drm_device *dev = encoder->dev;
2678 struct radeon_device *rdev = dev->dev_private;
2679 uint32_t bios_6_scratch;
2680
2681 if (rdev->family >= CHIP_R600)
2682 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2683 else
2684 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2685
87364760 2686 if (lock) {
771fe6b9 2687 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
87364760
AD		 2688 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2689 } else {
771fe6b9 2690 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
87364760
AD		 2691 bios_6_scratch |= ATOM_S6_ACC_MODE;
2692 }
771fe6b9
JG		 2693
2694 if (rdev->family >= CHIP_R600)
2695 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2696 else
2697 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2698}
2699
2700/* at some point we may want to break this out into individual functions */
2701void
2702radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2703 struct drm_encoder *encoder,
2704 bool connected)
2705{
2706 struct drm_device *dev = connector->dev;
2707 struct radeon_device *rdev = dev->dev_private;
2708 struct radeon_connector *radeon_connector =
2709 to_radeon_connector(connector);
2710 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2711 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2712
2713 if (rdev->family >= CHIP_R600) {
2714 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2715 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2716 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2717 } else {
2718 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2719 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2720 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2721 }
2722
2723 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2724 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2725 if (connected) {
d9fdaafb 2726 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2727 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2728 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2729 } else {
d9fdaafb 2730 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2731 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2732 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2733 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2734 }
2735 }
2736 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2737 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2738 if (connected) {
d9fdaafb 2739 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2740 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2741 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2742 } else {
d9fdaafb 2743 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2744 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2745 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2746 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2747 }
2748 }
2749 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2750 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2751 if (connected) {
d9fdaafb 2752 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2753 bios_0_scratch |= ATOM_S0_LCD1;
2754 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2755 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2756 } else {
d9fdaafb 2757 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2758 bios_0_scratch &= ~ATOM_S0_LCD1;
2759 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2760 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2761 }
2762 }
2763 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2764 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2765 if (connected) {
d9fdaafb 2766 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2767 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2768 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2769 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2770 } else {
d9fdaafb 2771 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2772 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2773 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2774 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2775 }
2776 }
2777 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2778 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2779 if (connected) {
d9fdaafb 2780 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2781 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2782 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2783 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2784 } else {
d9fdaafb 2785 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2786 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2787 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2788 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2789 }
2790 }
2791 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2792 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2793 if (connected) {
d9fdaafb 2794 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2795 bios_0_scratch |= ATOM_S0_DFP1;
2796 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2797 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2798 } else {
d9fdaafb 2799 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2800 bios_0_scratch &= ~ATOM_S0_DFP1;
2801 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2802 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2803 }
2804 }
2805 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2806 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2807 if (connected) {
d9fdaafb 2808 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2809 bios_0_scratch |= ATOM_S0_DFP2;
2810 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2811 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2812 } else {
d9fdaafb 2813 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2814 bios_0_scratch &= ~ATOM_S0_DFP2;
2815 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2816 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2817 }
2818 }
2819 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2820 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2821 if (connected) {
d9fdaafb 2822 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2823 bios_0_scratch |= ATOM_S0_DFP3;
2824 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2825 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2826 } else {
d9fdaafb 2827 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2828 bios_0_scratch &= ~ATOM_S0_DFP3;
2829 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2830 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2831 }
2832 }
2833 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2834 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2835 if (connected) {
d9fdaafb 2836 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2837 bios_0_scratch |= ATOM_S0_DFP4;
2838 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2839 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2840 } else {
d9fdaafb 2841 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2842 bios_0_scratch &= ~ATOM_S0_DFP4;
2843 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2844 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2845 }
2846 }
2847 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2848 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2849 if (connected) {
d9fdaafb 2850 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2851 bios_0_scratch |= ATOM_S0_DFP5;
2852 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2853 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2854 } else {
d9fdaafb 2855 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2856 bios_0_scratch &= ~ATOM_S0_DFP5;
2857 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2858 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2859 }
2860 }
2861
2862 if (rdev->family >= CHIP_R600) {
2863 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2864 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2865 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2866 } else {
2867 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2868 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2869 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2870 }
2871}
2872
2873void
2874radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2875{
2876 struct drm_device *dev = encoder->dev;
2877 struct radeon_device *rdev = dev->dev_private;
2878 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2879 uint32_t bios_3_scratch;
2880
2881 if (rdev->family >= CHIP_R600)
2882 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2883 else
2884 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2885
2886 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2887 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2888 bios_3_scratch |= (crtc << 18);
2889 }
2890 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2891 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2892 bios_3_scratch |= (crtc << 24);
2893 }
2894 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2895 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2896 bios_3_scratch |= (crtc << 16);
2897 }
2898 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2899 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2900 bios_3_scratch |= (crtc << 20);
2901 }
2902 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2903 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2904 bios_3_scratch |= (crtc << 17);
2905 }
2906 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2907 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2908 bios_3_scratch |= (crtc << 19);
2909 }
2910 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2911 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2912 bios_3_scratch |= (crtc << 23);
2913 }
2914 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2915 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2916 bios_3_scratch |= (crtc << 25);
2917 }
2918
2919 if (rdev->family >= CHIP_R600)
2920 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2921 else
2922 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2923}
2924
2925void
2926radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2927{
2928 struct drm_device *dev = encoder->dev;
2929 struct radeon_device *rdev = dev->dev_private;
2930 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2931 uint32_t bios_2_scratch;
2932
2933 if (rdev->family >= CHIP_R600)
2934 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2935 else
2936 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2937
2938 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2939 if (on)
2940 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2941 else
2942 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2943 }
2944 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2945 if (on)
2946 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2947 else
2948 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2949 }
2950 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2951 if (on)
2952 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2953 else
2954 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2955 }
2956 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2957 if (on)
2958 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2959 else
2960 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2961 }
2962 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2963 if (on)
2964 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2965 else
2966 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2967 }
2968 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2969 if (on)
2970 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2971 else
2972 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2973 }
2974 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2975 if (on)
2976 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2977 else
2978 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2979 }
2980 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2981 if (on)
2982 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2983 else
2984 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2985 }
2986 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2987 if (on)
2988 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2989 else
2990 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2991 }
2992 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2993 if (on)
2994 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2995 else
2996 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2997 }
2998
2999 if (rdev->family >= CHIP_R600)
3000 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3001 else
3002 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3003}
kernel source for telekom puls (alcatel/mediatek)