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drm/radeon/kms: fix num_banks tiling config for fusion
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
5137ee94
AD		 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
771fe6b9
JG		 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
5137ee94 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
36868bda 40 uint32_t supported_device, u16 caps);
771fe6b9
JG		 41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
5137ee94 49 uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
5137ee94 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
eed45b30
AD		 65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
771fe6b9 67{
771fe6b9 68 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 73 uint16_t data_offset, size;
74 int i, num_indices;
771fe6b9
JG		 75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
95beb690 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
95beb690
AD		 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 86 gpio = &i2c_info->asGPIO_Info[i];
87
ea39302b
AD		 88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
4589433c 91 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
ea39302b
AD		 92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
3074adc8
AD		 101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
103 if ((i == 4) &&
4589433c 104 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
3074adc8
AD		 105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
107 }
108
a084e6ee
AD		 109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
126
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
129 else
130 i2c.hw_capable = false;
131
132 if (gpio->sucI2cId.ucAccess == 0xa0)
133 i2c.mm_i2c = true;
134 else
135 i2c.mm_i2c = false;
136
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
138
f376b94f
AD		 139 if (i2c.mask_clk_reg)
140 i2c.valid = true;
a084e6ee
AD		 141 break;
142 }
d3f420d1
AD		 143 }
144 }
771fe6b9
JG		 145
146 return i2c;
147}
148
f376b94f
AD		 149void radeon_atombios_i2c_init(struct radeon_device *rdev)
150{
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
157 int i, num_indices;
158 char stmp[32];
159
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
161
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
164
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
167
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
170 i2c.valid = false;
ea39302b
AD		 171
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev)) {
174 if ((i == 7) &&
4589433c 175 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
ea39302b
AD		 176 (gpio->sucI2cId.ucAccess == 0)) {
177 gpio->sucI2cId.ucAccess = 0x97;
178 gpio->ucDataMaskShift = 8;
179 gpio->ucDataEnShift = 8;
180 gpio->ucDataY_Shift = 8;
181 gpio->ucDataA_Shift = 8;
182 }
183 }
184
3074adc8
AD		 185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
187 if ((i == 4) &&
4589433c 188 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
3074adc8
AD		 189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
191 }
192
f376b94f
AD		 193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
204 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
209
210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
211 i2c.hw_capable = true;
212 else
213 i2c.hw_capable = false;
214
215 if (gpio->sucI2cId.ucAccess == 0xa0)
216 i2c.mm_i2c = true;
217 else
218 i2c.mm_i2c = false;
219
220 i2c.i2c_id = gpio->sucI2cId.ucAccess;
221
222 if (i2c.mask_clk_reg) {
223 i2c.valid = true;
224 sprintf(stmp, "0x%x", i2c.i2c_id);
225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
226 }
227 }
228 }
229}
230
eed45b30
AD		 231static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
232 u8 id)
233{
234 struct atom_context *ctx = rdev->mode_info.atom_context;
235 struct radeon_gpio_rec gpio;
236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
237 struct _ATOM_GPIO_PIN_LUT *gpio_info;
238 ATOM_GPIO_PIN_ASSIGNMENT *pin;
239 u16 data_offset, size;
240 int i, num_indices;
241
242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
243 gpio.valid = false;
244
a084e6ee
AD		 245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 247
a084e6ee
AD		 248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 250
a084e6ee
AD		 251 for (i = 0; i < num_indices; i++) {
252 pin = &gpio_info->asGPIO_Pin[i];
253 if (id == pin->ucGPIO_ID) {
254 gpio.id = pin->ucGPIO_ID;
4589433c 255 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
a084e6ee
AD		 256 gpio.mask = (1 << pin->ucGpioPinBitShift);
257 gpio.valid = true;
258 break;
259 }
eed45b30
AD		 260 }
261 }
262
263 return gpio;
264}
265
266static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
267 struct radeon_gpio_rec *gpio)
268{
269 struct radeon_hpd hpd;
bcc1c2a1
AD		 270 u32 reg;
271
1d978dac
JD		 272 memset(&hpd, 0, sizeof(struct radeon_hpd));
273
bcc1c2a1
AD		 274 if (ASIC_IS_DCE4(rdev))
275 reg = EVERGREEN_DC_GPIO_HPD_A;
276 else
277 reg = AVIVO_DC_GPIO_HPD_A;
278
eed45b30 279 hpd.gpio = *gpio;
bcc1c2a1 280 if (gpio->reg == reg) {
eed45b30
AD		 281 switch(gpio->mask) {
282 case (1 << 0):
283 hpd.hpd = RADEON_HPD_1;
284 break;
285 case (1 << 8):
286 hpd.hpd = RADEON_HPD_2;
287 break;
288 case (1 << 16):
289 hpd.hpd = RADEON_HPD_3;
290 break;
291 case (1 << 24):
292 hpd.hpd = RADEON_HPD_4;
293 break;
294 case (1 << 26):
295 hpd.hpd = RADEON_HPD_5;
296 break;
297 case (1 << 28):
298 hpd.hpd = RADEON_HPD_6;
299 break;
300 default:
301 hpd.hpd = RADEON_HPD_NONE;
302 break;
303 }
304 } else
305 hpd.hpd = RADEON_HPD_NONE;
306 return hpd;
307}
308
771fe6b9
JG		 309static bool radeon_atom_apply_quirks(struct drm_device *dev,
310 uint32_t supported_device,
311 int *connector_type,
848577ee 312 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 313 uint16_t *line_mux,
314 struct radeon_hpd *hpd)
771fe6b9
JG		 315{
316
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev->pdev->device == 0x791e) &&
319 (dev->pdev->subsystem_vendor == 0x1043) &&
320 (dev->pdev->subsystem_device == 0x826d)) {
321 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
323 *connector_type = DRM_MODE_CONNECTOR_DVID;
324 }
325
c86a9038
AD		 326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x1849) &&
329 (dev->pdev->subsystem_device == 0x7941)) {
330 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
331 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
332 *connector_type = DRM_MODE_CONNECTOR_DVID;
333 }
334
f36fce0f
AD		 335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev->pdev->device == 0x796e) &&
337 (dev->pdev->subsystem_vendor == 0x1462) &&
338 (dev->pdev->subsystem_device == 0x7302)) {
339 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
340 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
341 return false;
342 }
343
771fe6b9
JG		 344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev->pdev->device == 0x7941) &&
346 (dev->pdev->subsystem_vendor == 0x147b) &&
347 (dev->pdev->subsystem_device == 0x2412)) {
348 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
349 return false;
350 }
351
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev->pdev->device == 0x5653) &&
354 (dev->pdev->subsystem_vendor == 0x1462) &&
355 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 356 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 357 i2c_bus->valid = false;
848577ee
AD		 358 *line_mux = 53;
359 }
771fe6b9
JG		 360 }
361
4e3f9b78
AD		 362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev->pdev->device == 0x7146) &&
364 (dev->pdev->subsystem_vendor == 0x17af) &&
365 (dev->pdev->subsystem_device == 0x2058)) {
366 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
367 return false;
368 }
369
aa1a750e
DA		 370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev->pdev->device == 0x7142) &&
372 (dev->pdev->subsystem_vendor == 0x1458) &&
373 (dev->pdev->subsystem_device == 0x2134)) {
374 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
375 return false;
376 }
377
378
771fe6b9
JG		 379 /* Funky macbooks */
380 if ((dev->pdev->device == 0x71C5) &&
381 (dev->pdev->subsystem_vendor == 0x106b) &&
382 (dev->pdev->subsystem_device == 0x0080)) {
383 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
384 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
385 return false;
e1e8a5dd
AD		 386 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
387 *line_mux = 0x90;
771fe6b9
JG		 388 }
389
be23da8a
AD		 390 /* mac rv630, rv730, others */
391 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
392 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
393 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
394 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
f598aa75
AD		 395 }
396
771fe6b9
JG		 397 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
398 if ((dev->pdev->device == 0x9598) &&
399 (dev->pdev->subsystem_vendor == 0x1043) &&
400 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 402 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 403 }
404 }
405
e153b70b
AD		 406 /* ASUS HD 3600 board lists the DVI port as HDMI */
407 if ((dev->pdev->device == 0x9598) &&
408 (dev->pdev->subsystem_vendor == 0x1043) &&
409 (dev->pdev->subsystem_device == 0x01e4)) {
410 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
411 *connector_type = DRM_MODE_CONNECTOR_DVII;
412 }
413 }
414
705af9c7
AD		 415 /* ASUS HD 3450 board lists the DVI port as HDMI */
416 if ((dev->pdev->device == 0x95C5) &&
417 (dev->pdev->subsystem_vendor == 0x1043) &&
418 (dev->pdev->subsystem_device == 0x01e2)) {
419 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 420 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 421 }
422 }
423
705af9c7
AD		 424 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
425 * HDMI + VGA reporting as HDMI
426 */
427 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
428 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
429 *connector_type = DRM_MODE_CONNECTOR_VGA;
430 *line_mux = 0;
431 }
432 }
433
4f87af46 434 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
2f299d5d
AD		 435 * on the laptop and a DVI port on the docking station and
436 * both share the same encoder, hpd pin, and ddc line.
437 * So while the bios table is technically correct,
438 * we drop the DVI port here since xrandr has no concept of
439 * encoders and will try and drive both connectors
440 * with different crtcs which isn't possible on the hardware
441 * side and leaves no crtcs for LVDS or VGA.
442 */
4f87af46 443 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
3e5f8ff3
AD		 444 (dev->pdev->subsystem_vendor == 0x1025) &&
445 (dev->pdev->subsystem_device == 0x013c)) {
446 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be 447 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
2f299d5d 448 /* actually it's a DVI-D port not DVI-I */
3e5f8ff3 449 *connector_type = DRM_MODE_CONNECTOR_DVID;
2f299d5d 450 return false;
9ea2c4be 451 }
3e5f8ff3
AD		 452 }
453
efa8450f
DA		 454 /* XFX Pine Group device rv730 reports no VGA DDC lines
455 * even though they are wired up to record 0x93
456 */
457 if ((dev->pdev->device == 0x9498) &&
458 (dev->pdev->subsystem_vendor == 0x1682) &&
459 (dev->pdev->subsystem_device == 0x2452)) {
460 struct radeon_device *rdev = dev->dev_private;
461 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
462 }
771fe6b9
JG		 463 return true;
464}
465
466const int supported_devices_connector_convert[] = {
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_VGA,
469 DRM_MODE_CONNECTOR_DVII,
470 DRM_MODE_CONNECTOR_DVID,
471 DRM_MODE_CONNECTOR_DVIA,
472 DRM_MODE_CONNECTOR_SVIDEO,
473 DRM_MODE_CONNECTOR_Composite,
474 DRM_MODE_CONNECTOR_LVDS,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_HDMIA,
478 DRM_MODE_CONNECTOR_HDMIB,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_9PinDIN,
482 DRM_MODE_CONNECTOR_DisplayPort
483};
484
b75fad06
AD		 485const uint16_t supported_devices_connector_object_id_convert[] = {
486 CONNECTOR_OBJECT_ID_NONE,
487 CONNECTOR_OBJECT_ID_VGA,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE,
492 CONNECTOR_OBJECT_ID_SVIDEO,
493 CONNECTOR_OBJECT_ID_LVDS,
494 CONNECTOR_OBJECT_ID_9PIN_DIN,
495 CONNECTOR_OBJECT_ID_9PIN_DIN,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
499 CONNECTOR_OBJECT_ID_SVIDEO
500};
501
771fe6b9
JG		 502const int object_connector_convert[] = {
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DVII,
505 DRM_MODE_CONNECTOR_DVII,
506 DRM_MODE_CONNECTOR_DVID,
507 DRM_MODE_CONNECTOR_DVID,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_Composite,
510 DRM_MODE_CONNECTOR_SVIDEO,
511 DRM_MODE_CONNECTOR_Unknown,
705af9c7 512 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 513 DRM_MODE_CONNECTOR_9PinDIN,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_HDMIA,
516 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 517 DRM_MODE_CONNECTOR_LVDS,
518 DRM_MODE_CONNECTOR_9PinDIN,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 522 DRM_MODE_CONNECTOR_DisplayPort,
523 DRM_MODE_CONNECTOR_eDP,
524 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 525};
526
527bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
528{
529 struct radeon_device *rdev = dev->dev_private;
530 struct radeon_mode_info *mode_info = &rdev->mode_info;
531 struct atom_context *ctx = mode_info->atom_context;
532 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 533 u16 size, data_offset;
534 u8 frev, crev;
771fe6b9 535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
36868bda 536 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
26b5bc98 537 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
539 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 540 int i, j, k, path_size, device_support;
771fe6b9 541 int connector_type;
eed45b30 542 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9 543 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 544 struct radeon_router router;
eed45b30
AD		 545 struct radeon_gpio_rec gpio;
546 struct radeon_hpd hpd;
547
a084e6ee 548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 549 return false;
550
551 if (crev < 2)
552 return false;
553
554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usDisplayPathTableOffset));
558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
36868bda
AD		 561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
562 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
26b5bc98
AD		 564 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 567 device_support = le16_to_cpu(obj_header->usDeviceSupport);
568
569 path_size = 0;
570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
571 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
572 ATOM_DISPLAY_OBJECT_PATH *path;
573 addr += path_size;
574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
575 path_size += le16_to_cpu(path->usSize);
5137ee94 576
771fe6b9
JG		 577 if (device_support & le16_to_cpu(path->usDeviceTag)) {
578 uint8_t con_obj_id, con_obj_num, con_obj_type;
579
580 con_obj_id =
581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
582 >> OBJECT_ID_SHIFT;
583 con_obj_num =
584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
585 >> ENUM_ID_SHIFT;
586 con_obj_type =
587 (le16_to_cpu(path->usConnObjectId) &
588 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
589
4bbd4973
DA		 590 /* TODO CV support */
591 if (le16_to_cpu(path->usDeviceTag) ==
592 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 593 continue;
594
ee59f2b4
AD		 595 /* IGP chips */
596 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 597 (con_obj_id ==
598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
599 uint16_t igp_offset = 0;
600 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
601
602 index =
603 GetIndexIntoMasterTable(DATA,
604 IntegratedSystemInfo);
605
a084e6ee
AD		 606 if (atom_parse_data_header(ctx, index, &size, &frev,
607 &crev, &igp_offset)) {
608
609 if (crev >= 2) {
610 igp_obj =
611 (ATOM_INTEGRATED_SYSTEM_INFO_V2
612 *) (ctx->bios + igp_offset);
613
614 if (igp_obj) {
615 uint32_t slot_config, ct;
616
617 if (con_obj_num == 1)
618 slot_config =
619 igp_obj->
620 ulDDISlot1Config;
621 else
622 slot_config =
623 igp_obj->
624 ulDDISlot2Config;
625
626 ct = (slot_config >> 16) & 0xff;
627 connector_type =
628 object_connector_convert
629 [ct];
630 connector_object_id = ct;
631 igp_lane_info =
632 slot_config & 0xffff;
633 } else
634 continue;
771fe6b9
JG		 635 } else
636 continue;
a084e6ee
AD		 637 } else {
638 igp_lane_info = 0;
639 connector_type =
640 object_connector_convert[con_obj_id];
641 connector_object_id = con_obj_id;
642 }
771fe6b9
JG		 643 } else {
644 igp_lane_info = 0;
645 connector_type =
646 object_connector_convert[con_obj_id];
b75fad06 647 connector_object_id = con_obj_id;
771fe6b9
JG		 648 }
649
650 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
651 continue;
652
bdd91b2b
TW		 653 router.ddc_valid = false;
654 router.cd_valid = false;
26b5bc98
AD		 655 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
656 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 657
26b5bc98 658 grph_obj_id =
771fe6b9
JG		 659 (le16_to_cpu(path->usGraphicObjIds[j]) &
660 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 661 grph_obj_num =
771fe6b9
JG		 662 (le16_to_cpu(path->usGraphicObjIds[j]) &
663 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 664 grph_obj_type =
771fe6b9
JG		 665 (le16_to_cpu(path->usGraphicObjIds[j]) &
666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
667
26b5bc98 668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
36868bda
AD		 669 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
670 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
671 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
672 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
673 (ctx->bios + data_offset +
674 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
675 ATOM_ENCODER_CAP_RECORD *cap_record;
676 u16 caps = 0;
771fe6b9 677
97ea530f
JL		 678 while (record->ucRecordSize > 0 &&
679 record->ucRecordType > 0 &&
36868bda
AD		 680 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
681 switch (record->ucRecordType) {
682 case ATOM_ENCODER_CAP_RECORD_TYPE:
683 cap_record =(ATOM_ENCODER_CAP_RECORD *)
684 record;
685 caps = le16_to_cpu(cap_record->usEncoderCap);
686 break;
687 }
688 record = (ATOM_COMMON_RECORD_HEADER *)
689 ((char *)record + record->ucRecordSize);
690 }
691 radeon_add_atom_encoder(dev,
692 encoder_obj,
693 le16_to_cpu
694 (path->
695 usDeviceTag),
696 caps);
697 }
698 }
26b5bc98 699 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
26b5bc98 700 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
bdd91b2b 701 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
26b5bc98
AD		 702 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
703 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
704 (ctx->bios + data_offset +
705 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
706 ATOM_I2C_RECORD *i2c_record;
707 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
708 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
fb939dfc 709 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
26b5bc98
AD		 710 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
711 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
712 (ctx->bios + data_offset +
713 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
714 int enum_id;
715
716 router.router_id = router_obj_id;
717 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
718 enum_id++) {
719 if (le16_to_cpu(path->usConnObjectId) ==
720 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
721 break;
722 }
723
97ea530f
JL		 724 while (record->ucRecordSize > 0 &&
725 record->ucRecordType > 0 &&
26b5bc98
AD		 726 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
727 switch (record->ucRecordType) {
728 case ATOM_I2C_RECORD_TYPE:
729 i2c_record =
730 (ATOM_I2C_RECORD *)
731 record;
732 i2c_config =
733 (ATOM_I2C_ID_CONFIG_ACCESS *)
734 &i2c_record->sucI2cId;
735 router.i2c_info =
736 radeon_lookup_i2c_gpio(rdev,
737 i2c_config->
738 ucAccess);
739 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
740 break;
741 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
742 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
743 record;
fb939dfc
AD		 744 router.ddc_valid = true;
745 router.ddc_mux_type = ddc_path->ucMuxType;
746 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
747 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
748 break;
749 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
750 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
751 record;
752 router.cd_valid = true;
753 router.cd_mux_type = cd_path->ucMuxType;
754 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
755 router.cd_mux_state = cd_path->ucMuxState[enum_id];
26b5bc98
AD		 756 break;
757 }
758 record = (ATOM_COMMON_RECORD_HEADER *)
759 ((char *)record + record->ucRecordSize);
760 }
761 }
762 }
771fe6b9
JG		 763 }
764 }
765
eed45b30 766 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 767 ddc_bus.valid = false;
768 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 769 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 770 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 771 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
772 if (le16_to_cpu(path->usConnObjectId) ==
773 le16_to_cpu(con_obj->asObjects[j].
774 usObjectID)) {
775 ATOM_COMMON_RECORD_HEADER
776 *record =
777 (ATOM_COMMON_RECORD_HEADER
778 *)
779 (ctx->bios + data_offset +
780 le16_to_cpu(con_obj->
781 asObjects[j].
782 usRecordOffset));
783 ATOM_I2C_RECORD *i2c_record;
eed45b30 784 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 785 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 786
97ea530f
JL		 787 while (record->ucRecordSize > 0 &&
788 record->ucRecordType > 0 &&
789 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 790 switch (record->ucRecordType) {
771fe6b9
JG		 791 case ATOM_I2C_RECORD_TYPE:
792 i2c_record =
eed45b30
AD		 793 (ATOM_I2C_RECORD *)
794 record;
d3f420d1
AD		 795 i2c_config =
796 (ATOM_I2C_ID_CONFIG_ACCESS *)
797 &i2c_record->sucI2cId;
eed45b30 798 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 799 i2c_config->
800 ucAccess);
eed45b30
AD		 801 break;
802 case ATOM_HPD_INT_RECORD_TYPE:
803 hpd_record =
804 (ATOM_HPD_INT_RECORD *)
805 record;
806 gpio = radeon_lookup_gpio(rdev,
807 hpd_record->ucHPDIntGPIOID);
808 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
809 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 810 break;
811 }
812 record =
813 (ATOM_COMMON_RECORD_HEADER
814 *) ((char *)record
815 +
816 record->
817 ucRecordSize);
818 }
819 break;
820 }
821 }
eed45b30 822 }
771fe6b9 823
bcc1c2a1 824 /* needed for aux chan transactions */
8e36ed00 825 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 826
705af9c7
AD		 827 conn_id = le16_to_cpu(path->usConnObjectId);
828
829 if (!radeon_atom_apply_quirks
830 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 831 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 832 continue;
833
771fe6b9 834 radeon_add_atom_connector(dev,
705af9c7 835 conn_id,
771fe6b9
JG		 836 le16_to_cpu(path->
837 usDeviceTag),
838 connector_type, &ddc_bus,
5137ee94 839 igp_lane_info,
eed45b30 840 connector_object_id,
26b5bc98
AD		 841 &hpd,
842 &router);
771fe6b9
JG		 843
844 }
845 }
846
847 radeon_link_encoder_connector(dev);
848
849 return true;
850}
851
b75fad06
AD		 852static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
853 int connector_type,
854 uint16_t devices)
855{
856 struct radeon_device *rdev = dev->dev_private;
857
858 if (rdev->flags & RADEON_IS_IGP) {
859 return supported_devices_connector_object_id_convert
860 [connector_type];
861 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
862 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
863 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
864 struct radeon_mode_info *mode_info = &rdev->mode_info;
865 struct atom_context *ctx = mode_info->atom_context;
866 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
867 uint16_t size, data_offset;
868 uint8_t frev, crev;
869 ATOM_XTMDS_INFO *xtmds;
870
a084e6ee
AD		 871 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
872 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 873
a084e6ee
AD		 874 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
879 } else {
880 if (connector_type == DRM_MODE_CONNECTOR_DVII)
881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
882 else
883 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
884 }
885 } else
886 return supported_devices_connector_object_id_convert
887 [connector_type];
b75fad06
AD		 888 } else {
889 return supported_devices_connector_object_id_convert
890 [connector_type];
891 }
892}
893
771fe6b9
JG		 894struct bios_connector {
895 bool valid;
705af9c7 896 uint16_t line_mux;
771fe6b9
JG		 897 uint16_t devices;
898 int connector_type;
899 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 900 struct radeon_hpd hpd;
771fe6b9
JG		 901};
902
903bool radeon_get_atom_connector_info_from_supported_devices_table(struct
904 drm_device
905 *dev)
906{
907 struct radeon_device *rdev = dev->dev_private;
908 struct radeon_mode_info *mode_info = &rdev->mode_info;
909 struct atom_context *ctx = mode_info->atom_context;
910 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
911 uint16_t size, data_offset;
912 uint8_t frev, crev;
913 uint16_t device_support;
914 uint8_t dac;
915 union atom_supported_devices *supported_devices;
eed45b30 916 int i, j, max_device;
f49d273d
PB		 917 struct bios_connector *bios_connectors;
918 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 919 struct radeon_router router;
920
fb939dfc
AD		 921 router.ddc_valid = false;
922 router.cd_valid = false;
771fe6b9 923
f49d273d
PB		 924 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
925 if (!bios_connectors)
926 return false;
927
928 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
929 &data_offset)) {
930 kfree(bios_connectors);
a084e6ee 931 return false;
f49d273d 932 }
771fe6b9
JG		 933
934 supported_devices =
935 (union atom_supported_devices *)(ctx->bios + data_offset);
936
937 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
938
eed45b30
AD		 939 if (frev > 1)
940 max_device = ATOM_MAX_SUPPORTED_DEVICE;
941 else
942 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
943
944 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 945 ATOM_CONNECTOR_INFO_I2C ci =
946 supported_devices->info.asConnInfo[i];
947
948 bios_connectors[i].valid = false;
949
950 if (!(device_support & (1 << i))) {
951 continue;
952 }
953
954 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 955 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 956 continue;
957 }
958
771fe6b9
JG		 959 bios_connectors[i].connector_type =
960 supported_devices_connector_convert[ci.sucConnectorInfo.
961 sbfAccess.
962 bfConnectorType];
963
964 if (bios_connectors[i].connector_type ==
965 DRM_MODE_CONNECTOR_Unknown)
966 continue;
967
968 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
969
d3f420d1
AD		 970 bios_connectors[i].line_mux =
971 ci.sucI2cId.ucAccess;
771fe6b9
JG		 972
973 /* give tv unique connector ids */
974 if (i == ATOM_DEVICE_TV1_INDEX) {
975 bios_connectors[i].ddc_bus.valid = false;
976 bios_connectors[i].line_mux = 50;
977 } else if (i == ATOM_DEVICE_TV2_INDEX) {
978 bios_connectors[i].ddc_bus.valid = false;
979 bios_connectors[i].line_mux = 51;
980 } else if (i == ATOM_DEVICE_CV_INDEX) {
981 bios_connectors[i].ddc_bus.valid = false;
982 bios_connectors[i].line_mux = 52;
983 } else
984 bios_connectors[i].ddc_bus =
eed45b30
AD		 985 radeon_lookup_i2c_gpio(rdev,
986 bios_connectors[i].line_mux);
987
988 if ((crev > 1) && (frev > 1)) {
989 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
990 switch (isb) {
991 case 0x4:
992 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
993 break;
994 case 0xa:
995 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
996 break;
997 default:
998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
999 break;
1000 }
1001 } else {
1002 if (i == ATOM_DEVICE_DFP1_INDEX)
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004 else if (i == ATOM_DEVICE_DFP2_INDEX)
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1006 else
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1008 }
771fe6b9
JG		 1009
1010 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1011 * shared with a DVI port, we'll pick up the DVI connector when we
1012 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1013 */
1014 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1015 bios_connectors[i].connector_type =
1016 DRM_MODE_CONNECTOR_VGA;
1017
1018 if (!radeon_atom_apply_quirks
1019 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 1020 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1021 &bios_connectors[i].hpd))
771fe6b9
JG		 1022 continue;
1023
1024 bios_connectors[i].valid = true;
1025 bios_connectors[i].devices = (1 << i);
1026
1027 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1028 radeon_add_atom_encoder(dev,
5137ee94 1029 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1030 (1 << i),
1031 dac),
36868bda
AD		 1032 (1 << i),
1033 0);
771fe6b9
JG		 1034 else
1035 radeon_add_legacy_encoder(dev,
5137ee94 1036 radeon_get_encoder_enum(dev,
f56cd64f 1037 (1 << i),
771fe6b9
JG		 1038 dac),
1039 (1 << i));
1040 }
1041
1042 /* combine shared connectors */
eed45b30 1043 for (i = 0; i < max_device; i++) {
771fe6b9 1044 if (bios_connectors[i].valid) {
eed45b30 1045 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 1046 if (bios_connectors[j].valid && (i != j)) {
1047 if (bios_connectors[i].line_mux ==
1048 bios_connectors[j].line_mux) {
f56cd64f
AD		 1049 /* make sure not to combine LVDS */
1050 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[i].line_mux = 53;
1052 bios_connectors[i].ddc_bus.valid = false;
1053 continue;
1054 }
1055 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1056 bios_connectors[j].line_mux = 53;
1057 bios_connectors[j].ddc_bus.valid = false;
1058 continue;
1059 }
1060 /* combine analog and digital for DVI-I */
1061 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1063 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1065 bios_connectors[i].devices |=
1066 bios_connectors[j].devices;
1067 bios_connectors[i].connector_type =
1068 DRM_MODE_CONNECTOR_DVII;
1069 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 1070 bios_connectors[i].hpd =
1071 bios_connectors[j].hpd;
f56cd64f 1072 bios_connectors[j].valid = false;
771fe6b9
JG		 1073 }
1074 }
1075 }
1076 }
1077 }
1078 }
1079
1080 /* add the connectors */
eed45b30 1081 for (i = 0; i < max_device; i++) {
b75fad06
AD		 1082 if (bios_connectors[i].valid) {
1083 uint16_t connector_object_id =
1084 atombios_get_connector_object_id(dev,
1085 bios_connectors[i].connector_type,
1086 bios_connectors[i].devices);
771fe6b9
JG		 1087 radeon_add_atom_connector(dev,
1088 bios_connectors[i].line_mux,
1089 bios_connectors[i].devices,
1090 bios_connectors[i].
1091 connector_type,
1092 &bios_connectors[i].ddc_bus,
5137ee94 1093 0,
eed45b30 1094 connector_object_id,
26b5bc98
AD		 1095 &bios_connectors[i].hpd,
1096 &router);
b75fad06 1097 }
771fe6b9
JG		 1098 }
1099
1100 radeon_link_encoder_connector(dev);
1101
f49d273d 1102 kfree(bios_connectors);
771fe6b9
JG		 1103 return true;
1104}
1105
1106union firmware_info {
1107 ATOM_FIRMWARE_INFO info;
1108 ATOM_FIRMWARE_INFO_V1_2 info_12;
1109 ATOM_FIRMWARE_INFO_V1_3 info_13;
1110 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1111 ATOM_FIRMWARE_INFO_V2_1 info_21;
f82b3ddc 1112 ATOM_FIRMWARE_INFO_V2_2 info_22;
771fe6b9
JG		 1113};
1114
1115bool radeon_atom_get_clock_info(struct drm_device *dev)
1116{
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1120 union firmware_info *firmware_info;
1121 uint8_t frev, crev;
1122 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1123 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1124 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1125 struct radeon_pll *spll = &rdev->clock.spll;
1126 struct radeon_pll *mpll = &rdev->clock.mpll;
1127 uint16_t data_offset;
1128
a084e6ee
AD		 1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 firmware_info =
1132 (union firmware_info *)(mode_info->atom_context->bios +
1133 data_offset);
771fe6b9
JG		 1134 /* pixel clocks */
1135 p1pll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 p1pll->reference_div = 0;
1138
bc293e58
MF		 1139 if (crev < 2)
1140 p1pll->pll_out_min =
1141 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1142 else
1143 p1pll->pll_out_min =
1144 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1145 p1pll->pll_out_max =
1146 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1147
86cb2bbf
AD		 1148 if (crev >= 4) {
1149 p1pll->lcd_pll_out_min =
1150 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1151 if (p1pll->lcd_pll_out_min == 0)
1152 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1153 p1pll->lcd_pll_out_max =
1154 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_max == 0)
1156 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1157 } else {
1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160 }
1161
771fe6b9
JG		 1162 if (p1pll->pll_out_min == 0) {
1163 if (ASIC_IS_AVIVO(rdev))
1164 p1pll->pll_out_min = 64800;
1165 else
1166 p1pll->pll_out_min = 20000;
1167 }
1168
1169 p1pll->pll_in_min =
1170 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1171 p1pll->pll_in_max =
1172 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1173
1174 *p2pll = *p1pll;
1175
1176 /* system clock */
f82b3ddc
AD		 1177 if (ASIC_IS_DCE4(rdev))
1178 spll->reference_freq =
1179 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1180 else
1181 spll->reference_freq =
1182 le16_to_cpu(firmware_info->info.usReferenceClock);
771fe6b9
JG		 1183 spll->reference_div = 0;
1184
1185 spll->pll_out_min =
1186 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1187 spll->pll_out_max =
1188 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1189
1190 /* ??? */
1191 if (spll->pll_out_min == 0) {
1192 if (ASIC_IS_AVIVO(rdev))
1193 spll->pll_out_min = 64800;
1194 else
1195 spll->pll_out_min = 20000;
1196 }
1197
1198 spll->pll_in_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1200 spll->pll_in_max =
1201 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1202
1203 /* memory clock */
f82b3ddc
AD		 1204 if (ASIC_IS_DCE4(rdev))
1205 mpll->reference_freq =
1206 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1207 else
1208 mpll->reference_freq =
1209 le16_to_cpu(firmware_info->info.usReferenceClock);
771fe6b9
JG		 1210 mpll->reference_div = 0;
1211
1212 mpll->pll_out_min =
1213 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1214 mpll->pll_out_max =
1215 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1216
1217 /* ??? */
1218 if (mpll->pll_out_min == 0) {
1219 if (ASIC_IS_AVIVO(rdev))
1220 mpll->pll_out_min = 64800;
1221 else
1222 mpll->pll_out_min = 20000;
1223 }
1224
1225 mpll->pll_in_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1227 mpll->pll_in_max =
1228 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1229
1230 rdev->clock.default_sclk =
1231 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1232 rdev->clock.default_mclk =
1233 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1234
bcc1c2a1
AD		 1235 if (ASIC_IS_DCE4(rdev)) {
1236 rdev->clock.default_dispclk =
1237 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
f82b3ddc
AD		 1238 if (rdev->clock.default_dispclk == 0) {
1239 if (ASIC_IS_DCE5(rdev))
1240 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1241 else
1242 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1243 }
bcc1c2a1
AD		 1244 rdev->clock.dp_extclk =
1245 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1246 }
1247 *dcpll = *p1pll;
1248
b20f9bef
AD		 1249 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1250 if (rdev->clock.max_pixel_clock == 0)
1251 rdev->clock.max_pixel_clock = 40000;
1252
771fe6b9
JG		 1253 return true;
1254 }
bcc1c2a1 1255
771fe6b9
JG		 1256 return false;
1257}
1258
06b6476d
AD		 1259union igp_info {
1260 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1261 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1262};
1263
1264bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1265{
1266 struct radeon_mode_info *mode_info = &rdev->mode_info;
1267 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1268 union igp_info *igp_info;
1269 u8 frev, crev;
1270 u16 data_offset;
1271
4c70b2ea
AD		 1272 /* sideport is AMD only */
1273 if (rdev->family == CHIP_RS600)
1274 return false;
1275
a084e6ee
AD		 1276 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1277 &frev, &crev, &data_offset)) {
1278 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1279 data_offset);
06b6476d
AD		 1280 switch (crev) {
1281 case 1:
4589433c 1282 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
4c70b2ea 1283 return true;
06b6476d
AD		 1284 break;
1285 case 2:
4589433c 1286 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
06b6476d
AD		 1287 return true;
1288 break;
1289 default:
1290 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1291 break;
1292 }
1293 }
1294 return false;
1295}
1296
445282db
DA		 1297bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1298 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1299{
1300 struct drm_device *dev = encoder->base.dev;
1301 struct radeon_device *rdev = dev->dev_private;
1302 struct radeon_mode_info *mode_info = &rdev->mode_info;
1303 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1304 uint16_t data_offset;
1305 struct _ATOM_TMDS_INFO *tmds_info;
1306 uint8_t frev, crev;
1307 uint16_t maxfreq;
1308 int i;
771fe6b9 1309
a084e6ee
AD		 1310 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1311 &frev, &crev, &data_offset)) {
1312 tmds_info =
1313 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1314 data_offset);
771fe6b9 1315
771fe6b9
JG		 1316 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1317 for (i = 0; i < 4; i++) {
1318 tmds->tmds_pll[i].freq =
1319 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1320 tmds->tmds_pll[i].value =
1321 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1322 tmds->tmds_pll[i].value |=
1323 (tmds_info->asMiscInfo[i].
1324 ucPLL_VCO_Gain & 0x3f) << 6;
1325 tmds->tmds_pll[i].value |=
1326 (tmds_info->asMiscInfo[i].
1327 ucPLL_DutyCycle & 0xf) << 12;
1328 tmds->tmds_pll[i].value |=
1329 (tmds_info->asMiscInfo[i].
1330 ucPLL_VoltageSwing & 0xf) << 16;
1331
d9fdaafb 1332 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1333 tmds->tmds_pll[i].freq,
1334 tmds->tmds_pll[i].value);
1335
1336 if (maxfreq == tmds->tmds_pll[i].freq) {
1337 tmds->tmds_pll[i].freq = 0xffffffff;
1338 break;
1339 }
1340 }
445282db 1341 return true;
771fe6b9 1342 }
445282db 1343 return false;
771fe6b9
JG		 1344}
1345
ba032a58
AD		 1346bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1347 struct radeon_atom_ss *ss,
1348 int id)
ebbe1cb9 1349{
ebbe1cb9
AD		 1350 struct radeon_mode_info *mode_info = &rdev->mode_info;
1351 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
ba032a58 1352 uint16_t data_offset, size;
ebbe1cb9
AD		 1353 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1354 uint8_t frev, crev;
ba032a58 1355 int i, num_indices;
ebbe1cb9 1356
ba032a58
AD		 1357 memset(ss, 0, sizeof(struct radeon_atom_ss));
1358 if (atom_parse_data_header(mode_info->atom_context, index, &size,
a084e6ee
AD		 1359 &frev, &crev, &data_offset)) {
1360 ss_info =
1361 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1362
ba032a58
AD		 1363 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1364 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
ebbe1cb9 1365
ba032a58 1366 for (i = 0; i < num_indices; i++) {
279b215e
AD		 1367 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1368 ss->percentage =
1369 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1370 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1371 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1372 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1373 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1374 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
ba032a58
AD		 1375 return true;
1376 }
1377 }
1378 }
1379 return false;
1380}
1381
4339c442
AD		 1382static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1383 struct radeon_atom_ss *ss,
1384 int id)
1385{
1386 struct radeon_mode_info *mode_info = &rdev->mode_info;
1387 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1388 u16 data_offset, size;
1389 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1390 u8 frev, crev;
1391 u16 percentage = 0, rate = 0;
1392
1393 /* get any igp specific overrides */
1394 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1395 &frev, &crev, &data_offset)) {
1396 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1397 (mode_info->atom_context->bios + data_offset);
1398 switch (id) {
1399 case ASIC_INTERNAL_SS_ON_TMDS:
1400 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1401 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1402 break;
1403 case ASIC_INTERNAL_SS_ON_HDMI:
1404 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1405 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1406 break;
1407 case ASIC_INTERNAL_SS_ON_LVDS:
1408 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1409 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1410 break;
1411 }
1412 if (percentage)
1413 ss->percentage = percentage;
1414 if (rate)
1415 ss->rate = rate;
1416 }
1417}
1418
ba032a58
AD		 1419union asic_ss_info {
1420 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1421 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1422 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1423};
1424
1425bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1426 struct radeon_atom_ss *ss,
1427 int id, u32 clock)
1428{
1429 struct radeon_mode_info *mode_info = &rdev->mode_info;
1430 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1431 uint16_t data_offset, size;
1432 union asic_ss_info *ss_info;
1433 uint8_t frev, crev;
1434 int i, num_indices;
1435
1436 memset(ss, 0, sizeof(struct radeon_atom_ss));
1437 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1438 &frev, &crev, &data_offset)) {
1439
1440 ss_info =
1441 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1442
1443 switch (frev) {
1444 case 1:
1445 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1446 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1447
1448 for (i = 0; i < num_indices; i++) {
1449 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
4589433c 1450 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
ba032a58
AD		 1451 ss->percentage =
1452 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1453 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1454 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1455 return true;
1456 }
279b215e 1457 }
ba032a58
AD		 1458 break;
1459 case 2:
1460 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1461 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1462 for (i = 0; i < num_indices; i++) {
1463 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
4589433c 1464 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
ba032a58
AD		 1465 ss->percentage =
1466 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1467 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1468 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1469 return true;
1470 }
1471 }
1472 break;
1473 case 3:
1474 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1475 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1476 for (i = 0; i < num_indices; i++) {
1477 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
4589433c 1478 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
ba032a58
AD		 1479 ss->percentage =
1480 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1481 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1482 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
4339c442
AD		 1483 if (rdev->flags & RADEON_IS_IGP)
1484 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
ba032a58
AD		 1485 return true;
1486 }
1487 }
1488 break;
1489 default:
1490 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1491 break;
279b215e 1492 }
ba032a58 1493
ebbe1cb9 1494 }
ba032a58 1495 return false;
ebbe1cb9
AD		 1496}
1497
771fe6b9
JG		 1498union lvds_info {
1499 struct _ATOM_LVDS_INFO info;
1500 struct _ATOM_LVDS_INFO_V12 info_12;
1501};
1502
1503struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1504 radeon_encoder
1505 *encoder)
1506{
1507 struct drm_device *dev = encoder->base.dev;
1508 struct radeon_device *rdev = dev->dev_private;
1509 struct radeon_mode_info *mode_info = &rdev->mode_info;
1510 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1511 uint16_t data_offset, misc;
771fe6b9
JG		 1512 union lvds_info *lvds_info;
1513 uint8_t frev, crev;
1514 struct radeon_encoder_atom_dig *lvds = NULL;
5137ee94 1515 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9 1516
a084e6ee
AD		 1517 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1518 &frev, &crev, &data_offset)) {
1519 lvds_info =
1520 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1521 lvds =
1522 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1523
1524 if (!lvds)
1525 return NULL;
1526
de2103e4 1527 lvds->native_mode.clock =
771fe6b9 1528 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1529 lvds->native_mode.hdisplay =
771fe6b9 1530 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1531 lvds->native_mode.vdisplay =
771fe6b9 1532 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1533 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1534 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1535 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1536 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1537 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1538 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1539 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1540 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1541 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1542 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1543 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1544 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1545 lvds->panel_pwr_delay =
1546 le16_to_cpu(lvds_info->info.usOffDelayInMs);
ba032a58 1547 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1548
1549 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1550 if (misc & ATOM_VSYNC_POLARITY)
1551 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1552 if (misc & ATOM_HSYNC_POLARITY)
1553 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1554 if (misc & ATOM_COMPOSITESYNC)
1555 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1556 if (misc & ATOM_INTERLACE)
1557 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1558 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1559 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1560
4589433c
CC		 1561 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1562 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
7a868e18 1563
de2103e4
AD		 1564 /* set crtc values */
1565 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1566
ba032a58 1567 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
ebbe1cb9 1568
771fe6b9 1569 encoder->native_mode = lvds->native_mode;
5137ee94
AD		 1570
1571 if (encoder_enum == 2)
1572 lvds->linkb = true;
1573 else
1574 lvds->linkb = false;
1575
c324acd5 1576 /* parse the lcd record table */
4589433c 1577 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
c324acd5
AD		 1578 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1579 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1580 bool bad_record = false;
05fa7ea7
AD		 1581 u8 *record;
1582
1583 if ((frev == 1) && (crev < 2))
1584 /* absolute */
1585 record = (u8 *)(mode_info->atom_context->bios +
1586 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1587 else
1588 /* relative */
1589 record = (u8 *)(mode_info->atom_context->bios +
1590 data_offset +
1591 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
c324acd5
AD		 1592 while (*record != ATOM_RECORD_END_TYPE) {
1593 switch (*record) {
1594 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1595 record += sizeof(ATOM_PATCH_RECORD_MODE);
1596 break;
1597 case LCD_RTS_RECORD_TYPE:
1598 record += sizeof(ATOM_LCD_RTS_RECORD);
1599 break;
1600 case LCD_CAP_RECORD_TYPE:
1601 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1602 break;
1603 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1604 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1605 if (fake_edid_record->ucFakeEDIDLength) {
1606 struct edid *edid;
1607 int edid_size =
1608 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1609 edid = kmalloc(edid_size, GFP_KERNEL);
1610 if (edid) {
1611 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1612 fake_edid_record->ucFakeEDIDLength);
1613
eaa4f5e1 1614 if (drm_edid_is_valid(edid)) {
c324acd5 1615 rdev->mode_info.bios_hardcoded_edid = edid;
eaa4f5e1
DA		 1616 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1617 } else
c324acd5
AD		 1618 kfree(edid);
1619 }
1620 }
1621 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1622 break;
1623 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1624 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1625 lvds->native_mode.width_mm = panel_res_record->usHSize;
1626 lvds->native_mode.height_mm = panel_res_record->usVSize;
1627 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1628 break;
1629 default:
1630 DRM_ERROR("Bad LCD record %d\n", *record);
1631 bad_record = true;
1632 break;
1633 }
1634 if (bad_record)
1635 break;
1636 }
1637 }
771fe6b9
JG		 1638 }
1639 return lvds;
1640}
1641
6fe7ac3f
AD		 1642struct radeon_encoder_primary_dac *
1643radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1644{
1645 struct drm_device *dev = encoder->base.dev;
1646 struct radeon_device *rdev = dev->dev_private;
1647 struct radeon_mode_info *mode_info = &rdev->mode_info;
1648 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1649 uint16_t data_offset;
1650 struct _COMPASSIONATE_DATA *dac_info;
1651 uint8_t frev, crev;
1652 uint8_t bg, dac;
6fe7ac3f
AD		 1653 struct radeon_encoder_primary_dac *p_dac = NULL;
1654
a084e6ee
AD		 1655 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1656 &frev, &crev, &data_offset)) {
1657 dac_info = (struct _COMPASSIONATE_DATA *)
1658 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1659
6fe7ac3f
AD		 1660 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1661
1662 if (!p_dac)
1663 return NULL;
1664
1665 bg = dac_info->ucDAC1_BG_Adjustment;
1666 dac = dac_info->ucDAC1_DAC_Adjustment;
1667 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1668
1669 }
1670 return p_dac;
1671}
1672
4ce001ab 1673bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1674 struct drm_display_mode *mode)
4ce001ab
DA		 1675{
1676 struct radeon_mode_info *mode_info = &rdev->mode_info;
1677 ATOM_ANALOG_TV_INFO *tv_info;
1678 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1679 ATOM_DTD_FORMAT *dtd_timings;
1680 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1681 u8 frev, crev;
5a9bcacc 1682 u16 data_offset, misc;
4ce001ab 1683
a084e6ee
AD		 1684 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1685 &frev, &crev, &data_offset))
1686 return false;
4ce001ab
DA		 1687
1688 switch (crev) {
1689 case 1:
1690 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1691 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1692 return false;
1693
5a9bcacc
AD		 1694 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1695 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1696 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1697 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1698 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1699
1700 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1701 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1702 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1703 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1704 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1705
1706 mode->flags = 0;
1707 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1708 if (misc & ATOM_VSYNC_POLARITY)
1709 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1710 if (misc & ATOM_HSYNC_POLARITY)
1711 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1712 if (misc & ATOM_COMPOSITESYNC)
1713 mode->flags |= DRM_MODE_FLAG_CSYNC;
1714 if (misc & ATOM_INTERLACE)
1715 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1716 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1717 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1718
1719 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1720
1721 if (index == 1) {
1722 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1723 mode->crtc_htotal -= 1;
1724 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1725 }
1726 break;
1727 case 2:
1728 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1729 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1730 return false;
1731
1732 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1733 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1734 le16_to_cpu(dtd_timings->usHBlanking_Time);
1735 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1736 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1737 le16_to_cpu(dtd_timings->usHSyncOffset);
1738 mode->crtc_hsync_end = mode->crtc_hsync_start +
1739 le16_to_cpu(dtd_timings->usHSyncWidth);
1740
1741 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1742 le16_to_cpu(dtd_timings->usVBlanking_Time);
1743 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1744 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1745 le16_to_cpu(dtd_timings->usVSyncOffset);
1746 mode->crtc_vsync_end = mode->crtc_vsync_start +
1747 le16_to_cpu(dtd_timings->usVSyncWidth);
1748
1749 mode->flags = 0;
1750 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1751 if (misc & ATOM_VSYNC_POLARITY)
1752 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1753 if (misc & ATOM_HSYNC_POLARITY)
1754 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1755 if (misc & ATOM_COMPOSITESYNC)
1756 mode->flags |= DRM_MODE_FLAG_CSYNC;
1757 if (misc & ATOM_INTERLACE)
1758 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1759 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1760 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1761
1762 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1763 break;
1764 }
1765 return true;
1766}
1767
d79766fa
AD		 1768enum radeon_tv_std
1769radeon_atombios_get_tv_info(struct radeon_device *rdev)
1770{
1771 struct radeon_mode_info *mode_info = &rdev->mode_info;
1772 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1773 uint16_t data_offset;
1774 uint8_t frev, crev;
1775 struct _ATOM_ANALOG_TV_INFO *tv_info;
1776 enum radeon_tv_std tv_std = TV_STD_NTSC;
1777
a084e6ee
AD		 1778 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1779 &frev, &crev, &data_offset)) {
d79766fa 1780
a084e6ee
AD		 1781 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1782 (mode_info->atom_context->bios + data_offset);
d79766fa 1783
a084e6ee
AD		 1784 switch (tv_info->ucTV_BootUpDefaultStandard) {
1785 case ATOM_TV_NTSC:
1786 tv_std = TV_STD_NTSC;
40f76d81 1787 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
a084e6ee
AD		 1788 break;
1789 case ATOM_TV_NTSCJ:
1790 tv_std = TV_STD_NTSC_J;
40f76d81 1791 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
a084e6ee
AD		 1792 break;
1793 case ATOM_TV_PAL:
1794 tv_std = TV_STD_PAL;
40f76d81 1795 DRM_DEBUG_KMS("Default TV standard: PAL\n");
a084e6ee
AD		 1796 break;
1797 case ATOM_TV_PALM:
1798 tv_std = TV_STD_PAL_M;
40f76d81 1799 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
a084e6ee
AD		 1800 break;
1801 case ATOM_TV_PALN:
1802 tv_std = TV_STD_PAL_N;
40f76d81 1803 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
a084e6ee
AD		 1804 break;
1805 case ATOM_TV_PALCN:
1806 tv_std = TV_STD_PAL_CN;
40f76d81 1807 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
a084e6ee
AD		 1808 break;
1809 case ATOM_TV_PAL60:
1810 tv_std = TV_STD_PAL_60;
40f76d81 1811 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
a084e6ee
AD		 1812 break;
1813 case ATOM_TV_SECAM:
1814 tv_std = TV_STD_SECAM;
40f76d81 1815 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
a084e6ee
AD		 1816 break;
1817 default:
1818 tv_std = TV_STD_NTSC;
40f76d81 1819 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
a084e6ee
AD		 1820 break;
1821 }
d79766fa
AD		 1822 }
1823 return tv_std;
1824}
1825
6fe7ac3f
AD		 1826struct radeon_encoder_tv_dac *
1827radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1828{
1829 struct drm_device *dev = encoder->base.dev;
1830 struct radeon_device *rdev = dev->dev_private;
1831 struct radeon_mode_info *mode_info = &rdev->mode_info;
1832 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1833 uint16_t data_offset;
1834 struct _COMPASSIONATE_DATA *dac_info;
1835 uint8_t frev, crev;
1836 uint8_t bg, dac;
6fe7ac3f
AD		 1837 struct radeon_encoder_tv_dac *tv_dac = NULL;
1838
a084e6ee
AD		 1839 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1840 &frev, &crev, &data_offset)) {
6fe7ac3f 1841
a084e6ee
AD		 1842 dac_info = (struct _COMPASSIONATE_DATA *)
1843 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1844
6fe7ac3f
AD		 1845 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1846
1847 if (!tv_dac)
1848 return NULL;
1849
1850 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1851 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1852 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1853
1854 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1855 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1856 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1857
1858 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1859 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1860 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1861
d79766fa 1862 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1863 }
1864 return tv_dac;
1865}
1866
29fb52ca
AD		 1867static const char *thermal_controller_names[] = {
1868 "NONE",
678e7dfa
AD		 1869 "lm63",
1870 "adm1032",
1871 "adm1030",
1872 "max6649",
1873 "lm64",
1874 "f75375",
1875 "asc7xxx",
29fb52ca
AD		 1876};
1877
1878static const char *pp_lib_thermal_controller_names[] = {
1879 "NONE",
678e7dfa
AD		 1880 "lm63",
1881 "adm1032",
1882 "adm1030",
1883 "max6649",
1884 "lm64",
1885 "f75375",
29fb52ca
AD		 1886 "RV6xx",
1887 "RV770",
678e7dfa 1888 "adt7473",
560154e9 1889 "NONE",
49f65982
AD		 1890 "External GPIO",
1891 "Evergreen",
b0e66414
AD		 1892 "emc2103",
1893 "Sumo",
4fddba1f 1894 "Northern Islands",
29fb52ca
AD		 1895};
1896
56278a8e
AD		 1897union power_info {
1898 struct _ATOM_POWERPLAY_INFO info;
1899 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1900 struct _ATOM_POWERPLAY_INFO_V3 info_3;
560154e9 1901 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
b0e66414
AD		 1902 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1903 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
56278a8e
AD		 1904};
1905
560154e9
AD		 1906union pplib_clock_info {
1907 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1908 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1909 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
b0e66414 1910 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
560154e9
AD		 1911};
1912
1913union pplib_power_state {
1914 struct _ATOM_PPLIB_STATE v1;
1915 struct _ATOM_PPLIB_STATE_V2 v2;
1916};
1917
1918static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1919 int state_index,
1920 u32 misc, u32 misc2)
1921{
1922 rdev->pm.power_state[state_index].misc = misc;
1923 rdev->pm.power_state[state_index].misc2 = misc2;
1924 /* order matters! */
1925 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1926 rdev->pm.power_state[state_index].type =
1927 POWER_STATE_TYPE_POWERSAVE;
1928 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1929 rdev->pm.power_state[state_index].type =
1930 POWER_STATE_TYPE_BATTERY;
1931 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1932 rdev->pm.power_state[state_index].type =
1933 POWER_STATE_TYPE_BATTERY;
1934 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1935 rdev->pm.power_state[state_index].type =
1936 POWER_STATE_TYPE_BALANCED;
1937 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1938 rdev->pm.power_state[state_index].type =
1939 POWER_STATE_TYPE_PERFORMANCE;
1940 rdev->pm.power_state[state_index].flags &=
1941 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1942 }
1943 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1944 rdev->pm.power_state[state_index].type =
1945 POWER_STATE_TYPE_BALANCED;
1946 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1947 rdev->pm.power_state[state_index].type =
1948 POWER_STATE_TYPE_DEFAULT;
1949 rdev->pm.default_power_state_index = state_index;
1950 rdev->pm.power_state[state_index].default_clock_mode =
1951 &rdev->pm.power_state[state_index].clock_info[0];
1952 } else if (state_index == 0) {
1953 rdev->pm.power_state[state_index].clock_info[0].flags |=
1954 RADEON_PM_MODE_NO_DISPLAY;
1955 }
1956}
1957
1958static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
771fe6b9 1959{
56278a8e 1960 struct radeon_mode_info *mode_info = &rdev->mode_info;
560154e9
AD		 1961 u32 misc, misc2 = 0;
1962 int num_modes = 0, i;
1963 int state_index = 0;
1964 struct radeon_i2c_bus_rec i2c_bus;
1965 union power_info *power_info;
56278a8e 1966 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
560154e9 1967 u16 data_offset;
56278a8e 1968 u8 frev, crev;
771fe6b9 1969
560154e9
AD		 1970 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1971 &frev, &crev, &data_offset))
1972 return state_index;
1973 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1974
1975 /* add the i2c bus for thermal/fan chip */
1976 if (power_info->info.ucOverdriveThermalController > 0) {
1977 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1978 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1979 power_info->info.ucOverdriveControllerAddress >> 1);
1980 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1981 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1982 if (rdev->pm.i2c_bus) {
1983 struct i2c_board_info info = { };
1984 const char *name = thermal_controller_names[power_info->info.
1985 ucOverdriveThermalController];
1986 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1987 strlcpy(info.type, name, sizeof(info.type));
1988 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1989 }
1990 }
1991 num_modes = power_info->info.ucNumOfPowerModeEntries;
1992 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1993 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
0975b162
AD		 1994 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
1995 if (!rdev->pm.power_state)
1996 return state_index;
560154e9
AD		 1997 /* last mode is usually default, array is low to high */
1998 for (i = 0; i < num_modes; i++) {
1999 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2000 switch (frev) {
2001 case 1:
2002 rdev->pm.power_state[state_index].num_clock_modes = 1;
2003 rdev->pm.power_state[state_index].clock_info[0].mclk =
2004 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2005 rdev->pm.power_state[state_index].clock_info[0].sclk =
2006 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2007 /* skip invalid modes */
2008 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2009 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2010 continue;
2011 rdev->pm.power_state[state_index].pcie_lanes =
2012 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2013 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2014 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2015 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2016 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2017 VOLTAGE_GPIO;
2018 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2019 radeon_lookup_gpio(rdev,
2020 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2021 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2022 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2023 true;
2024 else
2025 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2026 false;
2027 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2028 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2029 VOLTAGE_VDDC;
2030 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2031 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
29fb52ca 2032 }
560154e9
AD		 2033 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2034 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2035 state_index++;
2036 break;
2037 case 2:
2038 rdev->pm.power_state[state_index].num_clock_modes = 1;
2039 rdev->pm.power_state[state_index].clock_info[0].mclk =
2040 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2041 rdev->pm.power_state[state_index].clock_info[0].sclk =
2042 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2043 /* skip invalid modes */
2044 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2045 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2046 continue;
2047 rdev->pm.power_state[state_index].pcie_lanes =
2048 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2049 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2050 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2051 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2052 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2053 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2054 VOLTAGE_GPIO;
2055 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2056 radeon_lookup_gpio(rdev,
2057 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2058 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2059 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2060 true;
2061 else
2062 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2063 false;
2064 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2065 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2066 VOLTAGE_VDDC;
2067 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2068 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
56278a8e 2069 }
560154e9
AD		 2070 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2071 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2072 state_index++;
2073 break;
2074 case 3:
2075 rdev->pm.power_state[state_index].num_clock_modes = 1;
2076 rdev->pm.power_state[state_index].clock_info[0].mclk =
2077 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2078 rdev->pm.power_state[state_index].clock_info[0].sclk =
2079 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2080 /* skip invalid modes */
2081 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2082 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2083 continue;
2084 rdev->pm.power_state[state_index].pcie_lanes =
2085 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2086 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2087 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2088 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2089 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2090 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2091 VOLTAGE_GPIO;
2092 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2093 radeon_lookup_gpio(rdev,
2094 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2095 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2096 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2097 true;
2098 else
2099 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2100 false;
2101 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2102 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2103 VOLTAGE_VDDC;
2104 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2105 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2106 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2107 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2108 true;
2109 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2110 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2111 }
02b17cc0 2112 }
560154e9
AD		 2113 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2114 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2115 state_index++;
2116 break;
2117 }
2118 }
2119 /* last mode is usually default */
2120 if (rdev->pm.default_power_state_index == -1) {
2121 rdev->pm.power_state[state_index - 1].type =
2122 POWER_STATE_TYPE_DEFAULT;
2123 rdev->pm.default_power_state_index = state_index - 1;
2124 rdev->pm.power_state[state_index - 1].default_clock_mode =
2125 &rdev->pm.power_state[state_index - 1].clock_info[0];
2126 rdev->pm.power_state[state_index].flags &=
2127 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2128 rdev->pm.power_state[state_index].misc = 0;
2129 rdev->pm.power_state[state_index].misc2 = 0;
2130 }
2131 return state_index;
2132}
2133
2134static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2135 ATOM_PPLIB_THERMALCONTROLLER *controller)
2136{
2137 struct radeon_i2c_bus_rec i2c_bus;
2138
2139 /* add the i2c bus for thermal/fan chip */
2140 if (controller->ucType > 0) {
2141 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2142 DRM_INFO("Internal thermal controller %s fan control\n",
2143 (controller->ucFanParameters &
2144 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2145 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2146 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2147 DRM_INFO("Internal thermal controller %s fan control\n",
2148 (controller->ucFanParameters &
2149 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2150 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2151 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2152 DRM_INFO("Internal thermal controller %s fan control\n",
2153 (controller->ucFanParameters &
2154 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2155 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
b0e66414
AD		 2156 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2157 DRM_INFO("Internal thermal controller %s fan control\n",
2158 (controller->ucFanParameters &
2159 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2160 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
4fddba1f
AD		 2161 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2162 DRM_INFO("Internal thermal controller %s fan control\n",
2163 (controller->ucFanParameters &
2164 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2165 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
560154e9
AD		 2166 } else if ((controller->ucType ==
2167 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2168 (controller->ucType ==
b0e66414
AD		 2169 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2170 (controller->ucType ==
2171 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
560154e9 2172 DRM_INFO("Special thermal controller config\n");
49f65982 2173 } else {
560154e9
AD		 2174 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2175 pp_lib_thermal_controller_names[controller->ucType],
2176 controller->ucI2cAddress >> 1,
2177 (controller->ucFanParameters &
2178 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2179 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2180 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2181 if (rdev->pm.i2c_bus) {
2182 struct i2c_board_info info = { };
2183 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2184 info.addr = controller->ucI2cAddress >> 1;
2185 strlcpy(info.type, name, sizeof(info.type));
2186 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
c5e8ce61 2187 }
560154e9
AD		 2188 }
2189 }
2190}
c5e8ce61 2191
2feea49a
AD		 2192static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2193 u16 *vddc, u16 *vddci)
560154e9
AD		 2194{
2195 struct radeon_mode_info *mode_info = &rdev->mode_info;
2196 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2197 u8 frev, crev;
2198 u16 data_offset;
2199 union firmware_info *firmware_info;
2feea49a
AD		 2200
2201 *vddc = 0;
2202 *vddci = 0;
678e7dfa 2203
560154e9
AD		 2204 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2205 &frev, &crev, &data_offset)) {
2206 firmware_info =
2207 (union firmware_info *)(mode_info->atom_context->bios +
2208 data_offset);
2feea49a
AD		 2209 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2210 if ((frev == 2) && (crev >= 2))
2211 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
560154e9 2212 }
560154e9
AD		 2213}
2214
2215static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2216 int state_index, int mode_index,
2217 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2218{
2219 int j;
2220 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2221 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2feea49a
AD		 2222 u16 vddc, vddci;
2223
2224 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
560154e9
AD		 2225
2226 rdev->pm.power_state[state_index].misc = misc;
2227 rdev->pm.power_state[state_index].misc2 = misc2;
2228 rdev->pm.power_state[state_index].pcie_lanes =
2229 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2230 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2231 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2232 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2233 rdev->pm.power_state[state_index].type =
2234 POWER_STATE_TYPE_BATTERY;
2235 break;
2236 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2237 rdev->pm.power_state[state_index].type =
2238 POWER_STATE_TYPE_BALANCED;
2239 break;
2240 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2241 rdev->pm.power_state[state_index].type =
2242 POWER_STATE_TYPE_PERFORMANCE;
2243 break;
2244 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2245 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2246 rdev->pm.power_state[state_index].type =
2247 POWER_STATE_TYPE_PERFORMANCE;
2248 break;
2249 }
2250 rdev->pm.power_state[state_index].flags = 0;
2251 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2252 rdev->pm.power_state[state_index].flags |=
2253 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2254 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2255 rdev->pm.power_state[state_index].type =
2256 POWER_STATE_TYPE_DEFAULT;
2257 rdev->pm.default_power_state_index = state_index;
2258 rdev->pm.power_state[state_index].default_clock_mode =
2259 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
9ace9f7b
AD		 2260 if (ASIC_IS_DCE5(rdev)) {
2261 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2262 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2263 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2264 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2feea49a 2265 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
9ace9f7b
AD		 2266 } else {
2267 /* patch the table values with the default slck/mclk from firmware info */
2268 for (j = 0; j < mode_index; j++) {
2269 rdev->pm.power_state[state_index].clock_info[j].mclk =
2270 rdev->clock.default_mclk;
2271 rdev->pm.power_state[state_index].clock_info[j].sclk =
2272 rdev->clock.default_sclk;
2273 if (vddc)
2274 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2275 vddc;
2276 }
560154e9
AD		 2277 }
2278 }
2279}
2280
2281static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2282 int state_index, int mode_index,
2283 union pplib_clock_info *clock_info)
2284{
2285 u32 sclk, mclk;
2286
2287 if (rdev->flags & RADEON_IS_IGP) {
b0e66414
AD		 2288 if (rdev->family >= CHIP_PALM) {
2289 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2290 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2291 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2292 } else {
2293 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2294 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2295 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2296 }
560154e9
AD		 2297 } else if (ASIC_IS_DCE4(rdev)) {
2298 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2299 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2300 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2301 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2302 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2303 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2304 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2305 VOLTAGE_SW;
2306 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
4589433c 2307 le16_to_cpu(clock_info->evergreen.usVDDC);
2feea49a
AD		 2308 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2309 le16_to_cpu(clock_info->evergreen.usVDDCI);
560154e9
AD		 2310 } else {
2311 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2312 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2313 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2314 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2315 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2316 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2317 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2318 VOLTAGE_SW;
2319 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
4589433c 2320 le16_to_cpu(clock_info->r600.usVDDC);
560154e9
AD		 2321 }
2322
2323 if (rdev->flags & RADEON_IS_IGP) {
2324 /* skip invalid modes */
2325 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2326 return false;
2327 } else {
2328 /* skip invalid modes */
2329 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2330 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2331 return false;
2332 }
2333 return true;
2334}
2335
2336static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2337{
2338 struct radeon_mode_info *mode_info = &rdev->mode_info;
2339 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2340 union pplib_power_state *power_state;
2341 int i, j;
2342 int state_index = 0, mode_index = 0;
2343 union pplib_clock_info *clock_info;
2344 bool valid;
2345 union power_info *power_info;
2346 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2347 u16 data_offset;
2348 u8 frev, crev;
2349
2350 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2351 &frev, &crev, &data_offset))
2352 return state_index;
2353 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2354
2355 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
0975b162
AD		 2356 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2357 power_info->pplib.ucNumStates, GFP_KERNEL);
2358 if (!rdev->pm.power_state)
2359 return state_index;
560154e9
AD		 2360 /* first mode is usually default, followed by low to high */
2361 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2362 mode_index = 0;
2363 power_state = (union pplib_power_state *)
2364 (mode_info->atom_context->bios + data_offset +
2365 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2366 i * power_info->pplib.ucStateEntrySize);
2367 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2368 (mode_info->atom_context->bios + data_offset +
2369 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2370 (power_state->v1.ucNonClockStateIndex *
2371 power_info->pplib.ucNonClockSize));
2372 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2373 clock_info = (union pplib_clock_info *)
2374 (mode_info->atom_context->bios + data_offset +
2375 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2376 (power_state->v1.ucClockStateIndices[j] *
2377 power_info->pplib.ucClockInfoSize));
2378 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2379 state_index, mode_index,
2380 clock_info);
2381 if (valid)
2382 mode_index++;
2383 }
2384 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2385 if (mode_index) {
2386 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2387 non_clock_info);
2388 state_index++;
2389 }
2390 }
2391 /* if multiple clock modes, mark the lowest as no display */
2392 for (i = 0; i < state_index; i++) {
2393 if (rdev->pm.power_state[i].num_clock_modes > 1)
2394 rdev->pm.power_state[i].clock_info[0].flags |=
2395 RADEON_PM_MODE_NO_DISPLAY;
2396 }
2397 /* first mode is usually default */
2398 if (rdev->pm.default_power_state_index == -1) {
2399 rdev->pm.power_state[0].type =
2400 POWER_STATE_TYPE_DEFAULT;
2401 rdev->pm.default_power_state_index = 0;
2402 rdev->pm.power_state[0].default_clock_mode =
2403 &rdev->pm.power_state[0].clock_info[0];
2404 }
2405 return state_index;
2406}
2407
b0e66414
AD		 2408static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2409{
2410 struct radeon_mode_info *mode_info = &rdev->mode_info;
2411 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2412 union pplib_power_state *power_state;
2413 int i, j, non_clock_array_index, clock_array_index;
2414 int state_index = 0, mode_index = 0;
2415 union pplib_clock_info *clock_info;
2416 struct StateArray *state_array;
2417 struct ClockInfoArray *clock_info_array;
2418 struct NonClockInfoArray *non_clock_info_array;
2419 bool valid;
2420 union power_info *power_info;
2421 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2422 u16 data_offset;
2423 u8 frev, crev;
2424
2425 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2426 &frev, &crev, &data_offset))
2427 return state_index;
2428 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2429
2430 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2431 state_array = (struct StateArray *)
2432 (mode_info->atom_context->bios + data_offset +
4589433c 2433 le16_to_cpu(power_info->pplib.usStateArrayOffset));
b0e66414
AD		 2434 clock_info_array = (struct ClockInfoArray *)
2435 (mode_info->atom_context->bios + data_offset +
4589433c 2436 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
b0e66414
AD		 2437 non_clock_info_array = (struct NonClockInfoArray *)
2438 (mode_info->atom_context->bios + data_offset +
4589433c 2439 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
0975b162
AD		 2440 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2441 state_array->ucNumEntries, GFP_KERNEL);
2442 if (!rdev->pm.power_state)
2443 return state_index;
b0e66414
AD		 2444 for (i = 0; i < state_array->ucNumEntries; i++) {
2445 mode_index = 0;
2446 power_state = (union pplib_power_state *)&state_array->states[i];
2447 /* XXX this might be an inagua bug... */
2448 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2449 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2450 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2451 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2452 clock_array_index = power_state->v2.clockInfoIndex[j];
2453 /* XXX this might be an inagua bug... */
2454 if (clock_array_index >= clock_info_array->ucNumEntries)
2455 continue;
2456 clock_info = (union pplib_clock_info *)
2457 &clock_info_array->clockInfo[clock_array_index];
2458 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2459 state_index, mode_index,
2460 clock_info);
2461 if (valid)
2462 mode_index++;
2463 }
2464 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2465 if (mode_index) {
2466 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2467 non_clock_info);
2468 state_index++;
2469 }
2470 }
2471 /* if multiple clock modes, mark the lowest as no display */
2472 for (i = 0; i < state_index; i++) {
2473 if (rdev->pm.power_state[i].num_clock_modes > 1)
2474 rdev->pm.power_state[i].clock_info[0].flags |=
2475 RADEON_PM_MODE_NO_DISPLAY;
2476 }
2477 /* first mode is usually default */
2478 if (rdev->pm.default_power_state_index == -1) {
2479 rdev->pm.power_state[0].type =
2480 POWER_STATE_TYPE_DEFAULT;
2481 rdev->pm.default_power_state_index = 0;
2482 rdev->pm.power_state[0].default_clock_mode =
2483 &rdev->pm.power_state[0].clock_info[0];
2484 }
2485 return state_index;
2486}
2487
560154e9
AD		 2488void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2489{
2490 struct radeon_mode_info *mode_info = &rdev->mode_info;
2491 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2492 u16 data_offset;
2493 u8 frev, crev;
2494 int state_index = 0;
2495
2496 rdev->pm.default_power_state_index = -1;
2497
2498 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2499 &frev, &crev, &data_offset)) {
2500 switch (frev) {
2501 case 1:
2502 case 2:
2503 case 3:
2504 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2505 break;
2506 case 4:
2507 case 5:
2508 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2509 break;
b0e66414
AD		 2510 case 6:
2511 state_index = radeon_atombios_parse_power_table_6(rdev);
2512 break;
560154e9
AD		 2513 default:
2514 break;
56278a8e
AD		 2515 }
2516 } else {
0975b162
AD		 2517 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2518 if (rdev->pm.power_state) {
2519 /* add the default mode */
2520 rdev->pm.power_state[state_index].type =
2521 POWER_STATE_TYPE_DEFAULT;
2522 rdev->pm.power_state[state_index].num_clock_modes = 1;
2523 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2524 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2525 rdev->pm.power_state[state_index].default_clock_mode =
2526 &rdev->pm.power_state[state_index].clock_info[0];
2527 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2528 rdev->pm.power_state[state_index].pcie_lanes = 16;
2529 rdev->pm.default_power_state_index = state_index;
2530 rdev->pm.power_state[state_index].flags = 0;
2531 state_index++;
2532 }
56278a8e 2533 }
02b17cc0 2534
56278a8e 2535 rdev->pm.num_power_states = state_index;
9038dfdf 2536
a48b9b4e
AD		 2537 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2538 rdev->pm.current_clock_mode_index = 0;
4d60173f 2539 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 2540}
2541
771fe6b9 2542void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2543{
771fe6b9
JG		 2544 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2545 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2546
2547 args.ucEnable = enable;
2548
2549 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2550}
2551
7433874e
RM		 2552uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2553{
2554 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2555 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2556
2557 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4589433c 2558 return le32_to_cpu(args.ulReturnEngineClock);
7433874e
RM		 2559}
2560
2561uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2562{
2563 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2564 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2565
2566 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4589433c 2567 return le32_to_cpu(args.ulReturnMemoryClock);
7433874e
RM		 2568}
2569
771fe6b9
JG		 2570void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2571 uint32_t eng_clock)
2572{
2573 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2574 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2575
4589433c 2576 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
771fe6b9
JG		 2577
2578 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2579}
2580
2581void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2582 uint32_t mem_clock)
2583{
2584 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2585 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2586
2587 if (rdev->flags & RADEON_IS_IGP)
2588 return;
2589
4589433c 2590 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
771fe6b9
JG		 2591
2592 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2593}
2594
7ac9aa5a
AD		 2595union set_voltage {
2596 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2597 struct _SET_VOLTAGE_PARAMETERS v1;
2598 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2599};
2600
8a83ec5e 2601void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
7ac9aa5a
AD		 2602{
2603 union set_voltage args;
2604 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
8a83ec5e 2605 u8 frev, crev, volt_index = voltage_level;
7ac9aa5a
AD		 2606
2607 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2608 return;
2609
a377e187
AD		 2610 /* 0xff01 is a flag rather then an actual voltage */
2611 if (voltage_level == 0xff01)
2612 return;
2613
7ac9aa5a
AD		 2614 switch (crev) {
2615 case 1:
8a83ec5e 2616 args.v1.ucVoltageType = voltage_type;
7ac9aa5a
AD		 2617 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2618 args.v1.ucVoltageIndex = volt_index;
2619 break;
2620 case 2:
8a83ec5e 2621 args.v2.ucVoltageType = voltage_type;
7ac9aa5a 2622 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
8a83ec5e 2623 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
7ac9aa5a
AD		 2624 break;
2625 default:
2626 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2627 return;
2628 }
2629
2630 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2631}
2632
2633
2634
771fe6b9
JG		 2635void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2636{
2637 struct radeon_device *rdev = dev->dev_private;
2638 uint32_t bios_2_scratch, bios_6_scratch;
2639
2640 if (rdev->family >= CHIP_R600) {
4ce001ab 2641 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2642 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2643 } else {
4ce001ab 2644 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2645 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2646 }
2647
2648 /* let the bios control the backlight */
2649 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2650
2651 /* tell the bios not to handle mode switching */
87364760 2652 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
771fe6b9
JG		 2653
2654 if (rdev->family >= CHIP_R600) {
2655 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2656 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2657 } else {
2658 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2659 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2660 }
2661
2662}
2663
f657c2a7
YZ		 2664void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2665{
2666 uint32_t scratch_reg;
2667 int i;
2668
2669 if (rdev->family >= CHIP_R600)
2670 scratch_reg = R600_BIOS_0_SCRATCH;
2671 else
2672 scratch_reg = RADEON_BIOS_0_SCRATCH;
2673
2674 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2675 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2676}
2677
2678void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2679{
2680 uint32_t scratch_reg;
2681 int i;
2682
2683 if (rdev->family >= CHIP_R600)
2684 scratch_reg = R600_BIOS_0_SCRATCH;
2685 else
2686 scratch_reg = RADEON_BIOS_0_SCRATCH;
2687
2688 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2689 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2690}
2691
771fe6b9
JG		 2692void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2693{
2694 struct drm_device *dev = encoder->dev;
2695 struct radeon_device *rdev = dev->dev_private;
2696 uint32_t bios_6_scratch;
2697
2698 if (rdev->family >= CHIP_R600)
2699 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2700 else
2701 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2702
87364760 2703 if (lock) {
771fe6b9 2704 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
87364760
AD		 2705 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2706 } else {
771fe6b9 2707 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
87364760
AD		 2708 bios_6_scratch |= ATOM_S6_ACC_MODE;
2709 }
771fe6b9
JG		 2710
2711 if (rdev->family >= CHIP_R600)
2712 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2713 else
2714 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2715}
2716
2717/* at some point we may want to break this out into individual functions */
2718void
2719radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2720 struct drm_encoder *encoder,
2721 bool connected)
2722{
2723 struct drm_device *dev = connector->dev;
2724 struct radeon_device *rdev = dev->dev_private;
2725 struct radeon_connector *radeon_connector =
2726 to_radeon_connector(connector);
2727 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2728 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2729
2730 if (rdev->family >= CHIP_R600) {
2731 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2732 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2733 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2734 } else {
2735 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2736 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2737 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2738 }
2739
2740 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2741 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2742 if (connected) {
d9fdaafb 2743 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2744 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2745 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2746 } else {
d9fdaafb 2747 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2748 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2749 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2750 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2751 }
2752 }
2753 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2754 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2755 if (connected) {
d9fdaafb 2756 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2757 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2758 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2759 } else {
d9fdaafb 2760 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2761 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2762 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2763 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2764 }
2765 }
2766 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2767 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2768 if (connected) {
d9fdaafb 2769 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2770 bios_0_scratch |= ATOM_S0_LCD1;
2771 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2772 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2773 } else {
d9fdaafb 2774 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2775 bios_0_scratch &= ~ATOM_S0_LCD1;
2776 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2777 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2778 }
2779 }
2780 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2781 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2782 if (connected) {
d9fdaafb 2783 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2784 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2785 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2786 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2787 } else {
d9fdaafb 2788 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2789 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2790 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2791 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2792 }
2793 }
2794 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2795 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2796 if (connected) {
d9fdaafb 2797 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2798 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2799 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2800 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2801 } else {
d9fdaafb 2802 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2803 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2804 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2805 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2806 }
2807 }
2808 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2809 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2810 if (connected) {
d9fdaafb 2811 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2812 bios_0_scratch |= ATOM_S0_DFP1;
2813 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2814 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2815 } else {
d9fdaafb 2816 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2817 bios_0_scratch &= ~ATOM_S0_DFP1;
2818 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2819 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2820 }
2821 }
2822 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2823 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2824 if (connected) {
d9fdaafb 2825 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2826 bios_0_scratch |= ATOM_S0_DFP2;
2827 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2828 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2829 } else {
d9fdaafb 2830 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2831 bios_0_scratch &= ~ATOM_S0_DFP2;
2832 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2833 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2834 }
2835 }
2836 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2837 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2838 if (connected) {
d9fdaafb 2839 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2840 bios_0_scratch |= ATOM_S0_DFP3;
2841 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2842 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2843 } else {
d9fdaafb 2844 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2845 bios_0_scratch &= ~ATOM_S0_DFP3;
2846 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2847 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2848 }
2849 }
2850 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2851 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2852 if (connected) {
d9fdaafb 2853 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2854 bios_0_scratch |= ATOM_S0_DFP4;
2855 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2856 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2857 } else {
d9fdaafb 2858 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2859 bios_0_scratch &= ~ATOM_S0_DFP4;
2860 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2861 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2862 }
2863 }
2864 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2865 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2866 if (connected) {
d9fdaafb 2867 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2868 bios_0_scratch |= ATOM_S0_DFP5;
2869 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2870 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2871 } else {
d9fdaafb 2872 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2873 bios_0_scratch &= ~ATOM_S0_DFP5;
2874 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2875 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2876 }
2877 }
2878
2879 if (rdev->family >= CHIP_R600) {
2880 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2881 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2882 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2883 } else {
2884 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2885 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2886 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2887 }
2888}
2889
2890void
2891radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2892{
2893 struct drm_device *dev = encoder->dev;
2894 struct radeon_device *rdev = dev->dev_private;
2895 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2896 uint32_t bios_3_scratch;
2897
2898 if (rdev->family >= CHIP_R600)
2899 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2900 else
2901 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2902
2903 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2904 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2905 bios_3_scratch |= (crtc << 18);
2906 }
2907 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2908 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2909 bios_3_scratch |= (crtc << 24);
2910 }
2911 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2912 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2913 bios_3_scratch |= (crtc << 16);
2914 }
2915 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2916 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2917 bios_3_scratch |= (crtc << 20);
2918 }
2919 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2920 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2921 bios_3_scratch |= (crtc << 17);
2922 }
2923 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2924 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2925 bios_3_scratch |= (crtc << 19);
2926 }
2927 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2928 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2929 bios_3_scratch |= (crtc << 23);
2930 }
2931 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2932 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2933 bios_3_scratch |= (crtc << 25);
2934 }
2935
2936 if (rdev->family >= CHIP_R600)
2937 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2938 else
2939 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2940}
2941
2942void
2943radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2944{
2945 struct drm_device *dev = encoder->dev;
2946 struct radeon_device *rdev = dev->dev_private;
2947 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2948 uint32_t bios_2_scratch;
2949
2950 if (rdev->family >= CHIP_R600)
2951 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2952 else
2953 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2954
2955 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2956 if (on)
2957 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2958 else
2959 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2960 }
2961 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2962 if (on)
2963 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2964 else
2965 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2966 }
2967 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2968 if (on)
2969 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2970 else
2971 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2972 }
2973 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2974 if (on)
2975 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2976 else
2977 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2978 }
2979 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2980 if (on)
2981 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2982 else
2983 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2984 }
2985 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2986 if (on)
2987 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2988 else
2989 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2990 }
2991 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2992 if (on)
2993 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2994 else
2995 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2996 }
2997 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2998 if (on)
2999 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3000 else
3001 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3002 }
3003 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3004 if (on)
3005 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3006 else
3007 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3008 }
3009 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3010 if (on)
3011 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3012 else
3013 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3014 }
3015
3016 if (rdev->family >= CHIP_R600)
3017 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3018 else
3019 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3020}
kernel source for telekom puls (alcatel/mediatek)