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drm/radeon/kms/r600: use blit for BO moves
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info);
50
51/* from radeon_legacy_encoder.c */
52extern void
53radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
54 uint32_t supported_device);
55
56union atom_supported_devices {
57 struct _ATOM_SUPPORTED_DEVICES_INFO info;
58 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
60};
61
62static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
63 *dev, uint8_t id)
64{
65 struct radeon_device *rdev = dev->dev_private;
66 struct atom_context *ctx = rdev->mode_info.atom_context;
67 ATOM_GPIO_I2C_ASSIGMENT gpio;
68 struct radeon_i2c_bus_rec i2c;
69 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
70 struct _ATOM_GPIO_I2C_INFO *i2c_info;
71 uint16_t data_offset;
72
73 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
74 i2c.valid = false;
75
76 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
77
78 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
79
80 gpio = i2c_info->asGPIO_Info[id];
81
82 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
83 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
84 i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
85 i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
86 i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
87 i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
88 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
89 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
90 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
91 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
92 i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
93 i2c.put_data_mask = (1 << gpio.ucDataEnShift);
94 i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
95 i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
96 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
97 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
98 i2c.valid = true;
99
100 return i2c;
101}
102
103static bool radeon_atom_apply_quirks(struct drm_device *dev,
104 uint32_t supported_device,
105 int *connector_type,
848577ee
AD		 106 struct radeon_i2c_bus_rec *i2c_bus,
107 uint8_t *line_mux)
771fe6b9
JG		 108{
109
110 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
111 if ((dev->pdev->device == 0x791e) &&
112 (dev->pdev->subsystem_vendor == 0x1043) &&
113 (dev->pdev->subsystem_device == 0x826d)) {
114 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
115 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
116 *connector_type = DRM_MODE_CONNECTOR_DVID;
117 }
118
119 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
120 if ((dev->pdev->device == 0x7941) &&
121 (dev->pdev->subsystem_vendor == 0x147b) &&
122 (dev->pdev->subsystem_device == 0x2412)) {
123 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
124 return false;
125 }
126
127 /* Falcon NW laptop lists vga ddc line for LVDS */
128 if ((dev->pdev->device == 0x5653) &&
129 (dev->pdev->subsystem_vendor == 0x1462) &&
130 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 131 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 132 i2c_bus->valid = false;
848577ee
AD		 133 *line_mux = 53;
134 }
771fe6b9
JG		 135 }
136
137 /* Funky macbooks */
138 if ((dev->pdev->device == 0x71C5) &&
139 (dev->pdev->subsystem_vendor == 0x106b) &&
140 (dev->pdev->subsystem_device == 0x0080)) {
141 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
142 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
143 return false;
144 }
145
146 /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */
147 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
148 (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
149 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
150 return false;
151 }
152 }
153
154 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
155 if ((dev->pdev->device == 0x9598) &&
156 (dev->pdev->subsystem_vendor == 0x1043) &&
157 (dev->pdev->subsystem_device == 0x01da)) {
158 if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) {
159 *connector_type = DRM_MODE_CONNECTOR_DVID;
160 }
161 }
162
163 return true;
164}
165
166const int supported_devices_connector_convert[] = {
167 DRM_MODE_CONNECTOR_Unknown,
168 DRM_MODE_CONNECTOR_VGA,
169 DRM_MODE_CONNECTOR_DVII,
170 DRM_MODE_CONNECTOR_DVID,
171 DRM_MODE_CONNECTOR_DVIA,
172 DRM_MODE_CONNECTOR_SVIDEO,
173 DRM_MODE_CONNECTOR_Composite,
174 DRM_MODE_CONNECTOR_LVDS,
175 DRM_MODE_CONNECTOR_Unknown,
176 DRM_MODE_CONNECTOR_Unknown,
177 DRM_MODE_CONNECTOR_HDMIA,
178 DRM_MODE_CONNECTOR_HDMIB,
179 DRM_MODE_CONNECTOR_Unknown,
180 DRM_MODE_CONNECTOR_Unknown,
181 DRM_MODE_CONNECTOR_9PinDIN,
182 DRM_MODE_CONNECTOR_DisplayPort
183};
184
185const int object_connector_convert[] = {
186 DRM_MODE_CONNECTOR_Unknown,
187 DRM_MODE_CONNECTOR_DVII,
188 DRM_MODE_CONNECTOR_DVII,
189 DRM_MODE_CONNECTOR_DVID,
190 DRM_MODE_CONNECTOR_DVID,
191 DRM_MODE_CONNECTOR_VGA,
192 DRM_MODE_CONNECTOR_Composite,
193 DRM_MODE_CONNECTOR_SVIDEO,
194 DRM_MODE_CONNECTOR_Unknown,
195 DRM_MODE_CONNECTOR_9PinDIN,
196 DRM_MODE_CONNECTOR_Unknown,
197 DRM_MODE_CONNECTOR_HDMIA,
198 DRM_MODE_CONNECTOR_HDMIB,
199 DRM_MODE_CONNECTOR_HDMIB,
200 DRM_MODE_CONNECTOR_LVDS,
201 DRM_MODE_CONNECTOR_9PinDIN,
202 DRM_MODE_CONNECTOR_Unknown,
203 DRM_MODE_CONNECTOR_Unknown,
204 DRM_MODE_CONNECTOR_Unknown,
205 DRM_MODE_CONNECTOR_DisplayPort
206};
207
208bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
209{
210 struct radeon_device *rdev = dev->dev_private;
211 struct radeon_mode_info *mode_info = &rdev->mode_info;
212 struct atom_context *ctx = mode_info->atom_context;
213 int index = GetIndexIntoMasterTable(DATA, Object_Header);
214 uint16_t size, data_offset;
215 uint8_t frev, crev, line_mux = 0;
216 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
217 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
218 ATOM_OBJECT_HEADER *obj_header;
219 int i, j, path_size, device_support;
220 int connector_type;
221 uint16_t igp_lane_info;
222 bool linkb;
223 struct radeon_i2c_bus_rec ddc_bus;
224
225 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
226
227 if (data_offset == 0)
228 return false;
229
230 if (crev < 2)
231 return false;
232
233 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
234 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
235 (ctx->bios + data_offset +
236 le16_to_cpu(obj_header->usDisplayPathTableOffset));
237 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
238 (ctx->bios + data_offset +
239 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
240 device_support = le16_to_cpu(obj_header->usDeviceSupport);
241
242 path_size = 0;
243 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
244 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
245 ATOM_DISPLAY_OBJECT_PATH *path;
246 addr += path_size;
247 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
248 path_size += le16_to_cpu(path->usSize);
249 linkb = false;
250
251 if (device_support & le16_to_cpu(path->usDeviceTag)) {
252 uint8_t con_obj_id, con_obj_num, con_obj_type;
253
254 con_obj_id =
255 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
256 >> OBJECT_ID_SHIFT;
257 con_obj_num =
258 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
259 >> ENUM_ID_SHIFT;
260 con_obj_type =
261 (le16_to_cpu(path->usConnObjectId) &
262 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
263
264 if ((le16_to_cpu(path->usDeviceTag) ==
265 ATOM_DEVICE_TV1_SUPPORT)
266 || (le16_to_cpu(path->usDeviceTag) ==
267 ATOM_DEVICE_TV2_SUPPORT)
268 || (le16_to_cpu(path->usDeviceTag) ==
269 ATOM_DEVICE_CV_SUPPORT))
270 continue;
271
272 if ((rdev->family == CHIP_RS780) &&
273 (con_obj_id ==
274 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
275 uint16_t igp_offset = 0;
276 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
277
278 index =
279 GetIndexIntoMasterTable(DATA,
280 IntegratedSystemInfo);
281
282 atom_parse_data_header(ctx, index, &size, &frev,
283 &crev, &igp_offset);
284
285 if (crev >= 2) {
286 igp_obj =
287 (ATOM_INTEGRATED_SYSTEM_INFO_V2
288 *) (ctx->bios + igp_offset);
289
290 if (igp_obj) {
291 uint32_t slot_config, ct;
292
293 if (con_obj_num == 1)
294 slot_config =
295 igp_obj->
296 ulDDISlot1Config;
297 else
298 slot_config =
299 igp_obj->
300 ulDDISlot2Config;
301
302 ct = (slot_config >> 16) & 0xff;
303 connector_type =
304 object_connector_convert
305 [ct];
306 igp_lane_info =
307 slot_config & 0xffff;
308 } else
309 continue;
310 } else
311 continue;
312 } else {
313 igp_lane_info = 0;
314 connector_type =
315 object_connector_convert[con_obj_id];
316 }
317
318 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
319 continue;
320
321 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
322 j++) {
323 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
324
325 enc_obj_id =
326 (le16_to_cpu(path->usGraphicObjIds[j]) &
327 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
328 enc_obj_num =
329 (le16_to_cpu(path->usGraphicObjIds[j]) &
330 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
331 enc_obj_type =
332 (le16_to_cpu(path->usGraphicObjIds[j]) &
333 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
334
335 /* FIXME: add support for router objects */
336 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
337 if (enc_obj_num == 2)
338 linkb = true;
339 else
340 linkb = false;
341
342 radeon_add_atom_encoder(dev,
343 enc_obj_id,
344 le16_to_cpu
345 (path->
346 usDeviceTag));
347
348 }
349 }
350
351 /* look up gpio for ddc */
352 if ((le16_to_cpu(path->usDeviceTag) &
353 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
354 == 0) {
355 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
356 if (le16_to_cpu(path->usConnObjectId) ==
357 le16_to_cpu(con_obj->asObjects[j].
358 usObjectID)) {
359 ATOM_COMMON_RECORD_HEADER
360 *record =
361 (ATOM_COMMON_RECORD_HEADER
362 *)
363 (ctx->bios + data_offset +
364 le16_to_cpu(con_obj->
365 asObjects[j].
366 usRecordOffset));
367 ATOM_I2C_RECORD *i2c_record;
368
369 while (record->ucRecordType > 0
370 && record->
371 ucRecordType <=
372 ATOM_MAX_OBJECT_RECORD_NUMBER) {
771fe6b9
JG		 373 switch (record->
374 ucRecordType) {
375 case ATOM_I2C_RECORD_TYPE:
376 i2c_record =
377 (ATOM_I2C_RECORD
378 *) record;
379 line_mux =
380 i2c_record->
381 sucI2cId.
382 bfI2C_LineMux;
383 break;
384 }
385 record =
386 (ATOM_COMMON_RECORD_HEADER
387 *) ((char *)record
388 +
389 record->
390 ucRecordSize);
391 }
392 break;
393 }
394 }
395 } else
396 line_mux = 0;
397
398 if ((le16_to_cpu(path->usDeviceTag) ==
399 ATOM_DEVICE_TV1_SUPPORT)
400 || (le16_to_cpu(path->usDeviceTag) ==
401 ATOM_DEVICE_TV2_SUPPORT)
402 || (le16_to_cpu(path->usDeviceTag) ==
403 ATOM_DEVICE_CV_SUPPORT))
404 ddc_bus.valid = false;
405 else
406 ddc_bus = radeon_lookup_gpio(dev, line_mux);
407
408 radeon_add_atom_connector(dev,
409 le16_to_cpu(path->
410 usConnObjectId),
411 le16_to_cpu(path->
412 usDeviceTag),
413 connector_type, &ddc_bus,
414 linkb, igp_lane_info);
415
416 }
417 }
418
419 radeon_link_encoder_connector(dev);
420
421 return true;
422}
423
424struct bios_connector {
425 bool valid;
426 uint8_t line_mux;
427 uint16_t devices;
428 int connector_type;
429 struct radeon_i2c_bus_rec ddc_bus;
430};
431
432bool radeon_get_atom_connector_info_from_supported_devices_table(struct
433 drm_device
434 *dev)
435{
436 struct radeon_device *rdev = dev->dev_private;
437 struct radeon_mode_info *mode_info = &rdev->mode_info;
438 struct atom_context *ctx = mode_info->atom_context;
439 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
440 uint16_t size, data_offset;
441 uint8_t frev, crev;
442 uint16_t device_support;
443 uint8_t dac;
444 union atom_supported_devices *supported_devices;
445 int i, j;
446 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
447
448 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
449
450 supported_devices =
451 (union atom_supported_devices *)(ctx->bios + data_offset);
452
453 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
454
455 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
456 ATOM_CONNECTOR_INFO_I2C ci =
457 supported_devices->info.asConnInfo[i];
458
459 bios_connectors[i].valid = false;
460
461 if (!(device_support & (1 << i))) {
462 continue;
463 }
464
465 if (i == ATOM_DEVICE_CV_INDEX) {
466 DRM_DEBUG("Skipping Component Video\n");
467 continue;
468 }
469
771fe6b9
JG		 470 bios_connectors[i].connector_type =
471 supported_devices_connector_convert[ci.sucConnectorInfo.
472 sbfAccess.
473 bfConnectorType];
474
475 if (bios_connectors[i].connector_type ==
476 DRM_MODE_CONNECTOR_Unknown)
477 continue;
478
479 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
480
481 if ((rdev->family == CHIP_RS690) ||
482 (rdev->family == CHIP_RS740)) {
483 if ((i == ATOM_DEVICE_DFP2_INDEX)
484 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
485 bios_connectors[i].line_mux =
486 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
487 else if ((i == ATOM_DEVICE_DFP3_INDEX)
488 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
489 bios_connectors[i].line_mux =
490 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
491 else
492 bios_connectors[i].line_mux =
493 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
494 } else
495 bios_connectors[i].line_mux =
496 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
497
498 /* give tv unique connector ids */
499 if (i == ATOM_DEVICE_TV1_INDEX) {
500 bios_connectors[i].ddc_bus.valid = false;
501 bios_connectors[i].line_mux = 50;
502 } else if (i == ATOM_DEVICE_TV2_INDEX) {
503 bios_connectors[i].ddc_bus.valid = false;
504 bios_connectors[i].line_mux = 51;
505 } else if (i == ATOM_DEVICE_CV_INDEX) {
506 bios_connectors[i].ddc_bus.valid = false;
507 bios_connectors[i].line_mux = 52;
508 } else
509 bios_connectors[i].ddc_bus =
510 radeon_lookup_gpio(dev,
511 bios_connectors[i].line_mux);
512
513 /* Always set the connector type to VGA for CRT1/CRT2. if they are
514 * shared with a DVI port, we'll pick up the DVI connector when we
515 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
516 */
517 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
518 bios_connectors[i].connector_type =
519 DRM_MODE_CONNECTOR_VGA;
520
521 if (!radeon_atom_apply_quirks
522 (dev, (1 << i), &bios_connectors[i].connector_type,
848577ee 523 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
771fe6b9
JG		 524 continue;
525
526 bios_connectors[i].valid = true;
527 bios_connectors[i].devices = (1 << i);
528
529 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
530 radeon_add_atom_encoder(dev,
531 radeon_get_encoder_id(dev,
532 (1 << i),
533 dac),
534 (1 << i));
535 else
536 radeon_add_legacy_encoder(dev,
537 radeon_get_encoder_id(dev,
538 (1 <<
539 i),
540 dac),
541 (1 << i));
542 }
543
544 /* combine shared connectors */
545 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
546 if (bios_connectors[i].valid) {
547 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
548 if (bios_connectors[j].valid && (i != j)) {
549 if (bios_connectors[i].line_mux ==
550 bios_connectors[j].line_mux) {
551 if (((bios_connectors[i].
552 devices &
553 (ATOM_DEVICE_DFP_SUPPORT))
554 && (bios_connectors[j].
555 devices &
556 (ATOM_DEVICE_CRT_SUPPORT)))
557 ||
558 ((bios_connectors[j].
559 devices &
560 (ATOM_DEVICE_DFP_SUPPORT))
561 && (bios_connectors[i].
562 devices &
563 (ATOM_DEVICE_CRT_SUPPORT)))) {
564 bios_connectors[i].
565 devices |=
566 bios_connectors[j].
567 devices;
568 bios_connectors[i].
569 connector_type =
570 DRM_MODE_CONNECTOR_DVII;
571 bios_connectors[j].
572 valid = false;
573 }
574 }
575 }
576 }
577 }
578 }
579
580 /* add the connectors */
581 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
582 if (bios_connectors[i].valid)
583 radeon_add_atom_connector(dev,
584 bios_connectors[i].line_mux,
585 bios_connectors[i].devices,
586 bios_connectors[i].
587 connector_type,
588 &bios_connectors[i].ddc_bus,
589 false, 0);
590 }
591
592 radeon_link_encoder_connector(dev);
593
594 return true;
595}
596
597union firmware_info {
598 ATOM_FIRMWARE_INFO info;
599 ATOM_FIRMWARE_INFO_V1_2 info_12;
600 ATOM_FIRMWARE_INFO_V1_3 info_13;
601 ATOM_FIRMWARE_INFO_V1_4 info_14;
602};
603
604bool radeon_atom_get_clock_info(struct drm_device *dev)
605{
606 struct radeon_device *rdev = dev->dev_private;
607 struct radeon_mode_info *mode_info = &rdev->mode_info;
608 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
609 union firmware_info *firmware_info;
610 uint8_t frev, crev;
611 struct radeon_pll *p1pll = &rdev->clock.p1pll;
612 struct radeon_pll *p2pll = &rdev->clock.p2pll;
613 struct radeon_pll *spll = &rdev->clock.spll;
614 struct radeon_pll *mpll = &rdev->clock.mpll;
615 uint16_t data_offset;
616
617 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
618 &crev, &data_offset);
619
620 firmware_info =
621 (union firmware_info *)(mode_info->atom_context->bios +
622 data_offset);
623
624 if (firmware_info) {
625 /* pixel clocks */
626 p1pll->reference_freq =
627 le16_to_cpu(firmware_info->info.usReferenceClock);
628 p1pll->reference_div = 0;
629
630 p1pll->pll_out_min =
631 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
632 p1pll->pll_out_max =
633 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
634
635 if (p1pll->pll_out_min == 0) {
636 if (ASIC_IS_AVIVO(rdev))
637 p1pll->pll_out_min = 64800;
638 else
639 p1pll->pll_out_min = 20000;
640 }
641
642 p1pll->pll_in_min =
643 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
644 p1pll->pll_in_max =
645 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
646
647 *p2pll = *p1pll;
648
649 /* system clock */
650 spll->reference_freq =
651 le16_to_cpu(firmware_info->info.usReferenceClock);
652 spll->reference_div = 0;
653
654 spll->pll_out_min =
655 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
656 spll->pll_out_max =
657 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
658
659 /* ??? */
660 if (spll->pll_out_min == 0) {
661 if (ASIC_IS_AVIVO(rdev))
662 spll->pll_out_min = 64800;
663 else
664 spll->pll_out_min = 20000;
665 }
666
667 spll->pll_in_min =
668 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
669 spll->pll_in_max =
670 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
671
672 /* memory clock */
673 mpll->reference_freq =
674 le16_to_cpu(firmware_info->info.usReferenceClock);
675 mpll->reference_div = 0;
676
677 mpll->pll_out_min =
678 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
679 mpll->pll_out_max =
680 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
681
682 /* ??? */
683 if (mpll->pll_out_min == 0) {
684 if (ASIC_IS_AVIVO(rdev))
685 mpll->pll_out_min = 64800;
686 else
687 mpll->pll_out_min = 20000;
688 }
689
690 mpll->pll_in_min =
691 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
692 mpll->pll_in_max =
693 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
694
695 rdev->clock.default_sclk =
696 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
697 rdev->clock.default_mclk =
698 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
699
700 return true;
701 }
702 return false;
703}
704
705struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
706 radeon_encoder
707 *encoder)
708{
709 struct drm_device *dev = encoder->base.dev;
710 struct radeon_device *rdev = dev->dev_private;
711 struct radeon_mode_info *mode_info = &rdev->mode_info;
712 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
713 uint16_t data_offset;
714 struct _ATOM_TMDS_INFO *tmds_info;
715 uint8_t frev, crev;
716 uint16_t maxfreq;
717 int i;
718 struct radeon_encoder_int_tmds *tmds = NULL;
719
720 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
721 &crev, &data_offset);
722
723 tmds_info =
724 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
725 data_offset);
726
727 if (tmds_info) {
728 tmds =
729 kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
730
731 if (!tmds)
732 return NULL;
733
734 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
735 for (i = 0; i < 4; i++) {
736 tmds->tmds_pll[i].freq =
737 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
738 tmds->tmds_pll[i].value =
739 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
740 tmds->tmds_pll[i].value |=
741 (tmds_info->asMiscInfo[i].
742 ucPLL_VCO_Gain & 0x3f) << 6;
743 tmds->tmds_pll[i].value |=
744 (tmds_info->asMiscInfo[i].
745 ucPLL_DutyCycle & 0xf) << 12;
746 tmds->tmds_pll[i].value |=
747 (tmds_info->asMiscInfo[i].
748 ucPLL_VoltageSwing & 0xf) << 16;
749
750 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
751 tmds->tmds_pll[i].freq,
752 tmds->tmds_pll[i].value);
753
754 if (maxfreq == tmds->tmds_pll[i].freq) {
755 tmds->tmds_pll[i].freq = 0xffffffff;
756 break;
757 }
758 }
759 }
760 return tmds;
761}
762
763union lvds_info {
764 struct _ATOM_LVDS_INFO info;
765 struct _ATOM_LVDS_INFO_V12 info_12;
766};
767
768struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
769 radeon_encoder
770 *encoder)
771{
772 struct drm_device *dev = encoder->base.dev;
773 struct radeon_device *rdev = dev->dev_private;
774 struct radeon_mode_info *mode_info = &rdev->mode_info;
775 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
776 uint16_t data_offset;
777 union lvds_info *lvds_info;
778 uint8_t frev, crev;
779 struct radeon_encoder_atom_dig *lvds = NULL;
780
781 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
782 &crev, &data_offset);
783
784 lvds_info =
785 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
786
787 if (lvds_info) {
788 lvds =
789 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
790
791 if (!lvds)
792 return NULL;
793
794 lvds->native_mode.dotclock =
795 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
796 lvds->native_mode.panel_xres =
797 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
798 lvds->native_mode.panel_yres =
799 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
800 lvds->native_mode.hblank =
801 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
802 lvds->native_mode.hoverplus =
803 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
804 lvds->native_mode.hsync_width =
805 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
806 lvds->native_mode.vblank =
807 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
808 lvds->native_mode.voverplus =
809 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
810 lvds->native_mode.vsync_width =
811 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
812 lvds->panel_pwr_delay =
813 le16_to_cpu(lvds_info->info.usOffDelayInMs);
814 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
815
816 encoder->native_mode = lvds->native_mode;
817 }
818 return lvds;
819}
820
6fe7ac3f
AD		 821struct radeon_encoder_primary_dac *
822radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
823{
824 struct drm_device *dev = encoder->base.dev;
825 struct radeon_device *rdev = dev->dev_private;
826 struct radeon_mode_info *mode_info = &rdev->mode_info;
827 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
828 uint16_t data_offset;
829 struct _COMPASSIONATE_DATA *dac_info;
830 uint8_t frev, crev;
831 uint8_t bg, dac;
6fe7ac3f
AD		 832 struct radeon_encoder_primary_dac *p_dac = NULL;
833
834 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
835
836 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
837
838 if (dac_info) {
839 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
840
841 if (!p_dac)
842 return NULL;
843
844 bg = dac_info->ucDAC1_BG_Adjustment;
845 dac = dac_info->ucDAC1_DAC_Adjustment;
846 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
847
848 }
849 return p_dac;
850}
851
4ce001ab
DA		 852bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
853 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
854 int32_t *pixel_clock)
855{
856 struct radeon_mode_info *mode_info = &rdev->mode_info;
857 ATOM_ANALOG_TV_INFO *tv_info;
858 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
859 ATOM_DTD_FORMAT *dtd_timings;
860 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
861 u8 frev, crev;
862 uint16_t data_offset;
863
864 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
865
866 switch (crev) {
867 case 1:
868 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
869 if (index > MAX_SUPPORTED_TV_TIMING)
870 return false;
871
872 crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
873 crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
874 crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
875 crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
876
877 crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
878 crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
879 crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
880 crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
881
882 crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo;
883
884 crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight);
885 crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft);
886 crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom);
887 crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop);
888 *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
889
890 if (index == 1) {
891 /* PAL timings appear to have wrong values for totals */
892 crtc_timing->usH_Total -= 1;
893 crtc_timing->usV_Total -= 1;
894 }
895 break;
896 case 2:
897 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
898 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
899 return false;
900
901 dtd_timings = &tv_info_v1_2->aModeTimings[index];
902 crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time);
903 crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive);
904 crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset);
905 crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth);
906 crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time);
907 crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive);
908 crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset);
909 crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth);
910
911 crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
912 *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
913 break;
914 }
915 return true;
916}
917
6fe7ac3f
AD		 918struct radeon_encoder_tv_dac *
919radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
920{
921 struct drm_device *dev = encoder->base.dev;
922 struct radeon_device *rdev = dev->dev_private;
923 struct radeon_mode_info *mode_info = &rdev->mode_info;
924 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
925 uint16_t data_offset;
926 struct _COMPASSIONATE_DATA *dac_info;
927 uint8_t frev, crev;
928 uint8_t bg, dac;
6fe7ac3f
AD		 929 struct radeon_encoder_tv_dac *tv_dac = NULL;
930
931 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
932
933 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
934
935 if (dac_info) {
936 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
937
938 if (!tv_dac)
939 return NULL;
940
941 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
942 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
943 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
944
945 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
946 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
947 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
948
949 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
950 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
951 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
952
953 }
954 return tv_dac;
955}
956
771fe6b9
JG		 957void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
958{
959 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
960 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
961
962 args.ucEnable = enable;
963
964 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
965}
966
967void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
968{
969 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
970 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
971
972 args.ucEnable = enable;
973
974 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
975}
976
977void radeon_atom_set_engine_clock(struct radeon_device *rdev,
978 uint32_t eng_clock)
979{
980 SET_ENGINE_CLOCK_PS_ALLOCATION args;
981 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
982
983 args.ulTargetEngineClock = eng_clock; /* 10 khz */
984
985 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
986}
987
988void radeon_atom_set_memory_clock(struct radeon_device *rdev,
989 uint32_t mem_clock)
990{
991 SET_MEMORY_CLOCK_PS_ALLOCATION args;
992 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
993
994 if (rdev->flags & RADEON_IS_IGP)
995 return;
996
997 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
998
999 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1000}
1001
1002void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1003{
1004 struct radeon_device *rdev = dev->dev_private;
1005 uint32_t bios_2_scratch, bios_6_scratch;
1006
1007 if (rdev->family >= CHIP_R600) {
4ce001ab 1008 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 1009 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1010 } else {
4ce001ab 1011 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 1012 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1013 }
1014
1015 /* let the bios control the backlight */
1016 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1017
1018 /* tell the bios not to handle mode switching */
1019 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1020
1021 if (rdev->family >= CHIP_R600) {
1022 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1023 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1024 } else {
1025 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1026 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1027 }
1028
1029}
1030
1031void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1032{
1033 struct drm_device *dev = encoder->dev;
1034 struct radeon_device *rdev = dev->dev_private;
1035 uint32_t bios_6_scratch;
1036
1037 if (rdev->family >= CHIP_R600)
1038 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1039 else
1040 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1041
1042 if (lock)
1043 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1044 else
1045 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1046
1047 if (rdev->family >= CHIP_R600)
1048 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1049 else
1050 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1051}
1052
1053/* at some point we may want to break this out into individual functions */
1054void
1055radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1056 struct drm_encoder *encoder,
1057 bool connected)
1058{
1059 struct drm_device *dev = connector->dev;
1060 struct radeon_device *rdev = dev->dev_private;
1061 struct radeon_connector *radeon_connector =
1062 to_radeon_connector(connector);
1063 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1064 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1065
1066 if (rdev->family >= CHIP_R600) {
1067 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1068 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1069 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1070 } else {
1071 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1072 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1073 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1074 }
1075
1076 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1077 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1078 if (connected) {
1079 DRM_DEBUG("TV1 connected\n");
1080 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1081 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1082 } else {
1083 DRM_DEBUG("TV1 disconnected\n");
1084 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1085 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1086 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1087 }
1088 }
1089 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1090 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1091 if (connected) {
1092 DRM_DEBUG("CV connected\n");
1093 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1094 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1095 } else {
1096 DRM_DEBUG("CV disconnected\n");
1097 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1098 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1099 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1100 }
1101 }
1102 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1103 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1104 if (connected) {
1105 DRM_DEBUG("LCD1 connected\n");
1106 bios_0_scratch |= ATOM_S0_LCD1;
1107 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1108 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1109 } else {
1110 DRM_DEBUG("LCD1 disconnected\n");
1111 bios_0_scratch &= ~ATOM_S0_LCD1;
1112 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1113 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1114 }
1115 }
1116 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1117 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1118 if (connected) {
1119 DRM_DEBUG("CRT1 connected\n");
1120 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1121 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1122 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1123 } else {
1124 DRM_DEBUG("CRT1 disconnected\n");
1125 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1126 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1127 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1128 }
1129 }
1130 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1131 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1132 if (connected) {
1133 DRM_DEBUG("CRT2 connected\n");
1134 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1135 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1136 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1137 } else {
1138 DRM_DEBUG("CRT2 disconnected\n");
1139 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1140 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1141 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1142 }
1143 }
1144 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1145 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1146 if (connected) {
1147 DRM_DEBUG("DFP1 connected\n");
1148 bios_0_scratch |= ATOM_S0_DFP1;
1149 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1150 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1151 } else {
1152 DRM_DEBUG("DFP1 disconnected\n");
1153 bios_0_scratch &= ~ATOM_S0_DFP1;
1154 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1155 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1156 }
1157 }
1158 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1159 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1160 if (connected) {
1161 DRM_DEBUG("DFP2 connected\n");
1162 bios_0_scratch |= ATOM_S0_DFP2;
1163 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1164 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1165 } else {
1166 DRM_DEBUG("DFP2 disconnected\n");
1167 bios_0_scratch &= ~ATOM_S0_DFP2;
1168 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1169 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1170 }
1171 }
1172 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1173 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1174 if (connected) {
1175 DRM_DEBUG("DFP3 connected\n");
1176 bios_0_scratch |= ATOM_S0_DFP3;
1177 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1178 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1179 } else {
1180 DRM_DEBUG("DFP3 disconnected\n");
1181 bios_0_scratch &= ~ATOM_S0_DFP3;
1182 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1183 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1184 }
1185 }
1186 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1187 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1188 if (connected) {
1189 DRM_DEBUG("DFP4 connected\n");
1190 bios_0_scratch |= ATOM_S0_DFP4;
1191 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1192 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1193 } else {
1194 DRM_DEBUG("DFP4 disconnected\n");
1195 bios_0_scratch &= ~ATOM_S0_DFP4;
1196 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1197 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1198 }
1199 }
1200 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1201 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1202 if (connected) {
1203 DRM_DEBUG("DFP5 connected\n");
1204 bios_0_scratch |= ATOM_S0_DFP5;
1205 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1206 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1207 } else {
1208 DRM_DEBUG("DFP5 disconnected\n");
1209 bios_0_scratch &= ~ATOM_S0_DFP5;
1210 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1211 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1212 }
1213 }
1214
1215 if (rdev->family >= CHIP_R600) {
1216 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1217 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1218 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1219 } else {
1220 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1221 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1222 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1223 }
1224}
1225
1226void
1227radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1228{
1229 struct drm_device *dev = encoder->dev;
1230 struct radeon_device *rdev = dev->dev_private;
1231 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1232 uint32_t bios_3_scratch;
1233
1234 if (rdev->family >= CHIP_R600)
1235 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1236 else
1237 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1238
1239 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1240 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1241 bios_3_scratch |= (crtc << 18);
1242 }
1243 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1244 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1245 bios_3_scratch |= (crtc << 24);
1246 }
1247 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1248 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1249 bios_3_scratch |= (crtc << 16);
1250 }
1251 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1252 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1253 bios_3_scratch |= (crtc << 20);
1254 }
1255 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1256 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1257 bios_3_scratch |= (crtc << 17);
1258 }
1259 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1260 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1261 bios_3_scratch |= (crtc << 19);
1262 }
1263 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1264 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1265 bios_3_scratch |= (crtc << 23);
1266 }
1267 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1268 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1269 bios_3_scratch |= (crtc << 25);
1270 }
1271
1272 if (rdev->family >= CHIP_R600)
1273 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1274 else
1275 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1276}
1277
1278void
1279radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1280{
1281 struct drm_device *dev = encoder->dev;
1282 struct radeon_device *rdev = dev->dev_private;
1283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1284 uint32_t bios_2_scratch;
1285
1286 if (rdev->family >= CHIP_R600)
1287 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1288 else
1289 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1290
1291 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1292 if (on)
1293 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1294 else
1295 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1296 }
1297 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1298 if (on)
1299 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1300 else
1301 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1302 }
1303 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1304 if (on)
1305 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1306 else
1307 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1308 }
1309 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1310 if (on)
1311 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1312 else
1313 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1314 }
1315 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1316 if (on)
1317 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1318 else
1319 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1320 }
1321 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1322 if (on)
1323 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1324 else
1325 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1326 }
1327 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1328 if (on)
1329 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1330 else
1331 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1332 }
1333 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1334 if (on)
1335 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1336 else
1337 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1338 }
1339 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1340 if (on)
1341 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1342 else
1343 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1344 }
1345 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1346 if (on)
1347 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1348 else
1349 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1350 }
1351
1352 if (rdev->family >= CHIP_R600)
1353 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1354 else
1355 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1356}
kernel source for telekom puls (alcatel/mediatek)