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drm/radeon/kms: clean up DP debugging
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 49 bool linkb, uint32_t igp_lane_info,
6a93cb25 50 uint16_t connector_object_id);
771fe6b9
JG		 51
52/* from radeon_legacy_encoder.c */
53extern void
54radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
55 uint32_t supported_device);
56
57union atom_supported_devices {
58 struct _ATOM_SUPPORTED_DEVICES_INFO info;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
61};
62
746c1aa4
DA		 63static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device *dev,
64 uint8_t id)
771fe6b9
JG		 65{
66 struct radeon_device *rdev = dev->dev_private;
67 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset;
73
74 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
75 i2c.valid = false;
76
77 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
78
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
6a93cb25
AD		 81 gpio = &i2c_info->asGPIO_Info[id];
82
83 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
84 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
85 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
86 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
87 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
88 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
89 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
90 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
91 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
92 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
93 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
94 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
95 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
96 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
97 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
98 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
99
100 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
101 i2c.hw_capable = true;
102 else
103 i2c.hw_capable = false;
104
105 if (gpio->sucI2cId.ucAccess == 0xa0)
106 i2c.mm_i2c = true;
107 else
108 i2c.mm_i2c = false;
109
110 i2c.i2c_id = gpio->sucI2cId.ucAccess;
111
771fe6b9
JG		 112 i2c.valid = true;
113
114 return i2c;
115}
116
117static bool radeon_atom_apply_quirks(struct drm_device *dev,
118 uint32_t supported_device,
119 int *connector_type,
848577ee 120 struct radeon_i2c_bus_rec *i2c_bus,
705af9c7 121 uint16_t *line_mux)
771fe6b9
JG		 122{
123
124 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
125 if ((dev->pdev->device == 0x791e) &&
126 (dev->pdev->subsystem_vendor == 0x1043) &&
127 (dev->pdev->subsystem_device == 0x826d)) {
128 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
129 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
130 *connector_type = DRM_MODE_CONNECTOR_DVID;
131 }
132
133 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
134 if ((dev->pdev->device == 0x7941) &&
135 (dev->pdev->subsystem_vendor == 0x147b) &&
136 (dev->pdev->subsystem_device == 0x2412)) {
137 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
138 return false;
139 }
140
141 /* Falcon NW laptop lists vga ddc line for LVDS */
142 if ((dev->pdev->device == 0x5653) &&
143 (dev->pdev->subsystem_vendor == 0x1462) &&
144 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 145 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 146 i2c_bus->valid = false;
848577ee
AD		 147 *line_mux = 53;
148 }
771fe6b9
JG		 149 }
150
4e3f9b78
AD		 151 /* HIS X1300 is DVI+VGA, not DVI+DVI */
152 if ((dev->pdev->device == 0x7146) &&
153 (dev->pdev->subsystem_vendor == 0x17af) &&
154 (dev->pdev->subsystem_device == 0x2058)) {
155 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
156 return false;
157 }
158
aa1a750e
DA		 159 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
160 if ((dev->pdev->device == 0x7142) &&
161 (dev->pdev->subsystem_vendor == 0x1458) &&
162 (dev->pdev->subsystem_device == 0x2134)) {
163 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
164 return false;
165 }
166
167
771fe6b9
JG		 168 /* Funky macbooks */
169 if ((dev->pdev->device == 0x71C5) &&
170 (dev->pdev->subsystem_vendor == 0x106b) &&
171 (dev->pdev->subsystem_device == 0x0080)) {
172 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
173 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
174 return false;
175 }
176
771fe6b9
JG		 177 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
178 if ((dev->pdev->device == 0x9598) &&
179 (dev->pdev->subsystem_vendor == 0x1043) &&
180 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 181 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 182 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 183 }
184 }
185
186 /* ASUS HD 3450 board lists the DVI port as HDMI */
187 if ((dev->pdev->device == 0x95C5) &&
188 (dev->pdev->subsystem_vendor == 0x1043) &&
189 (dev->pdev->subsystem_device == 0x01e2)) {
190 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 191 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 192 }
193 }
194
705af9c7
AD		 195 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
196 * HDMI + VGA reporting as HDMI
197 */
198 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
199 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
200 *connector_type = DRM_MODE_CONNECTOR_VGA;
201 *line_mux = 0;
202 }
203 }
204
3e5f8ff3
AD		 205 /* Acer laptop reports DVI-D as DVI-I */
206 if ((dev->pdev->device == 0x95c4) &&
207 (dev->pdev->subsystem_vendor == 0x1025) &&
208 (dev->pdev->subsystem_device == 0x013c)) {
209 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
210 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
211 *connector_type = DRM_MODE_CONNECTOR_DVID;
212 }
213
771fe6b9
JG		 214 return true;
215}
216
217const int supported_devices_connector_convert[] = {
218 DRM_MODE_CONNECTOR_Unknown,
219 DRM_MODE_CONNECTOR_VGA,
220 DRM_MODE_CONNECTOR_DVII,
221 DRM_MODE_CONNECTOR_DVID,
222 DRM_MODE_CONNECTOR_DVIA,
223 DRM_MODE_CONNECTOR_SVIDEO,
224 DRM_MODE_CONNECTOR_Composite,
225 DRM_MODE_CONNECTOR_LVDS,
226 DRM_MODE_CONNECTOR_Unknown,
227 DRM_MODE_CONNECTOR_Unknown,
228 DRM_MODE_CONNECTOR_HDMIA,
229 DRM_MODE_CONNECTOR_HDMIB,
230 DRM_MODE_CONNECTOR_Unknown,
231 DRM_MODE_CONNECTOR_Unknown,
232 DRM_MODE_CONNECTOR_9PinDIN,
233 DRM_MODE_CONNECTOR_DisplayPort
234};
235
b75fad06
AD		 236const uint16_t supported_devices_connector_object_id_convert[] = {
237 CONNECTOR_OBJECT_ID_NONE,
238 CONNECTOR_OBJECT_ID_VGA,
239 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
240 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
241 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
242 CONNECTOR_OBJECT_ID_COMPOSITE,
243 CONNECTOR_OBJECT_ID_SVIDEO,
244 CONNECTOR_OBJECT_ID_LVDS,
245 CONNECTOR_OBJECT_ID_9PIN_DIN,
246 CONNECTOR_OBJECT_ID_9PIN_DIN,
247 CONNECTOR_OBJECT_ID_DISPLAYPORT,
248 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
249 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
250 CONNECTOR_OBJECT_ID_SVIDEO
251};
252
771fe6b9
JG		 253const int object_connector_convert[] = {
254 DRM_MODE_CONNECTOR_Unknown,
255 DRM_MODE_CONNECTOR_DVII,
256 DRM_MODE_CONNECTOR_DVII,
257 DRM_MODE_CONNECTOR_DVID,
258 DRM_MODE_CONNECTOR_DVID,
259 DRM_MODE_CONNECTOR_VGA,
260 DRM_MODE_CONNECTOR_Composite,
261 DRM_MODE_CONNECTOR_SVIDEO,
262 DRM_MODE_CONNECTOR_Unknown,
705af9c7 263 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 264 DRM_MODE_CONNECTOR_9PinDIN,
265 DRM_MODE_CONNECTOR_Unknown,
266 DRM_MODE_CONNECTOR_HDMIA,
267 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 268 DRM_MODE_CONNECTOR_LVDS,
269 DRM_MODE_CONNECTOR_9PinDIN,
270 DRM_MODE_CONNECTOR_Unknown,
271 DRM_MODE_CONNECTOR_Unknown,
272 DRM_MODE_CONNECTOR_Unknown,
273 DRM_MODE_CONNECTOR_DisplayPort
274};
275
276bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
277{
278 struct radeon_device *rdev = dev->dev_private;
279 struct radeon_mode_info *mode_info = &rdev->mode_info;
280 struct atom_context *ctx = mode_info->atom_context;
281 int index = GetIndexIntoMasterTable(DATA, Object_Header);
282 uint16_t size, data_offset;
283 uint8_t frev, crev, line_mux = 0;
284 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
285 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
286 ATOM_OBJECT_HEADER *obj_header;
287 int i, j, path_size, device_support;
288 int connector_type;
b75fad06 289 uint16_t igp_lane_info, conn_id, connector_object_id;
771fe6b9
JG		 290 bool linkb;
291 struct radeon_i2c_bus_rec ddc_bus;
771fe6b9
JG		 292 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
293
294 if (data_offset == 0)
295 return false;
296
297 if (crev < 2)
298 return false;
299
300 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
301 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
302 (ctx->bios + data_offset +
303 le16_to_cpu(obj_header->usDisplayPathTableOffset));
304 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
305 (ctx->bios + data_offset +
306 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
307 device_support = le16_to_cpu(obj_header->usDeviceSupport);
308
309 path_size = 0;
310 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
311 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
312 ATOM_DISPLAY_OBJECT_PATH *path;
313 addr += path_size;
314 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
315 path_size += le16_to_cpu(path->usSize);
316 linkb = false;
771fe6b9
JG		 317 if (device_support & le16_to_cpu(path->usDeviceTag)) {
318 uint8_t con_obj_id, con_obj_num, con_obj_type;
319
320 con_obj_id =
321 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
322 >> OBJECT_ID_SHIFT;
323 con_obj_num =
324 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
325 >> ENUM_ID_SHIFT;
326 con_obj_type =
327 (le16_to_cpu(path->usConnObjectId) &
328 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
329
4bbd4973
DA		 330 /* TODO CV support */
331 if (le16_to_cpu(path->usDeviceTag) ==
332 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 333 continue;
334
ee59f2b4
AD		 335 /* IGP chips */
336 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 337 (con_obj_id ==
338 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
339 uint16_t igp_offset = 0;
340 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
341
342 index =
343 GetIndexIntoMasterTable(DATA,
344 IntegratedSystemInfo);
345
346 atom_parse_data_header(ctx, index, &size, &frev,
347 &crev, &igp_offset);
348
349 if (crev >= 2) {
350 igp_obj =
351 (ATOM_INTEGRATED_SYSTEM_INFO_V2
352 *) (ctx->bios + igp_offset);
353
354 if (igp_obj) {
355 uint32_t slot_config, ct;
356
357 if (con_obj_num == 1)
358 slot_config =
359 igp_obj->
360 ulDDISlot1Config;
361 else
362 slot_config =
363 igp_obj->
364 ulDDISlot2Config;
365
366 ct = (slot_config >> 16) & 0xff;
367 connector_type =
368 object_connector_convert
369 [ct];
b75fad06 370 connector_object_id = ct;
771fe6b9
JG		 371 igp_lane_info =
372 slot_config & 0xffff;
373 } else
374 continue;
375 } else
376 continue;
377 } else {
378 igp_lane_info = 0;
379 connector_type =
380 object_connector_convert[con_obj_id];
b75fad06 381 connector_object_id = con_obj_id;
771fe6b9
JG		 382 }
383
384 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
385 continue;
386
387 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
388 j++) {
389 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
390
391 enc_obj_id =
392 (le16_to_cpu(path->usGraphicObjIds[j]) &
393 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
394 enc_obj_num =
395 (le16_to_cpu(path->usGraphicObjIds[j]) &
396 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
397 enc_obj_type =
398 (le16_to_cpu(path->usGraphicObjIds[j]) &
399 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
400
401 /* FIXME: add support for router objects */
402 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
403 if (enc_obj_num == 2)
404 linkb = true;
405 else
406 linkb = false;
407
408 radeon_add_atom_encoder(dev,
409 enc_obj_id,
410 le16_to_cpu
411 (path->
412 usDeviceTag));
413
414 }
415 }
416
417 /* look up gpio for ddc */
418 if ((le16_to_cpu(path->usDeviceTag) &
419 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
420 == 0) {
421 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
422 if (le16_to_cpu(path->usConnObjectId) ==
423 le16_to_cpu(con_obj->asObjects[j].
424 usObjectID)) {
425 ATOM_COMMON_RECORD_HEADER
426 *record =
427 (ATOM_COMMON_RECORD_HEADER
428 *)
429 (ctx->bios + data_offset +
430 le16_to_cpu(con_obj->
431 asObjects[j].
432 usRecordOffset));
433 ATOM_I2C_RECORD *i2c_record;
6a93cb25 434
771fe6b9
JG		 435 while (record->ucRecordType > 0
436 && record->
437 ucRecordType <=
438 ATOM_MAX_OBJECT_RECORD_NUMBER) {
771fe6b9
JG		 439 switch (record->
440 ucRecordType) {
441 case ATOM_I2C_RECORD_TYPE:
442 i2c_record =
443 (ATOM_I2C_RECORD
444 *) record;
445 line_mux =
446 i2c_record->
447 sucI2cId.
448 bfI2C_LineMux;
449 break;
450 }
451 record =
452 (ATOM_COMMON_RECORD_HEADER
453 *) ((char *)record
454 +
455 record->
456 ucRecordSize);
457 }
458 break;
459 }
460 }
461 } else
462 line_mux = 0;
463
464 if ((le16_to_cpu(path->usDeviceTag) ==
465 ATOM_DEVICE_TV1_SUPPORT)
466 || (le16_to_cpu(path->usDeviceTag) ==
467 ATOM_DEVICE_TV2_SUPPORT)
468 || (le16_to_cpu(path->usDeviceTag) ==
469 ATOM_DEVICE_CV_SUPPORT))
470 ddc_bus.valid = false;
471 else
472 ddc_bus = radeon_lookup_gpio(dev, line_mux);
473
705af9c7
AD		 474 conn_id = le16_to_cpu(path->usConnObjectId);
475
476 if (!radeon_atom_apply_quirks
477 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
478 &ddc_bus, &conn_id))
479 continue;
480
771fe6b9 481 radeon_add_atom_connector(dev,
705af9c7 482 conn_id,
771fe6b9
JG		 483 le16_to_cpu(path->
484 usDeviceTag),
485 connector_type, &ddc_bus,
b75fad06 486 linkb, igp_lane_info,
6a93cb25 487 connector_object_id);
771fe6b9
JG		 488
489 }
490 }
491
492 radeon_link_encoder_connector(dev);
493
494 return true;
495}
496
b75fad06
AD		 497static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
498 int connector_type,
499 uint16_t devices)
500{
501 struct radeon_device *rdev = dev->dev_private;
502
503 if (rdev->flags & RADEON_IS_IGP) {
504 return supported_devices_connector_object_id_convert
505 [connector_type];
506 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
507 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
508 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
509 struct radeon_mode_info *mode_info = &rdev->mode_info;
510 struct atom_context *ctx = mode_info->atom_context;
511 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
512 uint16_t size, data_offset;
513 uint8_t frev, crev;
514 ATOM_XTMDS_INFO *xtmds;
515
516 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
517 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
518
519 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
520 if (connector_type == DRM_MODE_CONNECTOR_DVII)
521 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
522 else
523 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
524 } else {
525 if (connector_type == DRM_MODE_CONNECTOR_DVII)
526 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
527 else
528 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
529 }
530 } else {
531 return supported_devices_connector_object_id_convert
532 [connector_type];
533 }
534}
535
771fe6b9
JG		 536struct bios_connector {
537 bool valid;
705af9c7 538 uint16_t line_mux;
771fe6b9
JG		 539 uint16_t devices;
540 int connector_type;
541 struct radeon_i2c_bus_rec ddc_bus;
542};
543
544bool radeon_get_atom_connector_info_from_supported_devices_table(struct
545 drm_device
546 *dev)
547{
548 struct radeon_device *rdev = dev->dev_private;
549 struct radeon_mode_info *mode_info = &rdev->mode_info;
550 struct atom_context *ctx = mode_info->atom_context;
551 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
552 uint16_t size, data_offset;
553 uint8_t frev, crev;
554 uint16_t device_support;
555 uint8_t dac;
556 union atom_supported_devices *supported_devices;
557 int i, j;
558 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
559
560 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
561
562 supported_devices =
563 (union atom_supported_devices *)(ctx->bios + data_offset);
564
565 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
566
567 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
568 ATOM_CONNECTOR_INFO_I2C ci =
569 supported_devices->info.asConnInfo[i];
570
571 bios_connectors[i].valid = false;
572
573 if (!(device_support & (1 << i))) {
574 continue;
575 }
576
577 if (i == ATOM_DEVICE_CV_INDEX) {
578 DRM_DEBUG("Skipping Component Video\n");
579 continue;
580 }
581
771fe6b9
JG		 582 bios_connectors[i].connector_type =
583 supported_devices_connector_convert[ci.sucConnectorInfo.
584 sbfAccess.
585 bfConnectorType];
586
587 if (bios_connectors[i].connector_type ==
588 DRM_MODE_CONNECTOR_Unknown)
589 continue;
590
591 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
592
593 if ((rdev->family == CHIP_RS690) ||
594 (rdev->family == CHIP_RS740)) {
595 if ((i == ATOM_DEVICE_DFP2_INDEX)
596 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
597 bios_connectors[i].line_mux =
598 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
599 else if ((i == ATOM_DEVICE_DFP3_INDEX)
600 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
601 bios_connectors[i].line_mux =
602 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
603 else
604 bios_connectors[i].line_mux =
605 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
606 } else
607 bios_connectors[i].line_mux =
608 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
609
610 /* give tv unique connector ids */
611 if (i == ATOM_DEVICE_TV1_INDEX) {
612 bios_connectors[i].ddc_bus.valid = false;
613 bios_connectors[i].line_mux = 50;
614 } else if (i == ATOM_DEVICE_TV2_INDEX) {
615 bios_connectors[i].ddc_bus.valid = false;
616 bios_connectors[i].line_mux = 51;
617 } else if (i == ATOM_DEVICE_CV_INDEX) {
618 bios_connectors[i].ddc_bus.valid = false;
619 bios_connectors[i].line_mux = 52;
620 } else
621 bios_connectors[i].ddc_bus =
622 radeon_lookup_gpio(dev,
623 bios_connectors[i].line_mux);
624
625 /* Always set the connector type to VGA for CRT1/CRT2. if they are
626 * shared with a DVI port, we'll pick up the DVI connector when we
627 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
628 */
629 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
630 bios_connectors[i].connector_type =
631 DRM_MODE_CONNECTOR_VGA;
632
633 if (!radeon_atom_apply_quirks
634 (dev, (1 << i), &bios_connectors[i].connector_type,
848577ee 635 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
771fe6b9
JG		 636 continue;
637
638 bios_connectors[i].valid = true;
639 bios_connectors[i].devices = (1 << i);
640
641 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
642 radeon_add_atom_encoder(dev,
643 radeon_get_encoder_id(dev,
644 (1 << i),
645 dac),
646 (1 << i));
647 else
648 radeon_add_legacy_encoder(dev,
649 radeon_get_encoder_id(dev,
650 (1 <<
651 i),
652 dac),
653 (1 << i));
654 }
655
656 /* combine shared connectors */
657 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
658 if (bios_connectors[i].valid) {
659 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
660 if (bios_connectors[j].valid && (i != j)) {
661 if (bios_connectors[i].line_mux ==
662 bios_connectors[j].line_mux) {
663 if (((bios_connectors[i].
664 devices &
665 (ATOM_DEVICE_DFP_SUPPORT))
666 && (bios_connectors[j].
667 devices &
668 (ATOM_DEVICE_CRT_SUPPORT)))
669 ||
670 ((bios_connectors[j].
671 devices &
672 (ATOM_DEVICE_DFP_SUPPORT))
673 && (bios_connectors[i].
674 devices &
675 (ATOM_DEVICE_CRT_SUPPORT)))) {
676 bios_connectors[i].
677 devices |=
678 bios_connectors[j].
679 devices;
680 bios_connectors[i].
681 connector_type =
682 DRM_MODE_CONNECTOR_DVII;
683 bios_connectors[j].
684 valid = false;
685 }
686 }
687 }
688 }
689 }
690 }
691
692 /* add the connectors */
693 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
b75fad06
AD		 694 if (bios_connectors[i].valid) {
695 uint16_t connector_object_id =
696 atombios_get_connector_object_id(dev,
697 bios_connectors[i].connector_type,
698 bios_connectors[i].devices);
771fe6b9
JG		 699 radeon_add_atom_connector(dev,
700 bios_connectors[i].line_mux,
701 bios_connectors[i].devices,
702 bios_connectors[i].
703 connector_type,
704 &bios_connectors[i].ddc_bus,
b75fad06 705 false, 0,
6a93cb25 706 connector_object_id);
b75fad06 707 }
771fe6b9
JG		 708 }
709
710 radeon_link_encoder_connector(dev);
711
712 return true;
713}
714
715union firmware_info {
716 ATOM_FIRMWARE_INFO info;
717 ATOM_FIRMWARE_INFO_V1_2 info_12;
718 ATOM_FIRMWARE_INFO_V1_3 info_13;
719 ATOM_FIRMWARE_INFO_V1_4 info_14;
720};
721
722bool radeon_atom_get_clock_info(struct drm_device *dev)
723{
724 struct radeon_device *rdev = dev->dev_private;
725 struct radeon_mode_info *mode_info = &rdev->mode_info;
726 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
727 union firmware_info *firmware_info;
728 uint8_t frev, crev;
729 struct radeon_pll *p1pll = &rdev->clock.p1pll;
730 struct radeon_pll *p2pll = &rdev->clock.p2pll;
731 struct radeon_pll *spll = &rdev->clock.spll;
732 struct radeon_pll *mpll = &rdev->clock.mpll;
733 uint16_t data_offset;
734
735 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
736 &crev, &data_offset);
737
738 firmware_info =
739 (union firmware_info *)(mode_info->atom_context->bios +
740 data_offset);
741
742 if (firmware_info) {
743 /* pixel clocks */
744 p1pll->reference_freq =
745 le16_to_cpu(firmware_info->info.usReferenceClock);
746 p1pll->reference_div = 0;
747
bc293e58
MF		 748 if (crev < 2)
749 p1pll->pll_out_min =
750 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
751 else
752 p1pll->pll_out_min =
753 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 754 p1pll->pll_out_max =
755 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
756
757 if (p1pll->pll_out_min == 0) {
758 if (ASIC_IS_AVIVO(rdev))
759 p1pll->pll_out_min = 64800;
760 else
761 p1pll->pll_out_min = 20000;
8f552a66
AD		 762 } else if (p1pll->pll_out_min > 64800) {
763 /* Limiting the pll output range is a good thing generally as
764 * it limits the number of possible pll combinations for a given
765 * frequency presumably to the ones that work best on each card.
766 * However, certain duallink DVI monitors seem to like
767 * pll combinations that would be limited by this at least on
768 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
769 * family.
770 */
771 p1pll->pll_out_min = 64800;
771fe6b9
JG		 772 }
773
774 p1pll->pll_in_min =
775 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
776 p1pll->pll_in_max =
777 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
778
779 *p2pll = *p1pll;
780
781 /* system clock */
782 spll->reference_freq =
783 le16_to_cpu(firmware_info->info.usReferenceClock);
784 spll->reference_div = 0;
785
786 spll->pll_out_min =
787 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
788 spll->pll_out_max =
789 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
790
791 /* ??? */
792 if (spll->pll_out_min == 0) {
793 if (ASIC_IS_AVIVO(rdev))
794 spll->pll_out_min = 64800;
795 else
796 spll->pll_out_min = 20000;
797 }
798
799 spll->pll_in_min =
800 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
801 spll->pll_in_max =
802 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
803
804 /* memory clock */
805 mpll->reference_freq =
806 le16_to_cpu(firmware_info->info.usReferenceClock);
807 mpll->reference_div = 0;
808
809 mpll->pll_out_min =
810 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
811 mpll->pll_out_max =
812 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
813
814 /* ??? */
815 if (mpll->pll_out_min == 0) {
816 if (ASIC_IS_AVIVO(rdev))
817 mpll->pll_out_min = 64800;
818 else
819 mpll->pll_out_min = 20000;
820 }
821
822 mpll->pll_in_min =
823 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
824 mpll->pll_in_max =
825 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
826
827 rdev->clock.default_sclk =
828 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
829 rdev->clock.default_mclk =
830 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
831
832 return true;
833 }
834 return false;
835}
836
445282db
DA		 837bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
838 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 839{
840 struct drm_device *dev = encoder->base.dev;
841 struct radeon_device *rdev = dev->dev_private;
842 struct radeon_mode_info *mode_info = &rdev->mode_info;
843 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
844 uint16_t data_offset;
845 struct _ATOM_TMDS_INFO *tmds_info;
846 uint8_t frev, crev;
847 uint16_t maxfreq;
848 int i;
771fe6b9
JG		 849
850 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
851 &crev, &data_offset);
852
853 tmds_info =
854 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
855 data_offset);
856
857 if (tmds_info) {
771fe6b9
JG		 858 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
859 for (i = 0; i < 4; i++) {
860 tmds->tmds_pll[i].freq =
861 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
862 tmds->tmds_pll[i].value =
863 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
864 tmds->tmds_pll[i].value |=
865 (tmds_info->asMiscInfo[i].
866 ucPLL_VCO_Gain & 0x3f) << 6;
867 tmds->tmds_pll[i].value |=
868 (tmds_info->asMiscInfo[i].
869 ucPLL_DutyCycle & 0xf) << 12;
870 tmds->tmds_pll[i].value |=
871 (tmds_info->asMiscInfo[i].
872 ucPLL_VoltageSwing & 0xf) << 16;
873
874 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
875 tmds->tmds_pll[i].freq,
876 tmds->tmds_pll[i].value);
877
878 if (maxfreq == tmds->tmds_pll[i].freq) {
879 tmds->tmds_pll[i].freq = 0xffffffff;
880 break;
881 }
882 }
445282db 883 return true;
771fe6b9 884 }
445282db 885 return false;
771fe6b9
JG		 886}
887
ebbe1cb9
AD		 888static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
889 radeon_encoder
890 *encoder,
891 int id)
892{
893 struct drm_device *dev = encoder->base.dev;
894 struct radeon_device *rdev = dev->dev_private;
895 struct radeon_mode_info *mode_info = &rdev->mode_info;
896 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
897 uint16_t data_offset;
898 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
899 uint8_t frev, crev;
900 struct radeon_atom_ss *ss = NULL;
901
902 if (id > ATOM_MAX_SS_ENTRY)
903 return NULL;
904
905 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
906 &crev, &data_offset);
907
908 ss_info =
909 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
910
911 if (ss_info) {
912 ss =
913 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
914
915 if (!ss)
916 return NULL;
917
918 ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage);
919 ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType;
920 ss->step = ss_info->asSS_Info[id].ucSS_Step;
921 ss->delay = ss_info->asSS_Info[id].ucSS_Delay;
922 ss->range = ss_info->asSS_Info[id].ucSS_Range;
923 ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div;
924 }
925 return ss;
926}
927
771fe6b9
JG		 928union lvds_info {
929 struct _ATOM_LVDS_INFO info;
930 struct _ATOM_LVDS_INFO_V12 info_12;
931};
932
933struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
934 radeon_encoder
935 *encoder)
936{
937 struct drm_device *dev = encoder->base.dev;
938 struct radeon_device *rdev = dev->dev_private;
939 struct radeon_mode_info *mode_info = &rdev->mode_info;
940 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 941 uint16_t data_offset, misc;
771fe6b9
JG		 942 union lvds_info *lvds_info;
943 uint8_t frev, crev;
944 struct radeon_encoder_atom_dig *lvds = NULL;
945
946 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
947 &crev, &data_offset);
948
949 lvds_info =
950 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
951
952 if (lvds_info) {
953 lvds =
954 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
955
956 if (!lvds)
957 return NULL;
958
de2103e4 959 lvds->native_mode.clock =
771fe6b9 960 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 961 lvds->native_mode.hdisplay =
771fe6b9 962 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 963 lvds->native_mode.vdisplay =
771fe6b9 964 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 965 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
966 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
967 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
968 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
969 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
970 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
971 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
972 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
973 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
974 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
975 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
976 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 977 lvds->panel_pwr_delay =
978 le16_to_cpu(lvds_info->info.usOffDelayInMs);
979 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 980
981 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
982 if (misc & ATOM_VSYNC_POLARITY)
983 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
984 if (misc & ATOM_HSYNC_POLARITY)
985 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
986 if (misc & ATOM_COMPOSITESYNC)
987 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
988 if (misc & ATOM_INTERLACE)
989 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
990 if (misc & ATOM_DOUBLE_CLOCK_MODE)
991 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
992
de2103e4
AD		 993 /* set crtc values */
994 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 995
ebbe1cb9
AD		 996 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
997
771fe6b9
JG		 998 encoder->native_mode = lvds->native_mode;
999 }
1000 return lvds;
1001}
1002
6fe7ac3f
AD		 1003struct radeon_encoder_primary_dac *
1004radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1005{
1006 struct drm_device *dev = encoder->base.dev;
1007 struct radeon_device *rdev = dev->dev_private;
1008 struct radeon_mode_info *mode_info = &rdev->mode_info;
1009 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1010 uint16_t data_offset;
1011 struct _COMPASSIONATE_DATA *dac_info;
1012 uint8_t frev, crev;
1013 uint8_t bg, dac;
6fe7ac3f
AD		 1014 struct radeon_encoder_primary_dac *p_dac = NULL;
1015
1016 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1017
1018 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1019
1020 if (dac_info) {
1021 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1022
1023 if (!p_dac)
1024 return NULL;
1025
1026 bg = dac_info->ucDAC1_BG_Adjustment;
1027 dac = dac_info->ucDAC1_DAC_Adjustment;
1028 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1029
1030 }
1031 return p_dac;
1032}
1033
4ce001ab 1034bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1035 struct drm_display_mode *mode)
4ce001ab
DA		 1036{
1037 struct radeon_mode_info *mode_info = &rdev->mode_info;
1038 ATOM_ANALOG_TV_INFO *tv_info;
1039 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1040 ATOM_DTD_FORMAT *dtd_timings;
1041 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1042 u8 frev, crev;
5a9bcacc 1043 u16 data_offset, misc;
4ce001ab
DA		 1044
1045 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1046
1047 switch (crev) {
1048 case 1:
1049 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1050 if (index > MAX_SUPPORTED_TV_TIMING)
1051 return false;
1052
5a9bcacc
AD		 1053 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1054 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1055 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1056 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1057 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1058
1059 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1060 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1061 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1062 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1063 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1064
1065 mode->flags = 0;
1066 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1067 if (misc & ATOM_VSYNC_POLARITY)
1068 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1069 if (misc & ATOM_HSYNC_POLARITY)
1070 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1071 if (misc & ATOM_COMPOSITESYNC)
1072 mode->flags |= DRM_MODE_FLAG_CSYNC;
1073 if (misc & ATOM_INTERLACE)
1074 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1075 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1076 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1077
1078 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1079
1080 if (index == 1) {
1081 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1082 mode->crtc_htotal -= 1;
1083 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1084 }
1085 break;
1086 case 2:
1087 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1088 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1089 return false;
1090
1091 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1092 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1093 le16_to_cpu(dtd_timings->usHBlanking_Time);
1094 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1095 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1096 le16_to_cpu(dtd_timings->usHSyncOffset);
1097 mode->crtc_hsync_end = mode->crtc_hsync_start +
1098 le16_to_cpu(dtd_timings->usHSyncWidth);
1099
1100 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1101 le16_to_cpu(dtd_timings->usVBlanking_Time);
1102 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1103 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1104 le16_to_cpu(dtd_timings->usVSyncOffset);
1105 mode->crtc_vsync_end = mode->crtc_vsync_start +
1106 le16_to_cpu(dtd_timings->usVSyncWidth);
1107
1108 mode->flags = 0;
1109 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1110 if (misc & ATOM_VSYNC_POLARITY)
1111 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1112 if (misc & ATOM_HSYNC_POLARITY)
1113 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1114 if (misc & ATOM_COMPOSITESYNC)
1115 mode->flags |= DRM_MODE_FLAG_CSYNC;
1116 if (misc & ATOM_INTERLACE)
1117 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1118 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1119 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1120
1121 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1122 break;
1123 }
1124 return true;
1125}
1126
6fe7ac3f
AD		 1127struct radeon_encoder_tv_dac *
1128radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1129{
1130 struct drm_device *dev = encoder->base.dev;
1131 struct radeon_device *rdev = dev->dev_private;
1132 struct radeon_mode_info *mode_info = &rdev->mode_info;
1133 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1134 uint16_t data_offset;
1135 struct _COMPASSIONATE_DATA *dac_info;
1136 uint8_t frev, crev;
1137 uint8_t bg, dac;
6fe7ac3f
AD		 1138 struct radeon_encoder_tv_dac *tv_dac = NULL;
1139
1140 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1141
1142 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1143
1144 if (dac_info) {
1145 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1146
1147 if (!tv_dac)
1148 return NULL;
1149
1150 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1151 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1152 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1153
1154 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1155 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1156 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1157
1158 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1159 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1160 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1161
1162 }
1163 return tv_dac;
1164}
1165
771fe6b9
JG		 1166void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1167{
1168 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1169 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1170
1171 args.ucEnable = enable;
1172
1173 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1174}
1175
1176void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1177{
1178 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1179 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1180
1181 args.ucEnable = enable;
1182
1183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1184}
1185
7433874e
RM		 1186uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1187{
1188 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1189 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1190
1191 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1192 return args.ulReturnEngineClock;
1193}
1194
1195uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1196{
1197 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1198 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1199
1200 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1201 return args.ulReturnMemoryClock;
1202}
1203
771fe6b9
JG		 1204void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1205 uint32_t eng_clock)
1206{
1207 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1208 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1209
1210 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1211
1212 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1213}
1214
1215void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1216 uint32_t mem_clock)
1217{
1218 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1219 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1220
1221 if (rdev->flags & RADEON_IS_IGP)
1222 return;
1223
1224 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1225
1226 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1227}
1228
1229void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1230{
1231 struct radeon_device *rdev = dev->dev_private;
1232 uint32_t bios_2_scratch, bios_6_scratch;
1233
1234 if (rdev->family >= CHIP_R600) {
4ce001ab 1235 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 1236 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1237 } else {
4ce001ab 1238 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 1239 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1240 }
1241
1242 /* let the bios control the backlight */
1243 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1244
1245 /* tell the bios not to handle mode switching */
1246 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1247
1248 if (rdev->family >= CHIP_R600) {
1249 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1250 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1251 } else {
1252 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1253 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1254 }
1255
1256}
1257
f657c2a7
YZ		 1258void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1259{
1260 uint32_t scratch_reg;
1261 int i;
1262
1263 if (rdev->family >= CHIP_R600)
1264 scratch_reg = R600_BIOS_0_SCRATCH;
1265 else
1266 scratch_reg = RADEON_BIOS_0_SCRATCH;
1267
1268 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1269 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1270}
1271
1272void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1273{
1274 uint32_t scratch_reg;
1275 int i;
1276
1277 if (rdev->family >= CHIP_R600)
1278 scratch_reg = R600_BIOS_0_SCRATCH;
1279 else
1280 scratch_reg = RADEON_BIOS_0_SCRATCH;
1281
1282 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1283 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1284}
1285
771fe6b9
JG		 1286void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1287{
1288 struct drm_device *dev = encoder->dev;
1289 struct radeon_device *rdev = dev->dev_private;
1290 uint32_t bios_6_scratch;
1291
1292 if (rdev->family >= CHIP_R600)
1293 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1294 else
1295 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1296
1297 if (lock)
1298 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1299 else
1300 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1301
1302 if (rdev->family >= CHIP_R600)
1303 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1304 else
1305 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1306}
1307
1308/* at some point we may want to break this out into individual functions */
1309void
1310radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1311 struct drm_encoder *encoder,
1312 bool connected)
1313{
1314 struct drm_device *dev = connector->dev;
1315 struct radeon_device *rdev = dev->dev_private;
1316 struct radeon_connector *radeon_connector =
1317 to_radeon_connector(connector);
1318 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1319 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1320
1321 if (rdev->family >= CHIP_R600) {
1322 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1323 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1324 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1325 } else {
1326 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1327 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1328 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1329 }
1330
1331 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1332 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1333 if (connected) {
1334 DRM_DEBUG("TV1 connected\n");
1335 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1336 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1337 } else {
1338 DRM_DEBUG("TV1 disconnected\n");
1339 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1340 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1341 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1342 }
1343 }
1344 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1345 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1346 if (connected) {
1347 DRM_DEBUG("CV connected\n");
1348 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1349 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1350 } else {
1351 DRM_DEBUG("CV disconnected\n");
1352 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1353 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1354 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1355 }
1356 }
1357 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1358 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1359 if (connected) {
1360 DRM_DEBUG("LCD1 connected\n");
1361 bios_0_scratch |= ATOM_S0_LCD1;
1362 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1363 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1364 } else {
1365 DRM_DEBUG("LCD1 disconnected\n");
1366 bios_0_scratch &= ~ATOM_S0_LCD1;
1367 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1368 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1369 }
1370 }
1371 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1372 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1373 if (connected) {
1374 DRM_DEBUG("CRT1 connected\n");
1375 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1376 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1377 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1378 } else {
1379 DRM_DEBUG("CRT1 disconnected\n");
1380 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1381 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1382 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1383 }
1384 }
1385 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1386 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1387 if (connected) {
1388 DRM_DEBUG("CRT2 connected\n");
1389 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1390 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1391 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1392 } else {
1393 DRM_DEBUG("CRT2 disconnected\n");
1394 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1395 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1396 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1397 }
1398 }
1399 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1400 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1401 if (connected) {
1402 DRM_DEBUG("DFP1 connected\n");
1403 bios_0_scratch |= ATOM_S0_DFP1;
1404 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1405 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1406 } else {
1407 DRM_DEBUG("DFP1 disconnected\n");
1408 bios_0_scratch &= ~ATOM_S0_DFP1;
1409 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1410 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1411 }
1412 }
1413 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1414 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1415 if (connected) {
1416 DRM_DEBUG("DFP2 connected\n");
1417 bios_0_scratch |= ATOM_S0_DFP2;
1418 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1419 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1420 } else {
1421 DRM_DEBUG("DFP2 disconnected\n");
1422 bios_0_scratch &= ~ATOM_S0_DFP2;
1423 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1424 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1425 }
1426 }
1427 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1428 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1429 if (connected) {
1430 DRM_DEBUG("DFP3 connected\n");
1431 bios_0_scratch |= ATOM_S0_DFP3;
1432 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1433 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1434 } else {
1435 DRM_DEBUG("DFP3 disconnected\n");
1436 bios_0_scratch &= ~ATOM_S0_DFP3;
1437 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1438 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1439 }
1440 }
1441 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1442 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1443 if (connected) {
1444 DRM_DEBUG("DFP4 connected\n");
1445 bios_0_scratch |= ATOM_S0_DFP4;
1446 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1447 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1448 } else {
1449 DRM_DEBUG("DFP4 disconnected\n");
1450 bios_0_scratch &= ~ATOM_S0_DFP4;
1451 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1452 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1453 }
1454 }
1455 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1456 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1457 if (connected) {
1458 DRM_DEBUG("DFP5 connected\n");
1459 bios_0_scratch |= ATOM_S0_DFP5;
1460 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1461 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1462 } else {
1463 DRM_DEBUG("DFP5 disconnected\n");
1464 bios_0_scratch &= ~ATOM_S0_DFP5;
1465 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1466 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1467 }
1468 }
1469
1470 if (rdev->family >= CHIP_R600) {
1471 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1472 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1473 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1474 } else {
1475 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1476 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1477 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1478 }
1479}
1480
1481void
1482radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1483{
1484 struct drm_device *dev = encoder->dev;
1485 struct radeon_device *rdev = dev->dev_private;
1486 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1487 uint32_t bios_3_scratch;
1488
1489 if (rdev->family >= CHIP_R600)
1490 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1491 else
1492 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1493
1494 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1495 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1496 bios_3_scratch |= (crtc << 18);
1497 }
1498 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1499 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1500 bios_3_scratch |= (crtc << 24);
1501 }
1502 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1503 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1504 bios_3_scratch |= (crtc << 16);
1505 }
1506 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1507 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1508 bios_3_scratch |= (crtc << 20);
1509 }
1510 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1511 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1512 bios_3_scratch |= (crtc << 17);
1513 }
1514 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1515 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1516 bios_3_scratch |= (crtc << 19);
1517 }
1518 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1519 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1520 bios_3_scratch |= (crtc << 23);
1521 }
1522 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1523 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1524 bios_3_scratch |= (crtc << 25);
1525 }
1526
1527 if (rdev->family >= CHIP_R600)
1528 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1529 else
1530 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1531}
1532
1533void
1534radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1535{
1536 struct drm_device *dev = encoder->dev;
1537 struct radeon_device *rdev = dev->dev_private;
1538 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1539 uint32_t bios_2_scratch;
1540
1541 if (rdev->family >= CHIP_R600)
1542 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1543 else
1544 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1545
1546 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1547 if (on)
1548 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1549 else
1550 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1551 }
1552 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1553 if (on)
1554 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1555 else
1556 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1557 }
1558 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1559 if (on)
1560 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1561 else
1562 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1563 }
1564 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1565 if (on)
1566 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1567 else
1568 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1569 }
1570 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1571 if (on)
1572 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1573 else
1574 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1575 }
1576 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1577 if (on)
1578 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1579 else
1580 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1581 }
1582 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1583 if (on)
1584 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1585 else
1586 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1587 }
1588 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1589 if (on)
1590 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1591 else
1592 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1593 }
1594 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1595 if (on)
1596 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1597 else
1598 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1599 }
1600 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1601 if (on)
1602 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1603 else
1604 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1605 }
1606
1607 if (rdev->family >= CHIP_R600)
1608 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1609 else
1610 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1611}
kernel source for telekom puls (alcatel/mediatek)