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drm/radeon/kms: don't use bios dividers for lvds on r4xx
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06
AD		 49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id);
771fe6b9
JG		 51
52/* from radeon_legacy_encoder.c */
53extern void
54radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
55 uint32_t supported_device);
56
57union atom_supported_devices {
58 struct _ATOM_SUPPORTED_DEVICES_INFO info;
59 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
61};
62
63static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
64 *dev, uint8_t id)
65{
66 struct radeon_device *rdev = dev->dev_private;
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset;
73
74 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
75 i2c.valid = false;
76
77 atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
78
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
81 gpio = i2c_info->asGPIO_Info[id];
82
83 i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
84 i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
9b9fe724
AD		 85 i2c.en_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
86 i2c.en_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
87 i2c.y_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
88 i2c.y_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
771fe6b9
JG		 89 i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
90 i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
91 i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
92 i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
9b9fe724
AD		 93 i2c.en_clk_mask = (1 << gpio.ucClkEnShift);
94 i2c.en_data_mask = (1 << gpio.ucDataEnShift);
95 i2c.y_clk_mask = (1 << gpio.ucClkY_Shift);
96 i2c.y_data_mask = (1 << gpio.ucDataY_Shift);
771fe6b9
JG		 97 i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
98 i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
99 i2c.valid = true;
100
101 return i2c;
102}
103
104static bool radeon_atom_apply_quirks(struct drm_device *dev,
105 uint32_t supported_device,
106 int *connector_type,
848577ee 107 struct radeon_i2c_bus_rec *i2c_bus,
705af9c7 108 uint16_t *line_mux)
771fe6b9
JG		 109{
110
111 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
112 if ((dev->pdev->device == 0x791e) &&
113 (dev->pdev->subsystem_vendor == 0x1043) &&
114 (dev->pdev->subsystem_device == 0x826d)) {
115 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
116 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
117 *connector_type = DRM_MODE_CONNECTOR_DVID;
118 }
119
120 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
121 if ((dev->pdev->device == 0x7941) &&
122 (dev->pdev->subsystem_vendor == 0x147b) &&
123 (dev->pdev->subsystem_device == 0x2412)) {
124 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
125 return false;
126 }
127
128 /* Falcon NW laptop lists vga ddc line for LVDS */
129 if ((dev->pdev->device == 0x5653) &&
130 (dev->pdev->subsystem_vendor == 0x1462) &&
131 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 132 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 133 i2c_bus->valid = false;
848577ee
AD		 134 *line_mux = 53;
135 }
771fe6b9
JG		 136 }
137
138 /* Funky macbooks */
139 if ((dev->pdev->device == 0x71C5) &&
140 (dev->pdev->subsystem_vendor == 0x106b) &&
141 (dev->pdev->subsystem_device == 0x0080)) {
142 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
143 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
144 return false;
145 }
146
771fe6b9
JG		 147 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
148 if ((dev->pdev->device == 0x9598) &&
149 (dev->pdev->subsystem_vendor == 0x1043) &&
150 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 151 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 152 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 153 }
154 }
155
156 /* ASUS HD 3450 board lists the DVI port as HDMI */
157 if ((dev->pdev->device == 0x95C5) &&
158 (dev->pdev->subsystem_vendor == 0x1043) &&
159 (dev->pdev->subsystem_device == 0x01e2)) {
160 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 161 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 162 }
163 }
164
705af9c7
AD		 165 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
166 * HDMI + VGA reporting as HDMI
167 */
168 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
169 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
170 *connector_type = DRM_MODE_CONNECTOR_VGA;
171 *line_mux = 0;
172 }
173 }
174
3e5f8ff3
AD		 175 /* Acer laptop reports DVI-D as DVI-I */
176 if ((dev->pdev->device == 0x95c4) &&
177 (dev->pdev->subsystem_vendor == 0x1025) &&
178 (dev->pdev->subsystem_device == 0x013c)) {
179 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
180 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
181 *connector_type = DRM_MODE_CONNECTOR_DVID;
182 }
183
771fe6b9
JG		 184 return true;
185}
186
187const int supported_devices_connector_convert[] = {
188 DRM_MODE_CONNECTOR_Unknown,
189 DRM_MODE_CONNECTOR_VGA,
190 DRM_MODE_CONNECTOR_DVII,
191 DRM_MODE_CONNECTOR_DVID,
192 DRM_MODE_CONNECTOR_DVIA,
193 DRM_MODE_CONNECTOR_SVIDEO,
194 DRM_MODE_CONNECTOR_Composite,
195 DRM_MODE_CONNECTOR_LVDS,
196 DRM_MODE_CONNECTOR_Unknown,
197 DRM_MODE_CONNECTOR_Unknown,
198 DRM_MODE_CONNECTOR_HDMIA,
199 DRM_MODE_CONNECTOR_HDMIB,
200 DRM_MODE_CONNECTOR_Unknown,
201 DRM_MODE_CONNECTOR_Unknown,
202 DRM_MODE_CONNECTOR_9PinDIN,
203 DRM_MODE_CONNECTOR_DisplayPort
204};
205
b75fad06
AD		 206const uint16_t supported_devices_connector_object_id_convert[] = {
207 CONNECTOR_OBJECT_ID_NONE,
208 CONNECTOR_OBJECT_ID_VGA,
209 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
210 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
211 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
212 CONNECTOR_OBJECT_ID_COMPOSITE,
213 CONNECTOR_OBJECT_ID_SVIDEO,
214 CONNECTOR_OBJECT_ID_LVDS,
215 CONNECTOR_OBJECT_ID_9PIN_DIN,
216 CONNECTOR_OBJECT_ID_9PIN_DIN,
217 CONNECTOR_OBJECT_ID_DISPLAYPORT,
218 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
219 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
220 CONNECTOR_OBJECT_ID_SVIDEO
221};
222
771fe6b9
JG		 223const int object_connector_convert[] = {
224 DRM_MODE_CONNECTOR_Unknown,
225 DRM_MODE_CONNECTOR_DVII,
226 DRM_MODE_CONNECTOR_DVII,
227 DRM_MODE_CONNECTOR_DVID,
228 DRM_MODE_CONNECTOR_DVID,
229 DRM_MODE_CONNECTOR_VGA,
230 DRM_MODE_CONNECTOR_Composite,
231 DRM_MODE_CONNECTOR_SVIDEO,
232 DRM_MODE_CONNECTOR_Unknown,
705af9c7 233 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 234 DRM_MODE_CONNECTOR_9PinDIN,
235 DRM_MODE_CONNECTOR_Unknown,
236 DRM_MODE_CONNECTOR_HDMIA,
237 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 238 DRM_MODE_CONNECTOR_LVDS,
239 DRM_MODE_CONNECTOR_9PinDIN,
240 DRM_MODE_CONNECTOR_Unknown,
241 DRM_MODE_CONNECTOR_Unknown,
242 DRM_MODE_CONNECTOR_Unknown,
243 DRM_MODE_CONNECTOR_DisplayPort
244};
245
246bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
247{
248 struct radeon_device *rdev = dev->dev_private;
249 struct radeon_mode_info *mode_info = &rdev->mode_info;
250 struct atom_context *ctx = mode_info->atom_context;
251 int index = GetIndexIntoMasterTable(DATA, Object_Header);
252 uint16_t size, data_offset;
253 uint8_t frev, crev, line_mux = 0;
254 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
255 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
256 ATOM_OBJECT_HEADER *obj_header;
257 int i, j, path_size, device_support;
258 int connector_type;
b75fad06 259 uint16_t igp_lane_info, conn_id, connector_object_id;
771fe6b9
JG		 260 bool linkb;
261 struct radeon_i2c_bus_rec ddc_bus;
262
263 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
264
265 if (data_offset == 0)
266 return false;
267
268 if (crev < 2)
269 return false;
270
271 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
272 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
273 (ctx->bios + data_offset +
274 le16_to_cpu(obj_header->usDisplayPathTableOffset));
275 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
276 (ctx->bios + data_offset +
277 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
278 device_support = le16_to_cpu(obj_header->usDeviceSupport);
279
280 path_size = 0;
281 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
282 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
283 ATOM_DISPLAY_OBJECT_PATH *path;
284 addr += path_size;
285 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
286 path_size += le16_to_cpu(path->usSize);
287 linkb = false;
288
289 if (device_support & le16_to_cpu(path->usDeviceTag)) {
290 uint8_t con_obj_id, con_obj_num, con_obj_type;
291
292 con_obj_id =
293 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
294 >> OBJECT_ID_SHIFT;
295 con_obj_num =
296 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
297 >> ENUM_ID_SHIFT;
298 con_obj_type =
299 (le16_to_cpu(path->usConnObjectId) &
300 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
301
4bbd4973
DA		 302 /* TODO CV support */
303 if (le16_to_cpu(path->usDeviceTag) ==
304 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 305 continue;
306
ee59f2b4
AD		 307 /* IGP chips */
308 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 309 (con_obj_id ==
310 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
311 uint16_t igp_offset = 0;
312 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
313
314 index =
315 GetIndexIntoMasterTable(DATA,
316 IntegratedSystemInfo);
317
318 atom_parse_data_header(ctx, index, &size, &frev,
319 &crev, &igp_offset);
320
321 if (crev >= 2) {
322 igp_obj =
323 (ATOM_INTEGRATED_SYSTEM_INFO_V2
324 *) (ctx->bios + igp_offset);
325
326 if (igp_obj) {
327 uint32_t slot_config, ct;
328
329 if (con_obj_num == 1)
330 slot_config =
331 igp_obj->
332 ulDDISlot1Config;
333 else
334 slot_config =
335 igp_obj->
336 ulDDISlot2Config;
337
338 ct = (slot_config >> 16) & 0xff;
339 connector_type =
340 object_connector_convert
341 [ct];
b75fad06 342 connector_object_id = ct;
771fe6b9
JG		 343 igp_lane_info =
344 slot_config & 0xffff;
345 } else
346 continue;
347 } else
348 continue;
349 } else {
350 igp_lane_info = 0;
351 connector_type =
352 object_connector_convert[con_obj_id];
b75fad06 353 connector_object_id = con_obj_id;
771fe6b9
JG		 354 }
355
356 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
357 continue;
358
359 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
360 j++) {
361 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
362
363 enc_obj_id =
364 (le16_to_cpu(path->usGraphicObjIds[j]) &
365 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
366 enc_obj_num =
367 (le16_to_cpu(path->usGraphicObjIds[j]) &
368 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
369 enc_obj_type =
370 (le16_to_cpu(path->usGraphicObjIds[j]) &
371 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
372
373 /* FIXME: add support for router objects */
374 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
375 if (enc_obj_num == 2)
376 linkb = true;
377 else
378 linkb = false;
379
380 radeon_add_atom_encoder(dev,
381 enc_obj_id,
382 le16_to_cpu
383 (path->
384 usDeviceTag));
385
386 }
387 }
388
389 /* look up gpio for ddc */
390 if ((le16_to_cpu(path->usDeviceTag) &
391 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
392 == 0) {
393 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
394 if (le16_to_cpu(path->usConnObjectId) ==
395 le16_to_cpu(con_obj->asObjects[j].
396 usObjectID)) {
397 ATOM_COMMON_RECORD_HEADER
398 *record =
399 (ATOM_COMMON_RECORD_HEADER
400 *)
401 (ctx->bios + data_offset +
402 le16_to_cpu(con_obj->
403 asObjects[j].
404 usRecordOffset));
405 ATOM_I2C_RECORD *i2c_record;
406
407 while (record->ucRecordType > 0
408 && record->
409 ucRecordType <=
410 ATOM_MAX_OBJECT_RECORD_NUMBER) {
771fe6b9
JG		 411 switch (record->
412 ucRecordType) {
413 case ATOM_I2C_RECORD_TYPE:
414 i2c_record =
415 (ATOM_I2C_RECORD
416 *) record;
417 line_mux =
418 i2c_record->
419 sucI2cId.
420 bfI2C_LineMux;
421 break;
422 }
423 record =
424 (ATOM_COMMON_RECORD_HEADER
425 *) ((char *)record
426 +
427 record->
428 ucRecordSize);
429 }
430 break;
431 }
432 }
433 } else
434 line_mux = 0;
435
436 if ((le16_to_cpu(path->usDeviceTag) ==
437 ATOM_DEVICE_TV1_SUPPORT)
438 || (le16_to_cpu(path->usDeviceTag) ==
439 ATOM_DEVICE_TV2_SUPPORT)
440 || (le16_to_cpu(path->usDeviceTag) ==
441 ATOM_DEVICE_CV_SUPPORT))
442 ddc_bus.valid = false;
443 else
444 ddc_bus = radeon_lookup_gpio(dev, line_mux);
445
705af9c7
AD		 446 conn_id = le16_to_cpu(path->usConnObjectId);
447
448 if (!radeon_atom_apply_quirks
449 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
450 &ddc_bus, &conn_id))
451 continue;
452
771fe6b9 453 radeon_add_atom_connector(dev,
705af9c7 454 conn_id,
771fe6b9
JG		 455 le16_to_cpu(path->
456 usDeviceTag),
457 connector_type, &ddc_bus,
b75fad06
AD		 458 linkb, igp_lane_info,
459 connector_object_id);
771fe6b9
JG		 460
461 }
462 }
463
464 radeon_link_encoder_connector(dev);
465
466 return true;
467}
468
b75fad06
AD		 469static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
470 int connector_type,
471 uint16_t devices)
472{
473 struct radeon_device *rdev = dev->dev_private;
474
475 if (rdev->flags & RADEON_IS_IGP) {
476 return supported_devices_connector_object_id_convert
477 [connector_type];
478 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
479 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
480 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
481 struct radeon_mode_info *mode_info = &rdev->mode_info;
482 struct atom_context *ctx = mode_info->atom_context;
483 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
484 uint16_t size, data_offset;
485 uint8_t frev, crev;
486 ATOM_XTMDS_INFO *xtmds;
487
488 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
489 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
490
491 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
492 if (connector_type == DRM_MODE_CONNECTOR_DVII)
493 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
494 else
495 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
496 } else {
497 if (connector_type == DRM_MODE_CONNECTOR_DVII)
498 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
499 else
500 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
501 }
502 } else {
503 return supported_devices_connector_object_id_convert
504 [connector_type];
505 }
506}
507
771fe6b9
JG		 508struct bios_connector {
509 bool valid;
705af9c7 510 uint16_t line_mux;
771fe6b9
JG		 511 uint16_t devices;
512 int connector_type;
513 struct radeon_i2c_bus_rec ddc_bus;
514};
515
516bool radeon_get_atom_connector_info_from_supported_devices_table(struct
517 drm_device
518 *dev)
519{
520 struct radeon_device *rdev = dev->dev_private;
521 struct radeon_mode_info *mode_info = &rdev->mode_info;
522 struct atom_context *ctx = mode_info->atom_context;
523 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
524 uint16_t size, data_offset;
525 uint8_t frev, crev;
526 uint16_t device_support;
527 uint8_t dac;
528 union atom_supported_devices *supported_devices;
529 int i, j;
530 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
531
532 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
533
534 supported_devices =
535 (union atom_supported_devices *)(ctx->bios + data_offset);
536
537 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
538
539 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
540 ATOM_CONNECTOR_INFO_I2C ci =
541 supported_devices->info.asConnInfo[i];
542
543 bios_connectors[i].valid = false;
544
545 if (!(device_support & (1 << i))) {
546 continue;
547 }
548
549 if (i == ATOM_DEVICE_CV_INDEX) {
550 DRM_DEBUG("Skipping Component Video\n");
551 continue;
552 }
553
771fe6b9
JG		 554 bios_connectors[i].connector_type =
555 supported_devices_connector_convert[ci.sucConnectorInfo.
556 sbfAccess.
557 bfConnectorType];
558
559 if (bios_connectors[i].connector_type ==
560 DRM_MODE_CONNECTOR_Unknown)
561 continue;
562
563 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
564
565 if ((rdev->family == CHIP_RS690) ||
566 (rdev->family == CHIP_RS740)) {
567 if ((i == ATOM_DEVICE_DFP2_INDEX)
568 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
569 bios_connectors[i].line_mux =
570 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
571 else if ((i == ATOM_DEVICE_DFP3_INDEX)
572 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
573 bios_connectors[i].line_mux =
574 ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
575 else
576 bios_connectors[i].line_mux =
577 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
578 } else
579 bios_connectors[i].line_mux =
580 ci.sucI2cId.sbfAccess.bfI2C_LineMux;
581
582 /* give tv unique connector ids */
583 if (i == ATOM_DEVICE_TV1_INDEX) {
584 bios_connectors[i].ddc_bus.valid = false;
585 bios_connectors[i].line_mux = 50;
586 } else if (i == ATOM_DEVICE_TV2_INDEX) {
587 bios_connectors[i].ddc_bus.valid = false;
588 bios_connectors[i].line_mux = 51;
589 } else if (i == ATOM_DEVICE_CV_INDEX) {
590 bios_connectors[i].ddc_bus.valid = false;
591 bios_connectors[i].line_mux = 52;
592 } else
593 bios_connectors[i].ddc_bus =
594 radeon_lookup_gpio(dev,
595 bios_connectors[i].line_mux);
596
597 /* Always set the connector type to VGA for CRT1/CRT2. if they are
598 * shared with a DVI port, we'll pick up the DVI connector when we
599 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
600 */
601 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
602 bios_connectors[i].connector_type =
603 DRM_MODE_CONNECTOR_VGA;
604
605 if (!radeon_atom_apply_quirks
606 (dev, (1 << i), &bios_connectors[i].connector_type,
848577ee 607 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux))
771fe6b9
JG		 608 continue;
609
610 bios_connectors[i].valid = true;
611 bios_connectors[i].devices = (1 << i);
612
613 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
614 radeon_add_atom_encoder(dev,
615 radeon_get_encoder_id(dev,
616 (1 << i),
617 dac),
618 (1 << i));
619 else
620 radeon_add_legacy_encoder(dev,
621 radeon_get_encoder_id(dev,
622 (1 <<
623 i),
624 dac),
625 (1 << i));
626 }
627
628 /* combine shared connectors */
629 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
630 if (bios_connectors[i].valid) {
631 for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
632 if (bios_connectors[j].valid && (i != j)) {
633 if (bios_connectors[i].line_mux ==
634 bios_connectors[j].line_mux) {
635 if (((bios_connectors[i].
636 devices &
637 (ATOM_DEVICE_DFP_SUPPORT))
638 && (bios_connectors[j].
639 devices &
640 (ATOM_DEVICE_CRT_SUPPORT)))
641 ||
642 ((bios_connectors[j].
643 devices &
644 (ATOM_DEVICE_DFP_SUPPORT))
645 && (bios_connectors[i].
646 devices &
647 (ATOM_DEVICE_CRT_SUPPORT)))) {
648 bios_connectors[i].
649 devices |=
650 bios_connectors[j].
651 devices;
652 bios_connectors[i].
653 connector_type =
654 DRM_MODE_CONNECTOR_DVII;
655 bios_connectors[j].
656 valid = false;
657 }
658 }
659 }
660 }
661 }
662 }
663
664 /* add the connectors */
665 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
b75fad06
AD		 666 if (bios_connectors[i].valid) {
667 uint16_t connector_object_id =
668 atombios_get_connector_object_id(dev,
669 bios_connectors[i].connector_type,
670 bios_connectors[i].devices);
771fe6b9
JG		 671 radeon_add_atom_connector(dev,
672 bios_connectors[i].line_mux,
673 bios_connectors[i].devices,
674 bios_connectors[i].
675 connector_type,
676 &bios_connectors[i].ddc_bus,
b75fad06
AD		 677 false, 0,
678 connector_object_id);
679 }
771fe6b9
JG		 680 }
681
682 radeon_link_encoder_connector(dev);
683
684 return true;
685}
686
687union firmware_info {
688 ATOM_FIRMWARE_INFO info;
689 ATOM_FIRMWARE_INFO_V1_2 info_12;
690 ATOM_FIRMWARE_INFO_V1_3 info_13;
691 ATOM_FIRMWARE_INFO_V1_4 info_14;
692};
693
694bool radeon_atom_get_clock_info(struct drm_device *dev)
695{
696 struct radeon_device *rdev = dev->dev_private;
697 struct radeon_mode_info *mode_info = &rdev->mode_info;
698 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
699 union firmware_info *firmware_info;
700 uint8_t frev, crev;
701 struct radeon_pll *p1pll = &rdev->clock.p1pll;
702 struct radeon_pll *p2pll = &rdev->clock.p2pll;
703 struct radeon_pll *spll = &rdev->clock.spll;
704 struct radeon_pll *mpll = &rdev->clock.mpll;
705 uint16_t data_offset;
706
707 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
708 &crev, &data_offset);
709
710 firmware_info =
711 (union firmware_info *)(mode_info->atom_context->bios +
712 data_offset);
713
714 if (firmware_info) {
715 /* pixel clocks */
716 p1pll->reference_freq =
717 le16_to_cpu(firmware_info->info.usReferenceClock);
718 p1pll->reference_div = 0;
719
bc293e58
MF		 720 if (crev < 2)
721 p1pll->pll_out_min =
722 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
723 else
724 p1pll->pll_out_min =
725 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 726 p1pll->pll_out_max =
727 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
728
729 if (p1pll->pll_out_min == 0) {
730 if (ASIC_IS_AVIVO(rdev))
731 p1pll->pll_out_min = 64800;
732 else
733 p1pll->pll_out_min = 20000;
8f552a66
AD		 734 } else if (p1pll->pll_out_min > 64800) {
735 /* Limiting the pll output range is a good thing generally as
736 * it limits the number of possible pll combinations for a given
737 * frequency presumably to the ones that work best on each card.
738 * However, certain duallink DVI monitors seem to like
739 * pll combinations that would be limited by this at least on
740 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
741 * family.
742 */
743 p1pll->pll_out_min = 64800;
771fe6b9
JG		 744 }
745
746 p1pll->pll_in_min =
747 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
748 p1pll->pll_in_max =
749 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
750
751 *p2pll = *p1pll;
752
753 /* system clock */
754 spll->reference_freq =
755 le16_to_cpu(firmware_info->info.usReferenceClock);
756 spll->reference_div = 0;
757
758 spll->pll_out_min =
759 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
760 spll->pll_out_max =
761 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
762
763 /* ??? */
764 if (spll->pll_out_min == 0) {
765 if (ASIC_IS_AVIVO(rdev))
766 spll->pll_out_min = 64800;
767 else
768 spll->pll_out_min = 20000;
769 }
770
771 spll->pll_in_min =
772 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
773 spll->pll_in_max =
774 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
775
776 /* memory clock */
777 mpll->reference_freq =
778 le16_to_cpu(firmware_info->info.usReferenceClock);
779 mpll->reference_div = 0;
780
781 mpll->pll_out_min =
782 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
783 mpll->pll_out_max =
784 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
785
786 /* ??? */
787 if (mpll->pll_out_min == 0) {
788 if (ASIC_IS_AVIVO(rdev))
789 mpll->pll_out_min = 64800;
790 else
791 mpll->pll_out_min = 20000;
792 }
793
794 mpll->pll_in_min =
795 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
796 mpll->pll_in_max =
797 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
798
799 rdev->clock.default_sclk =
800 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
801 rdev->clock.default_mclk =
802 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
803
804 return true;
805 }
806 return false;
807}
808
445282db
DA		 809bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
810 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 811{
812 struct drm_device *dev = encoder->base.dev;
813 struct radeon_device *rdev = dev->dev_private;
814 struct radeon_mode_info *mode_info = &rdev->mode_info;
815 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
816 uint16_t data_offset;
817 struct _ATOM_TMDS_INFO *tmds_info;
818 uint8_t frev, crev;
819 uint16_t maxfreq;
820 int i;
771fe6b9
JG		 821
822 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
823 &crev, &data_offset);
824
825 tmds_info =
826 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
827 data_offset);
828
829 if (tmds_info) {
771fe6b9
JG		 830 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
831 for (i = 0; i < 4; i++) {
832 tmds->tmds_pll[i].freq =
833 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
834 tmds->tmds_pll[i].value =
835 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
836 tmds->tmds_pll[i].value |=
837 (tmds_info->asMiscInfo[i].
838 ucPLL_VCO_Gain & 0x3f) << 6;
839 tmds->tmds_pll[i].value |=
840 (tmds_info->asMiscInfo[i].
841 ucPLL_DutyCycle & 0xf) << 12;
842 tmds->tmds_pll[i].value |=
843 (tmds_info->asMiscInfo[i].
844 ucPLL_VoltageSwing & 0xf) << 16;
845
846 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
847 tmds->tmds_pll[i].freq,
848 tmds->tmds_pll[i].value);
849
850 if (maxfreq == tmds->tmds_pll[i].freq) {
851 tmds->tmds_pll[i].freq = 0xffffffff;
852 break;
853 }
854 }
445282db 855 return true;
771fe6b9 856 }
445282db 857 return false;
771fe6b9
JG		 858}
859
ebbe1cb9
AD		 860static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
861 radeon_encoder
862 *encoder,
863 int id)
864{
865 struct drm_device *dev = encoder->base.dev;
866 struct radeon_device *rdev = dev->dev_private;
867 struct radeon_mode_info *mode_info = &rdev->mode_info;
868 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
869 uint16_t data_offset;
870 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
871 uint8_t frev, crev;
872 struct radeon_atom_ss *ss = NULL;
873
874 if (id > ATOM_MAX_SS_ENTRY)
875 return NULL;
876
877 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
878 &crev, &data_offset);
879
880 ss_info =
881 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
882
883 if (ss_info) {
884 ss =
885 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
886
887 if (!ss)
888 return NULL;
889
890 ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage);
891 ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType;
892 ss->step = ss_info->asSS_Info[id].ucSS_Step;
893 ss->delay = ss_info->asSS_Info[id].ucSS_Delay;
894 ss->range = ss_info->asSS_Info[id].ucSS_Range;
895 ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div;
896 }
897 return ss;
898}
899
771fe6b9
JG		 900union lvds_info {
901 struct _ATOM_LVDS_INFO info;
902 struct _ATOM_LVDS_INFO_V12 info_12;
903};
904
905struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
906 radeon_encoder
907 *encoder)
908{
909 struct drm_device *dev = encoder->base.dev;
910 struct radeon_device *rdev = dev->dev_private;
911 struct radeon_mode_info *mode_info = &rdev->mode_info;
912 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 913 uint16_t data_offset, misc;
771fe6b9
JG		 914 union lvds_info *lvds_info;
915 uint8_t frev, crev;
916 struct radeon_encoder_atom_dig *lvds = NULL;
917
918 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
919 &crev, &data_offset);
920
921 lvds_info =
922 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
923
924 if (lvds_info) {
925 lvds =
926 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
927
928 if (!lvds)
929 return NULL;
930
de2103e4 931 lvds->native_mode.clock =
771fe6b9 932 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 933 lvds->native_mode.hdisplay =
771fe6b9 934 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 935 lvds->native_mode.vdisplay =
771fe6b9 936 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 937 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
938 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
939 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
940 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
941 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
942 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
943 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
944 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
945 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
946 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
947 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
948 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 949 lvds->panel_pwr_delay =
950 le16_to_cpu(lvds_info->info.usOffDelayInMs);
951 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 952
953 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
954 if (misc & ATOM_VSYNC_POLARITY)
955 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
956 if (misc & ATOM_HSYNC_POLARITY)
957 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
958 if (misc & ATOM_COMPOSITESYNC)
959 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
960 if (misc & ATOM_INTERLACE)
961 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
962 if (misc & ATOM_DOUBLE_CLOCK_MODE)
963 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
964
de2103e4
AD		 965 /* set crtc values */
966 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 967
ebbe1cb9
AD		 968 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
969
771fe6b9
JG		 970 encoder->native_mode = lvds->native_mode;
971 }
972 return lvds;
973}
974
6fe7ac3f
AD		 975struct radeon_encoder_primary_dac *
976radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
977{
978 struct drm_device *dev = encoder->base.dev;
979 struct radeon_device *rdev = dev->dev_private;
980 struct radeon_mode_info *mode_info = &rdev->mode_info;
981 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
982 uint16_t data_offset;
983 struct _COMPASSIONATE_DATA *dac_info;
984 uint8_t frev, crev;
985 uint8_t bg, dac;
6fe7ac3f
AD		 986 struct radeon_encoder_primary_dac *p_dac = NULL;
987
988 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
989
990 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
991
992 if (dac_info) {
993 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
994
995 if (!p_dac)
996 return NULL;
997
998 bg = dac_info->ucDAC1_BG_Adjustment;
999 dac = dac_info->ucDAC1_DAC_Adjustment;
1000 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1001
1002 }
1003 return p_dac;
1004}
1005
4ce001ab 1006bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1007 struct drm_display_mode *mode)
4ce001ab
DA		 1008{
1009 struct radeon_mode_info *mode_info = &rdev->mode_info;
1010 ATOM_ANALOG_TV_INFO *tv_info;
1011 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1012 ATOM_DTD_FORMAT *dtd_timings;
1013 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1014 u8 frev, crev;
5a9bcacc 1015 u16 data_offset, misc;
4ce001ab
DA		 1016
1017 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
1018
1019 switch (crev) {
1020 case 1:
1021 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1022 if (index > MAX_SUPPORTED_TV_TIMING)
1023 return false;
1024
5a9bcacc
AD		 1025 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1026 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1027 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1028 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1029 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1030
1031 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1032 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1033 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1034 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1035 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1036
1037 mode->flags = 0;
1038 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1039 if (misc & ATOM_VSYNC_POLARITY)
1040 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1041 if (misc & ATOM_HSYNC_POLARITY)
1042 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1043 if (misc & ATOM_COMPOSITESYNC)
1044 mode->flags |= DRM_MODE_FLAG_CSYNC;
1045 if (misc & ATOM_INTERLACE)
1046 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1047 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1048 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1049
1050 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1051
1052 if (index == 1) {
1053 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1054 mode->crtc_htotal -= 1;
1055 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1056 }
1057 break;
1058 case 2:
1059 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1060 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1061 return false;
1062
1063 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1064 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1065 le16_to_cpu(dtd_timings->usHBlanking_Time);
1066 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1067 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1068 le16_to_cpu(dtd_timings->usHSyncOffset);
1069 mode->crtc_hsync_end = mode->crtc_hsync_start +
1070 le16_to_cpu(dtd_timings->usHSyncWidth);
1071
1072 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1073 le16_to_cpu(dtd_timings->usVBlanking_Time);
1074 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1075 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1076 le16_to_cpu(dtd_timings->usVSyncOffset);
1077 mode->crtc_vsync_end = mode->crtc_vsync_start +
1078 le16_to_cpu(dtd_timings->usVSyncWidth);
1079
1080 mode->flags = 0;
1081 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1082 if (misc & ATOM_VSYNC_POLARITY)
1083 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1084 if (misc & ATOM_HSYNC_POLARITY)
1085 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1086 if (misc & ATOM_COMPOSITESYNC)
1087 mode->flags |= DRM_MODE_FLAG_CSYNC;
1088 if (misc & ATOM_INTERLACE)
1089 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1090 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1091 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1092
1093 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1094 break;
1095 }
1096 return true;
1097}
1098
6fe7ac3f
AD		 1099struct radeon_encoder_tv_dac *
1100radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1101{
1102 struct drm_device *dev = encoder->base.dev;
1103 struct radeon_device *rdev = dev->dev_private;
1104 struct radeon_mode_info *mode_info = &rdev->mode_info;
1105 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1106 uint16_t data_offset;
1107 struct _COMPASSIONATE_DATA *dac_info;
1108 uint8_t frev, crev;
1109 uint8_t bg, dac;
6fe7ac3f
AD		 1110 struct radeon_encoder_tv_dac *tv_dac = NULL;
1111
1112 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
1113
1114 dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
1115
1116 if (dac_info) {
1117 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1118
1119 if (!tv_dac)
1120 return NULL;
1121
1122 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1123 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1124 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1125
1126 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1127 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1128 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1129
1130 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1131 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1132 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1133
1134 }
1135 return tv_dac;
1136}
1137
771fe6b9
JG		 1138void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1139{
1140 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1141 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1142
1143 args.ucEnable = enable;
1144
1145 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1146}
1147
1148void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
1149{
1150 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
1151 int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
1152
1153 args.ucEnable = enable;
1154
1155 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1156}
1157
7433874e
RM		 1158uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1159{
1160 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1161 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1162
1163 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1164 return args.ulReturnEngineClock;
1165}
1166
1167uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1168{
1169 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1170 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1171
1172 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1173 return args.ulReturnMemoryClock;
1174}
1175
771fe6b9
JG		 1176void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1177 uint32_t eng_clock)
1178{
1179 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1180 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1181
1182 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1183
1184 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1185}
1186
1187void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1188 uint32_t mem_clock)
1189{
1190 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1191 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1192
1193 if (rdev->flags & RADEON_IS_IGP)
1194 return;
1195
1196 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1197
1198 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1199}
1200
1201void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1202{
1203 struct radeon_device *rdev = dev->dev_private;
1204 uint32_t bios_2_scratch, bios_6_scratch;
1205
1206 if (rdev->family >= CHIP_R600) {
4ce001ab 1207 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 1208 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1209 } else {
4ce001ab 1210 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 1211 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1212 }
1213
1214 /* let the bios control the backlight */
1215 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1216
1217 /* tell the bios not to handle mode switching */
1218 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1219
1220 if (rdev->family >= CHIP_R600) {
1221 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1222 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1223 } else {
1224 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1225 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1226 }
1227
1228}
1229
f657c2a7
YZ		 1230void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1231{
1232 uint32_t scratch_reg;
1233 int i;
1234
1235 if (rdev->family >= CHIP_R600)
1236 scratch_reg = R600_BIOS_0_SCRATCH;
1237 else
1238 scratch_reg = RADEON_BIOS_0_SCRATCH;
1239
1240 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1241 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1242}
1243
1244void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1245{
1246 uint32_t scratch_reg;
1247 int i;
1248
1249 if (rdev->family >= CHIP_R600)
1250 scratch_reg = R600_BIOS_0_SCRATCH;
1251 else
1252 scratch_reg = RADEON_BIOS_0_SCRATCH;
1253
1254 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1255 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1256}
1257
771fe6b9
JG		 1258void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1259{
1260 struct drm_device *dev = encoder->dev;
1261 struct radeon_device *rdev = dev->dev_private;
1262 uint32_t bios_6_scratch;
1263
1264 if (rdev->family >= CHIP_R600)
1265 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1266 else
1267 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1268
1269 if (lock)
1270 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1271 else
1272 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1273
1274 if (rdev->family >= CHIP_R600)
1275 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1276 else
1277 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1278}
1279
1280/* at some point we may want to break this out into individual functions */
1281void
1282radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
1283 struct drm_encoder *encoder,
1284 bool connected)
1285{
1286 struct drm_device *dev = connector->dev;
1287 struct radeon_device *rdev = dev->dev_private;
1288 struct radeon_connector *radeon_connector =
1289 to_radeon_connector(connector);
1290 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1291 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
1292
1293 if (rdev->family >= CHIP_R600) {
1294 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1295 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1296 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1297 } else {
1298 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1299 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1300 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1301 }
1302
1303 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
1304 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
1305 if (connected) {
1306 DRM_DEBUG("TV1 connected\n");
1307 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
1308 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
1309 } else {
1310 DRM_DEBUG("TV1 disconnected\n");
1311 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
1312 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
1313 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
1314 }
1315 }
1316 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
1317 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
1318 if (connected) {
1319 DRM_DEBUG("CV connected\n");
1320 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
1321 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
1322 } else {
1323 DRM_DEBUG("CV disconnected\n");
1324 bios_0_scratch &= ~ATOM_S0_CV_MASK;
1325 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
1326 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
1327 }
1328 }
1329 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
1330 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
1331 if (connected) {
1332 DRM_DEBUG("LCD1 connected\n");
1333 bios_0_scratch |= ATOM_S0_LCD1;
1334 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
1335 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
1336 } else {
1337 DRM_DEBUG("LCD1 disconnected\n");
1338 bios_0_scratch &= ~ATOM_S0_LCD1;
1339 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
1340 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
1341 }
1342 }
1343 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
1344 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
1345 if (connected) {
1346 DRM_DEBUG("CRT1 connected\n");
1347 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
1348 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
1349 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
1350 } else {
1351 DRM_DEBUG("CRT1 disconnected\n");
1352 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
1353 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
1354 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
1355 }
1356 }
1357 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
1358 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
1359 if (connected) {
1360 DRM_DEBUG("CRT2 connected\n");
1361 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
1362 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
1363 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
1364 } else {
1365 DRM_DEBUG("CRT2 disconnected\n");
1366 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
1367 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
1368 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
1369 }
1370 }
1371 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
1372 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
1373 if (connected) {
1374 DRM_DEBUG("DFP1 connected\n");
1375 bios_0_scratch |= ATOM_S0_DFP1;
1376 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
1377 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
1378 } else {
1379 DRM_DEBUG("DFP1 disconnected\n");
1380 bios_0_scratch &= ~ATOM_S0_DFP1;
1381 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
1382 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
1383 }
1384 }
1385 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
1386 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
1387 if (connected) {
1388 DRM_DEBUG("DFP2 connected\n");
1389 bios_0_scratch |= ATOM_S0_DFP2;
1390 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
1391 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
1392 } else {
1393 DRM_DEBUG("DFP2 disconnected\n");
1394 bios_0_scratch &= ~ATOM_S0_DFP2;
1395 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
1396 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
1397 }
1398 }
1399 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
1400 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
1401 if (connected) {
1402 DRM_DEBUG("DFP3 connected\n");
1403 bios_0_scratch |= ATOM_S0_DFP3;
1404 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
1405 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
1406 } else {
1407 DRM_DEBUG("DFP3 disconnected\n");
1408 bios_0_scratch &= ~ATOM_S0_DFP3;
1409 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
1410 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
1411 }
1412 }
1413 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
1414 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
1415 if (connected) {
1416 DRM_DEBUG("DFP4 connected\n");
1417 bios_0_scratch |= ATOM_S0_DFP4;
1418 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
1419 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
1420 } else {
1421 DRM_DEBUG("DFP4 disconnected\n");
1422 bios_0_scratch &= ~ATOM_S0_DFP4;
1423 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
1424 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
1425 }
1426 }
1427 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
1428 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
1429 if (connected) {
1430 DRM_DEBUG("DFP5 connected\n");
1431 bios_0_scratch |= ATOM_S0_DFP5;
1432 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
1433 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
1434 } else {
1435 DRM_DEBUG("DFP5 disconnected\n");
1436 bios_0_scratch &= ~ATOM_S0_DFP5;
1437 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
1438 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
1439 }
1440 }
1441
1442 if (rdev->family >= CHIP_R600) {
1443 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
1444 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1445 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1446 } else {
1447 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
1448 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1449 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1450 }
1451}
1452
1453void
1454radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
1455{
1456 struct drm_device *dev = encoder->dev;
1457 struct radeon_device *rdev = dev->dev_private;
1458 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1459 uint32_t bios_3_scratch;
1460
1461 if (rdev->family >= CHIP_R600)
1462 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
1463 else
1464 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
1465
1466 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1467 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
1468 bios_3_scratch |= (crtc << 18);
1469 }
1470 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1471 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
1472 bios_3_scratch |= (crtc << 24);
1473 }
1474 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1475 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
1476 bios_3_scratch |= (crtc << 16);
1477 }
1478 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1479 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
1480 bios_3_scratch |= (crtc << 20);
1481 }
1482 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1483 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
1484 bios_3_scratch |= (crtc << 17);
1485 }
1486 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1487 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
1488 bios_3_scratch |= (crtc << 19);
1489 }
1490 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1491 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
1492 bios_3_scratch |= (crtc << 23);
1493 }
1494 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1495 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
1496 bios_3_scratch |= (crtc << 25);
1497 }
1498
1499 if (rdev->family >= CHIP_R600)
1500 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
1501 else
1502 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
1503}
1504
1505void
1506radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
1507{
1508 struct drm_device *dev = encoder->dev;
1509 struct radeon_device *rdev = dev->dev_private;
1510 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1511 uint32_t bios_2_scratch;
1512
1513 if (rdev->family >= CHIP_R600)
1514 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1515 else
1516 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1517
1518 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
1519 if (on)
1520 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
1521 else
1522 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
1523 }
1524 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
1525 if (on)
1526 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
1527 else
1528 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
1529 }
1530 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1531 if (on)
1532 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
1533 else
1534 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
1535 }
1536 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1537 if (on)
1538 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
1539 else
1540 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
1541 }
1542 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1543 if (on)
1544 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
1545 else
1546 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
1547 }
1548 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
1549 if (on)
1550 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
1551 else
1552 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
1553 }
1554 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
1555 if (on)
1556 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
1557 else
1558 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
1559 }
1560 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
1561 if (on)
1562 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
1563 else
1564 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
1565 }
1566 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
1567 if (on)
1568 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
1569 else
1570 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
1571 }
1572 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
1573 if (on)
1574 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
1575 else
1576 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
1577 }
1578
1579 if (rdev->family >= CHIP_R600)
1580 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1581 else
1582 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1583}
kernel source for telekom puls (alcatel/mediatek)