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drm-vblank: Always return true vblank count of scheduled vblank event.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon_atombios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
5137ee94
AD		 35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
771fe6b9
JG		 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
5137ee94 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 40 uint32_t supported_device);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
5137ee94 49 uint32_t igp_lane_info,
eed45b30 50 uint16_t connector_object_id,
26b5bc98
AD		 51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
771fe6b9
JG		 53
54/* from radeon_legacy_encoder.c */
55extern void
5137ee94 56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
771fe6b9
JG		 57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
eed45b30
AD		 65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
771fe6b9 67{
771fe6b9 68 struct atom_context *ctx = rdev->mode_info.atom_context;
6a93cb25 69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
771fe6b9
JG		 70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95beb690
AD		 73 uint16_t data_offset, size;
74 int i, num_indices;
771fe6b9
JG		 75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
95beb690 79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
a084e6ee
AD		 80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
95beb690
AD		 82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
a084e6ee
AD		 86 gpio = &i2c_info->asGPIO_Info[i];
87
ea39302b
AD		 88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (gpio->usClkMaskRegisterIndex == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
a084e6ee
AD		 101 if (gpio->sucI2cId.ucAccess == id) {
102 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
103 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
104 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
105 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
106 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
107 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
108 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
109 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
110 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
111 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
112 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
113 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
114 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
115 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
116 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
117 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
118
119 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
120 i2c.hw_capable = true;
121 else
122 i2c.hw_capable = false;
123
124 if (gpio->sucI2cId.ucAccess == 0xa0)
125 i2c.mm_i2c = true;
126 else
127 i2c.mm_i2c = false;
128
129 i2c.i2c_id = gpio->sucI2cId.ucAccess;
130
f376b94f
AD		 131 if (i2c.mask_clk_reg)
132 i2c.valid = true;
a084e6ee
AD		 133 break;
134 }
d3f420d1
AD		 135 }
136 }
771fe6b9
JG		 137
138 return i2c;
139}
140
f376b94f
AD		 141void radeon_atombios_i2c_init(struct radeon_device *rdev)
142{
143 struct atom_context *ctx = rdev->mode_info.atom_context;
144 ATOM_GPIO_I2C_ASSIGMENT *gpio;
145 struct radeon_i2c_bus_rec i2c;
146 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
147 struct _ATOM_GPIO_I2C_INFO *i2c_info;
148 uint16_t data_offset, size;
149 int i, num_indices;
150 char stmp[32];
151
152 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
153
154 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
155 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
156
157 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
158 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
159
160 for (i = 0; i < num_indices; i++) {
161 gpio = &i2c_info->asGPIO_Info[i];
162 i2c.valid = false;
ea39302b
AD		 163
164 /* some evergreen boards have bad data for this entry */
165 if (ASIC_IS_DCE4(rdev)) {
166 if ((i == 7) &&
167 (gpio->usClkMaskRegisterIndex == 0x1936) &&
168 (gpio->sucI2cId.ucAccess == 0)) {
169 gpio->sucI2cId.ucAccess = 0x97;
170 gpio->ucDataMaskShift = 8;
171 gpio->ucDataEnShift = 8;
172 gpio->ucDataY_Shift = 8;
173 gpio->ucDataA_Shift = 8;
174 }
175 }
176
f376b94f
AD		 177 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
178 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
179 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
180 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
181 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
182 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
183 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
184 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
185 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
186 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
187 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
188 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
189 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
190 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
191 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
192 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
193
194 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
195 i2c.hw_capable = true;
196 else
197 i2c.hw_capable = false;
198
199 if (gpio->sucI2cId.ucAccess == 0xa0)
200 i2c.mm_i2c = true;
201 else
202 i2c.mm_i2c = false;
203
204 i2c.i2c_id = gpio->sucI2cId.ucAccess;
205
206 if (i2c.mask_clk_reg) {
207 i2c.valid = true;
208 sprintf(stmp, "0x%x", i2c.i2c_id);
209 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
210 }
211 }
212 }
213}
214
eed45b30
AD		 215static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
216 u8 id)
217{
218 struct atom_context *ctx = rdev->mode_info.atom_context;
219 struct radeon_gpio_rec gpio;
220 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
221 struct _ATOM_GPIO_PIN_LUT *gpio_info;
222 ATOM_GPIO_PIN_ASSIGNMENT *pin;
223 u16 data_offset, size;
224 int i, num_indices;
225
226 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
227 gpio.valid = false;
228
a084e6ee
AD		 229 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
230 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
eed45b30 231
a084e6ee
AD		 232 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
233 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
eed45b30 234
a084e6ee
AD		 235 for (i = 0; i < num_indices; i++) {
236 pin = &gpio_info->asGPIO_Pin[i];
237 if (id == pin->ucGPIO_ID) {
238 gpio.id = pin->ucGPIO_ID;
239 gpio.reg = pin->usGpioPin_AIndex * 4;
240 gpio.mask = (1 << pin->ucGpioPinBitShift);
241 gpio.valid = true;
242 break;
243 }
eed45b30
AD		 244 }
245 }
246
247 return gpio;
248}
249
250static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
251 struct radeon_gpio_rec *gpio)
252{
253 struct radeon_hpd hpd;
bcc1c2a1
AD		 254 u32 reg;
255
1d978dac
JD		 256 memset(&hpd, 0, sizeof(struct radeon_hpd));
257
bcc1c2a1
AD		 258 if (ASIC_IS_DCE4(rdev))
259 reg = EVERGREEN_DC_GPIO_HPD_A;
260 else
261 reg = AVIVO_DC_GPIO_HPD_A;
262
eed45b30 263 hpd.gpio = *gpio;
bcc1c2a1 264 if (gpio->reg == reg) {
eed45b30
AD		 265 switch(gpio->mask) {
266 case (1 << 0):
267 hpd.hpd = RADEON_HPD_1;
268 break;
269 case (1 << 8):
270 hpd.hpd = RADEON_HPD_2;
271 break;
272 case (1 << 16):
273 hpd.hpd = RADEON_HPD_3;
274 break;
275 case (1 << 24):
276 hpd.hpd = RADEON_HPD_4;
277 break;
278 case (1 << 26):
279 hpd.hpd = RADEON_HPD_5;
280 break;
281 case (1 << 28):
282 hpd.hpd = RADEON_HPD_6;
283 break;
284 default:
285 hpd.hpd = RADEON_HPD_NONE;
286 break;
287 }
288 } else
289 hpd.hpd = RADEON_HPD_NONE;
290 return hpd;
291}
292
771fe6b9
JG		 293static bool radeon_atom_apply_quirks(struct drm_device *dev,
294 uint32_t supported_device,
295 int *connector_type,
848577ee 296 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 297 uint16_t *line_mux,
298 struct radeon_hpd *hpd)
771fe6b9 299{
9ea2c4be 300 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 301
302 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
303 if ((dev->pdev->device == 0x791e) &&
304 (dev->pdev->subsystem_vendor == 0x1043) &&
305 (dev->pdev->subsystem_device == 0x826d)) {
306 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
307 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
308 *connector_type = DRM_MODE_CONNECTOR_DVID;
309 }
310
c86a9038
AD		 311 /* Asrock RS600 board lists the DVI port as HDMI */
312 if ((dev->pdev->device == 0x7941) &&
313 (dev->pdev->subsystem_vendor == 0x1849) &&
314 (dev->pdev->subsystem_device == 0x7941)) {
315 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
316 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
317 *connector_type = DRM_MODE_CONNECTOR_DVID;
318 }
319
f36fce0f
AD		 320 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
321 if ((dev->pdev->device == 0x796e) &&
322 (dev->pdev->subsystem_vendor == 0x1462) &&
323 (dev->pdev->subsystem_device == 0x7302)) {
324 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
325 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
326 return false;
327 }
328
771fe6b9
JG		 329 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
330 if ((dev->pdev->device == 0x7941) &&
331 (dev->pdev->subsystem_vendor == 0x147b) &&
332 (dev->pdev->subsystem_device == 0x2412)) {
333 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
334 return false;
335 }
336
337 /* Falcon NW laptop lists vga ddc line for LVDS */
338 if ((dev->pdev->device == 0x5653) &&
339 (dev->pdev->subsystem_vendor == 0x1462) &&
340 (dev->pdev->subsystem_device == 0x0291)) {
848577ee 341 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
771fe6b9 342 i2c_bus->valid = false;
848577ee
AD		 343 *line_mux = 53;
344 }
771fe6b9
JG		 345 }
346
4e3f9b78
AD		 347 /* HIS X1300 is DVI+VGA, not DVI+DVI */
348 if ((dev->pdev->device == 0x7146) &&
349 (dev->pdev->subsystem_vendor == 0x17af) &&
350 (dev->pdev->subsystem_device == 0x2058)) {
351 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
352 return false;
353 }
354
aa1a750e
DA		 355 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
356 if ((dev->pdev->device == 0x7142) &&
357 (dev->pdev->subsystem_vendor == 0x1458) &&
358 (dev->pdev->subsystem_device == 0x2134)) {
359 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
360 return false;
361 }
362
363
771fe6b9
JG		 364 /* Funky macbooks */
365 if ((dev->pdev->device == 0x71C5) &&
366 (dev->pdev->subsystem_vendor == 0x106b) &&
367 (dev->pdev->subsystem_device == 0x0080)) {
368 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
369 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
370 return false;
e1e8a5dd
AD		 371 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
372 *line_mux = 0x90;
771fe6b9
JG		 373 }
374
771fe6b9
JG		 375 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
376 if ((dev->pdev->device == 0x9598) &&
377 (dev->pdev->subsystem_vendor == 0x1043) &&
378 (dev->pdev->subsystem_device == 0x01da)) {
705af9c7 379 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 380 *connector_type = DRM_MODE_CONNECTOR_DVII;
705af9c7
AD		 381 }
382 }
383
e153b70b
AD		 384 /* ASUS HD 3600 board lists the DVI port as HDMI */
385 if ((dev->pdev->device == 0x9598) &&
386 (dev->pdev->subsystem_vendor == 0x1043) &&
387 (dev->pdev->subsystem_device == 0x01e4)) {
388 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
389 *connector_type = DRM_MODE_CONNECTOR_DVII;
390 }
391 }
392
705af9c7
AD		 393 /* ASUS HD 3450 board lists the DVI port as HDMI */
394 if ((dev->pdev->device == 0x95C5) &&
395 (dev->pdev->subsystem_vendor == 0x1043) &&
396 (dev->pdev->subsystem_device == 0x01e2)) {
397 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
d42571ef 398 *connector_type = DRM_MODE_CONNECTOR_DVII;
771fe6b9
JG		 399 }
400 }
401
705af9c7
AD		 402 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
403 * HDMI + VGA reporting as HDMI
404 */
405 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
406 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
407 *connector_type = DRM_MODE_CONNECTOR_VGA;
408 *line_mux = 0;
409 }
410 }
411
9ea2c4be 412 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
3e5f8ff3
AD		 413 if ((dev->pdev->device == 0x95c4) &&
414 (dev->pdev->subsystem_vendor == 0x1025) &&
415 (dev->pdev->subsystem_device == 0x013c)) {
9ea2c4be
AD		 416 struct radeon_gpio_rec gpio;
417
3e5f8ff3 418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
9ea2c4be
AD		 419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
420 gpio = radeon_lookup_gpio(rdev, 6);
421 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
3e5f8ff3 422 *connector_type = DRM_MODE_CONNECTOR_DVID;
9ea2c4be
AD		 423 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
424 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
425 gpio = radeon_lookup_gpio(rdev, 7);
426 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
427 }
3e5f8ff3
AD		 428 }
429
efa8450f
DA		 430 /* XFX Pine Group device rv730 reports no VGA DDC lines
431 * even though they are wired up to record 0x93
432 */
433 if ((dev->pdev->device == 0x9498) &&
434 (dev->pdev->subsystem_vendor == 0x1682) &&
435 (dev->pdev->subsystem_device == 0x2452)) {
436 struct radeon_device *rdev = dev->dev_private;
437 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
438 }
771fe6b9
JG		 439 return true;
440}
441
442const int supported_devices_connector_convert[] = {
443 DRM_MODE_CONNECTOR_Unknown,
444 DRM_MODE_CONNECTOR_VGA,
445 DRM_MODE_CONNECTOR_DVII,
446 DRM_MODE_CONNECTOR_DVID,
447 DRM_MODE_CONNECTOR_DVIA,
448 DRM_MODE_CONNECTOR_SVIDEO,
449 DRM_MODE_CONNECTOR_Composite,
450 DRM_MODE_CONNECTOR_LVDS,
451 DRM_MODE_CONNECTOR_Unknown,
452 DRM_MODE_CONNECTOR_Unknown,
453 DRM_MODE_CONNECTOR_HDMIA,
454 DRM_MODE_CONNECTOR_HDMIB,
455 DRM_MODE_CONNECTOR_Unknown,
456 DRM_MODE_CONNECTOR_Unknown,
457 DRM_MODE_CONNECTOR_9PinDIN,
458 DRM_MODE_CONNECTOR_DisplayPort
459};
460
b75fad06
AD		 461const uint16_t supported_devices_connector_object_id_convert[] = {
462 CONNECTOR_OBJECT_ID_NONE,
463 CONNECTOR_OBJECT_ID_VGA,
464 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
465 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
466 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
467 CONNECTOR_OBJECT_ID_COMPOSITE,
468 CONNECTOR_OBJECT_ID_SVIDEO,
469 CONNECTOR_OBJECT_ID_LVDS,
470 CONNECTOR_OBJECT_ID_9PIN_DIN,
471 CONNECTOR_OBJECT_ID_9PIN_DIN,
472 CONNECTOR_OBJECT_ID_DISPLAYPORT,
473 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
474 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
475 CONNECTOR_OBJECT_ID_SVIDEO
476};
477
771fe6b9
JG		 478const int object_connector_convert[] = {
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_DVII,
481 DRM_MODE_CONNECTOR_DVII,
482 DRM_MODE_CONNECTOR_DVID,
483 DRM_MODE_CONNECTOR_DVID,
484 DRM_MODE_CONNECTOR_VGA,
485 DRM_MODE_CONNECTOR_Composite,
486 DRM_MODE_CONNECTOR_SVIDEO,
487 DRM_MODE_CONNECTOR_Unknown,
705af9c7 488 DRM_MODE_CONNECTOR_Unknown,
771fe6b9
JG		 489 DRM_MODE_CONNECTOR_9PinDIN,
490 DRM_MODE_CONNECTOR_Unknown,
491 DRM_MODE_CONNECTOR_HDMIA,
492 DRM_MODE_CONNECTOR_HDMIB,
771fe6b9
JG		 493 DRM_MODE_CONNECTOR_LVDS,
494 DRM_MODE_CONNECTOR_9PinDIN,
495 DRM_MODE_CONNECTOR_Unknown,
496 DRM_MODE_CONNECTOR_Unknown,
497 DRM_MODE_CONNECTOR_Unknown,
196c58d2
AD		 498 DRM_MODE_CONNECTOR_DisplayPort,
499 DRM_MODE_CONNECTOR_eDP,
500 DRM_MODE_CONNECTOR_Unknown
771fe6b9
JG		 501};
502
503bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
504{
505 struct radeon_device *rdev = dev->dev_private;
506 struct radeon_mode_info *mode_info = &rdev->mode_info;
507 struct atom_context *ctx = mode_info->atom_context;
508 int index = GetIndexIntoMasterTable(DATA, Object_Header);
eed45b30
AD		 509 u16 size, data_offset;
510 u8 frev, crev;
771fe6b9 511 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
26b5bc98 512 ATOM_OBJECT_TABLE *router_obj;
771fe6b9
JG		 513 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
514 ATOM_OBJECT_HEADER *obj_header;
26b5bc98 515 int i, j, k, path_size, device_support;
771fe6b9 516 int connector_type;
eed45b30 517 u16 igp_lane_info, conn_id, connector_object_id;
771fe6b9 518 struct radeon_i2c_bus_rec ddc_bus;
26b5bc98 519 struct radeon_router router;
eed45b30
AD		 520 struct radeon_gpio_rec gpio;
521 struct radeon_hpd hpd;
522
a084e6ee 523 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
771fe6b9
JG		 524 return false;
525
526 if (crev < 2)
527 return false;
528
529 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
530 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
531 (ctx->bios + data_offset +
532 le16_to_cpu(obj_header->usDisplayPathTableOffset));
533 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
534 (ctx->bios + data_offset +
535 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
26b5bc98
AD		 536 router_obj = (ATOM_OBJECT_TABLE *)
537 (ctx->bios + data_offset +
538 le16_to_cpu(obj_header->usRouterObjectTableOffset));
771fe6b9
JG		 539 device_support = le16_to_cpu(obj_header->usDeviceSupport);
540
541 path_size = 0;
542 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
543 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
544 ATOM_DISPLAY_OBJECT_PATH *path;
545 addr += path_size;
546 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
547 path_size += le16_to_cpu(path->usSize);
5137ee94 548
771fe6b9
JG		 549 if (device_support & le16_to_cpu(path->usDeviceTag)) {
550 uint8_t con_obj_id, con_obj_num, con_obj_type;
551
552 con_obj_id =
553 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
554 >> OBJECT_ID_SHIFT;
555 con_obj_num =
556 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
557 >> ENUM_ID_SHIFT;
558 con_obj_type =
559 (le16_to_cpu(path->usConnObjectId) &
560 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
561
4bbd4973
DA		 562 /* TODO CV support */
563 if (le16_to_cpu(path->usDeviceTag) ==
564 ATOM_DEVICE_CV_SUPPORT)
771fe6b9
JG		 565 continue;
566
ee59f2b4
AD		 567 /* IGP chips */
568 if ((rdev->flags & RADEON_IS_IGP) &&
771fe6b9
JG		 569 (con_obj_id ==
570 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
571 uint16_t igp_offset = 0;
572 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
573
574 index =
575 GetIndexIntoMasterTable(DATA,
576 IntegratedSystemInfo);
577
a084e6ee
AD		 578 if (atom_parse_data_header(ctx, index, &size, &frev,
579 &crev, &igp_offset)) {
580
581 if (crev >= 2) {
582 igp_obj =
583 (ATOM_INTEGRATED_SYSTEM_INFO_V2
584 *) (ctx->bios + igp_offset);
585
586 if (igp_obj) {
587 uint32_t slot_config, ct;
588
589 if (con_obj_num == 1)
590 slot_config =
591 igp_obj->
592 ulDDISlot1Config;
593 else
594 slot_config =
595 igp_obj->
596 ulDDISlot2Config;
597
598 ct = (slot_config >> 16) & 0xff;
599 connector_type =
600 object_connector_convert
601 [ct];
602 connector_object_id = ct;
603 igp_lane_info =
604 slot_config & 0xffff;
605 } else
606 continue;
771fe6b9
JG		 607 } else
608 continue;
a084e6ee
AD		 609 } else {
610 igp_lane_info = 0;
611 connector_type =
612 object_connector_convert[con_obj_id];
613 connector_object_id = con_obj_id;
614 }
771fe6b9
JG		 615 } else {
616 igp_lane_info = 0;
617 connector_type =
618 object_connector_convert[con_obj_id];
b75fad06 619 connector_object_id = con_obj_id;
771fe6b9
JG		 620 }
621
622 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
623 continue;
624
bdd91b2b
TW		 625 router.ddc_valid = false;
626 router.cd_valid = false;
26b5bc98
AD		 627 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
628 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
771fe6b9 629
26b5bc98 630 grph_obj_id =
771fe6b9
JG		 631 (le16_to_cpu(path->usGraphicObjIds[j]) &
632 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
26b5bc98 633 grph_obj_num =
771fe6b9
JG		 634 (le16_to_cpu(path->usGraphicObjIds[j]) &
635 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
26b5bc98 636 grph_obj_type =
771fe6b9
JG		 637 (le16_to_cpu(path->usGraphicObjIds[j]) &
638 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
639
26b5bc98 640 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
5137ee94 641 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
771fe6b9
JG		 642
643 radeon_add_atom_encoder(dev,
5137ee94 644 encoder_obj,
771fe6b9
JG		 645 le16_to_cpu
646 (path->
647 usDeviceTag));
648
26b5bc98 649 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
26b5bc98 650 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
bdd91b2b 651 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
26b5bc98
AD		 652 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
653 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
654 (ctx->bios + data_offset +
655 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
656 ATOM_I2C_RECORD *i2c_record;
657 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
658 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
fb939dfc 659 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
26b5bc98
AD		 660 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
661 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
662 (ctx->bios + data_offset +
663 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
664 int enum_id;
665
666 router.router_id = router_obj_id;
667 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
668 enum_id++) {
669 if (le16_to_cpu(path->usConnObjectId) ==
670 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
671 break;
672 }
673
674 while (record->ucRecordType > 0 &&
675 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
676 switch (record->ucRecordType) {
677 case ATOM_I2C_RECORD_TYPE:
678 i2c_record =
679 (ATOM_I2C_RECORD *)
680 record;
681 i2c_config =
682 (ATOM_I2C_ID_CONFIG_ACCESS *)
683 &i2c_record->sucI2cId;
684 router.i2c_info =
685 radeon_lookup_i2c_gpio(rdev,
686 i2c_config->
687 ucAccess);
688 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
689 break;
690 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
691 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
692 record;
fb939dfc
AD		 693 router.ddc_valid = true;
694 router.ddc_mux_type = ddc_path->ucMuxType;
695 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
696 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
697 break;
698 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
699 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
700 record;
701 router.cd_valid = true;
702 router.cd_mux_type = cd_path->ucMuxType;
703 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
704 router.cd_mux_state = cd_path->ucMuxState[enum_id];
26b5bc98
AD		 705 break;
706 }
707 record = (ATOM_COMMON_RECORD_HEADER *)
708 ((char *)record + record->ucRecordSize);
709 }
710 }
711 }
771fe6b9
JG		 712 }
713 }
714
eed45b30 715 /* look up gpio for ddc, hpd */
2bfcc0fc
AD		 716 ddc_bus.valid = false;
717 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 718 if ((le16_to_cpu(path->usDeviceTag) &
eed45b30 719 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771fe6b9
JG		 720 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
721 if (le16_to_cpu(path->usConnObjectId) ==
722 le16_to_cpu(con_obj->asObjects[j].
723 usObjectID)) {
724 ATOM_COMMON_RECORD_HEADER
725 *record =
726 (ATOM_COMMON_RECORD_HEADER
727 *)
728 (ctx->bios + data_offset +
729 le16_to_cpu(con_obj->
730 asObjects[j].
731 usRecordOffset));
732 ATOM_I2C_RECORD *i2c_record;
eed45b30 733 ATOM_HPD_INT_RECORD *hpd_record;
d3f420d1 734 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
6a93cb25 735
771fe6b9
JG		 736 while (record->ucRecordType > 0
737 && record->
738 ucRecordType <=
739 ATOM_MAX_OBJECT_RECORD_NUMBER) {
eed45b30 740 switch (record->ucRecordType) {
771fe6b9
JG		 741 case ATOM_I2C_RECORD_TYPE:
742 i2c_record =
eed45b30
AD		 743 (ATOM_I2C_RECORD *)
744 record;
d3f420d1
AD		 745 i2c_config =
746 (ATOM_I2C_ID_CONFIG_ACCESS *)
747 &i2c_record->sucI2cId;
eed45b30 748 ddc_bus = radeon_lookup_i2c_gpio(rdev,
d3f420d1
AD		 749 i2c_config->
750 ucAccess);
eed45b30
AD		 751 break;
752 case ATOM_HPD_INT_RECORD_TYPE:
753 hpd_record =
754 (ATOM_HPD_INT_RECORD *)
755 record;
756 gpio = radeon_lookup_gpio(rdev,
757 hpd_record->ucHPDIntGPIOID);
758 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
759 hpd.plugged_state = hpd_record->ucPlugged_PinState;
771fe6b9
JG		 760 break;
761 }
762 record =
763 (ATOM_COMMON_RECORD_HEADER
764 *) ((char *)record
765 +
766 record->
767 ucRecordSize);
768 }
769 break;
770 }
771 }
eed45b30 772 }
771fe6b9 773
bcc1c2a1 774 /* needed for aux chan transactions */
8e36ed00 775 ddc_bus.hpd = hpd.hpd;
bcc1c2a1 776
705af9c7
AD		 777 conn_id = le16_to_cpu(path->usConnObjectId);
778
779 if (!radeon_atom_apply_quirks
780 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
eed45b30 781 &ddc_bus, &conn_id, &hpd))
705af9c7
AD		 782 continue;
783
771fe6b9 784 radeon_add_atom_connector(dev,
705af9c7 785 conn_id,
771fe6b9
JG		 786 le16_to_cpu(path->
787 usDeviceTag),
788 connector_type, &ddc_bus,
5137ee94 789 igp_lane_info,
eed45b30 790 connector_object_id,
26b5bc98
AD		 791 &hpd,
792 &router);
771fe6b9
JG		 793
794 }
795 }
796
797 radeon_link_encoder_connector(dev);
798
799 return true;
800}
801
b75fad06
AD		 802static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
803 int connector_type,
804 uint16_t devices)
805{
806 struct radeon_device *rdev = dev->dev_private;
807
808 if (rdev->flags & RADEON_IS_IGP) {
809 return supported_devices_connector_object_id_convert
810 [connector_type];
811 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
812 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
813 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
814 struct radeon_mode_info *mode_info = &rdev->mode_info;
815 struct atom_context *ctx = mode_info->atom_context;
816 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
817 uint16_t size, data_offset;
818 uint8_t frev, crev;
819 ATOM_XTMDS_INFO *xtmds;
820
a084e6ee
AD		 821 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
822 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
b75fad06 823
a084e6ee
AD		 824 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
825 if (connector_type == DRM_MODE_CONNECTOR_DVII)
826 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
827 else
828 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
829 } else {
830 if (connector_type == DRM_MODE_CONNECTOR_DVII)
831 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
832 else
833 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
834 }
835 } else
836 return supported_devices_connector_object_id_convert
837 [connector_type];
b75fad06
AD		 838 } else {
839 return supported_devices_connector_object_id_convert
840 [connector_type];
841 }
842}
843
771fe6b9
JG		 844struct bios_connector {
845 bool valid;
705af9c7 846 uint16_t line_mux;
771fe6b9
JG		 847 uint16_t devices;
848 int connector_type;
849 struct radeon_i2c_bus_rec ddc_bus;
eed45b30 850 struct radeon_hpd hpd;
771fe6b9
JG		 851};
852
853bool radeon_get_atom_connector_info_from_supported_devices_table(struct
854 drm_device
855 *dev)
856{
857 struct radeon_device *rdev = dev->dev_private;
858 struct radeon_mode_info *mode_info = &rdev->mode_info;
859 struct atom_context *ctx = mode_info->atom_context;
860 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
861 uint16_t size, data_offset;
862 uint8_t frev, crev;
863 uint16_t device_support;
864 uint8_t dac;
865 union atom_supported_devices *supported_devices;
eed45b30 866 int i, j, max_device;
f49d273d
PB		 867 struct bios_connector *bios_connectors;
868 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
26b5bc98
AD		 869 struct radeon_router router;
870
fb939dfc
AD		 871 router.ddc_valid = false;
872 router.cd_valid = false;
771fe6b9 873
f49d273d
PB		 874 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
875 if (!bios_connectors)
876 return false;
877
878 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
879 &data_offset)) {
880 kfree(bios_connectors);
a084e6ee 881 return false;
f49d273d 882 }
771fe6b9
JG		 883
884 supported_devices =
885 (union atom_supported_devices *)(ctx->bios + data_offset);
886
887 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
888
eed45b30
AD		 889 if (frev > 1)
890 max_device = ATOM_MAX_SUPPORTED_DEVICE;
891 else
892 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
893
894 for (i = 0; i < max_device; i++) {
771fe6b9
JG		 895 ATOM_CONNECTOR_INFO_I2C ci =
896 supported_devices->info.asConnInfo[i];
897
898 bios_connectors[i].valid = false;
899
900 if (!(device_support & (1 << i))) {
901 continue;
902 }
903
904 if (i == ATOM_DEVICE_CV_INDEX) {
d9fdaafb 905 DRM_DEBUG_KMS("Skipping Component Video\n");
771fe6b9
JG		 906 continue;
907 }
908
771fe6b9
JG		 909 bios_connectors[i].connector_type =
910 supported_devices_connector_convert[ci.sucConnectorInfo.
911 sbfAccess.
912 bfConnectorType];
913
914 if (bios_connectors[i].connector_type ==
915 DRM_MODE_CONNECTOR_Unknown)
916 continue;
917
918 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
919
d3f420d1
AD		 920 bios_connectors[i].line_mux =
921 ci.sucI2cId.ucAccess;
771fe6b9
JG		 922
923 /* give tv unique connector ids */
924 if (i == ATOM_DEVICE_TV1_INDEX) {
925 bios_connectors[i].ddc_bus.valid = false;
926 bios_connectors[i].line_mux = 50;
927 } else if (i == ATOM_DEVICE_TV2_INDEX) {
928 bios_connectors[i].ddc_bus.valid = false;
929 bios_connectors[i].line_mux = 51;
930 } else if (i == ATOM_DEVICE_CV_INDEX) {
931 bios_connectors[i].ddc_bus.valid = false;
932 bios_connectors[i].line_mux = 52;
933 } else
934 bios_connectors[i].ddc_bus =
eed45b30
AD		 935 radeon_lookup_i2c_gpio(rdev,
936 bios_connectors[i].line_mux);
937
938 if ((crev > 1) && (frev > 1)) {
939 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
940 switch (isb) {
941 case 0x4:
942 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
943 break;
944 case 0xa:
945 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
946 break;
947 default:
948 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
949 break;
950 }
951 } else {
952 if (i == ATOM_DEVICE_DFP1_INDEX)
953 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
954 else if (i == ATOM_DEVICE_DFP2_INDEX)
955 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
956 else
957 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
958 }
771fe6b9
JG		 959
960 /* Always set the connector type to VGA for CRT1/CRT2. if they are
961 * shared with a DVI port, we'll pick up the DVI connector when we
962 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
963 */
964 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
965 bios_connectors[i].connector_type =
966 DRM_MODE_CONNECTOR_VGA;
967
968 if (!radeon_atom_apply_quirks
969 (dev, (1 << i), &bios_connectors[i].connector_type,
eed45b30
AD		 970 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
971 &bios_connectors[i].hpd))
771fe6b9
JG		 972 continue;
973
974 bios_connectors[i].valid = true;
975 bios_connectors[i].devices = (1 << i);
976
977 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
978 radeon_add_atom_encoder(dev,
5137ee94 979 radeon_get_encoder_enum(dev,
771fe6b9
JG		 980 (1 << i),
981 dac),
982 (1 << i));
983 else
984 radeon_add_legacy_encoder(dev,
5137ee94 985 radeon_get_encoder_enum(dev,
f56cd64f 986 (1 << i),
771fe6b9
JG		 987 dac),
988 (1 << i));
989 }
990
991 /* combine shared connectors */
eed45b30 992 for (i = 0; i < max_device; i++) {
771fe6b9 993 if (bios_connectors[i].valid) {
eed45b30 994 for (j = 0; j < max_device; j++) {
771fe6b9
JG		 995 if (bios_connectors[j].valid && (i != j)) {
996 if (bios_connectors[i].line_mux ==
997 bios_connectors[j].line_mux) {
f56cd64f
AD		 998 /* make sure not to combine LVDS */
999 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1000 bios_connectors[i].line_mux = 53;
1001 bios_connectors[i].ddc_bus.valid = false;
1002 continue;
1003 }
1004 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1005 bios_connectors[j].line_mux = 53;
1006 bios_connectors[j].ddc_bus.valid = false;
1007 continue;
1008 }
1009 /* combine analog and digital for DVI-I */
1010 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1011 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1012 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1013 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1014 bios_connectors[i].devices |=
1015 bios_connectors[j].devices;
1016 bios_connectors[i].connector_type =
1017 DRM_MODE_CONNECTOR_DVII;
1018 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
eed45b30
AD		 1019 bios_connectors[i].hpd =
1020 bios_connectors[j].hpd;
f56cd64f 1021 bios_connectors[j].valid = false;
771fe6b9
JG		 1022 }
1023 }
1024 }
1025 }
1026 }
1027 }
1028
1029 /* add the connectors */
eed45b30 1030 for (i = 0; i < max_device; i++) {
b75fad06
AD		 1031 if (bios_connectors[i].valid) {
1032 uint16_t connector_object_id =
1033 atombios_get_connector_object_id(dev,
1034 bios_connectors[i].connector_type,
1035 bios_connectors[i].devices);
771fe6b9
JG		 1036 radeon_add_atom_connector(dev,
1037 bios_connectors[i].line_mux,
1038 bios_connectors[i].devices,
1039 bios_connectors[i].
1040 connector_type,
1041 &bios_connectors[i].ddc_bus,
5137ee94 1042 0,
eed45b30 1043 connector_object_id,
26b5bc98
AD		 1044 &bios_connectors[i].hpd,
1045 &router);
b75fad06 1046 }
771fe6b9
JG		 1047 }
1048
1049 radeon_link_encoder_connector(dev);
1050
f49d273d 1051 kfree(bios_connectors);
771fe6b9
JG		 1052 return true;
1053}
1054
1055union firmware_info {
1056 ATOM_FIRMWARE_INFO info;
1057 ATOM_FIRMWARE_INFO_V1_2 info_12;
1058 ATOM_FIRMWARE_INFO_V1_3 info_13;
1059 ATOM_FIRMWARE_INFO_V1_4 info_14;
bcc1c2a1 1060 ATOM_FIRMWARE_INFO_V2_1 info_21;
771fe6b9
JG		 1061};
1062
1063bool radeon_atom_get_clock_info(struct drm_device *dev)
1064{
1065 struct radeon_device *rdev = dev->dev_private;
1066 struct radeon_mode_info *mode_info = &rdev->mode_info;
1067 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1068 union firmware_info *firmware_info;
1069 uint8_t frev, crev;
1070 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1071 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 1072 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 1073 struct radeon_pll *spll = &rdev->clock.spll;
1074 struct radeon_pll *mpll = &rdev->clock.mpll;
1075 uint16_t data_offset;
1076
a084e6ee
AD		 1077 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1078 &frev, &crev, &data_offset)) {
1079 firmware_info =
1080 (union firmware_info *)(mode_info->atom_context->bios +
1081 data_offset);
771fe6b9
JG		 1082 /* pixel clocks */
1083 p1pll->reference_freq =
1084 le16_to_cpu(firmware_info->info.usReferenceClock);
1085 p1pll->reference_div = 0;
1086
bc293e58
MF		 1087 if (crev < 2)
1088 p1pll->pll_out_min =
1089 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1090 else
1091 p1pll->pll_out_min =
1092 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
771fe6b9
JG		 1093 p1pll->pll_out_max =
1094 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1095
86cb2bbf
AD		 1096 if (crev >= 4) {
1097 p1pll->lcd_pll_out_min =
1098 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1099 if (p1pll->lcd_pll_out_min == 0)
1100 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1101 p1pll->lcd_pll_out_max =
1102 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1103 if (p1pll->lcd_pll_out_max == 0)
1104 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1105 } else {
1106 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1107 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1108 }
1109
771fe6b9
JG		 1110 if (p1pll->pll_out_min == 0) {
1111 if (ASIC_IS_AVIVO(rdev))
1112 p1pll->pll_out_min = 64800;
1113 else
1114 p1pll->pll_out_min = 20000;
8f552a66
AD		 1115 } else if (p1pll->pll_out_min > 64800) {
1116 /* Limiting the pll output range is a good thing generally as
1117 * it limits the number of possible pll combinations for a given
1118 * frequency presumably to the ones that work best on each card.
1119 * However, certain duallink DVI monitors seem to like
1120 * pll combinations that would be limited by this at least on
1121 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1122 * family.
1123 */
48dfaaeb 1124 p1pll->pll_out_min = 64800;
771fe6b9
JG		 1125 }
1126
1127 p1pll->pll_in_min =
1128 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1129 p1pll->pll_in_max =
1130 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1131
1132 *p2pll = *p1pll;
1133
1134 /* system clock */
1135 spll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 spll->reference_div = 0;
1138
1139 spll->pll_out_min =
1140 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1141 spll->pll_out_max =
1142 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1143
1144 /* ??? */
1145 if (spll->pll_out_min == 0) {
1146 if (ASIC_IS_AVIVO(rdev))
1147 spll->pll_out_min = 64800;
1148 else
1149 spll->pll_out_min = 20000;
1150 }
1151
1152 spll->pll_in_min =
1153 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1154 spll->pll_in_max =
1155 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1156
1157 /* memory clock */
1158 mpll->reference_freq =
1159 le16_to_cpu(firmware_info->info.usReferenceClock);
1160 mpll->reference_div = 0;
1161
1162 mpll->pll_out_min =
1163 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1164 mpll->pll_out_max =
1165 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1166
1167 /* ??? */
1168 if (mpll->pll_out_min == 0) {
1169 if (ASIC_IS_AVIVO(rdev))
1170 mpll->pll_out_min = 64800;
1171 else
1172 mpll->pll_out_min = 20000;
1173 }
1174
1175 mpll->pll_in_min =
1176 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1177 mpll->pll_in_max =
1178 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1179
1180 rdev->clock.default_sclk =
1181 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1182 rdev->clock.default_mclk =
1183 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1184
bcc1c2a1
AD		 1185 if (ASIC_IS_DCE4(rdev)) {
1186 rdev->clock.default_dispclk =
1187 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1188 if (rdev->clock.default_dispclk == 0)
1189 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1190 rdev->clock.dp_extclk =
1191 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1192 }
1193 *dcpll = *p1pll;
1194
771fe6b9
JG		 1195 return true;
1196 }
bcc1c2a1 1197
771fe6b9
JG		 1198 return false;
1199}
1200
06b6476d
AD		 1201union igp_info {
1202 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1203 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1204};
1205
1206bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1207{
1208 struct radeon_mode_info *mode_info = &rdev->mode_info;
1209 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1210 union igp_info *igp_info;
1211 u8 frev, crev;
1212 u16 data_offset;
1213
4c70b2ea
AD		 1214 /* sideport is AMD only */
1215 if (rdev->family == CHIP_RS600)
1216 return false;
1217
a084e6ee
AD		 1218 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1219 &frev, &crev, &data_offset)) {
1220 igp_info = (union igp_info *)(mode_info->atom_context->bios +
06b6476d 1221 data_offset);
06b6476d
AD		 1222 switch (crev) {
1223 case 1:
4c70b2ea
AD		 1224 if (igp_info->info.ulBootUpMemoryClock)
1225 return true;
06b6476d
AD		 1226 break;
1227 case 2:
4b80d954 1228 if (igp_info->info_2.ulBootUpSidePortClock)
06b6476d
AD		 1229 return true;
1230 break;
1231 default:
1232 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1233 break;
1234 }
1235 }
1236 return false;
1237}
1238
445282db
DA		 1239bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1240 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1241{
1242 struct drm_device *dev = encoder->base.dev;
1243 struct radeon_device *rdev = dev->dev_private;
1244 struct radeon_mode_info *mode_info = &rdev->mode_info;
1245 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1246 uint16_t data_offset;
1247 struct _ATOM_TMDS_INFO *tmds_info;
1248 uint8_t frev, crev;
1249 uint16_t maxfreq;
1250 int i;
771fe6b9 1251
a084e6ee
AD		 1252 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1253 &frev, &crev, &data_offset)) {
1254 tmds_info =
1255 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1256 data_offset);
771fe6b9 1257
771fe6b9
JG		 1258 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1259 for (i = 0; i < 4; i++) {
1260 tmds->tmds_pll[i].freq =
1261 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1262 tmds->tmds_pll[i].value =
1263 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1264 tmds->tmds_pll[i].value |=
1265 (tmds_info->asMiscInfo[i].
1266 ucPLL_VCO_Gain & 0x3f) << 6;
1267 tmds->tmds_pll[i].value |=
1268 (tmds_info->asMiscInfo[i].
1269 ucPLL_DutyCycle & 0xf) << 12;
1270 tmds->tmds_pll[i].value |=
1271 (tmds_info->asMiscInfo[i].
1272 ucPLL_VoltageSwing & 0xf) << 16;
1273
d9fdaafb 1274 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
771fe6b9
JG		 1275 tmds->tmds_pll[i].freq,
1276 tmds->tmds_pll[i].value);
1277
1278 if (maxfreq == tmds->tmds_pll[i].freq) {
1279 tmds->tmds_pll[i].freq = 0xffffffff;
1280 break;
1281 }
1282 }
445282db 1283 return true;
771fe6b9 1284 }
445282db 1285 return false;
771fe6b9
JG		 1286}
1287
ba032a58
AD		 1288bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1289 struct radeon_atom_ss *ss,
1290 int id)
ebbe1cb9 1291{
ebbe1cb9
AD		 1292 struct radeon_mode_info *mode_info = &rdev->mode_info;
1293 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
ba032a58 1294 uint16_t data_offset, size;
ebbe1cb9
AD		 1295 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1296 uint8_t frev, crev;
ba032a58 1297 int i, num_indices;
ebbe1cb9 1298
ba032a58
AD		 1299 memset(ss, 0, sizeof(struct radeon_atom_ss));
1300 if (atom_parse_data_header(mode_info->atom_context, index, &size,
a084e6ee
AD		 1301 &frev, &crev, &data_offset)) {
1302 ss_info =
1303 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
ebbe1cb9 1304
ba032a58
AD		 1305 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1306 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
ebbe1cb9 1307
ba032a58 1308 for (i = 0; i < num_indices; i++) {
279b215e
AD		 1309 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1310 ss->percentage =
1311 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1312 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1313 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1314 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1315 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1316 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
ba032a58
AD		 1317 return true;
1318 }
1319 }
1320 }
1321 return false;
1322}
1323
4339c442
AD		 1324static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1325 struct radeon_atom_ss *ss,
1326 int id)
1327{
1328 struct radeon_mode_info *mode_info = &rdev->mode_info;
1329 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1330 u16 data_offset, size;
1331 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1332 u8 frev, crev;
1333 u16 percentage = 0, rate = 0;
1334
1335 /* get any igp specific overrides */
1336 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1337 &frev, &crev, &data_offset)) {
1338 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1339 (mode_info->atom_context->bios + data_offset);
1340 switch (id) {
1341 case ASIC_INTERNAL_SS_ON_TMDS:
1342 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1343 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1344 break;
1345 case ASIC_INTERNAL_SS_ON_HDMI:
1346 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1347 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1348 break;
1349 case ASIC_INTERNAL_SS_ON_LVDS:
1350 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1351 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1352 break;
1353 }
1354 if (percentage)
1355 ss->percentage = percentage;
1356 if (rate)
1357 ss->rate = rate;
1358 }
1359}
1360
ba032a58
AD		 1361union asic_ss_info {
1362 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1363 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1364 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1365};
1366
1367bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1368 struct radeon_atom_ss *ss,
1369 int id, u32 clock)
1370{
1371 struct radeon_mode_info *mode_info = &rdev->mode_info;
1372 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1373 uint16_t data_offset, size;
1374 union asic_ss_info *ss_info;
1375 uint8_t frev, crev;
1376 int i, num_indices;
1377
1378 memset(ss, 0, sizeof(struct radeon_atom_ss));
1379 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1380 &frev, &crev, &data_offset)) {
1381
1382 ss_info =
1383 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1384
1385 switch (frev) {
1386 case 1:
1387 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1388 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1389
1390 for (i = 0; i < num_indices; i++) {
1391 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1392 (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1393 ss->percentage =
1394 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1395 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1396 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1397 return true;
1398 }
279b215e 1399 }
ba032a58
AD		 1400 break;
1401 case 2:
1402 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1403 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1404 for (i = 0; i < num_indices; i++) {
1405 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1406 (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1407 ss->percentage =
1408 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1409 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1410 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1411 return true;
1412 }
1413 }
1414 break;
1415 case 3:
1416 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1417 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1418 for (i = 0; i < num_indices; i++) {
1419 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1420 (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1421 ss->percentage =
1422 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1423 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1424 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
4339c442
AD		 1425 if (rdev->flags & RADEON_IS_IGP)
1426 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
ba032a58
AD		 1427 return true;
1428 }
1429 }
1430 break;
1431 default:
1432 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1433 break;
279b215e 1434 }
ba032a58 1435
ebbe1cb9 1436 }
ba032a58 1437 return false;
ebbe1cb9
AD		 1438}
1439
771fe6b9
JG		 1440union lvds_info {
1441 struct _ATOM_LVDS_INFO info;
1442 struct _ATOM_LVDS_INFO_V12 info_12;
1443};
1444
1445struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1446 radeon_encoder
1447 *encoder)
1448{
1449 struct drm_device *dev = encoder->base.dev;
1450 struct radeon_device *rdev = dev->dev_private;
1451 struct radeon_mode_info *mode_info = &rdev->mode_info;
1452 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
7dde8a19 1453 uint16_t data_offset, misc;
771fe6b9
JG		 1454 union lvds_info *lvds_info;
1455 uint8_t frev, crev;
1456 struct radeon_encoder_atom_dig *lvds = NULL;
5137ee94 1457 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
771fe6b9 1458
a084e6ee
AD		 1459 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1460 &frev, &crev, &data_offset)) {
1461 lvds_info =
1462 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
771fe6b9
JG		 1463 lvds =
1464 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1465
1466 if (!lvds)
1467 return NULL;
1468
de2103e4 1469 lvds->native_mode.clock =
771fe6b9 1470 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
de2103e4 1471 lvds->native_mode.hdisplay =
771fe6b9 1472 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
de2103e4 1473 lvds->native_mode.vdisplay =
771fe6b9 1474 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
de2103e4
AD		 1475 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1476 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1477 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1478 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1479 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1480 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1481 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1482 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1483 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1ff26a36 1484 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
de2103e4
AD		 1485 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1486 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
771fe6b9
JG		 1487 lvds->panel_pwr_delay =
1488 le16_to_cpu(lvds_info->info.usOffDelayInMs);
ba032a58 1489 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
7dde8a19
AD		 1490
1491 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1492 if (misc & ATOM_VSYNC_POLARITY)
1493 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1494 if (misc & ATOM_HSYNC_POLARITY)
1495 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1496 if (misc & ATOM_COMPOSITESYNC)
1497 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1498 if (misc & ATOM_INTERLACE)
1499 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1500 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1501 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1502
de2103e4
AD		 1503 /* set crtc values */
1504 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
771fe6b9 1505
ba032a58 1506 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
ebbe1cb9 1507
771fe6b9 1508 encoder->native_mode = lvds->native_mode;
5137ee94
AD		 1509
1510 if (encoder_enum == 2)
1511 lvds->linkb = true;
1512 else
1513 lvds->linkb = false;
1514
771fe6b9
JG		 1515 }
1516 return lvds;
1517}
1518
6fe7ac3f
AD		 1519struct radeon_encoder_primary_dac *
1520radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1521{
1522 struct drm_device *dev = encoder->base.dev;
1523 struct radeon_device *rdev = dev->dev_private;
1524 struct radeon_mode_info *mode_info = &rdev->mode_info;
1525 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1526 uint16_t data_offset;
1527 struct _COMPASSIONATE_DATA *dac_info;
1528 uint8_t frev, crev;
1529 uint8_t bg, dac;
6fe7ac3f
AD		 1530 struct radeon_encoder_primary_dac *p_dac = NULL;
1531
a084e6ee
AD		 1532 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1533 &frev, &crev, &data_offset)) {
1534 dac_info = (struct _COMPASSIONATE_DATA *)
1535 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1536
6fe7ac3f
AD		 1537 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1538
1539 if (!p_dac)
1540 return NULL;
1541
1542 bg = dac_info->ucDAC1_BG_Adjustment;
1543 dac = dac_info->ucDAC1_DAC_Adjustment;
1544 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1545
1546 }
1547 return p_dac;
1548}
1549
4ce001ab 1550bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
5a9bcacc 1551 struct drm_display_mode *mode)
4ce001ab
DA		 1552{
1553 struct radeon_mode_info *mode_info = &rdev->mode_info;
1554 ATOM_ANALOG_TV_INFO *tv_info;
1555 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1556 ATOM_DTD_FORMAT *dtd_timings;
1557 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1558 u8 frev, crev;
5a9bcacc 1559 u16 data_offset, misc;
4ce001ab 1560
a084e6ee
AD		 1561 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1562 &frev, &crev, &data_offset))
1563 return false;
4ce001ab
DA		 1564
1565 switch (crev) {
1566 case 1:
1567 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
0031c41b 1568 if (index >= MAX_SUPPORTED_TV_TIMING)
4ce001ab
DA		 1569 return false;
1570
5a9bcacc
AD		 1571 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1572 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1573 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1574 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1575 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1576
1577 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1578 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1579 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1580 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1581 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1582
1583 mode->flags = 0;
1584 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1585 if (misc & ATOM_VSYNC_POLARITY)
1586 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1587 if (misc & ATOM_HSYNC_POLARITY)
1588 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1589 if (misc & ATOM_COMPOSITESYNC)
1590 mode->flags |= DRM_MODE_FLAG_CSYNC;
1591 if (misc & ATOM_INTERLACE)
1592 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1593 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1594 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1595
1596 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
4ce001ab
DA		 1597
1598 if (index == 1) {
1599 /* PAL timings appear to have wrong values for totals */
5a9bcacc
AD		 1600 mode->crtc_htotal -= 1;
1601 mode->crtc_vtotal -= 1;
4ce001ab
DA		 1602 }
1603 break;
1604 case 2:
1605 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
0031c41b 1606 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
4ce001ab
DA		 1607 return false;
1608
1609 dtd_timings = &tv_info_v1_2->aModeTimings[index];
5a9bcacc
AD		 1610 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1611 le16_to_cpu(dtd_timings->usHBlanking_Time);
1612 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1613 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1614 le16_to_cpu(dtd_timings->usHSyncOffset);
1615 mode->crtc_hsync_end = mode->crtc_hsync_start +
1616 le16_to_cpu(dtd_timings->usHSyncWidth);
1617
1618 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1619 le16_to_cpu(dtd_timings->usVBlanking_Time);
1620 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1621 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1622 le16_to_cpu(dtd_timings->usVSyncOffset);
1623 mode->crtc_vsync_end = mode->crtc_vsync_start +
1624 le16_to_cpu(dtd_timings->usVSyncWidth);
1625
1626 mode->flags = 0;
1627 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1628 if (misc & ATOM_VSYNC_POLARITY)
1629 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1630 if (misc & ATOM_HSYNC_POLARITY)
1631 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1632 if (misc & ATOM_COMPOSITESYNC)
1633 mode->flags |= DRM_MODE_FLAG_CSYNC;
1634 if (misc & ATOM_INTERLACE)
1635 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1636 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1637 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1638
1639 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
4ce001ab
DA		 1640 break;
1641 }
1642 return true;
1643}
1644
d79766fa
AD		 1645enum radeon_tv_std
1646radeon_atombios_get_tv_info(struct radeon_device *rdev)
1647{
1648 struct radeon_mode_info *mode_info = &rdev->mode_info;
1649 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1650 uint16_t data_offset;
1651 uint8_t frev, crev;
1652 struct _ATOM_ANALOG_TV_INFO *tv_info;
1653 enum radeon_tv_std tv_std = TV_STD_NTSC;
1654
a084e6ee
AD		 1655 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1656 &frev, &crev, &data_offset)) {
d79766fa 1657
a084e6ee
AD		 1658 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1659 (mode_info->atom_context->bios + data_offset);
d79766fa 1660
a084e6ee
AD		 1661 switch (tv_info->ucTV_BootUpDefaultStandard) {
1662 case ATOM_TV_NTSC:
1663 tv_std = TV_STD_NTSC;
40f76d81 1664 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
a084e6ee
AD		 1665 break;
1666 case ATOM_TV_NTSCJ:
1667 tv_std = TV_STD_NTSC_J;
40f76d81 1668 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
a084e6ee
AD		 1669 break;
1670 case ATOM_TV_PAL:
1671 tv_std = TV_STD_PAL;
40f76d81 1672 DRM_DEBUG_KMS("Default TV standard: PAL\n");
a084e6ee
AD		 1673 break;
1674 case ATOM_TV_PALM:
1675 tv_std = TV_STD_PAL_M;
40f76d81 1676 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
a084e6ee
AD		 1677 break;
1678 case ATOM_TV_PALN:
1679 tv_std = TV_STD_PAL_N;
40f76d81 1680 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
a084e6ee
AD		 1681 break;
1682 case ATOM_TV_PALCN:
1683 tv_std = TV_STD_PAL_CN;
40f76d81 1684 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
a084e6ee
AD		 1685 break;
1686 case ATOM_TV_PAL60:
1687 tv_std = TV_STD_PAL_60;
40f76d81 1688 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
a084e6ee
AD		 1689 break;
1690 case ATOM_TV_SECAM:
1691 tv_std = TV_STD_SECAM;
40f76d81 1692 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
a084e6ee
AD		 1693 break;
1694 default:
1695 tv_std = TV_STD_NTSC;
40f76d81 1696 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
a084e6ee
AD		 1697 break;
1698 }
d79766fa
AD		 1699 }
1700 return tv_std;
1701}
1702
6fe7ac3f
AD		 1703struct radeon_encoder_tv_dac *
1704radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1705{
1706 struct drm_device *dev = encoder->base.dev;
1707 struct radeon_device *rdev = dev->dev_private;
1708 struct radeon_mode_info *mode_info = &rdev->mode_info;
1709 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1710 uint16_t data_offset;
1711 struct _COMPASSIONATE_DATA *dac_info;
1712 uint8_t frev, crev;
1713 uint8_t bg, dac;
6fe7ac3f
AD		 1714 struct radeon_encoder_tv_dac *tv_dac = NULL;
1715
a084e6ee
AD		 1716 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1717 &frev, &crev, &data_offset)) {
6fe7ac3f 1718
a084e6ee
AD		 1719 dac_info = (struct _COMPASSIONATE_DATA *)
1720 (mode_info->atom_context->bios + data_offset);
6fe7ac3f 1721
6fe7ac3f
AD		 1722 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1723
1724 if (!tv_dac)
1725 return NULL;
1726
1727 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1728 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1729 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1730
1731 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1732 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1733 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1734
1735 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1736 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1737 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1738
d79766fa 1739 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
6fe7ac3f
AD		 1740 }
1741 return tv_dac;
1742}
1743
29fb52ca
AD		 1744static const char *thermal_controller_names[] = {
1745 "NONE",
678e7dfa
AD		 1746 "lm63",
1747 "adm1032",
1748 "adm1030",
1749 "max6649",
1750 "lm64",
1751 "f75375",
1752 "asc7xxx",
29fb52ca
AD		 1753};
1754
1755static const char *pp_lib_thermal_controller_names[] = {
1756 "NONE",
678e7dfa
AD		 1757 "lm63",
1758 "adm1032",
1759 "adm1030",
1760 "max6649",
1761 "lm64",
1762 "f75375",
29fb52ca
AD		 1763 "RV6xx",
1764 "RV770",
678e7dfa 1765 "adt7473",
560154e9 1766 "NONE",
49f65982
AD		 1767 "External GPIO",
1768 "Evergreen",
b0e66414
AD		 1769 "emc2103",
1770 "Sumo",
29fb52ca
AD		 1771};
1772
56278a8e
AD		 1773union power_info {
1774 struct _ATOM_POWERPLAY_INFO info;
1775 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1776 struct _ATOM_POWERPLAY_INFO_V3 info_3;
560154e9 1777 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
b0e66414
AD		 1778 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1779 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
56278a8e
AD		 1780};
1781
560154e9
AD		 1782union pplib_clock_info {
1783 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1784 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1785 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
b0e66414 1786 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
560154e9
AD		 1787};
1788
1789union pplib_power_state {
1790 struct _ATOM_PPLIB_STATE v1;
1791 struct _ATOM_PPLIB_STATE_V2 v2;
1792};
1793
1794static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1795 int state_index,
1796 u32 misc, u32 misc2)
1797{
1798 rdev->pm.power_state[state_index].misc = misc;
1799 rdev->pm.power_state[state_index].misc2 = misc2;
1800 /* order matters! */
1801 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1802 rdev->pm.power_state[state_index].type =
1803 POWER_STATE_TYPE_POWERSAVE;
1804 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1805 rdev->pm.power_state[state_index].type =
1806 POWER_STATE_TYPE_BATTERY;
1807 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1808 rdev->pm.power_state[state_index].type =
1809 POWER_STATE_TYPE_BATTERY;
1810 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1811 rdev->pm.power_state[state_index].type =
1812 POWER_STATE_TYPE_BALANCED;
1813 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1814 rdev->pm.power_state[state_index].type =
1815 POWER_STATE_TYPE_PERFORMANCE;
1816 rdev->pm.power_state[state_index].flags &=
1817 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1818 }
1819 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1820 rdev->pm.power_state[state_index].type =
1821 POWER_STATE_TYPE_BALANCED;
1822 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1823 rdev->pm.power_state[state_index].type =
1824 POWER_STATE_TYPE_DEFAULT;
1825 rdev->pm.default_power_state_index = state_index;
1826 rdev->pm.power_state[state_index].default_clock_mode =
1827 &rdev->pm.power_state[state_index].clock_info[0];
1828 } else if (state_index == 0) {
1829 rdev->pm.power_state[state_index].clock_info[0].flags |=
1830 RADEON_PM_MODE_NO_DISPLAY;
1831 }
1832}
1833
1834static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
771fe6b9 1835{
56278a8e 1836 struct radeon_mode_info *mode_info = &rdev->mode_info;
560154e9
AD		 1837 u32 misc, misc2 = 0;
1838 int num_modes = 0, i;
1839 int state_index = 0;
1840 struct radeon_i2c_bus_rec i2c_bus;
1841 union power_info *power_info;
56278a8e 1842 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
560154e9 1843 u16 data_offset;
56278a8e 1844 u8 frev, crev;
771fe6b9 1845
560154e9
AD		 1846 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1847 &frev, &crev, &data_offset))
1848 return state_index;
1849 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1850
1851 /* add the i2c bus for thermal/fan chip */
1852 if (power_info->info.ucOverdriveThermalController > 0) {
1853 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1854 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1855 power_info->info.ucOverdriveControllerAddress >> 1);
1856 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1857 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1858 if (rdev->pm.i2c_bus) {
1859 struct i2c_board_info info = { };
1860 const char *name = thermal_controller_names[power_info->info.
1861 ucOverdriveThermalController];
1862 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1863 strlcpy(info.type, name, sizeof(info.type));
1864 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1865 }
1866 }
1867 num_modes = power_info->info.ucNumOfPowerModeEntries;
1868 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1869 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1870 /* last mode is usually default, array is low to high */
1871 for (i = 0; i < num_modes; i++) {
1872 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1873 switch (frev) {
1874 case 1:
1875 rdev->pm.power_state[state_index].num_clock_modes = 1;
1876 rdev->pm.power_state[state_index].clock_info[0].mclk =
1877 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1878 rdev->pm.power_state[state_index].clock_info[0].sclk =
1879 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1880 /* skip invalid modes */
1881 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1882 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1883 continue;
1884 rdev->pm.power_state[state_index].pcie_lanes =
1885 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1886 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1887 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1888 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1889 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1890 VOLTAGE_GPIO;
1891 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1892 radeon_lookup_gpio(rdev,
1893 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1894 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1895 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1896 true;
1897 else
1898 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1899 false;
1900 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1901 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1902 VOLTAGE_VDDC;
1903 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1904 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
29fb52ca 1905 }
560154e9
AD		 1906 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1907 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
1908 state_index++;
1909 break;
1910 case 2:
1911 rdev->pm.power_state[state_index].num_clock_modes = 1;
1912 rdev->pm.power_state[state_index].clock_info[0].mclk =
1913 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1914 rdev->pm.power_state[state_index].clock_info[0].sclk =
1915 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1916 /* skip invalid modes */
1917 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1918 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1919 continue;
1920 rdev->pm.power_state[state_index].pcie_lanes =
1921 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1922 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1923 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1924 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1925 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1926 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1927 VOLTAGE_GPIO;
1928 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1929 radeon_lookup_gpio(rdev,
1930 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1931 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1932 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1933 true;
1934 else
1935 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1936 false;
1937 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1938 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1939 VOLTAGE_VDDC;
1940 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1941 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
56278a8e 1942 }
560154e9
AD		 1943 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1944 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
1945 state_index++;
1946 break;
1947 case 3:
1948 rdev->pm.power_state[state_index].num_clock_modes = 1;
1949 rdev->pm.power_state[state_index].clock_info[0].mclk =
1950 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1951 rdev->pm.power_state[state_index].clock_info[0].sclk =
1952 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1953 /* skip invalid modes */
1954 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1955 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1956 continue;
1957 rdev->pm.power_state[state_index].pcie_lanes =
1958 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1959 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1960 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1961 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1962 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1963 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1964 VOLTAGE_GPIO;
1965 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1966 radeon_lookup_gpio(rdev,
1967 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1968 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1969 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1970 true;
1971 else
1972 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1973 false;
1974 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1975 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1976 VOLTAGE_VDDC;
1977 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1978 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1979 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1980 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1981 true;
1982 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1983 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1984 }
02b17cc0 1985 }
560154e9
AD		 1986 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1987 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
1988 state_index++;
1989 break;
1990 }
1991 }
1992 /* last mode is usually default */
1993 if (rdev->pm.default_power_state_index == -1) {
1994 rdev->pm.power_state[state_index - 1].type =
1995 POWER_STATE_TYPE_DEFAULT;
1996 rdev->pm.default_power_state_index = state_index - 1;
1997 rdev->pm.power_state[state_index - 1].default_clock_mode =
1998 &rdev->pm.power_state[state_index - 1].clock_info[0];
1999 rdev->pm.power_state[state_index].flags &=
2000 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2001 rdev->pm.power_state[state_index].misc = 0;
2002 rdev->pm.power_state[state_index].misc2 = 0;
2003 }
2004 return state_index;
2005}
2006
2007static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2008 ATOM_PPLIB_THERMALCONTROLLER *controller)
2009{
2010 struct radeon_i2c_bus_rec i2c_bus;
2011
2012 /* add the i2c bus for thermal/fan chip */
2013 if (controller->ucType > 0) {
2014 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2015 DRM_INFO("Internal thermal controller %s fan control\n",
2016 (controller->ucFanParameters &
2017 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2018 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2019 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2020 DRM_INFO("Internal thermal controller %s fan control\n",
2021 (controller->ucFanParameters &
2022 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2023 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2024 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2025 DRM_INFO("Internal thermal controller %s fan control\n",
2026 (controller->ucFanParameters &
2027 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2028 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
b0e66414
AD		 2029 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2030 DRM_INFO("Internal thermal controller %s fan control\n",
2031 (controller->ucFanParameters &
2032 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2033 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
560154e9
AD		 2034 } else if ((controller->ucType ==
2035 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2036 (controller->ucType ==
b0e66414
AD		 2037 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2038 (controller->ucType ==
2039 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
560154e9 2040 DRM_INFO("Special thermal controller config\n");
49f65982 2041 } else {
560154e9
AD		 2042 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2043 pp_lib_thermal_controller_names[controller->ucType],
2044 controller->ucI2cAddress >> 1,
2045 (controller->ucFanParameters &
2046 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2047 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2048 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2049 if (rdev->pm.i2c_bus) {
2050 struct i2c_board_info info = { };
2051 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2052 info.addr = controller->ucI2cAddress >> 1;
2053 strlcpy(info.type, name, sizeof(info.type));
2054 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
c5e8ce61 2055 }
560154e9
AD		 2056 }
2057 }
2058}
c5e8ce61 2059
560154e9
AD		 2060static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
2061{
2062 struct radeon_mode_info *mode_info = &rdev->mode_info;
2063 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2064 u8 frev, crev;
2065 u16 data_offset;
2066 union firmware_info *firmware_info;
2067 u16 vddc = 0;
678e7dfa 2068
560154e9
AD		 2069 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2070 &frev, &crev, &data_offset)) {
2071 firmware_info =
2072 (union firmware_info *)(mode_info->atom_context->bios +
2073 data_offset);
2074 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2075 }
2076
2077 return vddc;
2078}
2079
2080static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2081 int state_index, int mode_index,
2082 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2083{
2084 int j;
2085 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2086 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2087 u16 vddc = radeon_atombios_get_default_vddc(rdev);
2088
2089 rdev->pm.power_state[state_index].misc = misc;
2090 rdev->pm.power_state[state_index].misc2 = misc2;
2091 rdev->pm.power_state[state_index].pcie_lanes =
2092 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2093 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2094 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2095 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2096 rdev->pm.power_state[state_index].type =
2097 POWER_STATE_TYPE_BATTERY;
2098 break;
2099 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2100 rdev->pm.power_state[state_index].type =
2101 POWER_STATE_TYPE_BALANCED;
2102 break;
2103 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2104 rdev->pm.power_state[state_index].type =
2105 POWER_STATE_TYPE_PERFORMANCE;
2106 break;
2107 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2108 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2109 rdev->pm.power_state[state_index].type =
2110 POWER_STATE_TYPE_PERFORMANCE;
2111 break;
2112 }
2113 rdev->pm.power_state[state_index].flags = 0;
2114 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2115 rdev->pm.power_state[state_index].flags |=
2116 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2117 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2118 rdev->pm.power_state[state_index].type =
2119 POWER_STATE_TYPE_DEFAULT;
2120 rdev->pm.default_power_state_index = state_index;
2121 rdev->pm.power_state[state_index].default_clock_mode =
2122 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2123 /* patch the table values with the default slck/mclk from firmware info */
2124 for (j = 0; j < mode_index; j++) {
2125 rdev->pm.power_state[state_index].clock_info[j].mclk =
2126 rdev->clock.default_mclk;
2127 rdev->pm.power_state[state_index].clock_info[j].sclk =
2128 rdev->clock.default_sclk;
2129 if (vddc)
2130 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2131 vddc;
2132 }
2133 }
2134}
2135
2136static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2137 int state_index, int mode_index,
2138 union pplib_clock_info *clock_info)
2139{
2140 u32 sclk, mclk;
2141
2142 if (rdev->flags & RADEON_IS_IGP) {
b0e66414
AD		 2143 if (rdev->family >= CHIP_PALM) {
2144 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2145 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2146 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2147 } else {
2148 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2149 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2150 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2151 }
560154e9
AD		 2152 } else if (ASIC_IS_DCE4(rdev)) {
2153 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2154 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2155 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2156 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2157 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2158 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2159 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2160 VOLTAGE_SW;
2161 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2162 clock_info->evergreen.usVDDC;
2163 } else {
2164 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2165 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2166 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2167 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2168 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2169 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2170 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2171 VOLTAGE_SW;
2172 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2173 clock_info->r600.usVDDC;
2174 }
2175
2176 if (rdev->flags & RADEON_IS_IGP) {
2177 /* skip invalid modes */
2178 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2179 return false;
2180 } else {
2181 /* skip invalid modes */
2182 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2183 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2184 return false;
2185 }
2186 return true;
2187}
2188
2189static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2190{
2191 struct radeon_mode_info *mode_info = &rdev->mode_info;
2192 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2193 union pplib_power_state *power_state;
2194 int i, j;
2195 int state_index = 0, mode_index = 0;
2196 union pplib_clock_info *clock_info;
2197 bool valid;
2198 union power_info *power_info;
2199 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2200 u16 data_offset;
2201 u8 frev, crev;
2202
2203 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2204 &frev, &crev, &data_offset))
2205 return state_index;
2206 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2207
2208 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2209 /* first mode is usually default, followed by low to high */
2210 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2211 mode_index = 0;
2212 power_state = (union pplib_power_state *)
2213 (mode_info->atom_context->bios + data_offset +
2214 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2215 i * power_info->pplib.ucStateEntrySize);
2216 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2217 (mode_info->atom_context->bios + data_offset +
2218 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2219 (power_state->v1.ucNonClockStateIndex *
2220 power_info->pplib.ucNonClockSize));
2221 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2222 clock_info = (union pplib_clock_info *)
2223 (mode_info->atom_context->bios + data_offset +
2224 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2225 (power_state->v1.ucClockStateIndices[j] *
2226 power_info->pplib.ucClockInfoSize));
2227 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2228 state_index, mode_index,
2229 clock_info);
2230 if (valid)
2231 mode_index++;
2232 }
2233 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2234 if (mode_index) {
2235 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2236 non_clock_info);
2237 state_index++;
2238 }
2239 }
2240 /* if multiple clock modes, mark the lowest as no display */
2241 for (i = 0; i < state_index; i++) {
2242 if (rdev->pm.power_state[i].num_clock_modes > 1)
2243 rdev->pm.power_state[i].clock_info[0].flags |=
2244 RADEON_PM_MODE_NO_DISPLAY;
2245 }
2246 /* first mode is usually default */
2247 if (rdev->pm.default_power_state_index == -1) {
2248 rdev->pm.power_state[0].type =
2249 POWER_STATE_TYPE_DEFAULT;
2250 rdev->pm.default_power_state_index = 0;
2251 rdev->pm.power_state[0].default_clock_mode =
2252 &rdev->pm.power_state[0].clock_info[0];
2253 }
2254 return state_index;
2255}
2256
b0e66414
AD		 2257static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2258{
2259 struct radeon_mode_info *mode_info = &rdev->mode_info;
2260 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2261 union pplib_power_state *power_state;
2262 int i, j, non_clock_array_index, clock_array_index;
2263 int state_index = 0, mode_index = 0;
2264 union pplib_clock_info *clock_info;
2265 struct StateArray *state_array;
2266 struct ClockInfoArray *clock_info_array;
2267 struct NonClockInfoArray *non_clock_info_array;
2268 bool valid;
2269 union power_info *power_info;
2270 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2271 u16 data_offset;
2272 u8 frev, crev;
2273
2274 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2275 &frev, &crev, &data_offset))
2276 return state_index;
2277 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2278
2279 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2280 state_array = (struct StateArray *)
2281 (mode_info->atom_context->bios + data_offset +
2282 power_info->pplib.usStateArrayOffset);
2283 clock_info_array = (struct ClockInfoArray *)
2284 (mode_info->atom_context->bios + data_offset +
2285 power_info->pplib.usClockInfoArrayOffset);
2286 non_clock_info_array = (struct NonClockInfoArray *)
2287 (mode_info->atom_context->bios + data_offset +
2288 power_info->pplib.usNonClockInfoArrayOffset);
2289 for (i = 0; i < state_array->ucNumEntries; i++) {
2290 mode_index = 0;
2291 power_state = (union pplib_power_state *)&state_array->states[i];
2292 /* XXX this might be an inagua bug... */
2293 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2294 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2295 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2296 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2297 clock_array_index = power_state->v2.clockInfoIndex[j];
2298 /* XXX this might be an inagua bug... */
2299 if (clock_array_index >= clock_info_array->ucNumEntries)
2300 continue;
2301 clock_info = (union pplib_clock_info *)
2302 &clock_info_array->clockInfo[clock_array_index];
2303 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2304 state_index, mode_index,
2305 clock_info);
2306 if (valid)
2307 mode_index++;
2308 }
2309 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2310 if (mode_index) {
2311 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2312 non_clock_info);
2313 state_index++;
2314 }
2315 }
2316 /* if multiple clock modes, mark the lowest as no display */
2317 for (i = 0; i < state_index; i++) {
2318 if (rdev->pm.power_state[i].num_clock_modes > 1)
2319 rdev->pm.power_state[i].clock_info[0].flags |=
2320 RADEON_PM_MODE_NO_DISPLAY;
2321 }
2322 /* first mode is usually default */
2323 if (rdev->pm.default_power_state_index == -1) {
2324 rdev->pm.power_state[0].type =
2325 POWER_STATE_TYPE_DEFAULT;
2326 rdev->pm.default_power_state_index = 0;
2327 rdev->pm.power_state[0].default_clock_mode =
2328 &rdev->pm.power_state[0].clock_info[0];
2329 }
2330 return state_index;
2331}
2332
560154e9
AD		 2333void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2334{
2335 struct radeon_mode_info *mode_info = &rdev->mode_info;
2336 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2337 u16 data_offset;
2338 u8 frev, crev;
2339 int state_index = 0;
2340
2341 rdev->pm.default_power_state_index = -1;
2342
2343 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2344 &frev, &crev, &data_offset)) {
2345 switch (frev) {
2346 case 1:
2347 case 2:
2348 case 3:
2349 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2350 break;
2351 case 4:
2352 case 5:
2353 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2354 break;
b0e66414
AD		 2355 case 6:
2356 state_index = radeon_atombios_parse_power_table_6(rdev);
2357 break;
560154e9
AD		 2358 default:
2359 break;
56278a8e
AD		 2360 }
2361 } else {
56278a8e 2362 /* add the default mode */
0ec0e74f
AD		 2363 rdev->pm.power_state[state_index].type =
2364 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2365 rdev->pm.power_state[state_index].num_clock_modes = 1;
2366 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2367 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2368 rdev->pm.power_state[state_index].default_clock_mode =
2369 &rdev->pm.power_state[state_index].clock_info[0];
56278a8e 2370 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2371 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2372 rdev->pm.default_power_state_index = state_index;
2373 rdev->pm.power_state[state_index].flags = 0;
56278a8e
AD		 2374 state_index++;
2375 }
02b17cc0 2376
56278a8e 2377 rdev->pm.num_power_states = state_index;
9038dfdf 2378
a48b9b4e
AD		 2379 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2380 rdev->pm.current_clock_mode_index = 0;
4d60173f 2381 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
771fe6b9
JG		 2382}
2383
771fe6b9 2384void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
771fe6b9 2385{
771fe6b9
JG		 2386 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2387 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
771fe6b9
JG		 2388
2389 args.ucEnable = enable;
2390
2391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2392}
2393
7433874e
RM		 2394uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2395{
2396 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2397 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2398
2399 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2400 return args.ulReturnEngineClock;
2401}
2402
2403uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2404{
2405 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2406 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2407
2408 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2409 return args.ulReturnMemoryClock;
2410}
2411
771fe6b9
JG		 2412void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2413 uint32_t eng_clock)
2414{
2415 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2416 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2417
2418 args.ulTargetEngineClock = eng_clock; /* 10 khz */
2419
2420 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2421}
2422
2423void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2424 uint32_t mem_clock)
2425{
2426 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2427 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2428
2429 if (rdev->flags & RADEON_IS_IGP)
2430 return;
2431
2432 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
2433
2434 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2435}
2436
7ac9aa5a
AD		 2437union set_voltage {
2438 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2439 struct _SET_VOLTAGE_PARAMETERS v1;
2440 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2441};
2442
2443void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2444{
2445 union set_voltage args;
2446 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2447 u8 frev, crev, volt_index = level;
2448
2449 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2450 return;
2451
2452 switch (crev) {
2453 case 1:
2454 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2455 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2456 args.v1.ucVoltageIndex = volt_index;
2457 break;
2458 case 2:
2459 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2460 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2461 args.v2.usVoltageLevel = cpu_to_le16(level);
2462 break;
2463 default:
2464 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2465 return;
2466 }
2467
2468 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2469}
2470
2471
2472
771fe6b9
JG		 2473void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2474{
2475 struct radeon_device *rdev = dev->dev_private;
2476 uint32_t bios_2_scratch, bios_6_scratch;
2477
2478 if (rdev->family >= CHIP_R600) {
4ce001ab 2479 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
771fe6b9
JG		 2480 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2481 } else {
4ce001ab 2482 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
771fe6b9
JG		 2483 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2484 }
2485
2486 /* let the bios control the backlight */
2487 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2488
2489 /* tell the bios not to handle mode switching */
2490 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2491
2492 if (rdev->family >= CHIP_R600) {
2493 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2494 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2495 } else {
2496 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2497 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2498 }
2499
2500}
2501
f657c2a7
YZ		 2502void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2503{
2504 uint32_t scratch_reg;
2505 int i;
2506
2507 if (rdev->family >= CHIP_R600)
2508 scratch_reg = R600_BIOS_0_SCRATCH;
2509 else
2510 scratch_reg = RADEON_BIOS_0_SCRATCH;
2511
2512 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2513 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2514}
2515
2516void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2517{
2518 uint32_t scratch_reg;
2519 int i;
2520
2521 if (rdev->family >= CHIP_R600)
2522 scratch_reg = R600_BIOS_0_SCRATCH;
2523 else
2524 scratch_reg = RADEON_BIOS_0_SCRATCH;
2525
2526 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2527 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2528}
2529
771fe6b9
JG		 2530void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2531{
2532 struct drm_device *dev = encoder->dev;
2533 struct radeon_device *rdev = dev->dev_private;
2534 uint32_t bios_6_scratch;
2535
2536 if (rdev->family >= CHIP_R600)
2537 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2538 else
2539 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2540
2541 if (lock)
2542 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2543 else
2544 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2545
2546 if (rdev->family >= CHIP_R600)
2547 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2548 else
2549 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2550}
2551
2552/* at some point we may want to break this out into individual functions */
2553void
2554radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2555 struct drm_encoder *encoder,
2556 bool connected)
2557{
2558 struct drm_device *dev = connector->dev;
2559 struct radeon_device *rdev = dev->dev_private;
2560 struct radeon_connector *radeon_connector =
2561 to_radeon_connector(connector);
2562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2563 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2564
2565 if (rdev->family >= CHIP_R600) {
2566 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2567 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2568 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2569 } else {
2570 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2571 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2572 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2573 }
2574
2575 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2576 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2577 if (connected) {
d9fdaafb 2578 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 2579 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2580 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2581 } else {
d9fdaafb 2582 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 2583 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2584 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2585 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2586 }
2587 }
2588 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2589 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2590 if (connected) {
d9fdaafb 2591 DRM_DEBUG_KMS("CV connected\n");
771fe6b9
JG		 2592 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2593 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2594 } else {
d9fdaafb 2595 DRM_DEBUG_KMS("CV disconnected\n");
771fe6b9
JG		 2596 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2597 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2598 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2599 }
2600 }
2601 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2602 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2603 if (connected) {
d9fdaafb 2604 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 2605 bios_0_scratch |= ATOM_S0_LCD1;
2606 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2607 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2608 } else {
d9fdaafb 2609 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 2610 bios_0_scratch &= ~ATOM_S0_LCD1;
2611 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2612 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2613 }
2614 }
2615 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2616 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2617 if (connected) {
d9fdaafb 2618 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 2619 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2620 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2621 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2622 } else {
d9fdaafb 2623 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 2624 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2625 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2626 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2627 }
2628 }
2629 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2630 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2631 if (connected) {
d9fdaafb 2632 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 2633 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2634 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2635 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2636 } else {
d9fdaafb 2637 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 2638 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2639 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2640 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2641 }
2642 }
2643 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2644 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2645 if (connected) {
d9fdaafb 2646 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 2647 bios_0_scratch |= ATOM_S0_DFP1;
2648 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2649 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2650 } else {
d9fdaafb 2651 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 2652 bios_0_scratch &= ~ATOM_S0_DFP1;
2653 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2654 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2655 }
2656 }
2657 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2658 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2659 if (connected) {
d9fdaafb 2660 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 2661 bios_0_scratch |= ATOM_S0_DFP2;
2662 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2663 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2664 } else {
d9fdaafb 2665 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 2666 bios_0_scratch &= ~ATOM_S0_DFP2;
2667 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2668 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2669 }
2670 }
2671 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2672 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2673 if (connected) {
d9fdaafb 2674 DRM_DEBUG_KMS("DFP3 connected\n");
771fe6b9
JG		 2675 bios_0_scratch |= ATOM_S0_DFP3;
2676 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2677 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2678 } else {
d9fdaafb 2679 DRM_DEBUG_KMS("DFP3 disconnected\n");
771fe6b9
JG		 2680 bios_0_scratch &= ~ATOM_S0_DFP3;
2681 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2682 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2683 }
2684 }
2685 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2686 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2687 if (connected) {
d9fdaafb 2688 DRM_DEBUG_KMS("DFP4 connected\n");
771fe6b9
JG		 2689 bios_0_scratch |= ATOM_S0_DFP4;
2690 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2691 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2692 } else {
d9fdaafb 2693 DRM_DEBUG_KMS("DFP4 disconnected\n");
771fe6b9
JG		 2694 bios_0_scratch &= ~ATOM_S0_DFP4;
2695 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2696 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2697 }
2698 }
2699 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2700 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2701 if (connected) {
d9fdaafb 2702 DRM_DEBUG_KMS("DFP5 connected\n");
771fe6b9
JG		 2703 bios_0_scratch |= ATOM_S0_DFP5;
2704 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2705 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2706 } else {
d9fdaafb 2707 DRM_DEBUG_KMS("DFP5 disconnected\n");
771fe6b9
JG		 2708 bios_0_scratch &= ~ATOM_S0_DFP5;
2709 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2710 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2711 }
2712 }
2713
2714 if (rdev->family >= CHIP_R600) {
2715 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2716 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2717 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2718 } else {
2719 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2720 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2721 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2722 }
2723}
2724
2725void
2726radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2727{
2728 struct drm_device *dev = encoder->dev;
2729 struct radeon_device *rdev = dev->dev_private;
2730 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2731 uint32_t bios_3_scratch;
2732
2733 if (rdev->family >= CHIP_R600)
2734 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2735 else
2736 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2737
2738 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2739 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2740 bios_3_scratch |= (crtc << 18);
2741 }
2742 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2743 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2744 bios_3_scratch |= (crtc << 24);
2745 }
2746 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2747 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2748 bios_3_scratch |= (crtc << 16);
2749 }
2750 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2751 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2752 bios_3_scratch |= (crtc << 20);
2753 }
2754 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2755 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2756 bios_3_scratch |= (crtc << 17);
2757 }
2758 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2759 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2760 bios_3_scratch |= (crtc << 19);
2761 }
2762 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2763 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2764 bios_3_scratch |= (crtc << 23);
2765 }
2766 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2767 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2768 bios_3_scratch |= (crtc << 25);
2769 }
2770
2771 if (rdev->family >= CHIP_R600)
2772 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2773 else
2774 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2775}
2776
2777void
2778radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2779{
2780 struct drm_device *dev = encoder->dev;
2781 struct radeon_device *rdev = dev->dev_private;
2782 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2783 uint32_t bios_2_scratch;
2784
2785 if (rdev->family >= CHIP_R600)
2786 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2787 else
2788 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2789
2790 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2791 if (on)
2792 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2793 else
2794 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2795 }
2796 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2797 if (on)
2798 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2799 else
2800 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2801 }
2802 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2803 if (on)
2804 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2805 else
2806 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2807 }
2808 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2809 if (on)
2810 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2811 else
2812 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2813 }
2814 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2815 if (on)
2816 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2817 else
2818 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2819 }
2820 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2821 if (on)
2822 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2823 else
2824 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2825 }
2826 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2827 if (on)
2828 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2829 else
2830 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2831 }
2832 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2833 if (on)
2834 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2835 else
2836 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2837 }
2838 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2839 if (on)
2840 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2841 else
2842 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2843 }
2844 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2845 if (on)
2846 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2847 else
2848 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2849 }
2850
2851 if (rdev->family >= CHIP_R600)
2852 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2853 else
2854 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2855}
kernel source for telekom puls (alcatel/mediatek)