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drm/radeon/kms/atom: add support for spread spectrum (v2)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
d39c3b89
JG		 47/* Initialization path:
48 * We expect that acceleration initialization might fail for various
49 * reasons even thought we work hard to make it works on most
50 * configurations. In order to still have a working userspace in such
51 * situation the init path must succeed up to the memory controller
52 * initialization point. Failure before this point are considered as
53 * fatal error. Here is the init callchain :
54 * radeon_device_init perform common structure, mutex initialization
55 * asic_init setup the GPU memory layout and perform all
56 * one time initialization (failure in this
57 * function are considered fatal)
58 * asic_startup setup the GPU acceleration, in order to
59 * follow guideline the first thing this
60 * function should do is setting the GPU
61 * memory controller (only MC setup failure
62 * are considered as fatal)
63 */
64
771fe6b9
JG		 65#include <asm/atomic.h>
66#include <linux/wait.h>
67#include <linux/list.h>
68#include <linux/kref.h>
69
c2142715 70#include "radeon_family.h"
771fe6b9
JG		 71#include "radeon_mode.h"
72#include "radeon_reg.h"
771fe6b9
JG		 73
74/*
75 * Modules parameters.
76 */
77extern int radeon_no_wb;
78extern int radeon_modeset;
79extern int radeon_dynclks;
80extern int radeon_r4xx_atom;
81extern int radeon_agpmode;
82extern int radeon_vram_limit;
83extern int radeon_gart_size;
84extern int radeon_benchmarking;
ecc0b326 85extern int radeon_testing;
771fe6b9 86extern int radeon_connector_table;
4ce001ab 87extern int radeon_tv;
771fe6b9
JG		 88
89/*
90 * Copy from radeon_drv.h so we don't have to include both and have conflicting
91 * symbol;
92 */
93#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
94#define RADEON_IB_POOL_SIZE 16
95#define RADEON_DEBUGFS_MAX_NUM_FILES 32
96#define RADEONFB_CONN_LIMIT 4
f657c2a7 97#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 98
771fe6b9
JG		 99/*
100 * Errata workarounds.
101 */
102enum radeon_pll_errata {
103 CHIP_ERRATA_R300_CG = 0x00000001,
104 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
105 CHIP_ERRATA_PLL_DELAY = 0x00000004
106};
107
108
109struct radeon_device;
110
111
112/*
113 * BIOS.
114 */
115bool radeon_get_bios(struct radeon_device *rdev);
116
3ce0a23d 117
771fe6b9 118/*
3ce0a23d 119 * Dummy page
771fe6b9 120 */
3ce0a23d
JG		 121struct radeon_dummy_page {
122 struct page *page;
123 dma_addr_t addr;
124};
125int radeon_dummy_page_init(struct radeon_device *rdev);
126void radeon_dummy_page_fini(struct radeon_device *rdev);
127
771fe6b9 128
3ce0a23d
JG		 129/*
130 * Clocks
131 */
771fe6b9
JG		 132struct radeon_clock {
133 struct radeon_pll p1pll;
134 struct radeon_pll p2pll;
135 struct radeon_pll spll;
136 struct radeon_pll mpll;
137 /* 10 Khz units */
138 uint32_t default_mclk;
139 uint32_t default_sclk;
140};
141
3ce0a23d 142
771fe6b9
JG		 143/*
144 * Fences.
145 */
146struct radeon_fence_driver {
147 uint32_t scratch_reg;
148 atomic_t seq;
149 uint32_t last_seq;
150 unsigned long count_timeout;
151 wait_queue_head_t queue;
152 rwlock_t lock;
153 struct list_head created;
154 struct list_head emited;
155 struct list_head signaled;
156};
157
158struct radeon_fence {
159 struct radeon_device *rdev;
160 struct kref kref;
161 struct list_head list;
162 /* protected by radeon_fence.lock */
163 uint32_t seq;
164 unsigned long timeout;
165 bool emited;
166 bool signaled;
167};
168
169int radeon_fence_driver_init(struct radeon_device *rdev);
170void radeon_fence_driver_fini(struct radeon_device *rdev);
171int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
172int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
173void radeon_fence_process(struct radeon_device *rdev);
174bool radeon_fence_signaled(struct radeon_fence *fence);
175int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
176int radeon_fence_wait_next(struct radeon_device *rdev);
177int radeon_fence_wait_last(struct radeon_device *rdev);
178struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
179void radeon_fence_unref(struct radeon_fence **fence);
180
e024e110
DA		 181/*
182 * Tiling registers
183 */
184struct radeon_surface_reg {
185 struct radeon_object *robj;
186};
187
188#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 189
190/*
191 * Radeon buffer.
192 */
193struct radeon_object;
194
195struct radeon_object_list {
196 struct list_head list;
197 struct radeon_object *robj;
198 uint64_t gpu_offset;
199 unsigned rdomain;
200 unsigned wdomain;
e024e110 201 uint32_t tiling_flags;
771fe6b9
JG		 202};
203
204int radeon_object_init(struct radeon_device *rdev);
205void radeon_object_fini(struct radeon_device *rdev);
206int radeon_object_create(struct radeon_device *rdev,
207 struct drm_gem_object *gobj,
208 unsigned long size,
209 bool kernel,
210 uint32_t domain,
211 bool interruptible,
212 struct radeon_object **robj_ptr);
213int radeon_object_kmap(struct radeon_object *robj, void **ptr);
214void radeon_object_kunmap(struct radeon_object *robj);
215void radeon_object_unref(struct radeon_object **robj);
216int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
217 uint64_t *gpu_addr);
218void radeon_object_unpin(struct radeon_object *robj);
219int radeon_object_wait(struct radeon_object *robj);
cefb87ef 220int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
771fe6b9
JG		 221int radeon_object_evict_vram(struct radeon_device *rdev);
222int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
223void radeon_object_force_delete(struct radeon_device *rdev);
224void radeon_object_list_add_object(struct radeon_object_list *lobj,
225 struct list_head *head);
226int radeon_object_list_validate(struct list_head *head, void *fence);
227void radeon_object_list_unvalidate(struct list_head *head);
228void radeon_object_list_clean(struct list_head *head);
229int radeon_object_fbdev_mmap(struct radeon_object *robj,
230 struct vm_area_struct *vma);
231unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 232void radeon_object_clear_surface_reg(struct radeon_object *robj);
233int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
234 bool force_drop);
235void radeon_object_set_tiling_flags(struct radeon_object *robj,
236 uint32_t tiling_flags, uint32_t pitch);
237void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
238void radeon_bo_move_notify(struct ttm_buffer_object *bo,
239 struct ttm_mem_reg *mem);
240void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 241/*
242 * GEM objects.
243 */
244struct radeon_gem {
245 struct list_head objects;
246};
247
248int radeon_gem_init(struct radeon_device *rdev);
249void radeon_gem_fini(struct radeon_device *rdev);
250int radeon_gem_object_create(struct radeon_device *rdev, int size,
251 int alignment, int initial_domain,
252 bool discardable, bool kernel,
253 bool interruptible,
254 struct drm_gem_object **obj);
255int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
256 uint64_t *gpu_addr);
257void radeon_gem_object_unpin(struct drm_gem_object *obj);
258
259
260/*
261 * GART structures, functions & helpers
262 */
263struct radeon_mc;
264
265struct radeon_gart_table_ram {
266 volatile uint32_t *ptr;
267};
268
269struct radeon_gart_table_vram {
270 struct radeon_object *robj;
271 volatile uint32_t *ptr;
272};
273
274union radeon_gart_table {
275 struct radeon_gart_table_ram ram;
276 struct radeon_gart_table_vram vram;
277};
278
a77f1718
MT		 279#define RADEON_GPU_PAGE_SIZE 4096
280
771fe6b9
JG		 281struct radeon_gart {
282 dma_addr_t table_addr;
283 unsigned num_gpu_pages;
284 unsigned num_cpu_pages;
285 unsigned table_size;
286 union radeon_gart_table table;
287 struct page **pages;
288 dma_addr_t *pages_addr;
289 bool ready;
290};
291
292int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
293void radeon_gart_table_ram_free(struct radeon_device *rdev);
294int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
295void radeon_gart_table_vram_free(struct radeon_device *rdev);
296int radeon_gart_init(struct radeon_device *rdev);
297void radeon_gart_fini(struct radeon_device *rdev);
298void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
299 int pages);
300int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
301 int pages, struct page **pagelist);
302
303
304/*
305 * GPU MC structures, functions & helpers
306 */
307struct radeon_mc {
308 resource_size_t aper_size;
309 resource_size_t aper_base;
310 resource_size_t agp_base;
7a50f01a
DA		 311 /* for some chips with <= 32MB we need to lie
312 * about vram size near mc fb location */
3ce0a23d
JG		 313 u64 mc_vram_size;
314 u64 gtt_location;
315 u64 gtt_size;
316 u64 gtt_start;
317 u64 gtt_end;
318 u64 vram_location;
319 u64 vram_start;
320 u64 vram_end;
771fe6b9 321 unsigned vram_width;
3ce0a23d 322 u64 real_vram_size;
771fe6b9
JG		 323 int vram_mtrr;
324 bool vram_is_ddr;
325};
326
327int radeon_mc_setup(struct radeon_device *rdev);
328
329
330/*
331 * GPU scratch registers structures, functions & helpers
332 */
333struct radeon_scratch {
334 unsigned num_reg;
335 bool free[32];
336 uint32_t reg[32];
337};
338
339int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
340void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
341
342
343/*
344 * IRQS.
345 */
346struct radeon_irq {
347 bool installed;
348 bool sw_int;
349 /* FIXME: use a define max crtc rather than hardcode it */
350 bool crtc_vblank_int[2];
351};
352
353int radeon_irq_kms_init(struct radeon_device *rdev);
354void radeon_irq_kms_fini(struct radeon_device *rdev);
355
356
357/*
358 * CP & ring.
359 */
360struct radeon_ib {
361 struct list_head list;
362 unsigned long idx;
363 uint64_t gpu_addr;
364 struct radeon_fence *fence;
513bcb46 365 uint32_t *ptr;
771fe6b9
JG		 366 uint32_t length_dw;
367};
368
ecb114a1
DA		 369/*
370 * locking -
371 * mutex protects scheduled_ibs, ready, alloc_bm
372 */
771fe6b9
JG		 373struct radeon_ib_pool {
374 struct mutex mutex;
375 struct radeon_object *robj;
376 struct list_head scheduled_ibs;
377 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
378 bool ready;
379 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
380};
381
382struct radeon_cp {
383 struct radeon_object *ring_obj;
384 volatile uint32_t *ring;
385 unsigned rptr;
386 unsigned wptr;
387 unsigned wptr_old;
388 unsigned ring_size;
389 unsigned ring_free_dw;
390 int count_dw;
391 uint64_t gpu_addr;
392 uint32_t align_mask;
393 uint32_t ptr_mask;
394 struct mutex mutex;
395 bool ready;
396};
397
3ce0a23d
JG		 398struct r600_blit {
399 struct radeon_object *shader_obj;
400 u64 shader_gpu_addr;
401 u32 vs_offset, ps_offset;
402 u32 state_offset;
403 u32 state_len;
404 u32 vb_used, vb_total;
405 struct radeon_ib *vb_ib;
406};
407
771fe6b9
JG		 408int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
409void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
410int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
411int radeon_ib_pool_init(struct radeon_device *rdev);
412void radeon_ib_pool_fini(struct radeon_device *rdev);
413int radeon_ib_test(struct radeon_device *rdev);
414/* Ring access between begin & end cannot sleep */
415void radeon_ring_free_size(struct radeon_device *rdev);
416int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
417void radeon_ring_unlock_commit(struct radeon_device *rdev);
418void radeon_ring_unlock_undo(struct radeon_device *rdev);
419int radeon_ring_test(struct radeon_device *rdev);
420int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
421void radeon_ring_fini(struct radeon_device *rdev);
422
423
424/*
425 * CS.
426 */
427struct radeon_cs_reloc {
428 struct drm_gem_object *gobj;
429 struct radeon_object *robj;
430 struct radeon_object_list lobj;
431 uint32_t handle;
432 uint32_t flags;
433};
434
435struct radeon_cs_chunk {
436 uint32_t chunk_id;
437 uint32_t length_dw;
513bcb46
DA		 438 int kpage_idx[2];
439 uint32_t *kpage[2];
771fe6b9 440 uint32_t *kdata;
513bcb46
DA		 441 void __user *user_ptr;
442 int last_copied_page;
443 int last_page_index;
771fe6b9
JG		 444};
445
446struct radeon_cs_parser {
447 struct radeon_device *rdev;
448 struct drm_file *filp;
449 /* chunks */
450 unsigned nchunks;
451 struct radeon_cs_chunk *chunks;
452 uint64_t *chunks_array;
453 /* IB */
454 unsigned idx;
455 /* relocations */
456 unsigned nrelocs;
457 struct radeon_cs_reloc *relocs;
458 struct radeon_cs_reloc **relocs_ptr;
459 struct list_head validated;
460 /* indices of various chunks */
461 int chunk_ib_idx;
462 int chunk_relocs_idx;
463 struct radeon_ib *ib;
464 void *track;
3ce0a23d 465 unsigned family;
513bcb46 466 int parser_error;
771fe6b9
JG		 467};
468
513bcb46
DA		 469extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
470extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
471
472
473static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
474{
475 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
476 u32 pg_idx, pg_offset;
477 u32 idx_value = 0;
478 int new_page;
479
480 pg_idx = (idx * 4) / PAGE_SIZE;
481 pg_offset = (idx * 4) % PAGE_SIZE;
482
483 if (ibc->kpage_idx[0] == pg_idx)
484 return ibc->kpage[0][pg_offset/4];
485 if (ibc->kpage_idx[1] == pg_idx)
486 return ibc->kpage[1][pg_offset/4];
487
488 new_page = radeon_cs_update_pages(p, pg_idx);
489 if (new_page < 0) {
490 p->parser_error = new_page;
491 return 0;
492 }
493
494 idx_value = ibc->kpage[new_page][pg_offset/4];
495 return idx_value;
496}
497
771fe6b9
JG		 498struct radeon_cs_packet {
499 unsigned idx;
500 unsigned type;
501 unsigned reg;
502 unsigned opcode;
503 int count;
504 unsigned one_reg_wr;
505};
506
507typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
508 struct radeon_cs_packet *pkt,
509 unsigned idx, unsigned reg);
510typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
511 struct radeon_cs_packet *pkt);
512
513
514/*
515 * AGP
516 */
517int radeon_agp_init(struct radeon_device *rdev);
518void radeon_agp_fini(struct radeon_device *rdev);
519
520
521/*
522 * Writeback
523 */
524struct radeon_wb {
525 struct radeon_object *wb_obj;
526 volatile uint32_t *wb;
527 uint64_t gpu_addr;
528};
529
c93bb85b
JG		 530/**
531 * struct radeon_pm - power management datas
532 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
533 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
534 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
535 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
536 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
537 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
538 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
539 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
540 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
541 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
542 * @needed_bandwidth: current bandwidth needs
543 *
544 * It keeps track of various data needed to take powermanagement decision.
545 * Bandwith need is used to determine minimun clock of the GPU and memory.
546 * Equation between gpu/memory clock and available bandwidth is hw dependent
547 * (type of memory, bus size, efficiency, ...)
548 */
549struct radeon_pm {
550 fixed20_12 max_bandwidth;
551 fixed20_12 igp_sideport_mclk;
552 fixed20_12 igp_system_mclk;
553 fixed20_12 igp_ht_link_clk;
554 fixed20_12 igp_ht_link_width;
555 fixed20_12 k8_bandwidth;
556 fixed20_12 sideport_bandwidth;
557 fixed20_12 ht_bandwidth;
558 fixed20_12 core_bandwidth;
559 fixed20_12 sclk;
560 fixed20_12 needed_bandwidth;
561};
562
771fe6b9
JG		 563
564/*
565 * Benchmarking
566 */
567void radeon_benchmark(struct radeon_device *rdev);
568
569
ecc0b326
MD		 570/*
571 * Testing
572 */
573void radeon_test_moves(struct radeon_device *rdev);
574
575
771fe6b9
JG		 576/*
577 * Debugfs
578 */
579int radeon_debugfs_add_files(struct radeon_device *rdev,
580 struct drm_info_list *files,
581 unsigned nfiles);
582int radeon_debugfs_fence_init(struct radeon_device *rdev);
583int r100_debugfs_rbbm_init(struct radeon_device *rdev);
584int r100_debugfs_cp_init(struct radeon_device *rdev);
585
586
587/*
588 * ASIC specific functions.
589 */
590struct radeon_asic {
068a117c 591 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 592 void (*fini)(struct radeon_device *rdev);
593 int (*resume)(struct radeon_device *rdev);
594 int (*suspend)(struct radeon_device *rdev);
771fe6b9 595 int (*gpu_reset)(struct radeon_device *rdev);
771fe6b9
JG		 596 void (*gart_tlb_flush)(struct radeon_device *rdev);
597 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
598 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
599 void (*cp_fini)(struct radeon_device *rdev);
600 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 601 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 602 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 603 int (*ring_test)(struct radeon_device *rdev);
604 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 605 int (*irq_set)(struct radeon_device *rdev);
606 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 607 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 608 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
609 int (*cs_parse)(struct radeon_cs_parser *p);
610 int (*copy_blit)(struct radeon_device *rdev,
611 uint64_t src_offset,
612 uint64_t dst_offset,
613 unsigned num_pages,
614 struct radeon_fence *fence);
615 int (*copy_dma)(struct radeon_device *rdev,
616 uint64_t src_offset,
617 uint64_t dst_offset,
618 unsigned num_pages,
619 struct radeon_fence *fence);
620 int (*copy)(struct radeon_device *rdev,
621 uint64_t src_offset,
622 uint64_t dst_offset,
623 unsigned num_pages,
624 struct radeon_fence *fence);
625 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
626 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
627 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
628 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 629 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
630 uint32_t tiling_flags, uint32_t pitch,
631 uint32_t offset, uint32_t obj_size);
632 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 633 void (*bandwidth_update)(struct radeon_device *rdev);
771fe6b9
JG		 634};
635
21f9a437
JG		 636/*
637 * Asic structures
638 */
551ebd83
DA		 639struct r100_asic {
640 const unsigned *reg_safe_bm;
641 unsigned reg_safe_bm_size;
642};
643
21f9a437
JG		 644struct r300_asic {
645 const unsigned *reg_safe_bm;
646 unsigned reg_safe_bm_size;
647};
648
649struct r600_asic {
650 unsigned max_pipes;
651 unsigned max_tile_pipes;
652 unsigned max_simds;
653 unsigned max_backends;
654 unsigned max_gprs;
655 unsigned max_threads;
656 unsigned max_stack_entries;
657 unsigned max_hw_contexts;
658 unsigned max_gs_threads;
659 unsigned sx_max_export_size;
660 unsigned sx_max_export_pos_size;
661 unsigned sx_max_export_smx_size;
662 unsigned sq_num_cf_insts;
663};
664
665struct rv770_asic {
666 unsigned max_pipes;
667 unsigned max_tile_pipes;
668 unsigned max_simds;
669 unsigned max_backends;
670 unsigned max_gprs;
671 unsigned max_threads;
672 unsigned max_stack_entries;
673 unsigned max_hw_contexts;
674 unsigned max_gs_threads;
675 unsigned sx_max_export_size;
676 unsigned sx_max_export_pos_size;
677 unsigned sx_max_export_smx_size;
678 unsigned sq_num_cf_insts;
679 unsigned sx_num_of_sets;
680 unsigned sc_prim_fifo_size;
681 unsigned sc_hiz_tile_fifo_size;
682 unsigned sc_earlyz_tile_fifo_fize;
683};
684
068a117c
JG		 685union radeon_asic_config {
686 struct r300_asic r300;
551ebd83 687 struct r100_asic r100;
3ce0a23d
JG		 688 struct r600_asic r600;
689 struct rv770_asic rv770;
068a117c
JG		 690};
691
771fe6b9
JG		 692
693/*
694 * IOCTL.
695 */
696int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
697 struct drm_file *filp);
698int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
699 struct drm_file *filp);
700int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
701 struct drm_file *file_priv);
702int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
703 struct drm_file *file_priv);
704int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
705 struct drm_file *file_priv);
706int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
707 struct drm_file *file_priv);
708int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
709 struct drm_file *filp);
710int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *filp);
712int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
713 struct drm_file *filp);
714int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
715 struct drm_file *filp);
716int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 717int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
718 struct drm_file *filp);
719int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
720 struct drm_file *filp);
771fe6b9
JG		 721
722
723/*
724 * Core structure, functions and helpers.
725 */
726typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
727typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
728
729struct radeon_device {
9f022ddf 730 struct device *dev;
771fe6b9
JG		 731 struct drm_device *ddev;
732 struct pci_dev *pdev;
733 /* ASIC */
068a117c 734 union radeon_asic_config config;
771fe6b9
JG		 735 enum radeon_family family;
736 unsigned long flags;
737 int usec_timeout;
738 enum radeon_pll_errata pll_errata;
739 int num_gb_pipes;
f779b3e5 740 int num_z_pipes;
771fe6b9
JG		 741 int disp_priority;
742 /* BIOS */
743 uint8_t *bios;
744 bool is_atom_bios;
745 uint16_t bios_header_start;
746 struct radeon_object *stollen_vga_memory;
747 struct fb_info *fbdev_info;
748 struct radeon_object *fbdev_robj;
749 struct radeon_framebuffer *fbdev_rfb;
750 /* Register mmio */
4c9bc75c
DA		 751 resource_size_t rmmio_base;
752 resource_size_t rmmio_size;
771fe6b9 753 void *rmmio;
771fe6b9
JG		 754 radeon_rreg_t mc_rreg;
755 radeon_wreg_t mc_wreg;
756 radeon_rreg_t pll_rreg;
757 radeon_wreg_t pll_wreg;
de1b2898 758 uint32_t pcie_reg_mask;
771fe6b9
JG		 759 radeon_rreg_t pciep_rreg;
760 radeon_wreg_t pciep_wreg;
761 struct radeon_clock clock;
762 struct radeon_mc mc;
763 struct radeon_gart gart;
764 struct radeon_mode_info mode_info;
765 struct radeon_scratch scratch;
766 struct radeon_mman mman;
767 struct radeon_fence_driver fence_drv;
768 struct radeon_cp cp;
769 struct radeon_ib_pool ib_pool;
770 struct radeon_irq irq;
771 struct radeon_asic *asic;
772 struct radeon_gem gem;
c93bb85b 773 struct radeon_pm pm;
f657c2a7 774 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 775 struct mutex cs_mutex;
776 struct radeon_wb wb;
3ce0a23d 777 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 778 bool gpu_lockup;
779 bool shutdown;
780 bool suspend;
ad49f501 781 bool need_dma32;
733289c2 782 bool accel_working;
e024e110 783 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 784 const struct firmware *me_fw; /* all family ME firmware */
785 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
786 struct r600_blit r600_blit;
771fe6b9
JG		 787};
788
789int radeon_device_init(struct radeon_device *rdev,
790 struct drm_device *ddev,
791 struct pci_dev *pdev,
792 uint32_t flags);
793void radeon_device_fini(struct radeon_device *rdev);
794int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
795
3ce0a23d
JG		 796/* r600 blit */
797int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
798void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
799void r600_kms_blit_copy(struct radeon_device *rdev,
800 u64 src_gpu_addr, u64 dst_gpu_addr,
801 int size_bytes);
802
de1b2898
DA		 803static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
804{
805 if (reg < 0x10000)
806 return readl(((void __iomem *)rdev->rmmio) + reg);
807 else {
808 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
809 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
810 }
811}
812
813static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
814{
815 if (reg < 0x10000)
816 writel(v, ((void __iomem *)rdev->rmmio) + reg);
817 else {
818 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
819 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
820 }
821}
822
771fe6b9
JG		 823
824/*
825 * Registers read & write functions.
826 */
827#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
828#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 829#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 830#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 831#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 832#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
833#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
834#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
835#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
836#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
837#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 838#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
839#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 840#define WREG32_P(reg, val, mask) \
841 do { \
842 uint32_t tmp_ = RREG32(reg); \
843 tmp_ &= (mask); \
844 tmp_ |= ((val) & ~(mask)); \
845 WREG32(reg, tmp_); \
846 } while (0)
847#define WREG32_PLL_P(reg, val, mask) \
848 do { \
849 uint32_t tmp_ = RREG32_PLL(reg); \
850 tmp_ &= (mask); \
851 tmp_ |= ((val) & ~(mask)); \
852 WREG32_PLL(reg, tmp_); \
853 } while (0)
3ce0a23d 854#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 855
de1b2898
DA		 856/*
857 * Indirect registers accessor
858 */
859static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
860{
861 uint32_t r;
862
863 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
864 r = RREG32(RADEON_PCIE_DATA);
865 return r;
866}
867
868static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
869{
870 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
871 WREG32(RADEON_PCIE_DATA, (v));
872}
873
771fe6b9
JG		 874void r100_pll_errata_after_index(struct radeon_device *rdev);
875
876
877/*
878 * ASICs helpers.
879 */
b995e433
DA		 880#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
881 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 882#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
883 (rdev->family == CHIP_RV200) || \
884 (rdev->family == CHIP_RS100) || \
885 (rdev->family == CHIP_RS200) || \
886 (rdev->family == CHIP_RV250) || \
887 (rdev->family == CHIP_RV280) || \
888 (rdev->family == CHIP_RS300))
889#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
890 (rdev->family == CHIP_RV350) || \
891 (rdev->family == CHIP_R350) || \
892 (rdev->family == CHIP_RV380) || \
893 (rdev->family == CHIP_R420) || \
894 (rdev->family == CHIP_R423) || \
895 (rdev->family == CHIP_RV410) || \
896 (rdev->family == CHIP_RS400) || \
897 (rdev->family == CHIP_RS480))
898#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
899#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
900#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
901
902
903/*
904 * BIOS helpers.
905 */
906#define RBIOS8(i) (rdev->bios[i])
907#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
908#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
909
910int radeon_combios_init(struct radeon_device *rdev);
911void radeon_combios_fini(struct radeon_device *rdev);
912int radeon_atombios_init(struct radeon_device *rdev);
913void radeon_atombios_fini(struct radeon_device *rdev);
914
915
916/*
917 * RING helpers.
918 */
771fe6b9
JG		 919static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
920{
921#if DRM_DEBUG_CODE
922 if (rdev->cp.count_dw <= 0) {
923 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
924 }
925#endif
926 rdev->cp.ring[rdev->cp.wptr++] = v;
927 rdev->cp.wptr &= rdev->cp.ptr_mask;
928 rdev->cp.count_dw--;
929 rdev->cp.ring_free_dw--;
930}
931
932
933/*
934 * ASICs macro.
935 */
068a117c 936#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 937#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
938#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
939#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 940#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
771fe6b9 941#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
771fe6b9
JG		 942#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
943#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 944#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 945#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 946#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
947#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 948#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
949#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 950#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 951#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
952#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
953#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
954#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
955#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
956#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
957#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
958#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 959#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
960#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 961#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
771fe6b9 962
6cf8a3f5 963/* Common functions */
4aac0473 964extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 965extern int radeon_modeset_init(struct radeon_device *rdev);
966extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 967extern bool radeon_card_posted(struct radeon_device *rdev);
21f9a437
JG		 968extern int radeon_clocks_init(struct radeon_device *rdev);
969extern void radeon_clocks_fini(struct radeon_device *rdev);
970extern void radeon_scratch_init(struct radeon_device *rdev);
971extern void radeon_surface_init(struct radeon_device *rdev);
972extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 973extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 974extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
6cf8a3f5 975
a18d7ea1 976/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 977struct r100_mc_save {
978 u32 GENMO_WT;
979 u32 CRTC_EXT_CNTL;
980 u32 CRTC_GEN_CNTL;
981 u32 CRTC2_GEN_CNTL;
982 u32 CUR_OFFSET;
983 u32 CUR2_OFFSET;
984};
985extern void r100_cp_disable(struct radeon_device *rdev);
986extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
987extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 988extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 989extern int r100_pci_gart_init(struct radeon_device *rdev);
990extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 991extern int r100_pci_gart_enable(struct radeon_device *rdev);
992extern void r100_pci_gart_disable(struct radeon_device *rdev);
993extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 994extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
995extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
996extern void r100_ib_fini(struct radeon_device *rdev);
997extern int r100_ib_init(struct radeon_device *rdev);
998extern void r100_irq_disable(struct radeon_device *rdev);
999extern int r100_irq_set(struct radeon_device *rdev);
1000extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1001extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1002extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1003extern void r100_wb_disable(struct radeon_device *rdev);
1004extern void r100_wb_fini(struct radeon_device *rdev);
1005extern int r100_wb_init(struct radeon_device *rdev);
d39c3b89
JG		 1006extern void r100_hdp_reset(struct radeon_device *rdev);
1007extern int r100_rb2d_reset(struct radeon_device *rdev);
1008extern int r100_cp_reset(struct radeon_device *rdev);
ca6ffc64 1009extern void r100_vga_render_disable(struct radeon_device *rdev);
207bf9e9
JG		 1010extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1011 struct radeon_cs_packet *pkt,
1012 struct radeon_object *robj);
1013extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1014 struct radeon_cs_packet *pkt,
1015 const unsigned *auth, unsigned n,
1016 radeon_packet0_check_t check);
1017extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1018 struct radeon_cs_packet *pkt,
1019 unsigned idx);
9f022ddf 1020
d4550907
JG		 1021/* rv200,rv250,rv280 */
1022extern void r200_set_safe_registers(struct radeon_device *rdev);
1023
9f022ddf
JG		 1024/* r300,r350,rv350,rv370,rv380 */
1025extern void r300_set_reg_safe(struct radeon_device *rdev);
1026extern void r300_mc_program(struct radeon_device *rdev);
1027extern void r300_vram_info(struct radeon_device *rdev);
ca6ffc64
JG		 1028extern void r300_clock_startup(struct radeon_device *rdev);
1029extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473
JG		 1030extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1031extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1032extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1033extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1034
905b6822 1035/* r420,r423,rv410 */
d39c3b89 1036extern int r420_mc_init(struct radeon_device *rdev);
21f9a437
JG		 1037extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1038extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1039extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
d39c3b89 1040extern void r420_pipes_init(struct radeon_device *rdev);
905b6822 1041
21f9a437 1042/* rv515 */
d39c3b89
JG		 1043struct rv515_mc_save {
1044 u32 d1vga_control;
1045 u32 d2vga_control;
1046 u32 vga_render_control;
1047 u32 vga_hdp_control;
1048 u32 d1crtc_control;
1049 u32 d2crtc_control;
1050};
21f9a437 1051extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
d39c3b89
JG		 1052extern void rv515_vga_render_disable(struct radeon_device *rdev);
1053extern void rv515_set_safe_registers(struct radeon_device *rdev);
f0ed1f65
JG		 1054extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1055extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1056extern void rv515_clock_startup(struct radeon_device *rdev);
1057extern void rv515_debugfs(struct radeon_device *rdev);
1058extern int rv515_suspend(struct radeon_device *rdev);
21f9a437 1059
3bc68535
JG		 1060/* rs400 */
1061extern int rs400_gart_init(struct radeon_device *rdev);
1062extern int rs400_gart_enable(struct radeon_device *rdev);
1063extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1064extern void rs400_gart_disable(struct radeon_device *rdev);
1065extern void rs400_gart_fini(struct radeon_device *rdev);
1066
1067/* rs600 */
1068extern void rs600_set_safe_registers(struct radeon_device *rdev);
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JG		 1069extern int rs600_irq_set(struct radeon_device *rdev);
1070extern void rs600_irq_disable(struct radeon_device *rdev);
3bc68535 1071
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JG		 1072/* rs690, rs740 */
1073extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1074 struct drm_display_mode *mode1,
1075 struct drm_display_mode *mode2);
1076
1077/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1078extern bool r600_card_posted(struct radeon_device *rdev);
1079extern void r600_cp_stop(struct radeon_device *rdev);
1080extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1081extern int r600_cp_resume(struct radeon_device *rdev);
1082extern int r600_count_pipe_bits(uint32_t val);
1083extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1084extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1085extern int r600_pcie_gart_init(struct radeon_device *rdev);
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JG		 1086extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1087extern int r600_ib_test(struct radeon_device *rdev);
1088extern int r600_ring_test(struct radeon_device *rdev);
21f9a437 1089extern void r600_wb_fini(struct radeon_device *rdev);
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JG		 1090extern int r600_wb_enable(struct radeon_device *rdev);
1091extern void r600_wb_disable(struct radeon_device *rdev);
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JG		 1092extern void r600_scratch_init(struct radeon_device *rdev);
1093extern int r600_blit_init(struct radeon_device *rdev);
1094extern void r600_blit_fini(struct radeon_device *rdev);
1095extern int r600_cp_init_microcode(struct radeon_device *rdev);
fe62e1a4 1096extern int r600_gpu_reset(struct radeon_device *rdev);
21f9a437 1097
771fe6b9 1098#endif
kernel source for telekom puls (alcatel/mediatek)