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drm/i810: remove the BKL
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
771fe6b9
JG		 63#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
771fe6b9
JG		 96
97/*
98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 * symbol;
100 */
101#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
225758d8 102#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 103/* RADEON_IB_POOL_SIZE must be a power of 2 */
771fe6b9
JG		 104#define RADEON_IB_POOL_SIZE 16
105#define RADEON_DEBUGFS_MAX_NUM_FILES 32
106#define RADEONFB_CONN_LIMIT 4
f657c2a7 107#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 108
771fe6b9
JG		 109/*
110 * Errata workarounds.
111 */
112enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
116};
117
118
119struct radeon_device;
120
121
122/*
123 * BIOS.
124 */
6a9ee8af
DA		 125#define ATRM_BIOS_PAGE 4096
126
8edb381d 127#if defined(CONFIG_VGA_SWITCHEROO)
6a9ee8af
DA		 128bool radeon_atrm_supported(struct pci_dev *pdev);
129int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
8edb381d
DA		 130#else
131static inline bool radeon_atrm_supported(struct pci_dev *pdev)
132{
133 return false;
134}
135
136static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
137 return -EINVAL;
138}
139#endif
771fe6b9
JG		 140bool radeon_get_bios(struct radeon_device *rdev);
141
3ce0a23d 142
771fe6b9 143/*
3ce0a23d 144 * Dummy page
771fe6b9 145 */
3ce0a23d
JG		 146struct radeon_dummy_page {
147 struct page *page;
148 dma_addr_t addr;
149};
150int radeon_dummy_page_init(struct radeon_device *rdev);
151void radeon_dummy_page_fini(struct radeon_device *rdev);
152
771fe6b9 153
3ce0a23d
JG		 154/*
155 * Clocks
156 */
771fe6b9
JG		 157struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
bcc1c2a1 160 struct radeon_pll dcpll;
771fe6b9
JG		 161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163 /* 10 Khz units */
164 uint32_t default_mclk;
165 uint32_t default_sclk;
bcc1c2a1
AD		 166 uint32_t default_dispclk;
167 uint32_t dp_extclk;
771fe6b9
JG		 168};
169
7433874e
RM		 170/*
171 * Power management
172 */
173int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 174void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 175void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 176void radeon_pm_suspend(struct radeon_device *rdev);
177void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 178void radeon_combios_get_power_modes(struct radeon_device *rdev);
179void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7ac9aa5a 180void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
f892034a 181void rs690_pm_info(struct radeon_device *rdev);
20d391d7
AD		 182extern int rv6xx_get_temp(struct radeon_device *rdev);
183extern int rv770_get_temp(struct radeon_device *rdev);
184extern int evergreen_get_temp(struct radeon_device *rdev);
185extern int sumo_get_temp(struct radeon_device *rdev);
3ce0a23d 186
771fe6b9
JG		 187/*
188 * Fences.
189 */
190struct radeon_fence_driver {
191 uint32_t scratch_reg;
192 atomic_t seq;
193 uint32_t last_seq;
225758d8
JG		 194 unsigned long last_jiffies;
195 unsigned long last_timeout;
771fe6b9
JG		 196 wait_queue_head_t queue;
197 rwlock_t lock;
198 struct list_head created;
199 struct list_head emited;
200 struct list_head signaled;
0a0c7596 201 bool initialized;
771fe6b9
JG		 202};
203
204struct radeon_fence {
205 struct radeon_device *rdev;
206 struct kref kref;
207 struct list_head list;
208 /* protected by radeon_fence.lock */
209 uint32_t seq;
771fe6b9
JG		 210 bool emited;
211 bool signaled;
212};
213
214int radeon_fence_driver_init(struct radeon_device *rdev);
215void radeon_fence_driver_fini(struct radeon_device *rdev);
216int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
217int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
218void radeon_fence_process(struct radeon_device *rdev);
219bool radeon_fence_signaled(struct radeon_fence *fence);
220int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
221int radeon_fence_wait_next(struct radeon_device *rdev);
222int radeon_fence_wait_last(struct radeon_device *rdev);
223struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
224void radeon_fence_unref(struct radeon_fence **fence);
225
e024e110
DA		 226/*
227 * Tiling registers
228 */
229struct radeon_surface_reg {
4c788679 230 struct radeon_bo *bo;
e024e110
DA		 231};
232
233#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 234
235/*
4c788679 236 * TTM.
771fe6b9 237 */
4c788679
JG		 238struct radeon_mman {
239 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 240 struct drm_global_reference mem_global_ref;
4c788679 241 struct ttm_bo_device bdev;
0a0c7596
JG		 242 bool mem_global_referenced;
243 bool initialized;
4c788679
JG		 244};
245
246struct radeon_bo {
247 /* Protected by gem.mutex */
248 struct list_head list;
249 /* Protected by tbo.reserved */
312ea8da
JG		 250 u32 placements[3];
251 struct ttm_placement placement;
4c788679
JG		 252 struct ttm_buffer_object tbo;
253 struct ttm_bo_kmap_obj kmap;
254 unsigned pin_count;
255 void *kptr;
256 u32 tiling_flags;
257 u32 pitch;
258 int surface_reg;
259 /* Constant after initialization */
260 struct radeon_device *rdev;
261 struct drm_gem_object *gobj;
262};
771fe6b9 263
4c788679 264struct radeon_bo_list {
147666fb 265 struct ttm_validate_buffer tv;
4c788679 266 struct radeon_bo *bo;
771fe6b9
JG		 267 uint64_t gpu_offset;
268 unsigned rdomain;
269 unsigned wdomain;
4c788679 270 u32 tiling_flags;
771fe6b9
JG		 271};
272
771fe6b9
JG		 273/*
274 * GEM objects.
275 */
276struct radeon_gem {
4c788679 277 struct mutex mutex;
771fe6b9
JG		 278 struct list_head objects;
279};
280
281int radeon_gem_init(struct radeon_device *rdev);
282void radeon_gem_fini(struct radeon_device *rdev);
283int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 284 int alignment, int initial_domain,
285 bool discardable, bool kernel,
286 struct drm_gem_object **obj);
771fe6b9
JG		 287int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
288 uint64_t *gpu_addr);
289void radeon_gem_object_unpin(struct drm_gem_object *obj);
290
291
292/*
293 * GART structures, functions & helpers
294 */
295struct radeon_mc;
296
297struct radeon_gart_table_ram {
298 volatile uint32_t *ptr;
299};
300
301struct radeon_gart_table_vram {
4c788679 302 struct radeon_bo *robj;
771fe6b9
JG		 303 volatile uint32_t *ptr;
304};
305
306union radeon_gart_table {
307 struct radeon_gart_table_ram ram;
308 struct radeon_gart_table_vram vram;
309};
310
a77f1718 311#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 312#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
a77f1718 313
771fe6b9
JG		 314struct radeon_gart {
315 dma_addr_t table_addr;
316 unsigned num_gpu_pages;
317 unsigned num_cpu_pages;
318 unsigned table_size;
319 union radeon_gart_table table;
320 struct page **pages;
321 dma_addr_t *pages_addr;
322 bool ready;
323};
324
325int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
326void radeon_gart_table_ram_free(struct radeon_device *rdev);
327int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
328void radeon_gart_table_vram_free(struct radeon_device *rdev);
329int radeon_gart_init(struct radeon_device *rdev);
330void radeon_gart_fini(struct radeon_device *rdev);
331void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
332 int pages);
333int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
334 int pages, struct page **pagelist);
335
336
337/*
338 * GPU MC structures, functions & helpers
339 */
340struct radeon_mc {
341 resource_size_t aper_size;
342 resource_size_t aper_base;
343 resource_size_t agp_base;
7a50f01a
DA		 344 /* for some chips with <= 32MB we need to lie
345 * about vram size near mc fb location */
3ce0a23d 346 u64 mc_vram_size;
d594e46a 347 u64 visible_vram_size;
c919b371 348 u64 active_vram_size;
3ce0a23d
JG		 349 u64 gtt_size;
350 u64 gtt_start;
351 u64 gtt_end;
3ce0a23d
JG		 352 u64 vram_start;
353 u64 vram_end;
771fe6b9 354 unsigned vram_width;
3ce0a23d 355 u64 real_vram_size;
771fe6b9
JG		 356 int vram_mtrr;
357 bool vram_is_ddr;
d594e46a 358 bool igp_sideport_enabled;
8d369bb1 359 u64 gtt_base_align;
771fe6b9
JG		 360};
361
06b6476d
AD		 362bool radeon_combios_sideport_present(struct radeon_device *rdev);
363bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 364
365/*
366 * GPU scratch registers structures, functions & helpers
367 */
368struct radeon_scratch {
369 unsigned num_reg;
724c80e1 370 uint32_t reg_base;
771fe6b9
JG		 371 bool free[32];
372 uint32_t reg[32];
373};
374
375int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
376void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
377
378
379/*
380 * IRQS.
381 */
6f34be50
AD		 382
383struct radeon_unpin_work {
384 struct work_struct work;
385 struct radeon_device *rdev;
386 int crtc_id;
387 struct radeon_fence *fence;
388 struct drm_pending_vblank_event *event;
389 struct radeon_bo *old_rbo;
390 u64 new_crtc_base;
391};
392
393struct r500_irq_stat_regs {
394 u32 disp_int;
395};
396
397struct r600_irq_stat_regs {
398 u32 disp_int;
399 u32 disp_int_cont;
400 u32 disp_int_cont2;
401 u32 d1grph_int;
402 u32 d2grph_int;
403};
404
405struct evergreen_irq_stat_regs {
406 u32 disp_int;
407 u32 disp_int_cont;
408 u32 disp_int_cont2;
409 u32 disp_int_cont3;
410 u32 disp_int_cont4;
411 u32 disp_int_cont5;
412 u32 d1grph_int;
413 u32 d2grph_int;
414 u32 d3grph_int;
415 u32 d4grph_int;
416 u32 d5grph_int;
417 u32 d6grph_int;
418};
419
420union radeon_irq_stat_regs {
421 struct r500_irq_stat_regs r500;
422 struct r600_irq_stat_regs r600;
423 struct evergreen_irq_stat_regs evergreen;
424};
425
771fe6b9
JG		 426struct radeon_irq {
427 bool installed;
428 bool sw_int;
429 /* FIXME: use a define max crtc rather than hardcode it */
45f9a39b 430 bool crtc_vblank_int[6];
6f34be50 431 bool pflip[6];
73a6d3fc 432 wait_queue_head_t vblank_queue;
b500f680
AD		 433 /* FIXME: use defines for max hpd/dacs */
434 bool hpd[6];
2031f77c
AD		 435 bool gui_idle;
436 bool gui_idle_acked;
437 wait_queue_head_t idle_queue;
f2594933
CK		 438 /* FIXME: use defines for max HDMI blocks */
439 bool hdmi[2];
1614f8b1
DA		 440 spinlock_t sw_lock;
441 int sw_refcount;
6f34be50
AD		 442 union radeon_irq_stat_regs stat_regs;
443 spinlock_t pflip_lock[6];
444 int pflip_refcount[6];
771fe6b9
JG		 445};
446
447int radeon_irq_kms_init(struct radeon_device *rdev);
448void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 449void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
450void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
6f34be50
AD		 451void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
452void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 453
454/*
455 * CP & ring.
456 */
457struct radeon_ib {
458 struct list_head list;
e821767b 459 unsigned idx;
771fe6b9
JG		 460 uint64_t gpu_addr;
461 struct radeon_fence *fence;
e821767b 462 uint32_t *ptr;
771fe6b9 463 uint32_t length_dw;
e821767b 464 bool free;
771fe6b9
JG		 465};
466
ecb114a1
DA		 467/*
468 * locking -
469 * mutex protects scheduled_ibs, ready, alloc_bm
470 */
771fe6b9
JG		 471struct radeon_ib_pool {
472 struct mutex mutex;
4c788679 473 struct radeon_bo *robj;
9f93ed39 474 struct list_head bogus_ib;
771fe6b9
JG		 475 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
476 bool ready;
e821767b 477 unsigned head_id;
771fe6b9
JG		 478};
479
480struct radeon_cp {
4c788679 481 struct radeon_bo *ring_obj;
771fe6b9
JG		 482 volatile uint32_t *ring;
483 unsigned rptr;
484 unsigned wptr;
485 unsigned wptr_old;
486 unsigned ring_size;
487 unsigned ring_free_dw;
488 int count_dw;
489 uint64_t gpu_addr;
490 uint32_t align_mask;
491 uint32_t ptr_mask;
492 struct mutex mutex;
493 bool ready;
494};
495
d8f60cfc
AD		 496/*
497 * R6xx+ IH ring
498 */
499struct r600_ih {
4c788679 500 struct radeon_bo *ring_obj;
d8f60cfc
AD		 501 volatile uint32_t *ring;
502 unsigned rptr;
503 unsigned wptr;
504 unsigned wptr_old;
505 unsigned ring_size;
506 uint64_t gpu_addr;
d8f60cfc
AD		 507 uint32_t ptr_mask;
508 spinlock_t lock;
509 bool enabled;
510};
511
3ce0a23d 512struct r600_blit {
ff82f052 513 struct mutex mutex;
4c788679 514 struct radeon_bo *shader_obj;
3ce0a23d
JG		 515 u64 shader_gpu_addr;
516 u32 vs_offset, ps_offset;
517 u32 state_offset;
518 u32 state_len;
519 u32 vb_used, vb_total;
520 struct radeon_ib *vb_ib;
521};
522
771fe6b9
JG		 523int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
524void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
525int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
526int radeon_ib_pool_init(struct radeon_device *rdev);
527void radeon_ib_pool_fini(struct radeon_device *rdev);
528int radeon_ib_test(struct radeon_device *rdev);
9f93ed39 529extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 530/* Ring access between begin & end cannot sleep */
531void radeon_ring_free_size(struct radeon_device *rdev);
91700f3c 532int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
771fe6b9 533int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
91700f3c 534void radeon_ring_commit(struct radeon_device *rdev);
771fe6b9
JG		 535void radeon_ring_unlock_commit(struct radeon_device *rdev);
536void radeon_ring_unlock_undo(struct radeon_device *rdev);
537int radeon_ring_test(struct radeon_device *rdev);
538int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
539void radeon_ring_fini(struct radeon_device *rdev);
540
541
542/*
543 * CS.
544 */
545struct radeon_cs_reloc {
546 struct drm_gem_object *gobj;
4c788679
JG		 547 struct radeon_bo *robj;
548 struct radeon_bo_list lobj;
771fe6b9
JG		 549 uint32_t handle;
550 uint32_t flags;
551};
552
553struct radeon_cs_chunk {
554 uint32_t chunk_id;
555 uint32_t length_dw;
513bcb46
DA		 556 int kpage_idx[2];
557 uint32_t *kpage[2];
771fe6b9 558 uint32_t *kdata;
513bcb46
DA		 559 void __user *user_ptr;
560 int last_copied_page;
561 int last_page_index;
771fe6b9
JG		 562};
563
564struct radeon_cs_parser {
c8c15ff1 565 struct device *dev;
771fe6b9
JG		 566 struct radeon_device *rdev;
567 struct drm_file *filp;
568 /* chunks */
569 unsigned nchunks;
570 struct radeon_cs_chunk *chunks;
571 uint64_t *chunks_array;
572 /* IB */
573 unsigned idx;
574 /* relocations */
575 unsigned nrelocs;
576 struct radeon_cs_reloc *relocs;
577 struct radeon_cs_reloc **relocs_ptr;
578 struct list_head validated;
579 /* indices of various chunks */
580 int chunk_ib_idx;
581 int chunk_relocs_idx;
582 struct radeon_ib *ib;
583 void *track;
3ce0a23d 584 unsigned family;
513bcb46 585 int parser_error;
771fe6b9
JG		 586};
587
513bcb46
DA		 588extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
589extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
590
591
592static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
593{
594 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
595 u32 pg_idx, pg_offset;
596 u32 idx_value = 0;
597 int new_page;
598
599 pg_idx = (idx * 4) / PAGE_SIZE;
600 pg_offset = (idx * 4) % PAGE_SIZE;
601
602 if (ibc->kpage_idx[0] == pg_idx)
603 return ibc->kpage[0][pg_offset/4];
604 if (ibc->kpage_idx[1] == pg_idx)
605 return ibc->kpage[1][pg_offset/4];
606
607 new_page = radeon_cs_update_pages(p, pg_idx);
608 if (new_page < 0) {
609 p->parser_error = new_page;
610 return 0;
611 }
612
613 idx_value = ibc->kpage[new_page][pg_offset/4];
614 return idx_value;
615}
616
771fe6b9
JG		 617struct radeon_cs_packet {
618 unsigned idx;
619 unsigned type;
620 unsigned reg;
621 unsigned opcode;
622 int count;
623 unsigned one_reg_wr;
624};
625
626typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
627 struct radeon_cs_packet *pkt,
628 unsigned idx, unsigned reg);
629typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
630 struct radeon_cs_packet *pkt);
631
632
633/*
634 * AGP
635 */
636int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 637void radeon_agp_resume(struct radeon_device *rdev);
10b06122 638void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 639void radeon_agp_fini(struct radeon_device *rdev);
640
641
642/*
643 * Writeback
644 */
645struct radeon_wb {
4c788679 646 struct radeon_bo *wb_obj;
771fe6b9
JG		 647 volatile uint32_t *wb;
648 uint64_t gpu_addr;
724c80e1 649 bool enabled;
d0f8a854 650 bool use_event;
771fe6b9
JG		 651};
652
724c80e1
AD		 653#define RADEON_WB_SCRATCH_OFFSET 0
654#define RADEON_WB_CP_RPTR_OFFSET 1024
655#define R600_WB_IH_WPTR_OFFSET 2048
d0f8a854 656#define R600_WB_EVENT_OFFSET 3072
724c80e1 657
c93bb85b
JG		 658/**
659 * struct radeon_pm - power management datas
660 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
661 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
662 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
663 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
664 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
665 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
666 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
667 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
668 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
669 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
670 * @needed_bandwidth: current bandwidth needs
671 *
672 * It keeps track of various data needed to take powermanagement decision.
673 * Bandwith need is used to determine minimun clock of the GPU and memory.
674 * Equation between gpu/memory clock and available bandwidth is hw dependent
675 * (type of memory, bus size, efficiency, ...)
676 */
ce8f5370
AD		 677
678enum radeon_pm_method {
679 PM_METHOD_PROFILE,
680 PM_METHOD_DYNPM,
681};
682
683enum radeon_dynpm_state {
684 DYNPM_STATE_DISABLED,
685 DYNPM_STATE_MINIMUM,
686 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 687 DYNPM_STATE_ACTIVE,
688 DYNPM_STATE_SUSPENDED,
c913e23a 689};
ce8f5370
AD		 690enum radeon_dynpm_action {
691 DYNPM_ACTION_NONE,
692 DYNPM_ACTION_MINIMUM,
693 DYNPM_ACTION_DOWNCLOCK,
694 DYNPM_ACTION_UPCLOCK,
695 DYNPM_ACTION_DEFAULT
c913e23a 696};
56278a8e
AD		 697
698enum radeon_voltage_type {
699 VOLTAGE_NONE = 0,
700 VOLTAGE_GPIO,
701 VOLTAGE_VDDC,
702 VOLTAGE_SW
703};
704
0ec0e74f
AD		 705enum radeon_pm_state_type {
706 POWER_STATE_TYPE_DEFAULT,
707 POWER_STATE_TYPE_POWERSAVE,
708 POWER_STATE_TYPE_BATTERY,
709 POWER_STATE_TYPE_BALANCED,
710 POWER_STATE_TYPE_PERFORMANCE,
711};
712
ce8f5370
AD		 713enum radeon_pm_profile_type {
714 PM_PROFILE_DEFAULT,
715 PM_PROFILE_AUTO,
716 PM_PROFILE_LOW,
c9e75b21 717 PM_PROFILE_MID,
ce8f5370
AD		 718 PM_PROFILE_HIGH,
719};
720
721#define PM_PROFILE_DEFAULT_IDX 0
722#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 723#define PM_PROFILE_MID_SH_IDX 2
724#define PM_PROFILE_HIGH_SH_IDX 3
725#define PM_PROFILE_LOW_MH_IDX 4
726#define PM_PROFILE_MID_MH_IDX 5
727#define PM_PROFILE_HIGH_MH_IDX 6
728#define PM_PROFILE_MAX 7
ce8f5370
AD		 729
730struct radeon_pm_profile {
731 int dpms_off_ps_idx;
732 int dpms_on_ps_idx;
733 int dpms_off_cm_idx;
734 int dpms_on_cm_idx;
516d0e46
AD		 735};
736
21a8122a
AD		 737enum radeon_int_thermal_type {
738 THERMAL_TYPE_NONE,
739 THERMAL_TYPE_RV6XX,
740 THERMAL_TYPE_RV770,
741 THERMAL_TYPE_EVERGREEN,
e33df25f 742 THERMAL_TYPE_SUMO,
4fddba1f 743 THERMAL_TYPE_NI,
21a8122a
AD		 744};
745
56278a8e
AD		 746struct radeon_voltage {
747 enum radeon_voltage_type type;
748 /* gpio voltage */
749 struct radeon_gpio_rec gpio;
750 u32 delay; /* delay in usec from voltage drop to sclk change */
751 bool active_high; /* voltage drop is active when bit is high */
752 /* VDDC voltage */
753 u8 vddc_id; /* index into vddc voltage table */
754 u8 vddci_id; /* index into vddci voltage table */
755 bool vddci_enabled;
756 /* r6xx+ sw */
757 u32 voltage;
758};
759
d7311171
AD		 760/* clock mode flags */
761#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
762
56278a8e
AD		 763struct radeon_pm_clock_info {
764 /* memory clock */
765 u32 mclk;
766 /* engine clock */
767 u32 sclk;
768 /* voltage info */
769 struct radeon_voltage voltage;
d7311171 770 /* standardized clock flags */
56278a8e
AD		 771 u32 flags;
772};
773
a48b9b4e 774/* state flags */
d7311171 775#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 776
56278a8e 777struct radeon_power_state {
0ec0e74f 778 enum radeon_pm_state_type type;
56278a8e
AD		 779 /* XXX: use a define for num clock modes */
780 struct radeon_pm_clock_info clock_info[8];
781 /* number of valid clock modes in this power state */
782 int num_clock_modes;
56278a8e 783 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 784 /* standardized state flags */
785 u32 flags;
79daedc9
AD		 786 u32 misc; /* vbios specific flags */
787 u32 misc2; /* vbios specific flags */
788 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 789};
790
27459324
RM		 791/*
792 * Some modes are overclocked by very low value, accept them
793 */
794#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
795
c93bb85b 796struct radeon_pm {
c913e23a 797 struct mutex mutex;
a48b9b4e
AD		 798 u32 active_crtcs;
799 int active_crtc_count;
c913e23a 800 int req_vblank;
839461d3 801 bool vblank_sync;
2031f77c 802 bool gui_idle;
c93bb85b
JG		 803 fixed20_12 max_bandwidth;
804 fixed20_12 igp_sideport_mclk;
805 fixed20_12 igp_system_mclk;
806 fixed20_12 igp_ht_link_clk;
807 fixed20_12 igp_ht_link_width;
808 fixed20_12 k8_bandwidth;
809 fixed20_12 sideport_bandwidth;
810 fixed20_12 ht_bandwidth;
811 fixed20_12 core_bandwidth;
812 fixed20_12 sclk;
f47299c5 813 fixed20_12 mclk;
c93bb85b 814 fixed20_12 needed_bandwidth;
0975b162 815 struct radeon_power_state *power_state;
56278a8e
AD		 816 /* number of valid power states */
817 int num_power_states;
a48b9b4e
AD		 818 int current_power_state_index;
819 int current_clock_mode_index;
820 int requested_power_state_index;
821 int requested_clock_mode_index;
822 int default_power_state_index;
823 u32 current_sclk;
824 u32 current_mclk;
4d60173f 825 u32 current_vddc;
9ace9f7b
AD		 826 u32 default_sclk;
827 u32 default_mclk;
828 u32 default_vddc;
29fb52ca 829 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 830 /* selected pm method */
831 enum radeon_pm_method pm_method;
832 /* dynpm power management */
833 struct delayed_work dynpm_idle_work;
834 enum radeon_dynpm_state dynpm_state;
835 enum radeon_dynpm_action dynpm_planned_action;
836 unsigned long dynpm_action_timeout;
837 bool dynpm_can_upclock;
838 bool dynpm_can_downclock;
839 /* profile-based power management */
840 enum radeon_pm_profile_type profile;
841 int profile_index;
842 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 843 /* internal thermal controller on rv6xx+ */
844 enum radeon_int_thermal_type int_thermal_type;
845 struct device *int_hwmon_dev;
c93bb85b
JG		 846};
847
771fe6b9
JG		 848
849/*
850 * Benchmarking
851 */
852void radeon_benchmark(struct radeon_device *rdev);
853
854
ecc0b326
MD		 855/*
856 * Testing
857 */
858void radeon_test_moves(struct radeon_device *rdev);
859
860
771fe6b9
JG		 861/*
862 * Debugfs
863 */
864int radeon_debugfs_add_files(struct radeon_device *rdev,
865 struct drm_info_list *files,
866 unsigned nfiles);
867int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 868
869
870/*
871 * ASIC specific functions.
872 */
873struct radeon_asic {
068a117c 874 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 875 void (*fini)(struct radeon_device *rdev);
876 int (*resume)(struct radeon_device *rdev);
877 int (*suspend)(struct radeon_device *rdev);
28d52043 878 void (*vga_set_state)(struct radeon_device *rdev, bool state);
225758d8 879 bool (*gpu_is_lockup)(struct radeon_device *rdev);
a2d07b74 880 int (*asic_reset)(struct radeon_device *rdev);
771fe6b9
JG		 881 void (*gart_tlb_flush)(struct radeon_device *rdev);
882 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
883 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
884 void (*cp_fini)(struct radeon_device *rdev);
885 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 886 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 887 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 888 int (*ring_test)(struct radeon_device *rdev);
889 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 890 int (*irq_set)(struct radeon_device *rdev);
891 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 892 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 893 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
894 int (*cs_parse)(struct radeon_cs_parser *p);
895 int (*copy_blit)(struct radeon_device *rdev,
896 uint64_t src_offset,
897 uint64_t dst_offset,
898 unsigned num_pages,
899 struct radeon_fence *fence);
900 int (*copy_dma)(struct radeon_device *rdev,
901 uint64_t src_offset,
902 uint64_t dst_offset,
903 unsigned num_pages,
904 struct radeon_fence *fence);
905 int (*copy)(struct radeon_device *rdev,
906 uint64_t src_offset,
907 uint64_t dst_offset,
908 unsigned num_pages,
909 struct radeon_fence *fence);
7433874e 910 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 911 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 912 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9 913 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
c836a412 914 int (*get_pcie_lanes)(struct radeon_device *rdev);
771fe6b9
JG		 915 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
916 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 917 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
918 uint32_t tiling_flags, uint32_t pitch,
919 uint32_t offset, uint32_t obj_size);
9479c54f 920 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 921 void (*bandwidth_update)(struct radeon_device *rdev);
429770b3
AD		 922 void (*hpd_init)(struct radeon_device *rdev);
923 void (*hpd_fini)(struct radeon_device *rdev);
924 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
925 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
062b389c
JG		 926 /* ioctl hw specific callback. Some hw might want to perform special
927 * operation on specific ioctl. For instance on wait idle some hw
928 * might want to perform and HDP flush through MMIO as it seems that
929 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
930 * through ring.
931 */
932 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
def9ba9c 933 bool (*gui_idle)(struct radeon_device *rdev);
ce8f5370 934 /* power management */
49e02b73
AD		 935 void (*pm_misc)(struct radeon_device *rdev);
936 void (*pm_prepare)(struct radeon_device *rdev);
937 void (*pm_finish)(struct radeon_device *rdev);
ce8f5370
AD		 938 void (*pm_init_profile)(struct radeon_device *rdev);
939 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
6f34be50
AD		 940 /* pageflipping */
941 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
942 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
943 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 944};
945
21f9a437
JG		 946/*
947 * Asic structures
948 */
225758d8
JG		 949struct r100_gpu_lockup {
950 unsigned long last_jiffies;
951 u32 last_cp_rptr;
952};
953
551ebd83 954struct r100_asic {
225758d8
JG		 955 const unsigned *reg_safe_bm;
956 unsigned reg_safe_bm_size;
957 u32 hdp_cntl;
958 struct r100_gpu_lockup lockup;
551ebd83
DA		 959};
960
21f9a437 961struct r300_asic {
225758d8
JG		 962 const unsigned *reg_safe_bm;
963 unsigned reg_safe_bm_size;
964 u32 resync_scratch;
965 u32 hdp_cntl;
966 struct r100_gpu_lockup lockup;
21f9a437
JG		 967};
968
969struct r600_asic {
225758d8
JG		 970 unsigned max_pipes;
971 unsigned max_tile_pipes;
972 unsigned max_simds;
973 unsigned max_backends;
974 unsigned max_gprs;
975 unsigned max_threads;
976 unsigned max_stack_entries;
977 unsigned max_hw_contexts;
978 unsigned max_gs_threads;
979 unsigned sx_max_export_size;
980 unsigned sx_max_export_pos_size;
981 unsigned sx_max_export_smx_size;
982 unsigned sq_num_cf_insts;
983 unsigned tiling_nbanks;
984 unsigned tiling_npipes;
985 unsigned tiling_group_size;
e7aeeba6 986 unsigned tile_config;
225758d8 987 struct r100_gpu_lockup lockup;
21f9a437
JG		 988};
989
990struct rv770_asic {
225758d8
JG		 991 unsigned max_pipes;
992 unsigned max_tile_pipes;
993 unsigned max_simds;
994 unsigned max_backends;
995 unsigned max_gprs;
996 unsigned max_threads;
997 unsigned max_stack_entries;
998 unsigned max_hw_contexts;
999 unsigned max_gs_threads;
1000 unsigned sx_max_export_size;
1001 unsigned sx_max_export_pos_size;
1002 unsigned sx_max_export_smx_size;
1003 unsigned sq_num_cf_insts;
1004 unsigned sx_num_of_sets;
1005 unsigned sc_prim_fifo_size;
1006 unsigned sc_hiz_tile_fifo_size;
1007 unsigned sc_earlyz_tile_fifo_fize;
1008 unsigned tiling_nbanks;
1009 unsigned tiling_npipes;
1010 unsigned tiling_group_size;
e7aeeba6 1011 unsigned tile_config;
225758d8 1012 struct r100_gpu_lockup lockup;
21f9a437
JG		 1013};
1014
32fcdbf4
AD		 1015struct evergreen_asic {
1016 unsigned num_ses;
1017 unsigned max_pipes;
1018 unsigned max_tile_pipes;
1019 unsigned max_simds;
1020 unsigned max_backends;
1021 unsigned max_gprs;
1022 unsigned max_threads;
1023 unsigned max_stack_entries;
1024 unsigned max_hw_contexts;
1025 unsigned max_gs_threads;
1026 unsigned sx_max_export_size;
1027 unsigned sx_max_export_pos_size;
1028 unsigned sx_max_export_smx_size;
1029 unsigned sq_num_cf_insts;
1030 unsigned sx_num_of_sets;
1031 unsigned sc_prim_fifo_size;
1032 unsigned sc_hiz_tile_fifo_size;
1033 unsigned sc_earlyz_tile_fifo_size;
1034 unsigned tiling_nbanks;
1035 unsigned tiling_npipes;
1036 unsigned tiling_group_size;
e7aeeba6 1037 unsigned tile_config;
17db7042 1038 struct r100_gpu_lockup lockup;
32fcdbf4
AD		 1039};
1040
068a117c
JG		 1041union radeon_asic_config {
1042 struct r300_asic r300;
551ebd83 1043 struct r100_asic r100;
3ce0a23d
JG		 1044 struct r600_asic r600;
1045 struct rv770_asic rv770;
32fcdbf4 1046 struct evergreen_asic evergreen;
068a117c
JG		 1047};
1048
0a10c851
DV		 1049/*
1050 * asic initizalization from radeon_asic.c
1051 */
1052void radeon_agp_disable(struct radeon_device *rdev);
1053int radeon_asic_init(struct radeon_device *rdev);
1054
771fe6b9
JG		 1055
1056/*
1057 * IOCTL.
1058 */
1059int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1060 struct drm_file *filp);
1061int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1062 struct drm_file *filp);
1063int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1064 struct drm_file *file_priv);
1065int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1066 struct drm_file *file_priv);
1067int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1068 struct drm_file *file_priv);
1069int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1070 struct drm_file *file_priv);
1071int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1072 struct drm_file *filp);
1073int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1074 struct drm_file *filp);
1075int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1076 struct drm_file *filp);
1077int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *filp);
1079int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1080int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1081 struct drm_file *filp);
1082int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1083 struct drm_file *filp);
771fe6b9 1084
87cbf8f2
AD		 1085/* VRAM scratch page for HDP bug */
1086struct r700_vram_scratch {
1087 struct radeon_bo *robj;
1088 volatile uint32_t *ptr;
1089};
771fe6b9
JG		 1090
1091/*
1092 * Core structure, functions and helpers.
1093 */
1094typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1095typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1096
1097struct radeon_device {
9f022ddf 1098 struct device *dev;
771fe6b9
JG		 1099 struct drm_device *ddev;
1100 struct pci_dev *pdev;
1101 /* ASIC */
068a117c 1102 union radeon_asic_config config;
771fe6b9
JG		 1103 enum radeon_family family;
1104 unsigned long flags;
1105 int usec_timeout;
1106 enum radeon_pll_errata pll_errata;
1107 int num_gb_pipes;
f779b3e5 1108 int num_z_pipes;
771fe6b9
JG		 1109 int disp_priority;
1110 /* BIOS */
1111 uint8_t *bios;
1112 bool is_atom_bios;
1113 uint16_t bios_header_start;
4c788679 1114 struct radeon_bo *stollen_vga_memory;
771fe6b9 1115 /* Register mmio */
4c9bc75c
DA		 1116 resource_size_t rmmio_base;
1117 resource_size_t rmmio_size;
771fe6b9 1118 void *rmmio;
771fe6b9
JG		 1119 radeon_rreg_t mc_rreg;
1120 radeon_wreg_t mc_wreg;
1121 radeon_rreg_t pll_rreg;
1122 radeon_wreg_t pll_wreg;
de1b2898 1123 uint32_t pcie_reg_mask;
771fe6b9
JG		 1124 radeon_rreg_t pciep_rreg;
1125 radeon_wreg_t pciep_wreg;
351a52a2
AD		 1126 /* io port */
1127 void __iomem *rio_mem;
1128 resource_size_t rio_mem_size;
771fe6b9
JG		 1129 struct radeon_clock clock;
1130 struct radeon_mc mc;
1131 struct radeon_gart gart;
1132 struct radeon_mode_info mode_info;
1133 struct radeon_scratch scratch;
1134 struct radeon_mman mman;
1135 struct radeon_fence_driver fence_drv;
1136 struct radeon_cp cp;
1137 struct radeon_ib_pool ib_pool;
1138 struct radeon_irq irq;
1139 struct radeon_asic *asic;
1140 struct radeon_gem gem;
c93bb85b 1141 struct radeon_pm pm;
f657c2a7 1142 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 1143 struct mutex cs_mutex;
1144 struct radeon_wb wb;
3ce0a23d 1145 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 1146 bool gpu_lockup;
1147 bool shutdown;
1148 bool suspend;
ad49f501 1149 bool need_dma32;
733289c2 1150 bool accel_working;
e024e110 1151 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 1152 const struct firmware *me_fw; /* all family ME firmware */
1153 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 1154 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 1155 const struct firmware *mc_fw; /* NI MC firmware */
3ce0a23d 1156 struct r600_blit r600_blit;
87cbf8f2 1157 struct r700_vram_scratch vram_scratch;
3e5cb98d 1158 int msi_enabled; /* msi enabled */
d8f60cfc 1159 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2 1160 struct work_struct hotplug_work;
18917b60 1161 int num_crtc; /* number of crtcs */
40bacf16 1162 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
5876dd24 1163 struct mutex vram_mutex;
dafc3bd5
CK		 1164
1165 /* audio stuff */
7eea7e9e 1166 bool audio_enabled;
dafc3bd5
CK		 1167 struct timer_list audio_timer;
1168 int audio_channels;
1169 int audio_rate;
1170 int audio_bits_per_sample;
1171 uint8_t audio_status_bits;
1172 uint8_t audio_category_code;
6a9ee8af 1173
ce8f5370 1174 struct notifier_block acpi_nb;
9eba4a93 1175 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 1176 struct drm_file *hyperz_filp;
9eba4a93 1177 struct drm_file *cmask_filp;
f376b94f
AD		 1178 /* i2c buses */
1179 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
771fe6b9
JG		 1180};
1181
1182int radeon_device_init(struct radeon_device *rdev,
1183 struct drm_device *ddev,
1184 struct pci_dev *pdev,
1185 uint32_t flags);
1186void radeon_device_fini(struct radeon_device *rdev);
1187int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1188
3ce0a23d
JG		 1189/* r600 blit */
1190int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1191void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1192void r600_kms_blit_copy(struct radeon_device *rdev,
1193 u64 src_gpu_addr, u64 dst_gpu_addr,
1194 int size_bytes);
d7ccd8fc
AD		 1195/* evergreen blit */
1196int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1197void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1198void evergreen_kms_blit_copy(struct radeon_device *rdev,
1199 u64 src_gpu_addr, u64 dst_gpu_addr,
1200 int size_bytes);
3ce0a23d 1201
de1b2898
DA		 1202static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1203{
07bec2df 1204 if (reg < rdev->rmmio_size)
de1b2898
DA		 1205 return readl(((void __iomem *)rdev->rmmio) + reg);
1206 else {
1207 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1208 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1209 }
1210}
1211
1212static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1213{
07bec2df 1214 if (reg < rdev->rmmio_size)
de1b2898
DA		 1215 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1216 else {
1217 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1218 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1219 }
1220}
1221
351a52a2
AD		 1222static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1223{
1224 if (reg < rdev->rio_mem_size)
1225 return ioread32(rdev->rio_mem + reg);
1226 else {
1227 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1228 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1229 }
1230}
1231
1232static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1233{
1234 if (reg < rdev->rio_mem_size)
1235 iowrite32(v, rdev->rio_mem + reg);
1236 else {
1237 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1238 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1239 }
1240}
1241
4c788679
JG		 1242/*
1243 * Cast helper
1244 */
1245#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 1246
1247/*
1248 * Registers read & write functions.
1249 */
1250#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1251#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
9e46a48d
AD		 1252#define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
1253#define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 1254#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 1255#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 1256#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 1257#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1258#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1259#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1260#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1261#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1262#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 1263#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1264#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
aa5120d2
RM		 1265#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1266#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
771fe6b9
JG		 1267#define WREG32_P(reg, val, mask) \
1268 do { \
1269 uint32_t tmp_ = RREG32(reg); \
1270 tmp_ &= (mask); \
1271 tmp_ |= ((val) & ~(mask)); \
1272 WREG32(reg, tmp_); \
1273 } while (0)
1274#define WREG32_PLL_P(reg, val, mask) \
1275 do { \
1276 uint32_t tmp_ = RREG32_PLL(reg); \
1277 tmp_ &= (mask); \
1278 tmp_ |= ((val) & ~(mask)); \
1279 WREG32_PLL(reg, tmp_); \
1280 } while (0)
3ce0a23d 1281#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
351a52a2
AD		 1282#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1283#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 1284
de1b2898
DA		 1285/*
1286 * Indirect registers accessor
1287 */
1288static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1289{
1290 uint32_t r;
1291
1292 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1293 r = RREG32(RADEON_PCIE_DATA);
1294 return r;
1295}
1296
1297static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1298{
1299 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1300 WREG32(RADEON_PCIE_DATA, (v));
1301}
1302
771fe6b9
JG		 1303void r100_pll_errata_after_index(struct radeon_device *rdev);
1304
1305
1306/*
1307 * ASICs helpers.
1308 */
b995e433
DA		 1309#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1310 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 1311#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1312 (rdev->family == CHIP_RV200) || \
1313 (rdev->family == CHIP_RS100) || \
1314 (rdev->family == CHIP_RS200) || \
1315 (rdev->family == CHIP_RV250) || \
1316 (rdev->family == CHIP_RV280) || \
1317 (rdev->family == CHIP_RS300))
1318#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1319 (rdev->family == CHIP_RV350) || \
1320 (rdev->family == CHIP_R350) || \
1321 (rdev->family == CHIP_RV380) || \
1322 (rdev->family == CHIP_R420) || \
1323 (rdev->family == CHIP_R423) || \
1324 (rdev->family == CHIP_RV410) || \
1325 (rdev->family == CHIP_RS400) || \
1326 (rdev->family == CHIP_RS480))
3313e3d4
AD		 1327#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1328 (rdev->ddev->pdev->device == 0x9443) || \
1329 (rdev->ddev->pdev->device == 0x944B) || \
1330 (rdev->ddev->pdev->device == 0x9506) || \
1331 (rdev->ddev->pdev->device == 0x9509) || \
1332 (rdev->ddev->pdev->device == 0x950F) || \
1333 (rdev->ddev->pdev->device == 0x689C) || \
1334 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 1335#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 1336#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1337 (rdev->family == CHIP_RS690) || \
1338 (rdev->family == CHIP_RS740) || \
1339 (rdev->family >= CHIP_R600))
771fe6b9
JG		 1340#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1341#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 1342#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 1343#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1344 (rdev->flags & RADEON_IS_IGP))
1fe18305 1345#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
771fe6b9
JG		 1346
1347/*
1348 * BIOS helpers.
1349 */
1350#define RBIOS8(i) (rdev->bios[i])
1351#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1352#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1353
1354int radeon_combios_init(struct radeon_device *rdev);
1355void radeon_combios_fini(struct radeon_device *rdev);
1356int radeon_atombios_init(struct radeon_device *rdev);
1357void radeon_atombios_fini(struct radeon_device *rdev);
1358
1359
1360/*
1361 * RING helpers.
1362 */
771fe6b9
JG		 1363static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1364{
1365#if DRM_DEBUG_CODE
1366 if (rdev->cp.count_dw <= 0) {
1367 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1368 }
1369#endif
1370 rdev->cp.ring[rdev->cp.wptr++] = v;
1371 rdev->cp.wptr &= rdev->cp.ptr_mask;
1372 rdev->cp.count_dw--;
1373 rdev->cp.ring_free_dw--;
1374}
1375
1376
1377/*
1378 * ASICs macro.
1379 */
068a117c 1380#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 1381#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1382#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1383#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 1384#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 1385#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
225758d8 1386#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
a2d07b74 1387#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
771fe6b9
JG		 1388#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1389#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 1390#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 1391#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 1392#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1393#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 1394#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1395#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 1396#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 1397#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1398#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1399#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1400#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 1401#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 1402#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 1403#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 1404#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
c836a412 1405#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
771fe6b9
JG		 1406#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1407#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 1408#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1409#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 1410#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
429770b3
AD		 1411#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1412#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1413#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1414#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
def9ba9c 1415#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a424816f
AD		 1416#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1417#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1418#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
ce8f5370
AD		 1419#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1420#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
6f34be50
AD		 1421#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1422#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1423#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
771fe6b9 1424
6cf8a3f5 1425/* Common functions */
700a0cc0 1426/* AGP */
90aca4d2 1427extern int radeon_gpu_reset(struct radeon_device *rdev);
700a0cc0 1428extern void radeon_agp_disable(struct radeon_device *rdev);
4aac0473 1429extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
82568565 1430extern void radeon_gart_restore(struct radeon_device *rdev);
21f9a437
JG		 1431extern int radeon_modeset_init(struct radeon_device *rdev);
1432extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1433extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 1434extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 1435extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 1436extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 1437extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 1438extern void radeon_wb_fini(struct radeon_device *rdev);
1439extern int radeon_wb_init(struct radeon_device *rdev);
1440extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1441extern void radeon_surface_init(struct radeon_device *rdev);
1442extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1443extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1444extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1445extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1446extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 1447extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1448extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 1449extern int radeon_resume_kms(struct drm_device *dev);
1450extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
6cf8a3f5 1451
21f9a437
JG		 1452/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1453extern bool r600_card_posted(struct radeon_device *rdev);
1454extern void r600_cp_stop(struct radeon_device *rdev);
fe251e2f 1455extern int r600_cp_start(struct radeon_device *rdev);
21f9a437
JG		 1456extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1457extern int r600_cp_resume(struct radeon_device *rdev);
655efd3d 1458extern void r600_cp_fini(struct radeon_device *rdev);
21f9a437 1459extern int r600_count_pipe_bits(uint32_t val);
21f9a437 1460extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1461extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1462extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1463extern int r600_ib_test(struct radeon_device *rdev);
1464extern int r600_ring_test(struct radeon_device *rdev);
21f9a437
JG		 1465extern void r600_scratch_init(struct radeon_device *rdev);
1466extern int r600_blit_init(struct radeon_device *rdev);
1467extern void r600_blit_fini(struct radeon_device *rdev);
d8f60cfc 1468extern int r600_init_microcode(struct radeon_device *rdev);
a2d07b74 1469extern int r600_asic_reset(struct radeon_device *rdev);
d8f60cfc
AD		 1470/* r600 irq */
1471extern int r600_irq_init(struct radeon_device *rdev);
1472extern void r600_irq_fini(struct radeon_device *rdev);
1473extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1474extern int r600_irq_set(struct radeon_device *rdev);
0c45249f 1475extern void r600_irq_suspend(struct radeon_device *rdev);
45f9a39b
AD		 1476extern void r600_disable_interrupts(struct radeon_device *rdev);
1477extern void r600_rlc_stop(struct radeon_device *rdev);
0c45249f 1478/* r600 audio */
dafc3bd5
CK		 1479extern int r600_audio_init(struct radeon_device *rdev);
1480extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1481extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
58bd0863
CK		 1482extern int r600_audio_channels(struct radeon_device *rdev);
1483extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1484extern int r600_audio_rate(struct radeon_device *rdev);
1485extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1486extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
f2594933 1487extern void r600_audio_schedule_polling(struct radeon_device *rdev);
58bd0863
CK		 1488extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1489extern void r600_audio_disable_polling(struct drm_encoder *encoder);
dafc3bd5
CK		 1490extern void r600_audio_fini(struct radeon_device *rdev);
1491extern void r600_hdmi_init(struct drm_encoder *encoder);
2cd6218c
RM		 1492extern void r600_hdmi_enable(struct drm_encoder *encoder);
1493extern void r600_hdmi_disable(struct drm_encoder *encoder);
dafc3bd5
CK		 1494extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1495extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
58bd0863 1496extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
dafc3bd5 1497
0ef0c1f7 1498extern void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
fe251e2f
AD		 1499extern void r700_cp_stop(struct radeon_device *rdev);
1500extern void r700_cp_fini(struct radeon_device *rdev);
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AD		 1501extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1502extern int evergreen_irq_set(struct radeon_device *rdev);
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AD		 1503extern int evergreen_blit_init(struct radeon_device *rdev);
1504extern void evergreen_blit_fini(struct radeon_device *rdev);
fe251e2f 1505
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AD		 1506extern int ni_init_microcode(struct radeon_device *rdev);
1507extern int btc_mc_load_microcode(struct radeon_device *rdev);
1508
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AM		 1509/* radeon_acpi.c */
1510#if defined(CONFIG_ACPI)
1511extern int radeon_acpi_init(struct radeon_device *rdev);
1512#else
1513static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1514#endif
1515
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AD		 1516/* evergreen */
1517struct evergreen_mc_save {
1518 u32 vga_control[6];
1519 u32 vga_render_control;
1520 u32 vga_hdp_control;
1521 u32 crtc_control[6];
1522};
1523
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JG		 1524#include "radeon_object.h"
1525
771fe6b9 1526#endif
kernel source for telekom puls (alcatel/mediatek)