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UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / r600_blit_kms.c
CommitLineData
27849044
AD		 1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
3ce0a23d
JG		 28#include "radeon.h"
29
30#include "r600d.h"
31#include "r600_blit_shaders.h"
86a4d69c 32#include "radeon_blit_common.h"
7dbf41db 33
3ce0a23d
JG		 34/* emits 21 on rv770+, 23 on r600 */
35static void
36set_render_target(struct radeon_device *rdev, int format,
37 int w, int h, u64 gpu_addr)
38{
e32eb50d 39 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 40 u32 cb_color_info;
41 int pitch, slice;
42
d964fc54 43 h = ALIGN(h, 8);
3ce0a23d
JG		 44 if (h < 8)
45 h = 8;
46
3a38612e
IH		 47 cb_color_info = CB_FORMAT(format) |
48 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
49 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
3ce0a23d
JG		 50 pitch = (w / 8) - 1;
51 slice = ((w * h) / 64) - 1;
52
e32eb50d
CK		 53 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
54 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
55 radeon_ring_write(ring, gpu_addr >> 8);
3ce0a23d
JG		 56
57 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
e32eb50d
CK		 58 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
59 radeon_ring_write(ring, 2 << 0);
3ce0a23d
JG		 60 }
61
e32eb50d
CK		 62 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
63 radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
64 radeon_ring_write(ring, (pitch << 0) | (slice << 10));
3ce0a23d 65
e32eb50d
CK		 66 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
67 radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
68 radeon_ring_write(ring, 0);
3ce0a23d 69
e32eb50d
CK		 70 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
71 radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
72 radeon_ring_write(ring, cb_color_info);
3ce0a23d 73
e32eb50d
CK		 74 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
75 radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
76 radeon_ring_write(ring, 0);
3ce0a23d 77
e32eb50d
CK		 78 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
79 radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
80 radeon_ring_write(ring, 0);
3ce0a23d 81
e32eb50d
CK		 82 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
83 radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
84 radeon_ring_write(ring, 0);
3ce0a23d
JG		 85}
86
87/* emits 5dw */
88static void
89cp_set_surface_sync(struct radeon_device *rdev,
90 u32 sync_type, u32 size,
91 u64 mc_addr)
92{
e32eb50d 93 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 94 u32 cp_coher_size;
95
96 if (size == 0xffffffff)
97 cp_coher_size = 0xffffffff;
98 else
99 cp_coher_size = ((size + 255) >> 8);
100
e32eb50d
CK		 101 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
102 radeon_ring_write(ring, sync_type);
103 radeon_ring_write(ring, cp_coher_size);
104 radeon_ring_write(ring, mc_addr >> 8);
105 radeon_ring_write(ring, 10); /* poll interval */
3ce0a23d
JG		 106}
107
108/* emits 21dw + 1 surface sync = 26dw */
109static void
110set_shaders(struct radeon_device *rdev)
111{
e32eb50d 112 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 113 u64 gpu_addr;
114 u32 sq_pgm_resources;
115
116 /* setup shader regs */
117 sq_pgm_resources = (1 << 0);
118
119 /* VS */
120 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
e32eb50d
CK		 121 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
122 radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
123 radeon_ring_write(ring, gpu_addr >> 8);
3ce0a23d 124
e32eb50d
CK		 125 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
126 radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
127 radeon_ring_write(ring, sq_pgm_resources);
3ce0a23d 128
e32eb50d
CK		 129 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
130 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
131 radeon_ring_write(ring, 0);
3ce0a23d
JG		 132
133 /* PS */
134 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
e32eb50d
CK		 135 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
136 radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
137 radeon_ring_write(ring, gpu_addr >> 8);
3ce0a23d 138
e32eb50d
CK		 139 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
140 radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
141 radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
3ce0a23d 142
e32eb50d
CK		 143 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
144 radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
145 radeon_ring_write(ring, 2);
3ce0a23d 146
e32eb50d
CK		 147 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
148 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
149 radeon_ring_write(ring, 0);
3ce0a23d 150
119e20dc 151 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
3ce0a23d
JG		 152 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
153}
154
155/* emits 9 + 1 sync (5) = 14*/
156static void
157set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
158{
e32eb50d 159 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 160 u32 sq_vtx_constant_word2;
161
3a38612e
IH		 162 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
163 SQ_VTXC_STRIDE(16);
4eace7fd 164#ifdef __BIG_ENDIAN
3a38612e 165 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
4eace7fd 166#endif
3ce0a23d 167
e32eb50d
CK		 168 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
169 radeon_ring_write(ring, 0x460);
170 radeon_ring_write(ring, gpu_addr & 0xffffffff);
171 radeon_ring_write(ring, 48 - 1);
172 radeon_ring_write(ring, sq_vtx_constant_word2);
173 radeon_ring_write(ring, 1 << 0);
174 radeon_ring_write(ring, 0);
175 radeon_ring_write(ring, 0);
176 radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
3ce0a23d
JG		 177
178 if ((rdev->family == CHIP_RV610) ||
179 (rdev->family == CHIP_RV620) ||
180 (rdev->family == CHIP_RS780) ||
181 (rdev->family == CHIP_RS880) ||
182 (rdev->family == CHIP_RV710))
183 cp_set_surface_sync(rdev,
184 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
185 else
186 cp_set_surface_sync(rdev,
187 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
188}
189
190/* emits 9 */
191static void
192set_tex_resource(struct radeon_device *rdev,
193 int format, int w, int h, int pitch,
9bb7703c 194 u64 gpu_addr, u32 size)
3ce0a23d 195{
e32eb50d 196 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 197 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
198
199 if (h < 1)
200 h = 1;
201
3a38612e
IH		 202 sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
203 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
204 sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
205 S_038000_TEX_WIDTH(w - 1);
3ce0a23d 206
3a38612e
IH		 207 sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
208 sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
3ce0a23d 209
3a38612e
IH		 210 sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
211 S_038010_DST_SEL_X(SQ_SEL_X) |
212 S_038010_DST_SEL_Y(SQ_SEL_Y) |
213 S_038010_DST_SEL_Z(SQ_SEL_Z) |
214 S_038010_DST_SEL_W(SQ_SEL_W);
3ce0a23d 215
9bb7703c
AD		 216 cp_set_surface_sync(rdev,
217 PACKET3_TC_ACTION_ENA, size, gpu_addr);
218
e32eb50d
CK		 219 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
220 radeon_ring_write(ring, 0);
221 radeon_ring_write(ring, sq_tex_resource_word0);
222 radeon_ring_write(ring, sq_tex_resource_word1);
223 radeon_ring_write(ring, gpu_addr >> 8);
224 radeon_ring_write(ring, gpu_addr >> 8);
225 radeon_ring_write(ring, sq_tex_resource_word4);
226 radeon_ring_write(ring, 0);
227 radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
3ce0a23d
JG		 228}
229
230/* emits 12 */
231static void
232set_scissors(struct radeon_device *rdev, int x1, int y1,
233 int x2, int y2)
234{
e32eb50d
CK		 235 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
236 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
237 radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
238 radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
239 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
240
241 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
242 radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
243 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
244 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
245
246 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
247 radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
248 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
249 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
3ce0a23d
JG		 250}
251
252/* emits 10 */
253static void
254draw_auto(struct radeon_device *rdev)
255{
e32eb50d
CK		 256 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
257 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
258 radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
259 radeon_ring_write(ring, DI_PT_RECTLIST);
3ce0a23d 260
e32eb50d
CK		 261 radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
262 radeon_ring_write(ring,
4eace7fd
CC		 263#ifdef __BIG_ENDIAN
264 (2 << 2) |
265#endif
266 DI_INDEX_SIZE_16_BIT);
3ce0a23d 267
e32eb50d
CK		 268 radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
269 radeon_ring_write(ring, 1);
3ce0a23d 270
e32eb50d
CK		 271 radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
272 radeon_ring_write(ring, 3);
273 radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
3ce0a23d
JG		 274
275}
276
277/* emits 14 */
278static void
279set_default_state(struct radeon_device *rdev)
280{
e32eb50d 281 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 282 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
283 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
284 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
285 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
286 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
287 u64 gpu_addr;
119e20dc 288 int dwords;
3ce0a23d
JG		 289
290 switch (rdev->family) {
291 case CHIP_R600:
292 num_ps_gprs = 192;
293 num_vs_gprs = 56;
294 num_temp_gprs = 4;
295 num_gs_gprs = 0;
296 num_es_gprs = 0;
297 num_ps_threads = 136;
298 num_vs_threads = 48;
299 num_gs_threads = 4;
300 num_es_threads = 4;
301 num_ps_stack_entries = 128;
302 num_vs_stack_entries = 128;
303 num_gs_stack_entries = 0;
304 num_es_stack_entries = 0;
305 break;
306 case CHIP_RV630:
307 case CHIP_RV635:
308 num_ps_gprs = 84;
309 num_vs_gprs = 36;
310 num_temp_gprs = 4;
311 num_gs_gprs = 0;
312 num_es_gprs = 0;
313 num_ps_threads = 144;
314 num_vs_threads = 40;
315 num_gs_threads = 4;
316 num_es_threads = 4;
317 num_ps_stack_entries = 40;
318 num_vs_stack_entries = 40;
319 num_gs_stack_entries = 32;
320 num_es_stack_entries = 16;
321 break;
322 case CHIP_RV610:
323 case CHIP_RV620:
324 case CHIP_RS780:
325 case CHIP_RS880:
326 default:
327 num_ps_gprs = 84;
328 num_vs_gprs = 36;
329 num_temp_gprs = 4;
330 num_gs_gprs = 0;
331 num_es_gprs = 0;
332 num_ps_threads = 136;
333 num_vs_threads = 48;
334 num_gs_threads = 4;
335 num_es_threads = 4;
336 num_ps_stack_entries = 40;
337 num_vs_stack_entries = 40;
338 num_gs_stack_entries = 32;
339 num_es_stack_entries = 16;
340 break;
341 case CHIP_RV670:
342 num_ps_gprs = 144;
343 num_vs_gprs = 40;
344 num_temp_gprs = 4;
345 num_gs_gprs = 0;
346 num_es_gprs = 0;
347 num_ps_threads = 136;
348 num_vs_threads = 48;
349 num_gs_threads = 4;
350 num_es_threads = 4;
351 num_ps_stack_entries = 40;
352 num_vs_stack_entries = 40;
353 num_gs_stack_entries = 32;
354 num_es_stack_entries = 16;
355 break;
356 case CHIP_RV770:
357 num_ps_gprs = 192;
358 num_vs_gprs = 56;
359 num_temp_gprs = 4;
360 num_gs_gprs = 0;
361 num_es_gprs = 0;
362 num_ps_threads = 188;
363 num_vs_threads = 60;
364 num_gs_threads = 0;
365 num_es_threads = 0;
366 num_ps_stack_entries = 256;
367 num_vs_stack_entries = 256;
368 num_gs_stack_entries = 0;
369 num_es_stack_entries = 0;
370 break;
371 case CHIP_RV730:
372 case CHIP_RV740:
373 num_ps_gprs = 84;
374 num_vs_gprs = 36;
375 num_temp_gprs = 4;
376 num_gs_gprs = 0;
377 num_es_gprs = 0;
378 num_ps_threads = 188;
379 num_vs_threads = 60;
380 num_gs_threads = 0;
381 num_es_threads = 0;
382 num_ps_stack_entries = 128;
383 num_vs_stack_entries = 128;
384 num_gs_stack_entries = 0;
385 num_es_stack_entries = 0;
386 break;
387 case CHIP_RV710:
388 num_ps_gprs = 192;
389 num_vs_gprs = 56;
390 num_temp_gprs = 4;
391 num_gs_gprs = 0;
392 num_es_gprs = 0;
393 num_ps_threads = 144;
394 num_vs_threads = 48;
395 num_gs_threads = 0;
396 num_es_threads = 0;
397 num_ps_stack_entries = 128;
398 num_vs_stack_entries = 128;
399 num_gs_stack_entries = 0;
400 num_es_stack_entries = 0;
401 break;
402 }
403
404 if ((rdev->family == CHIP_RV610) ||
405 (rdev->family == CHIP_RV620) ||
406 (rdev->family == CHIP_RS780) ||
ee59f2b4 407 (rdev->family == CHIP_RS880) ||
3ce0a23d
JG		 408 (rdev->family == CHIP_RV710))
409 sq_config = 0;
410 else
411 sq_config = VC_ENABLE;
412
413 sq_config |= (DX9_CONSTS |
414 ALU_INST_PREFER_VECTOR |
415 PS_PRIO(0) |
416 VS_PRIO(1) |
417 GS_PRIO(2) |
418 ES_PRIO(3));
419
420 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
421 NUM_VS_GPRS(num_vs_gprs) |
422 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
423 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
424 NUM_ES_GPRS(num_es_gprs));
425 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
426 NUM_VS_THREADS(num_vs_threads) |
427 NUM_GS_THREADS(num_gs_threads) |
428 NUM_ES_THREADS(num_es_threads));
429 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
430 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
431 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
432 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
433
434 /* emit an IB pointing at default state */
d964fc54 435 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
3ce0a23d 436 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
e32eb50d
CK		 437 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
438 radeon_ring_write(ring,
4eace7fd
CC		 439#ifdef __BIG_ENDIAN
440 (2 << 0) |
441#endif
442 (gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 443 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
444 radeon_ring_write(ring, dwords);
3ce0a23d 445
3ce0a23d 446 /* SQ config */
e32eb50d
CK		 447 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
448 radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
449 radeon_ring_write(ring, sq_config);
450 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
451 radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
452 radeon_ring_write(ring, sq_thread_resource_mgmt);
453 radeon_ring_write(ring, sq_stack_resource_mgmt_1);
454 radeon_ring_write(ring, sq_stack_resource_mgmt_2);
3ce0a23d
JG		 455}
456
52b53a0b
IH		 457#define I2F_MAX_BITS 15
458#define I2F_MAX_INPUT ((1 << I2F_MAX_BITS) - 1)
459#define I2F_SHIFT (24 - I2F_MAX_BITS)
460
461/*
462 * Converts unsigned integer into 32-bit IEEE floating point representation.
463 * Conversion is not universal and only works for the range from 0
464 * to 2^I2F_MAX_BITS-1. Currently we only use it with inputs between
465 * 0 and 16384 (inclusive), so I2F_MAX_BITS=15 is enough. If necessary,
466 * I2F_MAX_BITS can be increased, but that will add to the loop iterations
467 * and slow us down. Conversion is done by shifting the input and counting
468 * down until the first 1 reaches bit position 23. The resulting counter
469 * and the shifted input are, respectively, the exponent and the fraction.
470 * The sign is always zero.
471 */
ce580fab 472static uint32_t i2f(uint32_t input)
3ce0a23d
JG		 473{
474 u32 result, i, exponent, fraction;
475
52b53a0b
IH		 476 WARN_ON_ONCE(input > I2F_MAX_INPUT);
477
478 if ((input & I2F_MAX_INPUT) == 0)
479 result = 0;
3ce0a23d 480 else {
52b53a0b
IH		 481 exponent = 126 + I2F_MAX_BITS;
482 fraction = (input & I2F_MAX_INPUT) << I2F_SHIFT;
483
484 for (i = 0; i < I2F_MAX_BITS; i++) {
3ce0a23d
JG		 485 if (fraction & 0x800000)
486 break;
487 else {
52b53a0b 488 fraction = fraction << 1;
3ce0a23d
JG		 489 exponent = exponent - 1;
490 }
491 }
52b53a0b 492 result = exponent << 23 | (fraction & 0x7fffff);
3ce0a23d
JG		 493 }
494 return result;
495}
496
497int r600_blit_init(struct radeon_device *rdev)
498{
499 u32 obj_size;
4eace7fd 500 int i, r, dwords;
3ce0a23d 501 void *ptr;
119e20dc
AD		 502 u32 packet2s[16];
503 int num_packet2s = 0;
3ce0a23d 504
8eec9d6f
IH		 505 rdev->r600_blit.primitives.set_render_target = set_render_target;
506 rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
507 rdev->r600_blit.primitives.set_shaders = set_shaders;
508 rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
509 rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
510 rdev->r600_blit.primitives.set_scissors = set_scissors;
511 rdev->r600_blit.primitives.draw_auto = draw_auto;
512 rdev->r600_blit.primitives.set_default_state = set_default_state;
513
220907d9
CK		 514 rdev->r600_blit.ring_size_common = 8; /* sync semaphore */
515 rdev->r600_blit.ring_size_common += 40; /* shaders + def state */
8eec9d6f 516 rdev->r600_blit.ring_size_common += 5; /* done copy */
77b1bad4 517 rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
8eec9d6f
IH		 518
519 rdev->r600_blit.ring_size_per_loop = 76;
520 /* set_render_target emits 2 extra dwords on rv6xx */
521 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
522 rdev->r600_blit.ring_size_per_loop += 2;
523
524 rdev->r600_blit.max_dim = 8192;
525
3ce0a23d
JG		 526 rdev->r600_blit.state_offset = 0;
527
528 if (rdev->family >= CHIP_RV770)
119e20dc 529 rdev->r600_blit.state_len = r7xx_default_size;
3ce0a23d 530 else
119e20dc
AD		 531 rdev->r600_blit.state_len = r6xx_default_size;
532
533 dwords = rdev->r600_blit.state_len;
534 while (dwords & 0xf) {
4eace7fd 535 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
119e20dc
AD		 536 dwords++;
537 }
3ce0a23d 538
119e20dc 539 obj_size = dwords * 4;
3ce0a23d
JG		 540 obj_size = ALIGN(obj_size, 256);
541
542 rdev->r600_blit.vs_offset = obj_size;
543 obj_size += r6xx_vs_size * 4;
544 obj_size = ALIGN(obj_size, 256);
545
546 rdev->r600_blit.ps_offset = obj_size;
547 obj_size += r6xx_ps_size * 4;
548 obj_size = ALIGN(obj_size, 256);
549
6f72a631
CK		 550 /* pin copy shader into vram if not already initialized */
551 if (rdev->r600_blit.shader_obj == NULL) {
552 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true,
553 RADEON_GEM_DOMAIN_VRAM,
554 NULL, &rdev->r600_blit.shader_obj);
555 if (r) {
556 DRM_ERROR("r600 failed to allocate shader\n");
557 return r;
558 }
559
560 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
561 if (unlikely(r != 0))
562 return r;
563 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
564 &rdev->r600_blit.shader_gpu_addr);
565 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
566 if (r) {
567 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
568 return r;
569 }
3ce0a23d
JG		 570 }
571
bc1a631e
DA		 572 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
573 obj_size,
3ce0a23d
JG		 574 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
575
4c788679
JG		 576 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
577 if (unlikely(r != 0))
578 return r;
579 r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
3ce0a23d
JG		 580 if (r) {
581 DRM_ERROR("failed to map blit object %d\n", r);
582 return r;
583 }
3ce0a23d 584 if (rdev->family >= CHIP_RV770)
119e20dc
AD		 585 memcpy_toio(ptr + rdev->r600_blit.state_offset,
586 r7xx_default_state, rdev->r600_blit.state_len * 4);
3ce0a23d 587 else
119e20dc
AD		 588 memcpy_toio(ptr + rdev->r600_blit.state_offset,
589 r6xx_default_state, rdev->r600_blit.state_len * 4);
590 if (num_packet2s)
591 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
592 packet2s, num_packet2s * 4);
4eace7fd
CC		 593 for (i = 0; i < r6xx_vs_size; i++)
594 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
595 for (i = 0; i < r6xx_ps_size; i++)
596 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
4c788679
JG		 597 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
598 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
b70d6bb3 599
53595338 600 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
3ce0a23d
JG		 601 return 0;
602}
603
604void r600_blit_fini(struct radeon_device *rdev)
605{
4c788679
JG		 606 int r;
607
53595338 608 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
30d2d9a5
JG		 609 if (rdev->r600_blit.shader_obj == NULL)
610 return;
611 /* If we can't reserve the bo, unref should be enough to destroy
612 * it when it becomes idle.
613 */
4c788679 614 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
30d2d9a5
JG		 615 if (!r) {
616 radeon_bo_unpin(rdev->r600_blit.shader_obj);
617 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
4c788679 618 }
4c788679 619 radeon_bo_unref(&rdev->r600_blit.shader_obj);
3ce0a23d
JG		 620}
621
b3530963 622static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
8eec9d6f 623 int *width, int *height, int max_dim)
7dbf41db
AD		 624{
625 unsigned max_pages;
b3530963 626 unsigned pages = num_gpu_pages;
7dbf41db
AD		 627 int w, h;
628
b3530963 629 if (num_gpu_pages == 0) {
7dbf41db
AD		 630 /* not supposed to be called with no pages, but just in case */
631 h = 0;
632 w = 0;
633 pages = 0;
634 WARN_ON(1);
635 } else {
636 int rect_order = 2;
637 h = RECT_UNIT_H;
b3530963 638 while (num_gpu_pages / rect_order) {
7dbf41db
AD		 639 h *= 2;
640 rect_order *= 4;
8eec9d6f
IH		 641 if (h >= max_dim) {
642 h = max_dim;
7dbf41db
AD		 643 break;
644 }
645 }
8eec9d6f 646 max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
7dbf41db
AD		 647 if (pages > max_pages)
648 pages = max_pages;
649 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
650 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
651 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
652 BUG_ON(pages == 0);
653 }
654
655
656 DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
657
658 /* return width and height only of the caller wants it */
659 if (height)
660 *height = h;
661 if (width)
662 *width = w;
663
664 return pages;
665}
666
667
f237750f 668int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
220907d9
CK		 669 struct radeon_fence **fence, struct radeon_sa_bo **vb,
670 struct radeon_semaphore **sem)
3ce0a23d 671{
e32eb50d 672 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d 673 int r;
7dbf41db 674 int ring_size;
8eec9d6f
IH		 675 int num_loops = 0;
676 int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
7cbb355e 677
7dbf41db 678 /* num loops */
b3530963
IH		 679 while (num_gpu_pages) {
680 num_gpu_pages -=
681 r600_blit_create_rect(num_gpu_pages, NULL, NULL,
682 rdev->r600_blit.max_dim);
7dbf41db
AD		 683 num_loops++;
684 }
3ce0a23d 685
69e130a6 686 /* 48 bytes for vertex per loop */
f237750f
CK		 687 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb,
688 (num_loops*48)+256, 256, true);
689 if (r) {
69e130a6 690 return r;
f237750f 691 }
69e130a6 692
220907d9
CK		 693 r = radeon_semaphore_create(rdev, sem);
694 if (r) {
695 radeon_sa_bo_free(rdev, vb, NULL);
696 return r;
697 }
698
7cbb355e
DA		 699 /* calculate number of loops correctly */
700 ring_size = num_loops * dwords_per_loop;
8eec9d6f 701 ring_size += rdev->r600_blit.ring_size_common;
e32eb50d 702 r = radeon_ring_lock(rdev, ring, ring_size);
f237750f
CK		 703 if (r) {
704 radeon_sa_bo_free(rdev, vb, NULL);
220907d9 705 radeon_semaphore_free(rdev, sem, NULL);
ff82f052 706 return r;
f237750f 707 }
3ce0a23d 708
220907d9
CK		 709 if (radeon_fence_need_sync(*fence, RADEON_RING_TYPE_GFX_INDEX)) {
710 radeon_semaphore_sync_rings(rdev, *sem, (*fence)->ring,
711 RADEON_RING_TYPE_GFX_INDEX);
712 radeon_fence_note_sync(*fence, RADEON_RING_TYPE_GFX_INDEX);
713 } else {
714 radeon_semaphore_free(rdev, sem, NULL);
715 }
716
8eec9d6f
IH		 717 rdev->r600_blit.primitives.set_default_state(rdev);
718 rdev->r600_blit.primitives.set_shaders(rdev);
3ce0a23d
JG		 719 return 0;
720}
721
876dc9f3 722void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
220907d9 723 struct radeon_sa_bo *vb, struct radeon_semaphore *sem)
3ce0a23d 724{
f237750f 725 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 726 int r;
727
876dc9f3 728 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
f237750f
CK		 729 if (r) {
730 radeon_ring_unlock_undo(rdev, ring);
731 return;
732 }
3ce0a23d 733
f237750f 734 radeon_ring_unlock_commit(rdev, ring);
876dc9f3 735 radeon_sa_bo_free(rdev, &vb, *fence);
220907d9 736 radeon_semaphore_free(rdev, &sem, *fence);
3ce0a23d
JG		 737}
738
739void r600_kms_blit_copy(struct radeon_device *rdev,
740 u64 src_gpu_addr, u64 dst_gpu_addr,
f237750f
CK		 741 unsigned num_gpu_pages,
742 struct radeon_sa_bo *vb)
3ce0a23d 743{
3ce0a23d 744 u64 vb_gpu_addr;
f237750f 745 u32 *vb_cpu_addr;
3ce0a23d 746
f237750f
CK		 747 DRM_DEBUG("emitting copy %16llx %16llx %d\n",
748 src_gpu_addr, dst_gpu_addr, num_gpu_pages);
749 vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb);
750 vb_gpu_addr = radeon_sa_bo_gpu_addr(vb);
3ce0a23d 751
b3530963 752 while (num_gpu_pages) {
7dbf41db
AD		 753 int w, h;
754 unsigned size_in_bytes;
8eec9d6f 755 unsigned pages_per_loop =
b3530963 756 r600_blit_create_rect(num_gpu_pages, &w, &h,
8eec9d6f 757 rdev->r600_blit.max_dim);
3ce0a23d 758
7dbf41db
AD		 759 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
760 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
3ce0a23d 761
f237750f
CK		 762 vb_cpu_addr[0] = 0;
763 vb_cpu_addr[1] = 0;
764 vb_cpu_addr[2] = 0;
765 vb_cpu_addr[3] = 0;
3ce0a23d 766
f237750f
CK		 767 vb_cpu_addr[4] = 0;
768 vb_cpu_addr[5] = i2f(h);
769 vb_cpu_addr[6] = 0;
770 vb_cpu_addr[7] = i2f(h);
3ce0a23d 771
f237750f
CK		 772 vb_cpu_addr[8] = i2f(w);
773 vb_cpu_addr[9] = i2f(h);
774 vb_cpu_addr[10] = i2f(w);
775 vb_cpu_addr[11] = i2f(h);
3ce0a23d 776
8eec9d6f 777 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
9bb7703c 778 w, h, w, src_gpu_addr, size_in_bytes);
8eec9d6f
IH		 779 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
780 w, h, dst_gpu_addr);
781 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
8eec9d6f
IH		 782 rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
783 rdev->r600_blit.primitives.draw_auto(rdev);
784 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
7dbf41db
AD		 785 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
786 size_in_bytes, dst_gpu_addr);
787
f237750f
CK		 788 vb_cpu_addr += 12;
789 vb_gpu_addr += 4*12;
7dbf41db
AD		 790 src_gpu_addr += size_in_bytes;
791 dst_gpu_addr += size_in_bytes;
b3530963 792 num_gpu_pages -= pages_per_loop;
3ce0a23d
JG		 793 }
794}
kernel source for telekom puls (alcatel/mediatek)