projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: add PRIME support (v2)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / r600_blit_kms.c
CommitLineData
27849044
AD		 1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 */
25
3ce0a23d
JG		 26#include "drmP.h"
27#include "drm.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30
31#include "r600d.h"
32#include "r600_blit_shaders.h"
86a4d69c 33#include "radeon_blit_common.h"
7dbf41db 34
3ce0a23d
JG		 35/* emits 21 on rv770+, 23 on r600 */
36static void
37set_render_target(struct radeon_device *rdev, int format,
38 int w, int h, u64 gpu_addr)
39{
e32eb50d 40 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 41 u32 cb_color_info;
42 int pitch, slice;
43
d964fc54 44 h = ALIGN(h, 8);
3ce0a23d
JG		 45 if (h < 8)
46 h = 8;
47
3a38612e
IH		 48 cb_color_info = CB_FORMAT(format) |
49 CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) |
50 CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1);
3ce0a23d
JG		 51 pitch = (w / 8) - 1;
52 slice = ((w * h) / 64) - 1;
53
e32eb50d
CK		 54 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
55 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
56 radeon_ring_write(ring, gpu_addr >> 8);
3ce0a23d
JG		 57
58 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
e32eb50d
CK		 59 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
60 radeon_ring_write(ring, 2 << 0);
3ce0a23d
JG		 61 }
62
e32eb50d
CK		 63 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
64 radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
65 radeon_ring_write(ring, (pitch << 0) | (slice << 10));
3ce0a23d 66
e32eb50d
CK		 67 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
68 radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
69 radeon_ring_write(ring, 0);
3ce0a23d 70
e32eb50d
CK		 71 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
72 radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
73 radeon_ring_write(ring, cb_color_info);
3ce0a23d 74
e32eb50d
CK		 75 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
76 radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
77 radeon_ring_write(ring, 0);
3ce0a23d 78
e32eb50d
CK		 79 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
80 radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
81 radeon_ring_write(ring, 0);
3ce0a23d 82
e32eb50d
CK		 83 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
84 radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
85 radeon_ring_write(ring, 0);
3ce0a23d
JG		 86}
87
88/* emits 5dw */
89static void
90cp_set_surface_sync(struct radeon_device *rdev,
91 u32 sync_type, u32 size,
92 u64 mc_addr)
93{
e32eb50d 94 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 95 u32 cp_coher_size;
96
97 if (size == 0xffffffff)
98 cp_coher_size = 0xffffffff;
99 else
100 cp_coher_size = ((size + 255) >> 8);
101
e32eb50d
CK		 102 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
103 radeon_ring_write(ring, sync_type);
104 radeon_ring_write(ring, cp_coher_size);
105 radeon_ring_write(ring, mc_addr >> 8);
106 radeon_ring_write(ring, 10); /* poll interval */
3ce0a23d
JG		 107}
108
109/* emits 21dw + 1 surface sync = 26dw */
110static void
111set_shaders(struct radeon_device *rdev)
112{
e32eb50d 113 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 114 u64 gpu_addr;
115 u32 sq_pgm_resources;
116
117 /* setup shader regs */
118 sq_pgm_resources = (1 << 0);
119
120 /* VS */
121 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
e32eb50d
CK		 122 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
123 radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
124 radeon_ring_write(ring, gpu_addr >> 8);
3ce0a23d 125
e32eb50d
CK		 126 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
127 radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
128 radeon_ring_write(ring, sq_pgm_resources);
3ce0a23d 129
e32eb50d
CK		 130 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
131 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
132 radeon_ring_write(ring, 0);
3ce0a23d
JG		 133
134 /* PS */
135 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
e32eb50d
CK		 136 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
137 radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
138 radeon_ring_write(ring, gpu_addr >> 8);
3ce0a23d 139
e32eb50d
CK		 140 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
141 radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
142 radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
3ce0a23d 143
e32eb50d
CK		 144 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
145 radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
146 radeon_ring_write(ring, 2);
3ce0a23d 147
e32eb50d
CK		 148 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
149 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
150 radeon_ring_write(ring, 0);
3ce0a23d 151
119e20dc 152 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
3ce0a23d
JG		 153 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
154}
155
156/* emits 9 + 1 sync (5) = 14*/
157static void
158set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
159{
e32eb50d 160 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 161 u32 sq_vtx_constant_word2;
162
3a38612e
IH		 163 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
164 SQ_VTXC_STRIDE(16);
4eace7fd 165#ifdef __BIG_ENDIAN
3a38612e 166 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
4eace7fd 167#endif
3ce0a23d 168
e32eb50d
CK		 169 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
170 radeon_ring_write(ring, 0x460);
171 radeon_ring_write(ring, gpu_addr & 0xffffffff);
172 radeon_ring_write(ring, 48 - 1);
173 radeon_ring_write(ring, sq_vtx_constant_word2);
174 radeon_ring_write(ring, 1 << 0);
175 radeon_ring_write(ring, 0);
176 radeon_ring_write(ring, 0);
177 radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
3ce0a23d
JG		 178
179 if ((rdev->family == CHIP_RV610) ||
180 (rdev->family == CHIP_RV620) ||
181 (rdev->family == CHIP_RS780) ||
182 (rdev->family == CHIP_RS880) ||
183 (rdev->family == CHIP_RV710))
184 cp_set_surface_sync(rdev,
185 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
186 else
187 cp_set_surface_sync(rdev,
188 PACKET3_VC_ACTION_ENA, 48, gpu_addr);
189}
190
191/* emits 9 */
192static void
193set_tex_resource(struct radeon_device *rdev,
194 int format, int w, int h, int pitch,
9bb7703c 195 u64 gpu_addr, u32 size)
3ce0a23d 196{
e32eb50d 197 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 198 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
199
200 if (h < 1)
201 h = 1;
202
3a38612e
IH		 203 sq_tex_resource_word0 = S_038000_DIM(V_038000_SQ_TEX_DIM_2D) |
204 S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
205 sq_tex_resource_word0 |= S_038000_PITCH((pitch >> 3) - 1) |
206 S_038000_TEX_WIDTH(w - 1);
3ce0a23d 207
3a38612e
IH		 208 sq_tex_resource_word1 = S_038004_DATA_FORMAT(format);
209 sq_tex_resource_word1 |= S_038004_TEX_HEIGHT(h - 1);
3ce0a23d 210
3a38612e
IH		 211 sq_tex_resource_word4 = S_038010_REQUEST_SIZE(1) |
212 S_038010_DST_SEL_X(SQ_SEL_X) |
213 S_038010_DST_SEL_Y(SQ_SEL_Y) |
214 S_038010_DST_SEL_Z(SQ_SEL_Z) |
215 S_038010_DST_SEL_W(SQ_SEL_W);
3ce0a23d 216
9bb7703c
AD		 217 cp_set_surface_sync(rdev,
218 PACKET3_TC_ACTION_ENA, size, gpu_addr);
219
e32eb50d
CK		 220 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
221 radeon_ring_write(ring, 0);
222 radeon_ring_write(ring, sq_tex_resource_word0);
223 radeon_ring_write(ring, sq_tex_resource_word1);
224 radeon_ring_write(ring, gpu_addr >> 8);
225 radeon_ring_write(ring, gpu_addr >> 8);
226 radeon_ring_write(ring, sq_tex_resource_word4);
227 radeon_ring_write(ring, 0);
228 radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
3ce0a23d
JG		 229}
230
231/* emits 12 */
232static void
233set_scissors(struct radeon_device *rdev, int x1, int y1,
234 int x2, int y2)
235{
e32eb50d
CK		 236 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
237 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
238 radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
239 radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
240 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
241
242 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
243 radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
244 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
245 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
246
247 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
248 radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
249 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
250 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
3ce0a23d
JG		 251}
252
253/* emits 10 */
254static void
255draw_auto(struct radeon_device *rdev)
256{
e32eb50d
CK		 257 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
258 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
259 radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
260 radeon_ring_write(ring, DI_PT_RECTLIST);
3ce0a23d 261
e32eb50d
CK		 262 radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
263 radeon_ring_write(ring,
4eace7fd
CC		 264#ifdef __BIG_ENDIAN
265 (2 << 2) |
266#endif
267 DI_INDEX_SIZE_16_BIT);
3ce0a23d 268
e32eb50d
CK		 269 radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
270 radeon_ring_write(ring, 1);
3ce0a23d 271
e32eb50d
CK		 272 radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
273 radeon_ring_write(ring, 3);
274 radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
3ce0a23d
JG		 275
276}
277
278/* emits 14 */
279static void
280set_default_state(struct radeon_device *rdev)
281{
e32eb50d 282 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 283 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
284 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
285 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
286 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
287 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
288 u64 gpu_addr;
119e20dc 289 int dwords;
3ce0a23d
JG		 290
291 switch (rdev->family) {
292 case CHIP_R600:
293 num_ps_gprs = 192;
294 num_vs_gprs = 56;
295 num_temp_gprs = 4;
296 num_gs_gprs = 0;
297 num_es_gprs = 0;
298 num_ps_threads = 136;
299 num_vs_threads = 48;
300 num_gs_threads = 4;
301 num_es_threads = 4;
302 num_ps_stack_entries = 128;
303 num_vs_stack_entries = 128;
304 num_gs_stack_entries = 0;
305 num_es_stack_entries = 0;
306 break;
307 case CHIP_RV630:
308 case CHIP_RV635:
309 num_ps_gprs = 84;
310 num_vs_gprs = 36;
311 num_temp_gprs = 4;
312 num_gs_gprs = 0;
313 num_es_gprs = 0;
314 num_ps_threads = 144;
315 num_vs_threads = 40;
316 num_gs_threads = 4;
317 num_es_threads = 4;
318 num_ps_stack_entries = 40;
319 num_vs_stack_entries = 40;
320 num_gs_stack_entries = 32;
321 num_es_stack_entries = 16;
322 break;
323 case CHIP_RV610:
324 case CHIP_RV620:
325 case CHIP_RS780:
326 case CHIP_RS880:
327 default:
328 num_ps_gprs = 84;
329 num_vs_gprs = 36;
330 num_temp_gprs = 4;
331 num_gs_gprs = 0;
332 num_es_gprs = 0;
333 num_ps_threads = 136;
334 num_vs_threads = 48;
335 num_gs_threads = 4;
336 num_es_threads = 4;
337 num_ps_stack_entries = 40;
338 num_vs_stack_entries = 40;
339 num_gs_stack_entries = 32;
340 num_es_stack_entries = 16;
341 break;
342 case CHIP_RV670:
343 num_ps_gprs = 144;
344 num_vs_gprs = 40;
345 num_temp_gprs = 4;
346 num_gs_gprs = 0;
347 num_es_gprs = 0;
348 num_ps_threads = 136;
349 num_vs_threads = 48;
350 num_gs_threads = 4;
351 num_es_threads = 4;
352 num_ps_stack_entries = 40;
353 num_vs_stack_entries = 40;
354 num_gs_stack_entries = 32;
355 num_es_stack_entries = 16;
356 break;
357 case CHIP_RV770:
358 num_ps_gprs = 192;
359 num_vs_gprs = 56;
360 num_temp_gprs = 4;
361 num_gs_gprs = 0;
362 num_es_gprs = 0;
363 num_ps_threads = 188;
364 num_vs_threads = 60;
365 num_gs_threads = 0;
366 num_es_threads = 0;
367 num_ps_stack_entries = 256;
368 num_vs_stack_entries = 256;
369 num_gs_stack_entries = 0;
370 num_es_stack_entries = 0;
371 break;
372 case CHIP_RV730:
373 case CHIP_RV740:
374 num_ps_gprs = 84;
375 num_vs_gprs = 36;
376 num_temp_gprs = 4;
377 num_gs_gprs = 0;
378 num_es_gprs = 0;
379 num_ps_threads = 188;
380 num_vs_threads = 60;
381 num_gs_threads = 0;
382 num_es_threads = 0;
383 num_ps_stack_entries = 128;
384 num_vs_stack_entries = 128;
385 num_gs_stack_entries = 0;
386 num_es_stack_entries = 0;
387 break;
388 case CHIP_RV710:
389 num_ps_gprs = 192;
390 num_vs_gprs = 56;
391 num_temp_gprs = 4;
392 num_gs_gprs = 0;
393 num_es_gprs = 0;
394 num_ps_threads = 144;
395 num_vs_threads = 48;
396 num_gs_threads = 0;
397 num_es_threads = 0;
398 num_ps_stack_entries = 128;
399 num_vs_stack_entries = 128;
400 num_gs_stack_entries = 0;
401 num_es_stack_entries = 0;
402 break;
403 }
404
405 if ((rdev->family == CHIP_RV610) ||
406 (rdev->family == CHIP_RV620) ||
407 (rdev->family == CHIP_RS780) ||
ee59f2b4 408 (rdev->family == CHIP_RS880) ||
3ce0a23d
JG		 409 (rdev->family == CHIP_RV710))
410 sq_config = 0;
411 else
412 sq_config = VC_ENABLE;
413
414 sq_config |= (DX9_CONSTS |
415 ALU_INST_PREFER_VECTOR |
416 PS_PRIO(0) |
417 VS_PRIO(1) |
418 GS_PRIO(2) |
419 ES_PRIO(3));
420
421 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
422 NUM_VS_GPRS(num_vs_gprs) |
423 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
424 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
425 NUM_ES_GPRS(num_es_gprs));
426 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
427 NUM_VS_THREADS(num_vs_threads) |
428 NUM_GS_THREADS(num_gs_threads) |
429 NUM_ES_THREADS(num_es_threads));
430 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
431 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
432 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
433 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
434
435 /* emit an IB pointing at default state */
d964fc54 436 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
3ce0a23d 437 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
e32eb50d
CK		 438 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
439 radeon_ring_write(ring,
4eace7fd
CC		 440#ifdef __BIG_ENDIAN
441 (2 << 0) |
442#endif
443 (gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 444 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
445 radeon_ring_write(ring, dwords);
3ce0a23d 446
3ce0a23d 447 /* SQ config */
e32eb50d
CK		 448 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
449 radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
450 radeon_ring_write(ring, sq_config);
451 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
452 radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
453 radeon_ring_write(ring, sq_thread_resource_mgmt);
454 radeon_ring_write(ring, sq_stack_resource_mgmt_1);
455 radeon_ring_write(ring, sq_stack_resource_mgmt_2);
3ce0a23d
JG		 456}
457
52b53a0b
IH		 458#define I2F_MAX_BITS 15
459#define I2F_MAX_INPUT ((1 << I2F_MAX_BITS) - 1)
460#define I2F_SHIFT (24 - I2F_MAX_BITS)
461
462/*
463 * Converts unsigned integer into 32-bit IEEE floating point representation.
464 * Conversion is not universal and only works for the range from 0
465 * to 2^I2F_MAX_BITS-1. Currently we only use it with inputs between
466 * 0 and 16384 (inclusive), so I2F_MAX_BITS=15 is enough. If necessary,
467 * I2F_MAX_BITS can be increased, but that will add to the loop iterations
468 * and slow us down. Conversion is done by shifting the input and counting
469 * down until the first 1 reaches bit position 23. The resulting counter
470 * and the shifted input are, respectively, the exponent and the fraction.
471 * The sign is always zero.
472 */
ce580fab 473static uint32_t i2f(uint32_t input)
3ce0a23d
JG		 474{
475 u32 result, i, exponent, fraction;
476
52b53a0b
IH		 477 WARN_ON_ONCE(input > I2F_MAX_INPUT);
478
479 if ((input & I2F_MAX_INPUT) == 0)
480 result = 0;
3ce0a23d 481 else {
52b53a0b
IH		 482 exponent = 126 + I2F_MAX_BITS;
483 fraction = (input & I2F_MAX_INPUT) << I2F_SHIFT;
484
485 for (i = 0; i < I2F_MAX_BITS; i++) {
3ce0a23d
JG		 486 if (fraction & 0x800000)
487 break;
488 else {
52b53a0b 489 fraction = fraction << 1;
3ce0a23d
JG		 490 exponent = exponent - 1;
491 }
492 }
52b53a0b 493 result = exponent << 23 | (fraction & 0x7fffff);
3ce0a23d
JG		 494 }
495 return result;
496}
497
498int r600_blit_init(struct radeon_device *rdev)
499{
500 u32 obj_size;
4eace7fd 501 int i, r, dwords;
3ce0a23d 502 void *ptr;
119e20dc
AD		 503 u32 packet2s[16];
504 int num_packet2s = 0;
3ce0a23d 505
8eec9d6f
IH		 506 rdev->r600_blit.primitives.set_render_target = set_render_target;
507 rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
508 rdev->r600_blit.primitives.set_shaders = set_shaders;
509 rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
510 rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
511 rdev->r600_blit.primitives.set_scissors = set_scissors;
512 rdev->r600_blit.primitives.draw_auto = draw_auto;
513 rdev->r600_blit.primitives.set_default_state = set_default_state;
514
515 rdev->r600_blit.ring_size_common = 40; /* shaders + def state */
8eec9d6f 516 rdev->r600_blit.ring_size_common += 5; /* done copy */
77b1bad4 517 rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
8eec9d6f
IH		 518
519 rdev->r600_blit.ring_size_per_loop = 76;
520 /* set_render_target emits 2 extra dwords on rv6xx */
521 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
522 rdev->r600_blit.ring_size_per_loop += 2;
523
524 rdev->r600_blit.max_dim = 8192;
525
b70d6bb3 526 /* pin copy shader into vram if already initialized */
90aca4d2 527 if (rdev->r600_blit.shader_obj)
b70d6bb3
AD		 528 goto done;
529
3ce0a23d
JG		 530 rdev->r600_blit.state_offset = 0;
531
532 if (rdev->family >= CHIP_RV770)
119e20dc 533 rdev->r600_blit.state_len = r7xx_default_size;
3ce0a23d 534 else
119e20dc
AD		 535 rdev->r600_blit.state_len = r6xx_default_size;
536
537 dwords = rdev->r600_blit.state_len;
538 while (dwords & 0xf) {
4eace7fd 539 packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0));
119e20dc
AD		 540 dwords++;
541 }
3ce0a23d 542
119e20dc 543 obj_size = dwords * 4;
3ce0a23d
JG		 544 obj_size = ALIGN(obj_size, 256);
545
546 rdev->r600_blit.vs_offset = obj_size;
547 obj_size += r6xx_vs_size * 4;
548 obj_size = ALIGN(obj_size, 256);
549
550 rdev->r600_blit.ps_offset = obj_size;
551 obj_size += r6xx_ps_size * 4;
552 obj_size = ALIGN(obj_size, 256);
553
441921d5 554 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
40f5cf99 555 NULL, &rdev->r600_blit.shader_obj);
3ce0a23d
JG		 556 if (r) {
557 DRM_ERROR("r600 failed to allocate shader\n");
558 return r;
559 }
560
bc1a631e
DA		 561 DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n",
562 obj_size,
3ce0a23d
JG		 563 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
564
4c788679
JG		 565 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
566 if (unlikely(r != 0))
567 return r;
568 r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
3ce0a23d
JG		 569 if (r) {
570 DRM_ERROR("failed to map blit object %d\n", r);
571 return r;
572 }
3ce0a23d 573 if (rdev->family >= CHIP_RV770)
119e20dc
AD		 574 memcpy_toio(ptr + rdev->r600_blit.state_offset,
575 r7xx_default_state, rdev->r600_blit.state_len * 4);
3ce0a23d 576 else
119e20dc
AD		 577 memcpy_toio(ptr + rdev->r600_blit.state_offset,
578 r6xx_default_state, rdev->r600_blit.state_len * 4);
579 if (num_packet2s)
580 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
581 packet2s, num_packet2s * 4);
4eace7fd
CC		 582 for (i = 0; i < r6xx_vs_size; i++)
583 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]);
584 for (i = 0; i < r6xx_ps_size; i++)
585 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]);
4c788679
JG		 586 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
587 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
b70d6bb3
AD		 588
589done:
590 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
591 if (unlikely(r != 0))
592 return r;
593 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
594 &rdev->r600_blit.shader_gpu_addr);
595 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
596 if (r) {
597 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
598 return r;
599 }
53595338 600 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
3ce0a23d
JG		 601 return 0;
602}
603
604void r600_blit_fini(struct radeon_device *rdev)
605{
4c788679
JG		 606 int r;
607
53595338 608 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
30d2d9a5
JG		 609 if (rdev->r600_blit.shader_obj == NULL)
610 return;
611 /* If we can't reserve the bo, unref should be enough to destroy
612 * it when it becomes idle.
613 */
4c788679 614 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
30d2d9a5
JG		 615 if (!r) {
616 radeon_bo_unpin(rdev->r600_blit.shader_obj);
617 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
4c788679 618 }
4c788679 619 radeon_bo_unref(&rdev->r600_blit.shader_obj);
3ce0a23d
JG		 620}
621
b3530963 622static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
8eec9d6f 623 int *width, int *height, int max_dim)
7dbf41db
AD		 624{
625 unsigned max_pages;
b3530963 626 unsigned pages = num_gpu_pages;
7dbf41db
AD		 627 int w, h;
628
b3530963 629 if (num_gpu_pages == 0) {
7dbf41db
AD		 630 /* not supposed to be called with no pages, but just in case */
631 h = 0;
632 w = 0;
633 pages = 0;
634 WARN_ON(1);
635 } else {
636 int rect_order = 2;
637 h = RECT_UNIT_H;
b3530963 638 while (num_gpu_pages / rect_order) {
7dbf41db
AD		 639 h *= 2;
640 rect_order *= 4;
8eec9d6f
IH		 641 if (h >= max_dim) {
642 h = max_dim;
7dbf41db
AD		 643 break;
644 }
645 }
8eec9d6f 646 max_pages = (max_dim * h) / (RECT_UNIT_W * RECT_UNIT_H);
7dbf41db
AD		 647 if (pages > max_pages)
648 pages = max_pages;
649 w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
650 w = (w / RECT_UNIT_W) * RECT_UNIT_W;
651 pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
652 BUG_ON(pages == 0);
653 }
654
655
656 DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
657
658 /* return width and height only of the caller wants it */
659 if (height)
660 *height = h;
661 if (width)
662 *width = w;
663
664 return pages;
665}
666
667
f237750f
CK		 668int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
669 struct radeon_sa_bo **vb)
3ce0a23d 670{
e32eb50d 671 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d 672 int r;
7dbf41db 673 int ring_size;
8eec9d6f
IH		 674 int num_loops = 0;
675 int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
7cbb355e 676
7dbf41db 677 /* num loops */
b3530963
IH		 678 while (num_gpu_pages) {
679 num_gpu_pages -=
680 r600_blit_create_rect(num_gpu_pages, NULL, NULL,
681 rdev->r600_blit.max_dim);
7dbf41db
AD		 682 num_loops++;
683 }
3ce0a23d 684
69e130a6 685 /* 48 bytes for vertex per loop */
f237750f
CK		 686 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb,
687 (num_loops*48)+256, 256, true);
688 if (r) {
69e130a6 689 return r;
f237750f 690 }
69e130a6 691
7cbb355e
DA		 692 /* calculate number of loops correctly */
693 ring_size = num_loops * dwords_per_loop;
8eec9d6f 694 ring_size += rdev->r600_blit.ring_size_common;
e32eb50d 695 r = radeon_ring_lock(rdev, ring, ring_size);
f237750f
CK		 696 if (r) {
697 radeon_sa_bo_free(rdev, vb, NULL);
ff82f052 698 return r;
f237750f 699 }
3ce0a23d 700
8eec9d6f
IH		 701 rdev->r600_blit.primitives.set_default_state(rdev);
702 rdev->r600_blit.primitives.set_shaders(rdev);
3ce0a23d
JG		 703 return 0;
704}
705
f237750f
CK		 706void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence,
707 struct radeon_sa_bo *vb)
3ce0a23d 708{
f237750f 709 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 710 int r;
711
f237750f
CK		 712 r = radeon_fence_emit(rdev, fence);
713 if (r) {
714 radeon_ring_unlock_undo(rdev, ring);
715 return;
716 }
3ce0a23d 717
f237750f
CK		 718 radeon_ring_unlock_commit(rdev, ring);
719 radeon_sa_bo_free(rdev, &vb, fence);
3ce0a23d
JG		 720}
721
722void r600_kms_blit_copy(struct radeon_device *rdev,
723 u64 src_gpu_addr, u64 dst_gpu_addr,
f237750f
CK		 724 unsigned num_gpu_pages,
725 struct radeon_sa_bo *vb)
3ce0a23d 726{
3ce0a23d 727 u64 vb_gpu_addr;
f237750f 728 u32 *vb_cpu_addr;
3ce0a23d 729
f237750f
CK		 730 DRM_DEBUG("emitting copy %16llx %16llx %d\n",
731 src_gpu_addr, dst_gpu_addr, num_gpu_pages);
732 vb_cpu_addr = (u32 *)radeon_sa_bo_cpu_addr(vb);
733 vb_gpu_addr = radeon_sa_bo_gpu_addr(vb);
3ce0a23d 734
b3530963 735 while (num_gpu_pages) {
7dbf41db
AD		 736 int w, h;
737 unsigned size_in_bytes;
8eec9d6f 738 unsigned pages_per_loop =
b3530963 739 r600_blit_create_rect(num_gpu_pages, &w, &h,
8eec9d6f 740 rdev->r600_blit.max_dim);
3ce0a23d 741
7dbf41db
AD		 742 size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
743 DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
3ce0a23d 744
f237750f
CK		 745 vb_cpu_addr[0] = 0;
746 vb_cpu_addr[1] = 0;
747 vb_cpu_addr[2] = 0;
748 vb_cpu_addr[3] = 0;
3ce0a23d 749
f237750f
CK		 750 vb_cpu_addr[4] = 0;
751 vb_cpu_addr[5] = i2f(h);
752 vb_cpu_addr[6] = 0;
753 vb_cpu_addr[7] = i2f(h);
3ce0a23d 754
f237750f
CK		 755 vb_cpu_addr[8] = i2f(w);
756 vb_cpu_addr[9] = i2f(h);
757 vb_cpu_addr[10] = i2f(w);
758 vb_cpu_addr[11] = i2f(h);
3ce0a23d 759
8eec9d6f 760 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8,
9bb7703c 761 w, h, w, src_gpu_addr, size_in_bytes);
8eec9d6f
IH		 762 rdev->r600_blit.primitives.set_render_target(rdev, COLOR_8_8_8_8,
763 w, h, dst_gpu_addr);
764 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h);
8eec9d6f
IH		 765 rdev->r600_blit.primitives.set_vtx_resource(rdev, vb_gpu_addr);
766 rdev->r600_blit.primitives.draw_auto(rdev);
767 rdev->r600_blit.primitives.cp_set_surface_sync(rdev,
7dbf41db
AD		 768 PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
769 size_in_bytes, dst_gpu_addr);
770
f237750f
CK		 771 vb_cpu_addr += 12;
772 vb_gpu_addr += 4*12;
7dbf41db
AD		 773 src_gpu_addr += size_in_bytes;
774 dst_gpu_addr += size_in_bytes;
b3530963 775 num_gpu_pages -= pages_per_loop;
3ce0a23d
JG		 776 }
777}
kernel source for telekom puls (alcatel/mediatek)