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drm/radeon: fall back to GTT if bo creation/validation in VRAM fails.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
771fe6b9 32#include "drmP.h"
3ce0a23d 33#include "radeon_drm.h"
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
771fe6b9 40
3ce0a23d
JG		 41#define PFP_UCODE_SIZE 576
42#define PM4_UCODE_SIZE 1792
d8f60cfc 43#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 44#define R700_PFP_UCODE_SIZE 848
45#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 46#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 49#define EVERGREEN_RLC_UCODE_SIZE 768
3ce0a23d
JG		 50
51/* Firmware Names */
52MODULE_FIRMWARE("radeon/R600_pfp.bin");
53MODULE_FIRMWARE("radeon/R600_me.bin");
54MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55MODULE_FIRMWARE("radeon/RV610_me.bin");
56MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57MODULE_FIRMWARE("radeon/RV630_me.bin");
58MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59MODULE_FIRMWARE("radeon/RV620_me.bin");
60MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61MODULE_FIRMWARE("radeon/RV635_me.bin");
62MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63MODULE_FIRMWARE("radeon/RV670_me.bin");
64MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65MODULE_FIRMWARE("radeon/RS780_me.bin");
66MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67MODULE_FIRMWARE("radeon/RV770_me.bin");
68MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69MODULE_FIRMWARE("radeon/RV730_me.bin");
70MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 72MODULE_FIRMWARE("radeon/R600_rlc.bin");
73MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 74MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 76MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 84MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
3ce0a23d
JG		 86
87int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 88
1a029b76 89/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 90int r600_mc_wait_for_idle(struct radeon_device *rdev);
91void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 92void r600_fini(struct radeon_device *rdev);
45f9a39b 93void r600_irq_disable(struct radeon_device *rdev);
771fe6b9 94
21a8122a
AD		 95/* get temperature in millidegrees */
96u32 rv6xx_get_temp(struct radeon_device *rdev)
97{
98 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
99 ASIC_T_SHIFT;
100 u32 actual_temp = 0;
101
102 if ((temp >> 7) & 1)
103 actual_temp = 0;
104 else
105 actual_temp = (temp >> 1) & 0xff;
106
107 return actual_temp * 1000;
108}
109
ce8f5370 110void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 111{
112 int i;
113
ce8f5370
AD		 114 rdev->pm.dynpm_can_upclock = true;
115 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 116
117 /* power state array is low to high, default is first */
118 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
119 int min_power_state_index = 0;
120
121 if (rdev->pm.num_power_states > 2)
122 min_power_state_index = 1;
123
ce8f5370
AD		 124 switch (rdev->pm.dynpm_planned_action) {
125 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 126 rdev->pm.requested_power_state_index = min_power_state_index;
127 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 128 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 129 break;
ce8f5370 130 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 131 if (rdev->pm.current_power_state_index == min_power_state_index) {
132 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 133 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 134 } else {
135 if (rdev->pm.active_crtc_count > 1) {
136 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 137 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 138 continue;
139 else if (i >= rdev->pm.current_power_state_index) {
140 rdev->pm.requested_power_state_index =
141 rdev->pm.current_power_state_index;
142 break;
143 } else {
144 rdev->pm.requested_power_state_index = i;
145 break;
146 }
147 }
773c3fa3
AD		 148 } else {
149 if (rdev->pm.current_power_state_index == 0)
150 rdev->pm.requested_power_state_index =
151 rdev->pm.num_power_states - 1;
152 else
153 rdev->pm.requested_power_state_index =
154 rdev->pm.current_power_state_index - 1;
155 }
a48b9b4e
AD		 156 }
157 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 158 /* don't use the power state if crtcs are active and no display flag is set */
159 if ((rdev->pm.active_crtc_count > 0) &&
160 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
161 clock_info[rdev->pm.requested_clock_mode_index].flags &
162 RADEON_PM_MODE_NO_DISPLAY)) {
163 rdev->pm.requested_power_state_index++;
164 }
a48b9b4e 165 break;
ce8f5370 166 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 167 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
168 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 169 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 170 } else {
171 if (rdev->pm.active_crtc_count > 1) {
172 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 173 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 174 continue;
175 else if (i <= rdev->pm.current_power_state_index) {
176 rdev->pm.requested_power_state_index =
177 rdev->pm.current_power_state_index;
178 break;
179 } else {
180 rdev->pm.requested_power_state_index = i;
181 break;
182 }
183 }
184 } else
185 rdev->pm.requested_power_state_index =
186 rdev->pm.current_power_state_index + 1;
187 }
188 rdev->pm.requested_clock_mode_index = 0;
189 break;
ce8f5370 190 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 191 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
192 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 193 rdev->pm.dynpm_can_upclock = false;
58e21dff 194 break;
ce8f5370 195 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 196 default:
197 DRM_ERROR("Requested mode for not defined action\n");
198 return;
199 }
200 } else {
201 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
202 /* for now just select the first power state and switch between clock modes */
203 /* power state array is low to high, default is first (0) */
204 if (rdev->pm.active_crtc_count > 1) {
205 rdev->pm.requested_power_state_index = -1;
206 /* start at 1 as we don't want the default mode */
207 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 208 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 209 continue;
210 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
211 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
212 rdev->pm.requested_power_state_index = i;
213 break;
214 }
215 }
216 /* if nothing selected, grab the default state. */
217 if (rdev->pm.requested_power_state_index == -1)
218 rdev->pm.requested_power_state_index = 0;
219 } else
220 rdev->pm.requested_power_state_index = 1;
221
ce8f5370
AD		 222 switch (rdev->pm.dynpm_planned_action) {
223 case DYNPM_ACTION_MINIMUM:
a48b9b4e 224 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 225 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 226 break;
ce8f5370 227 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 228 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
229 if (rdev->pm.current_clock_mode_index == 0) {
230 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 231 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 232 } else
233 rdev->pm.requested_clock_mode_index =
234 rdev->pm.current_clock_mode_index - 1;
235 } else {
236 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 237 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 238 }
d7311171
AD		 239 /* don't use the power state if crtcs are active and no display flag is set */
240 if ((rdev->pm.active_crtc_count > 0) &&
241 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
242 clock_info[rdev->pm.requested_clock_mode_index].flags &
243 RADEON_PM_MODE_NO_DISPLAY)) {
244 rdev->pm.requested_clock_mode_index++;
245 }
a48b9b4e 246 break;
ce8f5370 247 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 248 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
249 if (rdev->pm.current_clock_mode_index ==
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
251 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 252 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 253 } else
254 rdev->pm.requested_clock_mode_index =
255 rdev->pm.current_clock_mode_index + 1;
256 } else {
257 rdev->pm.requested_clock_mode_index =
258 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 259 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 260 }
261 break;
ce8f5370 262 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 263 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
264 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 265 rdev->pm.dynpm_can_upclock = false;
58e21dff 266 break;
ce8f5370 267 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 268 default:
269 DRM_ERROR("Requested mode for not defined action\n");
270 return;
271 }
272 }
273
ce8a3eb2
AD		 274 DRM_DEBUG("Requested: e: %d m: %d p: %d\n",
275 rdev->pm.power_state[rdev->pm.requested_power_state_index].
276 clock_info[rdev->pm.requested_clock_mode_index].sclk,
277 rdev->pm.power_state[rdev->pm.requested_power_state_index].
278 clock_info[rdev->pm.requested_clock_mode_index].mclk,
279 rdev->pm.power_state[rdev->pm.requested_power_state_index].
280 pcie_lanes);
a48b9b4e
AD		 281}
282
ce8f5370
AD		 283static int r600_pm_get_type_index(struct radeon_device *rdev,
284 enum radeon_pm_state_type ps_type,
285 int instance)
bae6b562 286{
ce8f5370
AD		 287 int i;
288 int found_instance = -1;
bae6b562 289
ce8f5370
AD		 290 for (i = 0; i < rdev->pm.num_power_states; i++) {
291 if (rdev->pm.power_state[i].type == ps_type) {
292 found_instance++;
293 if (found_instance == instance)
294 return i;
a424816f 295 }
ce8f5370
AD		 296 }
297 /* return default if no match */
298 return rdev->pm.default_power_state_index;
299}
300
301void rs780_pm_init_profile(struct radeon_device *rdev)
302{
303 if (rdev->pm.num_power_states == 2) {
304 /* default */
305 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
306 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
307 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
309 /* low sh */
310 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 314 /* mid sh */
315 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 319 /* high sh */
320 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
322 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
324 /* low mh */
325 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 329 /* mid mh */
330 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
332 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 334 /* high mh */
335 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
337 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
339 } else if (rdev->pm.num_power_states == 3) {
340 /* default */
341 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
342 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
343 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
345 /* low sh */
346 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 350 /* mid sh */
351 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
352 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 355 /* high sh */
356 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
357 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
358 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
359 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
360 /* low mh */
361 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
362 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
364 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 365 /* mid mh */
366 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
367 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
368 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
369 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 370 /* high mh */
371 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
372 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
373 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
374 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
375 } else {
376 /* default */
377 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
378 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
379 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
380 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
381 /* low sh */
382 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
384 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
385 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 386 /* mid sh */
387 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
388 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
389 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 391 /* high sh */
392 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
393 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
394 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
396 /* low mh */
397 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
398 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
399 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
400 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 401 /* mid mh */
402 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
403 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
404 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
405 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 406 /* high mh */
407 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
408 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
409 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
410 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
411 }
412}
bae6b562 413
ce8f5370
AD		 414void r600_pm_init_profile(struct radeon_device *rdev)
415{
416 if (rdev->family == CHIP_R600) {
417 /* XXX */
418 /* default */
419 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
420 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
421 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 422 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 423 /* low sh */
424 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
425 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
426 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 427 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 428 /* mid sh */
429 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
430 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
431 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
432 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 433 /* high sh */
434 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
435 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
436 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 437 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 438 /* low mh */
439 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
440 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
441 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 442 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 443 /* mid mh */
444 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
445 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
446 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
447 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 448 /* high mh */
449 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 452 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 453 } else {
454 if (rdev->pm.num_power_states < 4) {
455 /* default */
456 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
457 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
458 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
459 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
460 /* low sh */
4bff5171
AD		 461 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
462 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 463 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 464 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
465 /* mid sh */
466 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
467 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
468 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
469 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 470 /* high sh */
4bff5171
AD		 471 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
472 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 473 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
474 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
475 /* low mh */
4bff5171
AD		 476 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
477 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 478 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 479 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
480 /* low mh */
481 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
483 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
484 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 485 /* high mh */
4bff5171
AD		 486 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
487 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 488 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
489 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
490 } else {
491 /* default */
492 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
493 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
494 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
495 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
496 /* low sh */
4bff5171
AD		 497 if (rdev->flags & RADEON_IS_MOBILITY) {
498 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
499 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
500 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
501 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
502 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21 503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 504 } else {
505 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
506 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
507 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
508 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
509 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 510 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
511 }
512 /* mid sh */
513 if (rdev->flags & RADEON_IS_MOBILITY) {
514 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
515 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
516 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
517 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
518 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
519 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
520 } else {
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
522 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
523 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
524 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
525 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
526 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
4bff5171 527 }
ce8f5370 528 /* high sh */
4bff5171
AD		 529 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
530 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
531 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
532 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
ce8f5370
AD		 533 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
534 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
535 /* low mh */
4bff5171
AD		 536 if (rdev->flags & RADEON_IS_MOBILITY) {
537 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
538 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
539 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
540 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
541 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21 542 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 543 } else {
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
545 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
547 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
548 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 549 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
550 }
551 /* mid mh */
552 if (rdev->flags & RADEON_IS_MOBILITY) {
553 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
554 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
555 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
556 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
557 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
559 } else {
560 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
561 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
562 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
563 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
4bff5171 566 }
ce8f5370 567 /* high mh */
4bff5171
AD		 568 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
569 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
571 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
ce8f5370
AD		 572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
573 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
574 }
575 }
bae6b562
AD		 576}
577
49e02b73
AD		 578void r600_pm_misc(struct radeon_device *rdev)
579{
a081a9d6
RM		 580 int req_ps_idx = rdev->pm.requested_power_state_index;
581 int req_cm_idx = rdev->pm.requested_clock_mode_index;
582 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
583 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 584
4d60173f
AD		 585 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
586 if (voltage->voltage != rdev->pm.current_vddc) {
587 radeon_atom_set_voltage(rdev, voltage->voltage);
588 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 589 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 590 }
591 }
49e02b73
AD		 592}
593
def9ba9c
AD		 594bool r600_gui_idle(struct radeon_device *rdev)
595{
596 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
597 return false;
598 else
599 return true;
600}
601
e0df1ac5
AD		 602/* hpd for digital panel detect/disconnect */
603bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
604{
605 bool connected = false;
606
607 if (ASIC_IS_DCE3(rdev)) {
608 switch (hpd) {
609 case RADEON_HPD_1:
610 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
611 connected = true;
612 break;
613 case RADEON_HPD_2:
614 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
615 connected = true;
616 break;
617 case RADEON_HPD_3:
618 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
619 connected = true;
620 break;
621 case RADEON_HPD_4:
622 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
623 connected = true;
624 break;
625 /* DCE 3.2 */
626 case RADEON_HPD_5:
627 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
628 connected = true;
629 break;
630 case RADEON_HPD_6:
631 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
632 connected = true;
633 break;
634 default:
635 break;
636 }
637 } else {
638 switch (hpd) {
639 case RADEON_HPD_1:
640 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
641 connected = true;
642 break;
643 case RADEON_HPD_2:
644 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
645 connected = true;
646 break;
647 case RADEON_HPD_3:
648 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
649 connected = true;
650 break;
651 default:
652 break;
653 }
654 }
655 return connected;
656}
657
658void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 659 enum radeon_hpd_id hpd)
e0df1ac5
AD		 660{
661 u32 tmp;
662 bool connected = r600_hpd_sense(rdev, hpd);
663
664 if (ASIC_IS_DCE3(rdev)) {
665 switch (hpd) {
666 case RADEON_HPD_1:
667 tmp = RREG32(DC_HPD1_INT_CONTROL);
668 if (connected)
669 tmp &= ~DC_HPDx_INT_POLARITY;
670 else
671 tmp |= DC_HPDx_INT_POLARITY;
672 WREG32(DC_HPD1_INT_CONTROL, tmp);
673 break;
674 case RADEON_HPD_2:
675 tmp = RREG32(DC_HPD2_INT_CONTROL);
676 if (connected)
677 tmp &= ~DC_HPDx_INT_POLARITY;
678 else
679 tmp |= DC_HPDx_INT_POLARITY;
680 WREG32(DC_HPD2_INT_CONTROL, tmp);
681 break;
682 case RADEON_HPD_3:
683 tmp = RREG32(DC_HPD3_INT_CONTROL);
684 if (connected)
685 tmp &= ~DC_HPDx_INT_POLARITY;
686 else
687 tmp |= DC_HPDx_INT_POLARITY;
688 WREG32(DC_HPD3_INT_CONTROL, tmp);
689 break;
690 case RADEON_HPD_4:
691 tmp = RREG32(DC_HPD4_INT_CONTROL);
692 if (connected)
693 tmp &= ~DC_HPDx_INT_POLARITY;
694 else
695 tmp |= DC_HPDx_INT_POLARITY;
696 WREG32(DC_HPD4_INT_CONTROL, tmp);
697 break;
698 case RADEON_HPD_5:
699 tmp = RREG32(DC_HPD5_INT_CONTROL);
700 if (connected)
701 tmp &= ~DC_HPDx_INT_POLARITY;
702 else
703 tmp |= DC_HPDx_INT_POLARITY;
704 WREG32(DC_HPD5_INT_CONTROL, tmp);
705 break;
706 /* DCE 3.2 */
707 case RADEON_HPD_6:
708 tmp = RREG32(DC_HPD6_INT_CONTROL);
709 if (connected)
710 tmp &= ~DC_HPDx_INT_POLARITY;
711 else
712 tmp |= DC_HPDx_INT_POLARITY;
713 WREG32(DC_HPD6_INT_CONTROL, tmp);
714 break;
715 default:
716 break;
717 }
718 } else {
719 switch (hpd) {
720 case RADEON_HPD_1:
721 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
722 if (connected)
723 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
724 else
725 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
726 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
727 break;
728 case RADEON_HPD_2:
729 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
730 if (connected)
731 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
732 else
733 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
734 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
735 break;
736 case RADEON_HPD_3:
737 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
738 if (connected)
739 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
740 else
741 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
742 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
743 break;
744 default:
745 break;
746 }
747 }
748}
749
750void r600_hpd_init(struct radeon_device *rdev)
751{
752 struct drm_device *dev = rdev->ddev;
753 struct drm_connector *connector;
754
755 if (ASIC_IS_DCE3(rdev)) {
756 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
757 if (ASIC_IS_DCE32(rdev))
758 tmp |= DC_HPDx_EN;
759
760 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
761 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
762 switch (radeon_connector->hpd.hpd) {
763 case RADEON_HPD_1:
764 WREG32(DC_HPD1_CONTROL, tmp);
765 rdev->irq.hpd[0] = true;
766 break;
767 case RADEON_HPD_2:
768 WREG32(DC_HPD2_CONTROL, tmp);
769 rdev->irq.hpd[1] = true;
770 break;
771 case RADEON_HPD_3:
772 WREG32(DC_HPD3_CONTROL, tmp);
773 rdev->irq.hpd[2] = true;
774 break;
775 case RADEON_HPD_4:
776 WREG32(DC_HPD4_CONTROL, tmp);
777 rdev->irq.hpd[3] = true;
778 break;
779 /* DCE 3.2 */
780 case RADEON_HPD_5:
781 WREG32(DC_HPD5_CONTROL, tmp);
782 rdev->irq.hpd[4] = true;
783 break;
784 case RADEON_HPD_6:
785 WREG32(DC_HPD6_CONTROL, tmp);
786 rdev->irq.hpd[5] = true;
787 break;
788 default:
789 break;
790 }
791 }
792 } else {
793 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
794 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
795 switch (radeon_connector->hpd.hpd) {
796 case RADEON_HPD_1:
797 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
798 rdev->irq.hpd[0] = true;
799 break;
800 case RADEON_HPD_2:
801 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
802 rdev->irq.hpd[1] = true;
803 break;
804 case RADEON_HPD_3:
805 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
806 rdev->irq.hpd[2] = true;
807 break;
808 default:
809 break;
810 }
811 }
812 }
003e69f9
JG		 813 if (rdev->irq.installed)
814 r600_irq_set(rdev);
e0df1ac5
AD		 815}
816
817void r600_hpd_fini(struct radeon_device *rdev)
818{
819 struct drm_device *dev = rdev->ddev;
820 struct drm_connector *connector;
821
822 if (ASIC_IS_DCE3(rdev)) {
823 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
824 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
825 switch (radeon_connector->hpd.hpd) {
826 case RADEON_HPD_1:
827 WREG32(DC_HPD1_CONTROL, 0);
828 rdev->irq.hpd[0] = false;
829 break;
830 case RADEON_HPD_2:
831 WREG32(DC_HPD2_CONTROL, 0);
832 rdev->irq.hpd[1] = false;
833 break;
834 case RADEON_HPD_3:
835 WREG32(DC_HPD3_CONTROL, 0);
836 rdev->irq.hpd[2] = false;
837 break;
838 case RADEON_HPD_4:
839 WREG32(DC_HPD4_CONTROL, 0);
840 rdev->irq.hpd[3] = false;
841 break;
842 /* DCE 3.2 */
843 case RADEON_HPD_5:
844 WREG32(DC_HPD5_CONTROL, 0);
845 rdev->irq.hpd[4] = false;
846 break;
847 case RADEON_HPD_6:
848 WREG32(DC_HPD6_CONTROL, 0);
849 rdev->irq.hpd[5] = false;
850 break;
851 default:
852 break;
853 }
854 }
855 } else {
856 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
857 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
858 switch (radeon_connector->hpd.hpd) {
859 case RADEON_HPD_1:
860 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
861 rdev->irq.hpd[0] = false;
862 break;
863 case RADEON_HPD_2:
864 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
865 rdev->irq.hpd[1] = false;
866 break;
867 case RADEON_HPD_3:
868 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
869 rdev->irq.hpd[2] = false;
870 break;
871 default:
872 break;
873 }
874 }
875 }
876}
877
771fe6b9 878/*
3ce0a23d 879 * R600 PCIE GART
771fe6b9 880 */
3ce0a23d
JG		 881void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
882{
883 unsigned i;
884 u32 tmp;
885
2e98f10a
DA		 886 /* flush hdp cache so updates hit vram */
887 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
888
3ce0a23d
JG		 889 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
890 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
891 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
892 for (i = 0; i < rdev->usec_timeout; i++) {
893 /* read MC_STATUS */
894 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
895 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
896 if (tmp == 2) {
897 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
898 return;
899 }
900 if (tmp) {
901 return;
902 }
903 udelay(1);
904 }
905}
906
4aac0473 907int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 908{
4aac0473 909 int r;
3ce0a23d 910
4aac0473
JG		 911 if (rdev->gart.table.vram.robj) {
912 WARN(1, "R600 PCIE GART already initialized.\n");
913 return 0;
914 }
3ce0a23d
JG		 915 /* Initialize common gart structure */
916 r = radeon_gart_init(rdev);
4aac0473 917 if (r)
3ce0a23d 918 return r;
3ce0a23d 919 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 920 return radeon_gart_table_vram_alloc(rdev);
921}
922
923int r600_pcie_gart_enable(struct radeon_device *rdev)
924{
925 u32 tmp;
926 int r, i;
927
928 if (rdev->gart.table.vram.robj == NULL) {
929 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
930 return -EINVAL;
771fe6b9 931 }
4aac0473
JG		 932 r = radeon_gart_table_vram_pin(rdev);
933 if (r)
934 return r;
82568565 935 radeon_gart_restore(rdev);
bc1a631e 936
3ce0a23d
JG		 937 /* Setup L2 cache */
938 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
939 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
940 EFFECTIVE_L2_QUEUE_SIZE(7));
941 WREG32(VM_L2_CNTL2, 0);
942 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
943 /* Setup TLB control */
944 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
945 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
946 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
947 ENABLE_WAIT_L2_QUERY;
948 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
949 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
950 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
951 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
952 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
953 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
954 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
955 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
956 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
957 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
958 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
959 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
961 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
962 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 963 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 964 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
965 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
966 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
967 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
968 (u32)(rdev->dummy_page.addr >> 12));
969 for (i = 1; i < 7; i++)
970 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 971
3ce0a23d
JG		 972 r600_pcie_gart_tlb_flush(rdev);
973 rdev->gart.ready = true;
771fe6b9
JG		 974 return 0;
975}
976
3ce0a23d 977void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 978{
3ce0a23d 979 u32 tmp;
4c788679 980 int i, r;
771fe6b9 981
3ce0a23d
JG		 982 /* Disable all tables */
983 for (i = 0; i < 7; i++)
984 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 985
3ce0a23d
JG		 986 /* Disable L2 cache */
987 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
988 EFFECTIVE_L2_QUEUE_SIZE(7));
989 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
990 /* Setup L1 TLB control */
991 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
992 ENABLE_WAIT_L2_QUERY;
993 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
994 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
995 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
996 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
997 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
998 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
999 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1000 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1001 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1002 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1003 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 1007 if (rdev->gart.table.vram.robj) {
4c788679
JG		 1008 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1009 if (likely(r == 0)) {
1010 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1011 radeon_bo_unpin(rdev->gart.table.vram.robj);
1012 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1013 }
4aac0473
JG		 1014 }
1015}
1016
1017void r600_pcie_gart_fini(struct radeon_device *rdev)
1018{
f9274562 1019 radeon_gart_fini(rdev);
4aac0473
JG		 1020 r600_pcie_gart_disable(rdev);
1021 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1022}
1023
1a029b76
JG		 1024void r600_agp_enable(struct radeon_device *rdev)
1025{
1026 u32 tmp;
1027 int i;
1028
1029 /* Setup L2 cache */
1030 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1031 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1032 EFFECTIVE_L2_QUEUE_SIZE(7));
1033 WREG32(VM_L2_CNTL2, 0);
1034 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1035 /* Setup TLB control */
1036 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1037 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1038 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1039 ENABLE_WAIT_L2_QUERY;
1040 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1041 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1042 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1043 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1044 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1045 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1046 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1047 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1048 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1049 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1050 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1051 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1052 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1053 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1054 for (i = 0; i < 7; i++)
1055 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1056}
1057
771fe6b9
JG		 1058int r600_mc_wait_for_idle(struct radeon_device *rdev)
1059{
3ce0a23d
JG		 1060 unsigned i;
1061 u32 tmp;
1062
1063 for (i = 0; i < rdev->usec_timeout; i++) {
1064 /* read MC_STATUS */
1065 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1066 if (!tmp)
1067 return 0;
1068 udelay(1);
1069 }
1070 return -1;
771fe6b9
JG		 1071}
1072
a3c1945a 1073static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1074{
a3c1945a 1075 struct rv515_mc_save save;
3ce0a23d
JG		 1076 u32 tmp;
1077 int i, j;
771fe6b9 1078
3ce0a23d
JG		 1079 /* Initialize HDP */
1080 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1081 WREG32((0x2c14 + j), 0x00000000);
1082 WREG32((0x2c18 + j), 0x00000000);
1083 WREG32((0x2c1c + j), 0x00000000);
1084 WREG32((0x2c20 + j), 0x00000000);
1085 WREG32((0x2c24 + j), 0x00000000);
1086 }
1087 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1088
a3c1945a 1089 rv515_mc_stop(rdev, &save);
3ce0a23d 1090 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1091 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1092 }
a3c1945a 1093 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1094 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1095 /* Update configuration */
1a029b76
JG		 1096 if (rdev->flags & RADEON_IS_AGP) {
1097 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1098 /* VRAM before AGP */
1099 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1100 rdev->mc.vram_start >> 12);
1101 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1102 rdev->mc.gtt_end >> 12);
1103 } else {
1104 /* VRAM after AGP */
1105 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1106 rdev->mc.gtt_start >> 12);
1107 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1108 rdev->mc.vram_end >> 12);
1109 }
1110 } else {
1111 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1112 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1113 }
3ce0a23d 1114 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 1115 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1116 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1117 WREG32(MC_VM_FB_LOCATION, tmp);
1118 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1119 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1120 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1121 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1122 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1123 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1124 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1125 } else {
1126 WREG32(MC_VM_AGP_BASE, 0);
1127 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1128 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1129 }
3ce0a23d 1130 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1131 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1132 }
a3c1945a 1133 rv515_mc_resume(rdev, &save);
698443d9
DA		 1134 /* we need to own VRAM, so turn off the VGA renderer here
1135 * to stop it overwriting our objects */
d39c3b89 1136 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1137}
1138
d594e46a
JG		 1139/**
1140 * r600_vram_gtt_location - try to find VRAM & GTT location
1141 * @rdev: radeon device structure holding all necessary informations
1142 * @mc: memory controller structure holding memory informations
1143 *
1144 * Function will place try to place VRAM at same place as in CPU (PCI)
1145 * address space as some GPU seems to have issue when we reprogram at
1146 * different address space.
1147 *
1148 * If there is not enough space to fit the unvisible VRAM after the
1149 * aperture then we limit the VRAM size to the aperture.
1150 *
1151 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1152 * them to be in one from GPU point of view so that we can program GPU to
1153 * catch access outside them (weird GPU policy see ??).
1154 *
1155 * This function will never fails, worst case are limiting VRAM or GTT.
1156 *
1157 * Note: GTT start, end, size should be initialized before calling this
1158 * function on AGP platform.
1159 */
1160void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1161{
1162 u64 size_bf, size_af;
1163
1164 if (mc->mc_vram_size > 0xE0000000) {
1165 /* leave room for at least 512M GTT */
1166 dev_warn(rdev->dev, "limiting VRAM\n");
1167 mc->real_vram_size = 0xE0000000;
1168 mc->mc_vram_size = 0xE0000000;
1169 }
1170 if (rdev->flags & RADEON_IS_AGP) {
1171 size_bf = mc->gtt_start;
1172 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1173 if (size_bf > size_af) {
1174 if (mc->mc_vram_size > size_bf) {
1175 dev_warn(rdev->dev, "limiting VRAM\n");
1176 mc->real_vram_size = size_bf;
1177 mc->mc_vram_size = size_bf;
1178 }
1179 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1180 } else {
1181 if (mc->mc_vram_size > size_af) {
1182 dev_warn(rdev->dev, "limiting VRAM\n");
1183 mc->real_vram_size = size_af;
1184 mc->mc_vram_size = size_af;
1185 }
1186 mc->vram_start = mc->gtt_end;
1187 }
1188 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1189 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1190 mc->mc_vram_size >> 20, mc->vram_start,
1191 mc->vram_end, mc->real_vram_size >> 20);
1192 } else {
1193 u64 base = 0;
1194 if (rdev->flags & RADEON_IS_IGP)
1195 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1196 radeon_vram_location(rdev, &rdev->mc, base);
1197 radeon_gtt_location(rdev, mc);
1198 }
1199}
1200
3ce0a23d 1201int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1202{
3ce0a23d 1203 u32 tmp;
5885b7a9 1204 int chansize, numchan;
771fe6b9 1205
3ce0a23d 1206 /* Get VRAM informations */
771fe6b9 1207 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1208 tmp = RREG32(RAMCFG);
1209 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1210 chansize = 16;
3ce0a23d 1211 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1212 chansize = 64;
1213 } else {
1214 chansize = 32;
1215 }
5885b7a9
AD		 1216 tmp = RREG32(CHMAP);
1217 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1218 case 0:
1219 default:
1220 numchan = 1;
1221 break;
1222 case 1:
1223 numchan = 2;
1224 break;
1225 case 2:
1226 numchan = 4;
1227 break;
1228 case 3:
1229 numchan = 8;
1230 break;
771fe6b9 1231 }
5885b7a9 1232 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1233 /* Could aper size report 0 ? */
01d73a69
JC		 1234 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1235 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1236 /* Setup GPU memory space */
1237 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1238 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1239 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1240 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1241
f892034a
AD		 1242 if (rdev->flags & RADEON_IS_IGP) {
1243 rs690_pm_info(rdev);
06b6476d 1244 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1245 }
f47299c5 1246 radeon_update_bandwidth_info(rdev);
3ce0a23d 1247 return 0;
771fe6b9
JG		 1248}
1249
3ce0a23d
JG		 1250/* We doesn't check that the GPU really needs a reset we simply do the
1251 * reset, it's up to the caller to determine if the GPU needs one. We
1252 * might add an helper function to check that.
1253 */
1254int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1255{
a3c1945a 1256 struct rv515_mc_save save;
3ce0a23d
JG		 1257 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1258 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1259 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1260 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1261 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1262 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1263 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1264 S_008010_GUI_ACTIVE(1);
1265 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1266 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1267 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1268 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1269 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1270 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1271 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1272 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1273 u32 tmp;
771fe6b9 1274
1a029b76
JG		 1275 dev_info(rdev->dev, "GPU softreset \n");
1276 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1277 RREG32(R_008010_GRBM_STATUS));
1278 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1279 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1280 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1281 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1282 rv515_mc_stop(rdev, &save);
1283 if (r600_mc_wait_for_idle(rdev)) {
1284 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1285 }
3ce0a23d 1286 /* Disable CP parsing/prefetching */
90aca4d2 1287 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1288 /* Check if any of the rendering block is busy and reset it */
1289 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1290 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1291 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1292 S_008020_SOFT_RESET_DB(1) |
1293 S_008020_SOFT_RESET_CB(1) |
1294 S_008020_SOFT_RESET_PA(1) |
1295 S_008020_SOFT_RESET_SC(1) |
1296 S_008020_SOFT_RESET_SMX(1) |
1297 S_008020_SOFT_RESET_SPI(1) |
1298 S_008020_SOFT_RESET_SX(1) |
1299 S_008020_SOFT_RESET_SH(1) |
1300 S_008020_SOFT_RESET_TC(1) |
1301 S_008020_SOFT_RESET_TA(1) |
1302 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1303 S_008020_SOFT_RESET_VGT(1);
1a029b76 1304 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1305 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1306 RREG32(R_008020_GRBM_SOFT_RESET);
1307 mdelay(15);
3ce0a23d 1308 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1309 }
1310 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1311 tmp = S_008020_SOFT_RESET_CP(1);
1312 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1313 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1314 RREG32(R_008020_GRBM_SOFT_RESET);
1315 mdelay(15);
3ce0a23d 1316 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1317 /* Wait a little for things to settle down */
225758d8 1318 mdelay(1);
1a029b76
JG		 1319 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1320 RREG32(R_008010_GRBM_STATUS));
1321 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1322 RREG32(R_008014_GRBM_STATUS2));
1323 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1324 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1325 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1326 return 0;
1327}
1328
225758d8
JG		 1329bool r600_gpu_is_lockup(struct radeon_device *rdev)
1330{
1331 u32 srbm_status;
1332 u32 grbm_status;
1333 u32 grbm_status2;
1334 int r;
1335
1336 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1337 grbm_status = RREG32(R_008010_GRBM_STATUS);
1338 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1339 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1340 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1341 return false;
1342 }
1343 /* force CP activities */
1344 r = radeon_ring_lock(rdev, 2);
1345 if (!r) {
1346 /* PACKET2 NOP */
1347 radeon_ring_write(rdev, 0x80000000);
1348 radeon_ring_write(rdev, 0x80000000);
1349 radeon_ring_unlock_commit(rdev);
1350 }
1351 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1352 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1353}
1354
a2d07b74 1355int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1356{
1357 return r600_gpu_soft_reset(rdev);
1358}
1359
1360static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1361 u32 num_backends,
1362 u32 backend_disable_mask)
1363{
1364 u32 backend_map = 0;
1365 u32 enabled_backends_mask;
1366 u32 enabled_backends_count;
1367 u32 cur_pipe;
1368 u32 swizzle_pipe[R6XX_MAX_PIPES];
1369 u32 cur_backend;
1370 u32 i;
1371
1372 if (num_tile_pipes > R6XX_MAX_PIPES)
1373 num_tile_pipes = R6XX_MAX_PIPES;
1374 if (num_tile_pipes < 1)
1375 num_tile_pipes = 1;
1376 if (num_backends > R6XX_MAX_BACKENDS)
1377 num_backends = R6XX_MAX_BACKENDS;
1378 if (num_backends < 1)
1379 num_backends = 1;
1380
1381 enabled_backends_mask = 0;
1382 enabled_backends_count = 0;
1383 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1384 if (((backend_disable_mask >> i) & 1) == 0) {
1385 enabled_backends_mask |= (1 << i);
1386 ++enabled_backends_count;
1387 }
1388 if (enabled_backends_count == num_backends)
1389 break;
1390 }
1391
1392 if (enabled_backends_count == 0) {
1393 enabled_backends_mask = 1;
1394 enabled_backends_count = 1;
1395 }
1396
1397 if (enabled_backends_count != num_backends)
1398 num_backends = enabled_backends_count;
1399
1400 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1401 switch (num_tile_pipes) {
1402 case 1:
1403 swizzle_pipe[0] = 0;
1404 break;
1405 case 2:
1406 swizzle_pipe[0] = 0;
1407 swizzle_pipe[1] = 1;
1408 break;
1409 case 3:
1410 swizzle_pipe[0] = 0;
1411 swizzle_pipe[1] = 1;
1412 swizzle_pipe[2] = 2;
1413 break;
1414 case 4:
1415 swizzle_pipe[0] = 0;
1416 swizzle_pipe[1] = 1;
1417 swizzle_pipe[2] = 2;
1418 swizzle_pipe[3] = 3;
1419 break;
1420 case 5:
1421 swizzle_pipe[0] = 0;
1422 swizzle_pipe[1] = 1;
1423 swizzle_pipe[2] = 2;
1424 swizzle_pipe[3] = 3;
1425 swizzle_pipe[4] = 4;
1426 break;
1427 case 6:
1428 swizzle_pipe[0] = 0;
1429 swizzle_pipe[1] = 2;
1430 swizzle_pipe[2] = 4;
1431 swizzle_pipe[3] = 5;
1432 swizzle_pipe[4] = 1;
1433 swizzle_pipe[5] = 3;
1434 break;
1435 case 7:
1436 swizzle_pipe[0] = 0;
1437 swizzle_pipe[1] = 2;
1438 swizzle_pipe[2] = 4;
1439 swizzle_pipe[3] = 6;
1440 swizzle_pipe[4] = 1;
1441 swizzle_pipe[5] = 3;
1442 swizzle_pipe[6] = 5;
1443 break;
1444 case 8:
1445 swizzle_pipe[0] = 0;
1446 swizzle_pipe[1] = 2;
1447 swizzle_pipe[2] = 4;
1448 swizzle_pipe[3] = 6;
1449 swizzle_pipe[4] = 1;
1450 swizzle_pipe[5] = 3;
1451 swizzle_pipe[6] = 5;
1452 swizzle_pipe[7] = 7;
1453 break;
1454 }
1455
1456 cur_backend = 0;
1457 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1458 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1459 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1460
1461 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1462
1463 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1464 }
1465
1466 return backend_map;
1467}
1468
1469int r600_count_pipe_bits(uint32_t val)
1470{
1471 int i, ret = 0;
1472
1473 for (i = 0; i < 32; i++) {
1474 ret += val & 1;
1475 val >>= 1;
1476 }
1477 return ret;
771fe6b9
JG		 1478}
1479
3ce0a23d
JG		 1480void r600_gpu_init(struct radeon_device *rdev)
1481{
1482 u32 tiling_config;
1483 u32 ramcfg;
d03f5d59
AD		 1484 u32 backend_map;
1485 u32 cc_rb_backend_disable;
1486 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1487 u32 tmp;
1488 int i, j;
1489 u32 sq_config;
1490 u32 sq_gpr_resource_mgmt_1 = 0;
1491 u32 sq_gpr_resource_mgmt_2 = 0;
1492 u32 sq_thread_resource_mgmt = 0;
1493 u32 sq_stack_resource_mgmt_1 = 0;
1494 u32 sq_stack_resource_mgmt_2 = 0;
1495
1496 /* FIXME: implement */
1497 switch (rdev->family) {
1498 case CHIP_R600:
1499 rdev->config.r600.max_pipes = 4;
1500 rdev->config.r600.max_tile_pipes = 8;
1501 rdev->config.r600.max_simds = 4;
1502 rdev->config.r600.max_backends = 4;
1503 rdev->config.r600.max_gprs = 256;
1504 rdev->config.r600.max_threads = 192;
1505 rdev->config.r600.max_stack_entries = 256;
1506 rdev->config.r600.max_hw_contexts = 8;
1507 rdev->config.r600.max_gs_threads = 16;
1508 rdev->config.r600.sx_max_export_size = 128;
1509 rdev->config.r600.sx_max_export_pos_size = 16;
1510 rdev->config.r600.sx_max_export_smx_size = 128;
1511 rdev->config.r600.sq_num_cf_insts = 2;
1512 break;
1513 case CHIP_RV630:
1514 case CHIP_RV635:
1515 rdev->config.r600.max_pipes = 2;
1516 rdev->config.r600.max_tile_pipes = 2;
1517 rdev->config.r600.max_simds = 3;
1518 rdev->config.r600.max_backends = 1;
1519 rdev->config.r600.max_gprs = 128;
1520 rdev->config.r600.max_threads = 192;
1521 rdev->config.r600.max_stack_entries = 128;
1522 rdev->config.r600.max_hw_contexts = 8;
1523 rdev->config.r600.max_gs_threads = 4;
1524 rdev->config.r600.sx_max_export_size = 128;
1525 rdev->config.r600.sx_max_export_pos_size = 16;
1526 rdev->config.r600.sx_max_export_smx_size = 128;
1527 rdev->config.r600.sq_num_cf_insts = 2;
1528 break;
1529 case CHIP_RV610:
1530 case CHIP_RV620:
1531 case CHIP_RS780:
1532 case CHIP_RS880:
1533 rdev->config.r600.max_pipes = 1;
1534 rdev->config.r600.max_tile_pipes = 1;
1535 rdev->config.r600.max_simds = 2;
1536 rdev->config.r600.max_backends = 1;
1537 rdev->config.r600.max_gprs = 128;
1538 rdev->config.r600.max_threads = 192;
1539 rdev->config.r600.max_stack_entries = 128;
1540 rdev->config.r600.max_hw_contexts = 4;
1541 rdev->config.r600.max_gs_threads = 4;
1542 rdev->config.r600.sx_max_export_size = 128;
1543 rdev->config.r600.sx_max_export_pos_size = 16;
1544 rdev->config.r600.sx_max_export_smx_size = 128;
1545 rdev->config.r600.sq_num_cf_insts = 1;
1546 break;
1547 case CHIP_RV670:
1548 rdev->config.r600.max_pipes = 4;
1549 rdev->config.r600.max_tile_pipes = 4;
1550 rdev->config.r600.max_simds = 4;
1551 rdev->config.r600.max_backends = 4;
1552 rdev->config.r600.max_gprs = 192;
1553 rdev->config.r600.max_threads = 192;
1554 rdev->config.r600.max_stack_entries = 256;
1555 rdev->config.r600.max_hw_contexts = 8;
1556 rdev->config.r600.max_gs_threads = 16;
1557 rdev->config.r600.sx_max_export_size = 128;
1558 rdev->config.r600.sx_max_export_pos_size = 16;
1559 rdev->config.r600.sx_max_export_smx_size = 128;
1560 rdev->config.r600.sq_num_cf_insts = 2;
1561 break;
1562 default:
1563 break;
1564 }
1565
1566 /* Initialize HDP */
1567 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1568 WREG32((0x2c14 + j), 0x00000000);
1569 WREG32((0x2c18 + j), 0x00000000);
1570 WREG32((0x2c1c + j), 0x00000000);
1571 WREG32((0x2c20 + j), 0x00000000);
1572 WREG32((0x2c24 + j), 0x00000000);
1573 }
1574
1575 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1576
1577 /* Setup tiling */
1578 tiling_config = 0;
1579 ramcfg = RREG32(RAMCFG);
1580 switch (rdev->config.r600.max_tile_pipes) {
1581 case 1:
1582 tiling_config |= PIPE_TILING(0);
1583 break;
1584 case 2:
1585 tiling_config |= PIPE_TILING(1);
1586 break;
1587 case 4:
1588 tiling_config |= PIPE_TILING(2);
1589 break;
1590 case 8:
1591 tiling_config |= PIPE_TILING(3);
1592 break;
1593 default:
1594 break;
1595 }
d03f5d59 1596 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1597 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d
JG		 1598 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1599 tiling_config |= GROUP_SIZE(0);
961fb597 1600 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1601 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1602 if (tmp > 3) {
1603 tiling_config |= ROW_TILING(3);
1604 tiling_config |= SAMPLE_SPLIT(3);
1605 } else {
1606 tiling_config |= ROW_TILING(tmp);
1607 tiling_config |= SAMPLE_SPLIT(tmp);
1608 }
1609 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1610
1611 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1612 cc_rb_backend_disable |=
1613 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1614
1615 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1616 cc_gc_shader_pipe_config |=
1617 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1618 cc_gc_shader_pipe_config |=
1619 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1620
1621 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1622 (R6XX_MAX_BACKENDS -
1623 r600_count_pipe_bits((cc_rb_backend_disable &
1624 R6XX_MAX_BACKENDS_MASK) >> 16)),
1625 (cc_rb_backend_disable >> 16));
e7aeeba6 1626 rdev->config.r600.tile_config = tiling_config;
d03f5d59 1627 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1628 WREG32(GB_TILING_CONFIG, tiling_config);
1629 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1630 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1631
3ce0a23d 1632 /* Setup pipes */
d03f5d59
AD		 1633 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1634 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1635 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1636
d03f5d59 1637 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1638 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1639 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1640
1641 /* Setup some CP states */
1642 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1643 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1644
1645 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1646 SYNC_WALKER | SYNC_ALIGNER));
1647 /* Setup various GPU states */
1648 if (rdev->family == CHIP_RV670)
1649 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1650
1651 tmp = RREG32(SX_DEBUG_1);
1652 tmp |= SMX_EVENT_RELEASE;
1653 if ((rdev->family > CHIP_R600))
1654 tmp |= ENABLE_NEW_SMX_ADDRESS;
1655 WREG32(SX_DEBUG_1, tmp);
1656
1657 if (((rdev->family) == CHIP_R600) ||
1658 ((rdev->family) == CHIP_RV630) ||
1659 ((rdev->family) == CHIP_RV610) ||
1660 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1661 ((rdev->family) == CHIP_RS780) ||
1662 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1663 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1664 } else {
1665 WREG32(DB_DEBUG, 0);
1666 }
1667 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1668 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1669
1670 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1671 WREG32(VGT_NUM_INSTANCES, 0);
1672
1673 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1674 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1675
1676 tmp = RREG32(SQ_MS_FIFO_SIZES);
1677 if (((rdev->family) == CHIP_RV610) ||
1678 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1679 ((rdev->family) == CHIP_RS780) ||
1680 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1681 tmp = (CACHE_FIFO_SIZE(0xa) |
1682 FETCH_FIFO_HIWATER(0xa) |
1683 DONE_FIFO_HIWATER(0xe0) |
1684 ALU_UPDATE_FIFO_HIWATER(0x8));
1685 } else if (((rdev->family) == CHIP_R600) ||
1686 ((rdev->family) == CHIP_RV630)) {
1687 tmp &= ~DONE_FIFO_HIWATER(0xff);
1688 tmp |= DONE_FIFO_HIWATER(0x4);
1689 }
1690 WREG32(SQ_MS_FIFO_SIZES, tmp);
1691
1692 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1693 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1694 */
1695 sq_config = RREG32(SQ_CONFIG);
1696 sq_config &= ~(PS_PRIO(3) |
1697 VS_PRIO(3) |
1698 GS_PRIO(3) |
1699 ES_PRIO(3));
1700 sq_config |= (DX9_CONSTS |
1701 VC_ENABLE |
1702 PS_PRIO(0) |
1703 VS_PRIO(1) |
1704 GS_PRIO(2) |
1705 ES_PRIO(3));
1706
1707 if ((rdev->family) == CHIP_R600) {
1708 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1709 NUM_VS_GPRS(124) |
1710 NUM_CLAUSE_TEMP_GPRS(4));
1711 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1712 NUM_ES_GPRS(0));
1713 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1714 NUM_VS_THREADS(48) |
1715 NUM_GS_THREADS(4) |
1716 NUM_ES_THREADS(4));
1717 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1718 NUM_VS_STACK_ENTRIES(128));
1719 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1720 NUM_ES_STACK_ENTRIES(0));
1721 } else if (((rdev->family) == CHIP_RV610) ||
1722 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1723 ((rdev->family) == CHIP_RS780) ||
1724 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1725 /* no vertex cache */
1726 sq_config &= ~VC_ENABLE;
1727
1728 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1729 NUM_VS_GPRS(44) |
1730 NUM_CLAUSE_TEMP_GPRS(2));
1731 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1732 NUM_ES_GPRS(17));
1733 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1734 NUM_VS_THREADS(78) |
1735 NUM_GS_THREADS(4) |
1736 NUM_ES_THREADS(31));
1737 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1738 NUM_VS_STACK_ENTRIES(40));
1739 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1740 NUM_ES_STACK_ENTRIES(16));
1741 } else if (((rdev->family) == CHIP_RV630) ||
1742 ((rdev->family) == CHIP_RV635)) {
1743 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1744 NUM_VS_GPRS(44) |
1745 NUM_CLAUSE_TEMP_GPRS(2));
1746 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1747 NUM_ES_GPRS(18));
1748 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1749 NUM_VS_THREADS(78) |
1750 NUM_GS_THREADS(4) |
1751 NUM_ES_THREADS(31));
1752 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1753 NUM_VS_STACK_ENTRIES(40));
1754 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1755 NUM_ES_STACK_ENTRIES(16));
1756 } else if ((rdev->family) == CHIP_RV670) {
1757 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1758 NUM_VS_GPRS(44) |
1759 NUM_CLAUSE_TEMP_GPRS(2));
1760 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1761 NUM_ES_GPRS(17));
1762 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1763 NUM_VS_THREADS(78) |
1764 NUM_GS_THREADS(4) |
1765 NUM_ES_THREADS(31));
1766 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1767 NUM_VS_STACK_ENTRIES(64));
1768 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1769 NUM_ES_STACK_ENTRIES(64));
1770 }
1771
1772 WREG32(SQ_CONFIG, sq_config);
1773 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1774 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1775 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1776 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1777 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1778
1779 if (((rdev->family) == CHIP_RV610) ||
1780 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1781 ((rdev->family) == CHIP_RS780) ||
1782 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1783 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1784 } else {
1785 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1786 }
1787
1788 /* More default values. 2D/3D driver should adjust as needed */
1789 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1790 S1_X(0x4) | S1_Y(0xc)));
1791 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1792 S1_X(0x2) | S1_Y(0x2) |
1793 S2_X(0xa) | S2_Y(0x6) |
1794 S3_X(0x6) | S3_Y(0xa)));
1795 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1796 S1_X(0x4) | S1_Y(0xc) |
1797 S2_X(0x1) | S2_Y(0x6) |
1798 S3_X(0xa) | S3_Y(0xe)));
1799 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1800 S5_X(0x0) | S5_Y(0x0) |
1801 S6_X(0xb) | S6_Y(0x4) |
1802 S7_X(0x7) | S7_Y(0x8)));
1803
1804 WREG32(VGT_STRMOUT_EN, 0);
1805 tmp = rdev->config.r600.max_pipes * 16;
1806 switch (rdev->family) {
1807 case CHIP_RV610:
3ce0a23d 1808 case CHIP_RV620:
ee59f2b4
AD		 1809 case CHIP_RS780:
1810 case CHIP_RS880:
3ce0a23d
JG		 1811 tmp += 32;
1812 break;
1813 case CHIP_RV670:
1814 tmp += 128;
1815 break;
1816 default:
1817 break;
1818 }
1819 if (tmp > 256) {
1820 tmp = 256;
1821 }
1822 WREG32(VGT_ES_PER_GS, 128);
1823 WREG32(VGT_GS_PER_ES, tmp);
1824 WREG32(VGT_GS_PER_VS, 2);
1825 WREG32(VGT_GS_VERTEX_REUSE, 16);
1826
1827 /* more default values. 2D/3D driver should adjust as needed */
1828 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1829 WREG32(VGT_STRMOUT_EN, 0);
1830 WREG32(SX_MISC, 0);
1831 WREG32(PA_SC_MODE_CNTL, 0);
1832 WREG32(PA_SC_AA_CONFIG, 0);
1833 WREG32(PA_SC_LINE_STIPPLE, 0);
1834 WREG32(SPI_INPUT_Z, 0);
1835 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1836 WREG32(CB_COLOR7_FRAG, 0);
1837
1838 /* Clear render buffer base addresses */
1839 WREG32(CB_COLOR0_BASE, 0);
1840 WREG32(CB_COLOR1_BASE, 0);
1841 WREG32(CB_COLOR2_BASE, 0);
1842 WREG32(CB_COLOR3_BASE, 0);
1843 WREG32(CB_COLOR4_BASE, 0);
1844 WREG32(CB_COLOR5_BASE, 0);
1845 WREG32(CB_COLOR6_BASE, 0);
1846 WREG32(CB_COLOR7_BASE, 0);
1847 WREG32(CB_COLOR7_FRAG, 0);
1848
1849 switch (rdev->family) {
1850 case CHIP_RV610:
3ce0a23d 1851 case CHIP_RV620:
ee59f2b4
AD		 1852 case CHIP_RS780:
1853 case CHIP_RS880:
3ce0a23d
JG		 1854 tmp = TC_L2_SIZE(8);
1855 break;
1856 case CHIP_RV630:
1857 case CHIP_RV635:
1858 tmp = TC_L2_SIZE(4);
1859 break;
1860 case CHIP_R600:
1861 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1862 break;
1863 default:
1864 tmp = TC_L2_SIZE(0);
1865 break;
1866 }
1867 WREG32(TC_CNTL, tmp);
1868
1869 tmp = RREG32(HDP_HOST_PATH_CNTL);
1870 WREG32(HDP_HOST_PATH_CNTL, tmp);
1871
1872 tmp = RREG32(ARB_POP);
1873 tmp |= ENABLE_TC128;
1874 WREG32(ARB_POP, tmp);
1875
1876 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1877 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1878 NUM_CLIP_SEQ(3)));
1879 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1880}
1881
1882
771fe6b9
JG		 1883/*
1884 * Indirect registers accessor
1885 */
3ce0a23d
JG		 1886u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1887{
1888 u32 r;
1889
1890 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1891 (void)RREG32(PCIE_PORT_INDEX);
1892 r = RREG32(PCIE_PORT_DATA);
1893 return r;
1894}
1895
1896void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1897{
1898 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1899 (void)RREG32(PCIE_PORT_INDEX);
1900 WREG32(PCIE_PORT_DATA, (v));
1901 (void)RREG32(PCIE_PORT_DATA);
1902}
1903
3ce0a23d
JG		 1904/*
1905 * CP & Ring
1906 */
1907void r600_cp_stop(struct radeon_device *rdev)
1908{
1909 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1910}
1911
d8f60cfc 1912int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1913{
1914 struct platform_device *pdev;
1915 const char *chip_name;
d8f60cfc
AD		 1916 const char *rlc_chip_name;
1917 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1918 char fw_name[30];
1919 int err;
1920
1921 DRM_DEBUG("\n");
1922
1923 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1924 err = IS_ERR(pdev);
1925 if (err) {
1926 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1927 return -EINVAL;
1928 }
1929
1930 switch (rdev->family) {
d8f60cfc
AD		 1931 case CHIP_R600:
1932 chip_name = "R600";
1933 rlc_chip_name = "R600";
1934 break;
1935 case CHIP_RV610:
1936 chip_name = "RV610";
1937 rlc_chip_name = "R600";
1938 break;
1939 case CHIP_RV630:
1940 chip_name = "RV630";
1941 rlc_chip_name = "R600";
1942 break;
1943 case CHIP_RV620:
1944 chip_name = "RV620";
1945 rlc_chip_name = "R600";
1946 break;
1947 case CHIP_RV635:
1948 chip_name = "RV635";
1949 rlc_chip_name = "R600";
1950 break;
1951 case CHIP_RV670:
1952 chip_name = "RV670";
1953 rlc_chip_name = "R600";
1954 break;
3ce0a23d 1955 case CHIP_RS780:
d8f60cfc
AD		 1956 case CHIP_RS880:
1957 chip_name = "RS780";
1958 rlc_chip_name = "R600";
1959 break;
1960 case CHIP_RV770:
1961 chip_name = "RV770";
1962 rlc_chip_name = "R700";
1963 break;
3ce0a23d 1964 case CHIP_RV730:
d8f60cfc
AD		 1965 case CHIP_RV740:
1966 chip_name = "RV730";
1967 rlc_chip_name = "R700";
1968 break;
1969 case CHIP_RV710:
1970 chip_name = "RV710";
1971 rlc_chip_name = "R700";
1972 break;
fe251e2f
AD		 1973 case CHIP_CEDAR:
1974 chip_name = "CEDAR";
45f9a39b 1975 rlc_chip_name = "CEDAR";
fe251e2f
AD		 1976 break;
1977 case CHIP_REDWOOD:
1978 chip_name = "REDWOOD";
45f9a39b 1979 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 1980 break;
1981 case CHIP_JUNIPER:
1982 chip_name = "JUNIPER";
45f9a39b 1983 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 1984 break;
1985 case CHIP_CYPRESS:
1986 case CHIP_HEMLOCK:
1987 chip_name = "CYPRESS";
45f9a39b 1988 rlc_chip_name = "CYPRESS";
fe251e2f 1989 break;
3ce0a23d
JG		 1990 default: BUG();
1991 }
1992
fe251e2f
AD		 1993 if (rdev->family >= CHIP_CEDAR) {
1994 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1995 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 1996 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 1997 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 1998 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1999 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2000 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2001 } else {
2002 pfp_req_size = PFP_UCODE_SIZE * 4;
2003 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2004 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2005 }
2006
d8f60cfc 2007 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2008
2009 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2010 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2011 if (err)
2012 goto out;
2013 if (rdev->pfp_fw->size != pfp_req_size) {
2014 printk(KERN_ERR
2015 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2016 rdev->pfp_fw->size, fw_name);
2017 err = -EINVAL;
2018 goto out;
2019 }
2020
2021 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2022 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2023 if (err)
2024 goto out;
2025 if (rdev->me_fw->size != me_req_size) {
2026 printk(KERN_ERR
2027 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2028 rdev->me_fw->size, fw_name);
2029 err = -EINVAL;
2030 }
d8f60cfc
AD		 2031
2032 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2033 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2034 if (err)
2035 goto out;
2036 if (rdev->rlc_fw->size != rlc_req_size) {
2037 printk(KERN_ERR
2038 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2039 rdev->rlc_fw->size, fw_name);
2040 err = -EINVAL;
2041 }
2042
3ce0a23d
JG		 2043out:
2044 platform_device_unregister(pdev);
2045
2046 if (err) {
2047 if (err != -EINVAL)
2048 printk(KERN_ERR
2049 "r600_cp: Failed to load firmware \"%s\"\n",
2050 fw_name);
2051 release_firmware(rdev->pfp_fw);
2052 rdev->pfp_fw = NULL;
2053 release_firmware(rdev->me_fw);
2054 rdev->me_fw = NULL;
d8f60cfc
AD		 2055 release_firmware(rdev->rlc_fw);
2056 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2057 }
2058 return err;
2059}
2060
2061static int r600_cp_load_microcode(struct radeon_device *rdev)
2062{
2063 const __be32 *fw_data;
2064 int i;
2065
2066 if (!rdev->me_fw || !rdev->pfp_fw)
2067 return -EINVAL;
2068
2069 r600_cp_stop(rdev);
2070
2071 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2072
2073 /* Reset cp */
2074 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2075 RREG32(GRBM_SOFT_RESET);
2076 mdelay(15);
2077 WREG32(GRBM_SOFT_RESET, 0);
2078
2079 WREG32(CP_ME_RAM_WADDR, 0);
2080
2081 fw_data = (const __be32 *)rdev->me_fw->data;
2082 WREG32(CP_ME_RAM_WADDR, 0);
2083 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2084 WREG32(CP_ME_RAM_DATA,
2085 be32_to_cpup(fw_data++));
2086
2087 fw_data = (const __be32 *)rdev->pfp_fw->data;
2088 WREG32(CP_PFP_UCODE_ADDR, 0);
2089 for (i = 0; i < PFP_UCODE_SIZE; i++)
2090 WREG32(CP_PFP_UCODE_DATA,
2091 be32_to_cpup(fw_data++));
2092
2093 WREG32(CP_PFP_UCODE_ADDR, 0);
2094 WREG32(CP_ME_RAM_WADDR, 0);
2095 WREG32(CP_ME_RAM_RADDR, 0);
2096 return 0;
2097}
2098
2099int r600_cp_start(struct radeon_device *rdev)
2100{
2101 int r;
2102 uint32_t cp_me;
2103
2104 r = radeon_ring_lock(rdev, 7);
2105 if (r) {
2106 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2107 return r;
2108 }
2109 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2110 radeon_ring_write(rdev, 0x1);
fe251e2f
AD		 2111 if (rdev->family >= CHIP_CEDAR) {
2112 radeon_ring_write(rdev, 0x0);
2113 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
2114 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2115 radeon_ring_write(rdev, 0x0);
2116 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 2117 } else {
2118 radeon_ring_write(rdev, 0x3);
2119 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 2120 }
2121 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2122 radeon_ring_write(rdev, 0);
2123 radeon_ring_write(rdev, 0);
2124 radeon_ring_unlock_commit(rdev);
2125
2126 cp_me = 0xff;
2127 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2128 return 0;
2129}
2130
2131int r600_cp_resume(struct radeon_device *rdev)
2132{
2133 u32 tmp;
2134 u32 rb_bufsz;
2135 int r;
2136
2137 /* Reset cp */
2138 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2139 RREG32(GRBM_SOFT_RESET);
2140 mdelay(15);
2141 WREG32(GRBM_SOFT_RESET, 0);
2142
2143 /* Set ring buffer size */
2144 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
d6f28938 2145 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2146#ifdef __BIG_ENDIAN
d6f28938 2147 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2148#endif
d6f28938 2149 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 2150 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2151
2152 /* Set the write pointer delay */
2153 WREG32(CP_RB_WPTR_DELAY, 0);
2154
2155 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2156 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2157 WREG32(CP_RB_RPTR_WR, 0);
2158 WREG32(CP_RB_WPTR, 0);
2159 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
2160 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
2161 mdelay(1);
2162 WREG32(CP_RB_CNTL, tmp);
2163
2164 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2165 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2166
2167 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2168 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2169
2170 r600_cp_start(rdev);
2171 rdev->cp.ready = true;
2172 r = radeon_ring_test(rdev);
2173 if (r) {
2174 rdev->cp.ready = false;
2175 return r;
2176 }
2177 return 0;
2178}
2179
2180void r600_cp_commit(struct radeon_device *rdev)
2181{
2182 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2183 (void)RREG32(CP_RB_WPTR);
2184}
2185
2186void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2187{
2188 u32 rb_bufsz;
2189
2190 /* Align ring size */
2191 rb_bufsz = drm_order(ring_size / 8);
2192 ring_size = (1 << (rb_bufsz + 1)) * 4;
2193 rdev->cp.ring_size = ring_size;
2194 rdev->cp.align_mask = 16 - 1;
2195}
2196
655efd3d
JG		 2197void r600_cp_fini(struct radeon_device *rdev)
2198{
2199 r600_cp_stop(rdev);
2200 radeon_ring_fini(rdev);
2201}
2202
3ce0a23d
JG		 2203
2204/*
2205 * GPU scratch registers helpers function.
2206 */
2207void r600_scratch_init(struct radeon_device *rdev)
2208{
2209 int i;
2210
2211 rdev->scratch.num_reg = 7;
2212 for (i = 0; i < rdev->scratch.num_reg; i++) {
2213 rdev->scratch.free[i] = true;
2214 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
2215 }
2216}
2217
2218int r600_ring_test(struct radeon_device *rdev)
2219{
2220 uint32_t scratch;
2221 uint32_t tmp = 0;
2222 unsigned i;
2223 int r;
2224
2225 r = radeon_scratch_get(rdev, &scratch);
2226 if (r) {
2227 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2228 return r;
2229 }
2230 WREG32(scratch, 0xCAFEDEAD);
2231 r = radeon_ring_lock(rdev, 3);
2232 if (r) {
2233 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2234 radeon_scratch_free(rdev, scratch);
2235 return r;
2236 }
2237 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2238 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2239 radeon_ring_write(rdev, 0xDEADBEEF);
2240 radeon_ring_unlock_commit(rdev);
2241 for (i = 0; i < rdev->usec_timeout; i++) {
2242 tmp = RREG32(scratch);
2243 if (tmp == 0xDEADBEEF)
2244 break;
2245 DRM_UDELAY(1);
2246 }
2247 if (i < rdev->usec_timeout) {
2248 DRM_INFO("ring test succeeded in %d usecs\n", i);
2249 } else {
2250 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2251 scratch, tmp);
2252 r = -EINVAL;
2253 }
2254 radeon_scratch_free(rdev, scratch);
2255 return r;
2256}
2257
81cc35bf
JG		 2258void r600_wb_disable(struct radeon_device *rdev)
2259{
4c788679
JG		 2260 int r;
2261
81cc35bf
JG		 2262 WREG32(SCRATCH_UMSK, 0);
2263 if (rdev->wb.wb_obj) {
4c788679
JG		 2264 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2265 if (unlikely(r != 0))
2266 return;
2267 radeon_bo_kunmap(rdev->wb.wb_obj);
2268 radeon_bo_unpin(rdev->wb.wb_obj);
2269 radeon_bo_unreserve(rdev->wb.wb_obj);
81cc35bf
JG		 2270 }
2271}
2272
2273void r600_wb_fini(struct radeon_device *rdev)
2274{
2275 r600_wb_disable(rdev);
2276 if (rdev->wb.wb_obj) {
4c788679 2277 radeon_bo_unref(&rdev->wb.wb_obj);
81cc35bf
JG		 2278 rdev->wb.wb = NULL;
2279 rdev->wb.wb_obj = NULL;
2280 }
2281}
2282
2283int r600_wb_enable(struct radeon_device *rdev)
3ce0a23d
JG		 2284{
2285 int r;
2286
2287 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 2288 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2289 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
3ce0a23d 2290 if (r) {
4c788679 2291 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
3ce0a23d
JG		 2292 return r;
2293 }
4c788679
JG		 2294 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2295 if (unlikely(r != 0)) {
2296 r600_wb_fini(rdev);
3ce0a23d
JG		 2297 return r;
2298 }
4c788679 2299 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
81cc35bf 2300 &rdev->wb.gpu_addr);
3ce0a23d 2301 if (r) {
4c788679
JG		 2302 radeon_bo_unreserve(rdev->wb.wb_obj);
2303 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
81cc35bf 2304 r600_wb_fini(rdev);
3ce0a23d
JG		 2305 return r;
2306 }
4c788679
JG		 2307 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2308 radeon_bo_unreserve(rdev->wb.wb_obj);
3ce0a23d 2309 if (r) {
4c788679 2310 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
81cc35bf 2311 r600_wb_fini(rdev);
3ce0a23d
JG		 2312 return r;
2313 }
2314 }
2315 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2316 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2317 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2318 WREG32(SCRATCH_UMSK, 0xff);
2319 return 0;
2320}
2321
3ce0a23d
JG		 2322void r600_fence_ring_emit(struct radeon_device *rdev,
2323 struct radeon_fence *fence)
2324{
d8f60cfc 2325 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
44224c3f
AD		 2326
2327 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2328 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2329 /* wait for 3D idle clean */
2330 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2331 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2332 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
3ce0a23d
JG		 2333 /* Emit fence sequence & fire IRQ */
2334 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2335 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2336 radeon_ring_write(rdev, fence->seq);
d8f60cfc
AD		 2337 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2338 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2339 radeon_ring_write(rdev, RB_INT_STAT);
3ce0a23d
JG		 2340}
2341
3ce0a23d
JG		 2342int r600_copy_blit(struct radeon_device *rdev,
2343 uint64_t src_offset, uint64_t dst_offset,
2344 unsigned num_pages, struct radeon_fence *fence)
2345{
ff82f052
JG		 2346 int r;
2347
2348 mutex_lock(&rdev->r600_blit.mutex);
2349 rdev->r600_blit.vb_ib = NULL;
2350 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2351 if (r) {
2352 if (rdev->r600_blit.vb_ib)
2353 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2354 mutex_unlock(&rdev->r600_blit.mutex);
2355 return r;
2356 }
a77f1718 2357 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 2358 r600_blit_done_copy(rdev, fence);
ff82f052 2359 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2360 return 0;
2361}
2362
3ce0a23d
JG		 2363int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2364 uint32_t tiling_flags, uint32_t pitch,
2365 uint32_t offset, uint32_t obj_size)
2366{
2367 /* FIXME: implement */
2368 return 0;
2369}
2370
2371void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2372{
2373 /* FIXME: implement */
2374}
2375
2376
2377bool r600_card_posted(struct radeon_device *rdev)
2378{
2379 uint32_t reg;
2380
2381 /* first check CRTCs */
2382 reg = RREG32(D1CRTC_CONTROL) |
2383 RREG32(D2CRTC_CONTROL);
2384 if (reg & CRTC_EN)
2385 return true;
2386
2387 /* then check MEM_SIZE, in case the crtcs are off */
2388 if (RREG32(CONFIG_MEMSIZE))
2389 return true;
2390
2391 return false;
2392}
2393
fc30b8ef 2394int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 2395{
2396 int r;
2397
779720a3
AD		 2398 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2399 r = r600_init_microcode(rdev);
2400 if (r) {
2401 DRM_ERROR("Failed to load firmware!\n");
2402 return r;
2403 }
2404 }
2405
a3c1945a 2406 r600_mc_program(rdev);
1a029b76
JG		 2407 if (rdev->flags & RADEON_IS_AGP) {
2408 r600_agp_enable(rdev);
2409 } else {
2410 r = r600_pcie_gart_enable(rdev);
2411 if (r)
2412 return r;
2413 }
3ce0a23d 2414 r600_gpu_init(rdev);
c38c7b64
JG		 2415 r = r600_blit_init(rdev);
2416 if (r) {
2417 r600_blit_fini(rdev);
2418 rdev->asic->copy = NULL;
2419 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2420 }
ff82f052
JG		 2421 /* pin copy shader into vram */
2422 if (rdev->r600_blit.shader_obj) {
2423 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2424 if (unlikely(r != 0))
2425 return r;
2426 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2427 &rdev->r600_blit.shader_gpu_addr);
2428 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
7923c615 2429 if (r) {
ff82f052 2430 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
7923c615
AD		 2431 return r;
2432 }
2433 }
d8f60cfc 2434 /* Enable IRQ */
d8f60cfc
AD		 2435 r = r600_irq_init(rdev);
2436 if (r) {
2437 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2438 radeon_irq_kms_fini(rdev);
2439 return r;
2440 }
2441 r600_irq_set(rdev);
2442
3ce0a23d
JG		 2443 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2444 if (r)
2445 return r;
2446 r = r600_cp_load_microcode(rdev);
2447 if (r)
2448 return r;
2449 r = r600_cp_resume(rdev);
2450 if (r)
2451 return r;
81cc35bf
JG		 2452 /* write back buffer are not vital so don't worry about failure */
2453 r600_wb_enable(rdev);
3ce0a23d
JG		 2454 return 0;
2455}
2456
28d52043
DA		 2457void r600_vga_set_state(struct radeon_device *rdev, bool state)
2458{
2459 uint32_t temp;
2460
2461 temp = RREG32(CONFIG_CNTL);
2462 if (state == false) {
2463 temp &= ~(1<<0);
2464 temp |= (1<<1);
2465 } else {
2466 temp &= ~(1<<1);
2467 }
2468 WREG32(CONFIG_CNTL, temp);
2469}
2470
fc30b8ef
DA		 2471int r600_resume(struct radeon_device *rdev)
2472{
2473 int r;
2474
1a029b76
JG		 2475 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2476 * posting will perform necessary task to bring back GPU into good
2477 * shape.
2478 */
fc30b8ef 2479 /* post card */
e7d40b9a 2480 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2481 /* Initialize clocks */
2482 r = radeon_clocks_init(rdev);
2483 if (r) {
2484 return r;
2485 }
2486
2487 r = r600_startup(rdev);
2488 if (r) {
2489 DRM_ERROR("r600 startup failed on resume\n");
2490 return r;
2491 }
2492
62a8ea3f 2493 r = r600_ib_test(rdev);
fc30b8ef
DA		 2494 if (r) {
2495 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2496 return r;
2497 }
38fd2c6f
RM		 2498
2499 r = r600_audio_init(rdev);
2500 if (r) {
2501 DRM_ERROR("radeon: audio resume failed\n");
2502 return r;
2503 }
2504
fc30b8ef
DA		 2505 return r;
2506}
2507
3ce0a23d
JG		 2508int r600_suspend(struct radeon_device *rdev)
2509{
4c788679
JG		 2510 int r;
2511
38fd2c6f 2512 r600_audio_fini(rdev);
3ce0a23d
JG		 2513 /* FIXME: we should wait for ring to be empty */
2514 r600_cp_stop(rdev);
bc1a631e 2515 rdev->cp.ready = false;
0c45249f 2516 r600_irq_suspend(rdev);
81cc35bf 2517 r600_wb_disable(rdev);
4aac0473 2518 r600_pcie_gart_disable(rdev);
bc1a631e 2519 /* unpin shaders bo */
30d2d9a5
JG		 2520 if (rdev->r600_blit.shader_obj) {
2521 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2522 if (!r) {
2523 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2524 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2525 }
2526 }
3ce0a23d
JG		 2527 return 0;
2528}
2529
2530/* Plan is to move initialization in that function and use
2531 * helper function so that radeon_device_init pretty much
2532 * do nothing more than calling asic specific function. This
2533 * should also allow to remove a bunch of callback function
2534 * like vram_info.
2535 */
2536int r600_init(struct radeon_device *rdev)
771fe6b9 2537{
3ce0a23d 2538 int r;
771fe6b9 2539
3ce0a23d
JG		 2540 r = radeon_dummy_page_init(rdev);
2541 if (r)
2542 return r;
2543 if (r600_debugfs_mc_info_init(rdev)) {
2544 DRM_ERROR("Failed to register debugfs file for mc !\n");
2545 }
2546 /* This don't do much */
2547 r = radeon_gem_init(rdev);
2548 if (r)
2549 return r;
2550 /* Read BIOS */
2551 if (!radeon_get_bios(rdev)) {
2552 if (ASIC_IS_AVIVO(rdev))
2553 return -EINVAL;
2554 }
2555 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2556 if (!rdev->is_atom_bios) {
2557 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2558 return -EINVAL;
e7d40b9a 2559 }
3ce0a23d
JG		 2560 r = radeon_atombios_init(rdev);
2561 if (r)
2562 return r;
2563 /* Post card if necessary */
72542d77
DA		 2564 if (!r600_card_posted(rdev)) {
2565 if (!rdev->bios) {
2566 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2567 return -EINVAL;
2568 }
3ce0a23d
JG		 2569 DRM_INFO("GPU not posted. posting now...\n");
2570 atom_asic_init(rdev->mode_info.atom_context);
2571 }
2572 /* Initialize scratch registers */
2573 r600_scratch_init(rdev);
2574 /* Initialize surface registers */
2575 radeon_surface_init(rdev);
7433874e 2576 /* Initialize clocks */
5e6dde7e 2577 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2578 r = radeon_clocks_init(rdev);
2579 if (r)
2580 return r;
2581 /* Fence driver */
2582 r = radeon_fence_driver_init(rdev);
2583 if (r)
2584 return r;
700a0cc0
JG		 2585 if (rdev->flags & RADEON_IS_AGP) {
2586 r = radeon_agp_init(rdev);
2587 if (r)
2588 radeon_agp_disable(rdev);
2589 }
3ce0a23d 2590 r = r600_mc_init(rdev);
b574f251 2591 if (r)
3ce0a23d 2592 return r;
3ce0a23d 2593 /* Memory manager */
4c788679 2594 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2595 if (r)
2596 return r;
d8f60cfc
AD		 2597
2598 r = radeon_irq_kms_init(rdev);
2599 if (r)
2600 return r;
2601
3ce0a23d
JG		 2602 rdev->cp.ring_obj = NULL;
2603 r600_ring_init(rdev, 1024 * 1024);
2604
d8f60cfc
AD		 2605 rdev->ih.ring_obj = NULL;
2606 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2607
4aac0473
JG		 2608 r = r600_pcie_gart_init(rdev);
2609 if (r)
2610 return r;
2611
779720a3 2612 rdev->accel_working = true;
fc30b8ef 2613 r = r600_startup(rdev);
3ce0a23d 2614 if (r) {
655efd3d
JG		 2615 dev_err(rdev->dev, "disabling GPU acceleration\n");
2616 r600_cp_fini(rdev);
75c81298 2617 r600_wb_fini(rdev);
655efd3d
JG		 2618 r600_irq_fini(rdev);
2619 radeon_irq_kms_fini(rdev);
75c81298 2620 r600_pcie_gart_fini(rdev);
733289c2 2621 rdev->accel_working = false;
3ce0a23d 2622 }
733289c2
JG		 2623 if (rdev->accel_working) {
2624 r = radeon_ib_pool_init(rdev);
2625 if (r) {
db96380e 2626 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2627 rdev->accel_working = false;
db96380e
JG		 2628 } else {
2629 r = r600_ib_test(rdev);
2630 if (r) {
2631 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2632 rdev->accel_working = false;
2633 }
733289c2 2634 }
3ce0a23d 2635 }
dafc3bd5
CK		 2636
2637 r = r600_audio_init(rdev);
2638 if (r)
2639 return r; /* TODO error handling */
3ce0a23d
JG		 2640 return 0;
2641}
2642
2643void r600_fini(struct radeon_device *rdev)
2644{
dafc3bd5 2645 r600_audio_fini(rdev);
3ce0a23d 2646 r600_blit_fini(rdev);
655efd3d
JG		 2647 r600_cp_fini(rdev);
2648 r600_wb_fini(rdev);
d8f60cfc
AD		 2649 r600_irq_fini(rdev);
2650 radeon_irq_kms_fini(rdev);
4aac0473 2651 r600_pcie_gart_fini(rdev);
655efd3d 2652 radeon_agp_fini(rdev);
3ce0a23d
JG		 2653 radeon_gem_fini(rdev);
2654 radeon_fence_driver_fini(rdev);
2655 radeon_clocks_fini(rdev);
4c788679 2656 radeon_bo_fini(rdev);
e7d40b9a 2657 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2658 kfree(rdev->bios);
2659 rdev->bios = NULL;
2660 radeon_dummy_page_fini(rdev);
2661}
2662
2663
2664/*
2665 * CS stuff
2666 */
2667void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2668{
2669 /* FIXME: implement */
2670 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2671 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2672 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2673 radeon_ring_write(rdev, ib->length_dw);
2674}
2675
2676int r600_ib_test(struct radeon_device *rdev)
2677{
2678 struct radeon_ib *ib;
2679 uint32_t scratch;
2680 uint32_t tmp = 0;
2681 unsigned i;
2682 int r;
2683
2684 r = radeon_scratch_get(rdev, &scratch);
2685 if (r) {
2686 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2687 return r;
2688 }
2689 WREG32(scratch, 0xCAFEDEAD);
2690 r = radeon_ib_get(rdev, &ib);
2691 if (r) {
2692 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2693 return r;
2694 }
2695 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2696 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2697 ib->ptr[2] = 0xDEADBEEF;
2698 ib->ptr[3] = PACKET2(0);
2699 ib->ptr[4] = PACKET2(0);
2700 ib->ptr[5] = PACKET2(0);
2701 ib->ptr[6] = PACKET2(0);
2702 ib->ptr[7] = PACKET2(0);
2703 ib->ptr[8] = PACKET2(0);
2704 ib->ptr[9] = PACKET2(0);
2705 ib->ptr[10] = PACKET2(0);
2706 ib->ptr[11] = PACKET2(0);
2707 ib->ptr[12] = PACKET2(0);
2708 ib->ptr[13] = PACKET2(0);
2709 ib->ptr[14] = PACKET2(0);
2710 ib->ptr[15] = PACKET2(0);
2711 ib->length_dw = 16;
2712 r = radeon_ib_schedule(rdev, ib);
2713 if (r) {
2714 radeon_scratch_free(rdev, scratch);
2715 radeon_ib_free(rdev, &ib);
2716 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2717 return r;
2718 }
2719 r = radeon_fence_wait(ib->fence, false);
2720 if (r) {
2721 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2722 return r;
2723 }
2724 for (i = 0; i < rdev->usec_timeout; i++) {
2725 tmp = RREG32(scratch);
2726 if (tmp == 0xDEADBEEF)
2727 break;
2728 DRM_UDELAY(1);
2729 }
2730 if (i < rdev->usec_timeout) {
2731 DRM_INFO("ib test succeeded in %u usecs\n", i);
2732 } else {
2733 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2734 scratch, tmp);
2735 r = -EINVAL;
2736 }
2737 radeon_scratch_free(rdev, scratch);
2738 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2739 return r;
2740}
2741
d8f60cfc
AD		 2742/*
2743 * Interrupts
2744 *
2745 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2746 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2747 * writing to the ring and the GPU consuming, the GPU writes to the ring
2748 * and host consumes. As the host irq handler processes interrupts, it
2749 * increments the rptr. When the rptr catches up with the wptr, all the
2750 * current interrupts have been processed.
2751 */
2752
2753void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2754{
2755 u32 rb_bufsz;
2756
2757 /* Align ring size */
2758 rb_bufsz = drm_order(ring_size / 4);
2759 ring_size = (1 << rb_bufsz) * 4;
2760 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2761 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2762 rdev->ih.rptr = 0;
d8f60cfc
AD		 2763}
2764
0c45249f 2765static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2766{
2767 int r;
2768
d8f60cfc
AD		 2769 /* Allocate ring buffer */
2770 if (rdev->ih.ring_obj == NULL) {
4c788679
JG		 2771 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2772 true,
2773 RADEON_GEM_DOMAIN_GTT,
2774 &rdev->ih.ring_obj);
d8f60cfc
AD		 2775 if (r) {
2776 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2777 return r;
2778 }
4c788679
JG		 2779 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2780 if (unlikely(r != 0))
2781 return r;
2782 r = radeon_bo_pin(rdev->ih.ring_obj,
2783 RADEON_GEM_DOMAIN_GTT,
2784 &rdev->ih.gpu_addr);
d8f60cfc 2785 if (r) {
4c788679 2786 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2787 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2788 return r;
2789 }
4c788679
JG		 2790 r = radeon_bo_kmap(rdev->ih.ring_obj,
2791 (void **)&rdev->ih.ring);
2792 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2793 if (r) {
2794 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2795 return r;
2796 }
2797 }
d8f60cfc
AD		 2798 return 0;
2799}
2800
2801static void r600_ih_ring_fini(struct radeon_device *rdev)
2802{
4c788679 2803 int r;
d8f60cfc 2804 if (rdev->ih.ring_obj) {
4c788679
JG		 2805 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2806 if (likely(r == 0)) {
2807 radeon_bo_kunmap(rdev->ih.ring_obj);
2808 radeon_bo_unpin(rdev->ih.ring_obj);
2809 radeon_bo_unreserve(rdev->ih.ring_obj);
2810 }
2811 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2812 rdev->ih.ring = NULL;
2813 rdev->ih.ring_obj = NULL;
2814 }
2815}
2816
45f9a39b 2817void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2818{
2819
45f9a39b
AD		 2820 if ((rdev->family >= CHIP_RV770) &&
2821 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2822 /* r7xx asics need to soft reset RLC before halting */
2823 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2824 RREG32(SRBM_SOFT_RESET);
2825 udelay(15000);
2826 WREG32(SRBM_SOFT_RESET, 0);
2827 RREG32(SRBM_SOFT_RESET);
2828 }
2829
2830 WREG32(RLC_CNTL, 0);
2831}
2832
2833static void r600_rlc_start(struct radeon_device *rdev)
2834{
2835 WREG32(RLC_CNTL, RLC_ENABLE);
2836}
2837
2838static int r600_rlc_init(struct radeon_device *rdev)
2839{
2840 u32 i;
2841 const __be32 *fw_data;
2842
2843 if (!rdev->rlc_fw)
2844 return -EINVAL;
2845
2846 r600_rlc_stop(rdev);
2847
2848 WREG32(RLC_HB_BASE, 0);
2849 WREG32(RLC_HB_CNTL, 0);
2850 WREG32(RLC_HB_RPTR, 0);
2851 WREG32(RLC_HB_WPTR, 0);
2852 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2853 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2854 WREG32(RLC_MC_CNTL, 0);
2855 WREG32(RLC_UCODE_CNTL, 0);
2856
2857 fw_data = (const __be32 *)rdev->rlc_fw->data;
45f9a39b
AD		 2858 if (rdev->family >= CHIP_CEDAR) {
2859 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2860 WREG32(RLC_UCODE_ADDR, i);
2861 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2862 }
2863 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2864 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2865 WREG32(RLC_UCODE_ADDR, i);
2866 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2867 }
2868 } else {
2869 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2870 WREG32(RLC_UCODE_ADDR, i);
2871 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2872 }
2873 }
2874 WREG32(RLC_UCODE_ADDR, 0);
2875
2876 r600_rlc_start(rdev);
2877
2878 return 0;
2879}
2880
2881static void r600_enable_interrupts(struct radeon_device *rdev)
2882{
2883 u32 ih_cntl = RREG32(IH_CNTL);
2884 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2885
2886 ih_cntl |= ENABLE_INTR;
2887 ih_rb_cntl |= IH_RB_ENABLE;
2888 WREG32(IH_CNTL, ih_cntl);
2889 WREG32(IH_RB_CNTL, ih_rb_cntl);
2890 rdev->ih.enabled = true;
2891}
2892
45f9a39b 2893void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2894{
2895 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2896 u32 ih_cntl = RREG32(IH_CNTL);
2897
2898 ih_rb_cntl &= ~IH_RB_ENABLE;
2899 ih_cntl &= ~ENABLE_INTR;
2900 WREG32(IH_RB_CNTL, ih_rb_cntl);
2901 WREG32(IH_CNTL, ih_cntl);
2902 /* set rptr, wptr to 0 */
2903 WREG32(IH_RB_RPTR, 0);
2904 WREG32(IH_RB_WPTR, 0);
2905 rdev->ih.enabled = false;
2906 rdev->ih.wptr = 0;
2907 rdev->ih.rptr = 0;
2908}
2909
e0df1ac5
AD		 2910static void r600_disable_interrupt_state(struct radeon_device *rdev)
2911{
2912 u32 tmp;
2913
2914 WREG32(CP_INT_CNTL, 0);
2915 WREG32(GRBM_INT_CNTL, 0);
2916 WREG32(DxMODE_INT_MASK, 0);
2917 if (ASIC_IS_DCE3(rdev)) {
2918 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2919 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2920 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2921 WREG32(DC_HPD1_INT_CONTROL, tmp);
2922 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2923 WREG32(DC_HPD2_INT_CONTROL, tmp);
2924 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2925 WREG32(DC_HPD3_INT_CONTROL, tmp);
2926 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2927 WREG32(DC_HPD4_INT_CONTROL, tmp);
2928 if (ASIC_IS_DCE32(rdev)) {
2929 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2930 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2931 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2932 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2933 }
2934 } else {
2935 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2936 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2937 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2938 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2939 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2940 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2941 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2942 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2943 }
2944}
2945
d8f60cfc
AD		 2946int r600_irq_init(struct radeon_device *rdev)
2947{
2948 int ret = 0;
2949 int rb_bufsz;
2950 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2951
2952 /* allocate ring */
0c45249f 2953 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2954 if (ret)
2955 return ret;
2956
2957 /* disable irqs */
2958 r600_disable_interrupts(rdev);
2959
2960 /* init rlc */
2961 ret = r600_rlc_init(rdev);
2962 if (ret) {
2963 r600_ih_ring_fini(rdev);
2964 return ret;
2965 }
2966
2967 /* setup interrupt control */
2968 /* set dummy read address to ring address */
2969 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2970 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2971 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2972 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2973 */
2974 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2975 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2976 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2977 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2978
2979 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2980 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2981
2982 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2983 IH_WPTR_OVERFLOW_CLEAR |
2984 (rb_bufsz << 1));
2985 /* WPTR writeback, not yet */
2986 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2987 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2988 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2989
2990 WREG32(IH_RB_CNTL, ih_rb_cntl);
2991
2992 /* set rptr, wptr to 0 */
2993 WREG32(IH_RB_RPTR, 0);
2994 WREG32(IH_RB_WPTR, 0);
2995
2996 /* Default settings for IH_CNTL (disabled at first) */
2997 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2998 /* RPTR_REARM only works if msi's are enabled */
2999 if (rdev->msi_enabled)
3000 ih_cntl |= RPTR_REARM;
3001
3002#ifdef __BIG_ENDIAN
3003 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
3004#endif
3005 WREG32(IH_CNTL, ih_cntl);
3006
3007 /* force the active interrupt state to all disabled */
45f9a39b
AD		 3008 if (rdev->family >= CHIP_CEDAR)
3009 evergreen_disable_interrupt_state(rdev);
3010 else
3011 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3012
3013 /* enable irqs */
3014 r600_enable_interrupts(rdev);
3015
3016 return ret;
3017}
3018
0c45249f 3019void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3020{
45f9a39b 3021 r600_irq_disable(rdev);
d8f60cfc 3022 r600_rlc_stop(rdev);
0c45249f
JG		 3023}
3024
3025void r600_irq_fini(struct radeon_device *rdev)
3026{
3027 r600_irq_suspend(rdev);
d8f60cfc
AD		 3028 r600_ih_ring_fini(rdev);
3029}
3030
3031int r600_irq_set(struct radeon_device *rdev)
3032{
e0df1ac5
AD		 3033 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3034 u32 mode_int = 0;
3035 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3036 u32 grbm_int_cntl = 0;
f2594933 3037 u32 hdmi1, hdmi2;
d8f60cfc 3038
003e69f9
JG		 3039 if (!rdev->irq.installed) {
3040 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
3041 return -EINVAL;
3042 }
d8f60cfc 3043 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3044 if (!rdev->ih.enabled) {
3045 r600_disable_interrupts(rdev);
3046 /* force the active interrupt state to all disabled */
3047 r600_disable_interrupt_state(rdev);
d8f60cfc 3048 return 0;
79c2bbc5 3049 }
d8f60cfc 3050
f2594933 3051 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 3052 if (ASIC_IS_DCE3(rdev)) {
f2594933 3053 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3054 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3055 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3056 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3057 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3058 if (ASIC_IS_DCE32(rdev)) {
3059 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3060 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3061 }
3062 } else {
f2594933 3063 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3064 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3065 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3066 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3067 }
3068
d8f60cfc
AD		 3069 if (rdev->irq.sw_int) {
3070 DRM_DEBUG("r600_irq_set: sw int\n");
3071 cp_int_cntl |= RB_INT_ENABLE;
3072 }
3073 if (rdev->irq.crtc_vblank_int[0]) {
3074 DRM_DEBUG("r600_irq_set: vblank 0\n");
3075 mode_int |= D1MODE_VBLANK_INT_MASK;
3076 }
3077 if (rdev->irq.crtc_vblank_int[1]) {
3078 DRM_DEBUG("r600_irq_set: vblank 1\n");
3079 mode_int |= D2MODE_VBLANK_INT_MASK;
3080 }
e0df1ac5
AD		 3081 if (rdev->irq.hpd[0]) {
3082 DRM_DEBUG("r600_irq_set: hpd 1\n");
3083 hpd1 |= DC_HPDx_INT_EN;
3084 }
3085 if (rdev->irq.hpd[1]) {
3086 DRM_DEBUG("r600_irq_set: hpd 2\n");
3087 hpd2 |= DC_HPDx_INT_EN;
3088 }
3089 if (rdev->irq.hpd[2]) {
3090 DRM_DEBUG("r600_irq_set: hpd 3\n");
3091 hpd3 |= DC_HPDx_INT_EN;
3092 }
3093 if (rdev->irq.hpd[3]) {
3094 DRM_DEBUG("r600_irq_set: hpd 4\n");
3095 hpd4 |= DC_HPDx_INT_EN;
3096 }
3097 if (rdev->irq.hpd[4]) {
3098 DRM_DEBUG("r600_irq_set: hpd 5\n");
3099 hpd5 |= DC_HPDx_INT_EN;
3100 }
3101 if (rdev->irq.hpd[5]) {
3102 DRM_DEBUG("r600_irq_set: hpd 6\n");
3103 hpd6 |= DC_HPDx_INT_EN;
3104 }
f2594933
CK		 3105 if (rdev->irq.hdmi[0]) {
3106 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3107 hdmi1 |= R600_HDMI_INT_EN;
3108 }
3109 if (rdev->irq.hdmi[1]) {
3110 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3111 hdmi2 |= R600_HDMI_INT_EN;
3112 }
2031f77c
AD		 3113 if (rdev->irq.gui_idle) {
3114 DRM_DEBUG("gui idle\n");
3115 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3116 }
d8f60cfc
AD		 3117
3118 WREG32(CP_INT_CNTL, cp_int_cntl);
3119 WREG32(DxMODE_INT_MASK, mode_int);
2031f77c 3120 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 3121 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 3122 if (ASIC_IS_DCE3(rdev)) {
f2594933 3123 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3124 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3125 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3126 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3127 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3128 if (ASIC_IS_DCE32(rdev)) {
3129 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3130 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3131 }
3132 } else {
f2594933 3133 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3134 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3135 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3136 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3137 }
d8f60cfc
AD		 3138
3139 return 0;
3140}
3141
e0df1ac5
AD		 3142static inline void r600_irq_ack(struct radeon_device *rdev,
3143 u32 *disp_int,
3144 u32 *disp_int_cont,
3145 u32 *disp_int_cont2)
d8f60cfc 3146{
e0df1ac5
AD		 3147 u32 tmp;
3148
3149 if (ASIC_IS_DCE3(rdev)) {
3150 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3151 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3152 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3153 } else {
3154 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3155 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3156 *disp_int_cont2 = 0;
3157 }
d8f60cfc 3158
e0df1ac5 3159 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3160 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3161 if (*disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3162 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5 3163 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3164 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3165 if (*disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3166 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5
AD		 3167 if (*disp_int & DC_HPD1_INTERRUPT) {
3168 if (ASIC_IS_DCE3(rdev)) {
3169 tmp = RREG32(DC_HPD1_INT_CONTROL);
3170 tmp |= DC_HPDx_INT_ACK;
3171 WREG32(DC_HPD1_INT_CONTROL, tmp);
3172 } else {
3173 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3174 tmp |= DC_HPDx_INT_ACK;
3175 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3176 }
3177 }
3178 if (*disp_int & DC_HPD2_INTERRUPT) {
3179 if (ASIC_IS_DCE3(rdev)) {
3180 tmp = RREG32(DC_HPD2_INT_CONTROL);
3181 tmp |= DC_HPDx_INT_ACK;
3182 WREG32(DC_HPD2_INT_CONTROL, tmp);
3183 } else {
3184 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3185 tmp |= DC_HPDx_INT_ACK;
3186 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3187 }
3188 }
3189 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3190 if (ASIC_IS_DCE3(rdev)) {
3191 tmp = RREG32(DC_HPD3_INT_CONTROL);
3192 tmp |= DC_HPDx_INT_ACK;
3193 WREG32(DC_HPD3_INT_CONTROL, tmp);
3194 } else {
3195 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3196 tmp |= DC_HPDx_INT_ACK;
3197 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3198 }
3199 }
3200 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3201 tmp = RREG32(DC_HPD4_INT_CONTROL);
3202 tmp |= DC_HPDx_INT_ACK;
3203 WREG32(DC_HPD4_INT_CONTROL, tmp);
3204 }
3205 if (ASIC_IS_DCE32(rdev)) {
3206 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3207 tmp = RREG32(DC_HPD5_INT_CONTROL);
3208 tmp |= DC_HPDx_INT_ACK;
3209 WREG32(DC_HPD5_INT_CONTROL, tmp);
3210 }
3211 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3212 tmp = RREG32(DC_HPD5_INT_CONTROL);
3213 tmp |= DC_HPDx_INT_ACK;
3214 WREG32(DC_HPD6_INT_CONTROL, tmp);
3215 }
3216 }
f2594933
CK		 3217 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3218 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3219 }
3220 if (ASIC_IS_DCE3(rdev)) {
3221 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3222 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3223 }
3224 } else {
3225 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3226 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3227 }
3228 }
d8f60cfc
AD		 3229}
3230
3231void r600_irq_disable(struct radeon_device *rdev)
3232{
e0df1ac5 3233 u32 disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc
AD		 3234
3235 r600_disable_interrupts(rdev);
3236 /* Wait and acknowledge irq */
3237 mdelay(1);
e0df1ac5
AD		 3238 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3239 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3240}
3241
3242static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3243{
3244 u32 wptr, tmp;
3ce0a23d 3245
d8f60cfc
AD		 3246 /* XXX use writeback */
3247 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3248
d8f60cfc 3249 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3250 /* When a ring buffer overflow happen start parsing interrupt
3251 * from the last not overwritten vector (wptr + 16). Hopefully
3252 * this should allow us to catchup.
3253 */
3254 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3255 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3256 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3257 tmp = RREG32(IH_RB_CNTL);
3258 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3259 WREG32(IH_RB_CNTL, tmp);
3260 }
0c45249f 3261 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3262}
3ce0a23d 3263
d8f60cfc
AD		 3264/* r600 IV Ring
3265 * Each IV ring entry is 128 bits:
3266 * [7:0] - interrupt source id
3267 * [31:8] - reserved
3268 * [59:32] - interrupt source data
3269 * [127:60] - reserved
3270 *
3271 * The basic interrupt vector entries
3272 * are decoded as follows:
3273 * src_id src_data description
3274 * 1 0 D1 Vblank
3275 * 1 1 D1 Vline
3276 * 5 0 D2 Vblank
3277 * 5 1 D2 Vline
3278 * 19 0 FP Hot plug detection A
3279 * 19 1 FP Hot plug detection B
3280 * 19 2 DAC A auto-detection
3281 * 19 3 DAC B auto-detection
f2594933
CK		 3282 * 21 4 HDMI block A
3283 * 21 5 HDMI block B
d8f60cfc
AD		 3284 * 176 - CP_INT RB
3285 * 177 - CP_INT IB1
3286 * 178 - CP_INT IB2
3287 * 181 - EOP Interrupt
3288 * 233 - GUI Idle
3289 *
3290 * Note, these are based on r600 and may need to be
3291 * adjusted or added to on newer asics
3292 */
3293
3294int r600_irq_process(struct radeon_device *rdev)
3295{
3296 u32 wptr = r600_get_ih_wptr(rdev);
3297 u32 rptr = rdev->ih.rptr;
3298 u32 src_id, src_data;
e0df1ac5 3299 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc 3300 unsigned long flags;
d4877cf2 3301 bool queue_hotplug = false;
d8f60cfc
AD		 3302
3303 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
79c2bbc5
JG		 3304 if (!rdev->ih.enabled)
3305 return IRQ_NONE;
d8f60cfc
AD		 3306
3307 spin_lock_irqsave(&rdev->ih.lock, flags);
3308
3309 if (rptr == wptr) {
3310 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3311 return IRQ_NONE;
3312 }
3313 if (rdev->shutdown) {
3314 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3315 return IRQ_NONE;
3316 }
3317
3318restart_ih:
3319 /* display interrupts */
e0df1ac5 3320 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
d8f60cfc
AD		 3321
3322 rdev->ih.wptr = wptr;
3323 while (rptr != wptr) {
3324 /* wptr/rptr are in bytes! */
3325 ring_index = rptr / 4;
3326 src_id = rdev->ih.ring[ring_index] & 0xff;
3327 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3328
3329 switch (src_id) {
3330 case 1: /* D1 vblank/vline */
3331 switch (src_data) {
3332 case 0: /* D1 vblank */
3333 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3334 drm_handle_vblank(rdev->ddev, 0);
839461d3 3335 rdev->pm.vblank_sync = true;
73a6d3fc 3336 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3337 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3338 DRM_DEBUG("IH: D1 vblank\n");
3339 }
3340 break;
3341 case 1: /* D1 vline */
3342 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3343 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3344 DRM_DEBUG("IH: D1 vline\n");
3345 }
3346 break;
3347 default:
b042589c 3348 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3349 break;
3350 }
3351 break;
3352 case 5: /* D2 vblank/vline */
3353 switch (src_data) {
3354 case 0: /* D2 vblank */
3355 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3356 drm_handle_vblank(rdev->ddev, 1);
839461d3 3357 rdev->pm.vblank_sync = true;
73a6d3fc 3358 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3359 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3360 DRM_DEBUG("IH: D2 vblank\n");
3361 }
3362 break;
3363 case 1: /* D1 vline */
3364 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3365 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3366 DRM_DEBUG("IH: D2 vline\n");
3367 }
3368 break;
3369 default:
b042589c 3370 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3371 break;
3372 }
3373 break;
e0df1ac5
AD		 3374 case 19: /* HPD/DAC hotplug */
3375 switch (src_data) {
3376 case 0:
3377 if (disp_int & DC_HPD1_INTERRUPT) {
3378 disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3379 queue_hotplug = true;
3380 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3381 }
3382 break;
3383 case 1:
3384 if (disp_int & DC_HPD2_INTERRUPT) {
3385 disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3386 queue_hotplug = true;
3387 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3388 }
3389 break;
3390 case 4:
3391 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3392 disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3393 queue_hotplug = true;
3394 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3395 }
3396 break;
3397 case 5:
3398 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3399 disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3400 queue_hotplug = true;
3401 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3402 }
3403 break;
3404 case 10:
3405 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
5898b1f3 3406 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3407 queue_hotplug = true;
3408 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3409 }
3410 break;
3411 case 12:
3412 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
5898b1f3 3413 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3414 queue_hotplug = true;
3415 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3416 }
3417 break;
3418 default:
b042589c 3419 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3420 break;
3421 }
3422 break;
f2594933
CK		 3423 case 21: /* HDMI */
3424 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3425 r600_audio_schedule_polling(rdev);
3426 break;
d8f60cfc
AD		 3427 case 176: /* CP_INT in ring buffer */
3428 case 177: /* CP_INT in IB1 */
3429 case 178: /* CP_INT in IB2 */
3430 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3431 radeon_fence_process(rdev);
3432 break;
3433 case 181: /* CP EOP event */
3434 DRM_DEBUG("IH: CP EOP\n");
3435 break;
2031f77c
AD		 3436 case 233: /* GUI IDLE */
3437 DRM_DEBUG("IH: CP EOP\n");
3438 rdev->pm.gui_idle = true;
3439 wake_up(&rdev->irq.idle_queue);
3440 break;
d8f60cfc 3441 default:
b042589c 3442 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3443 break;
3444 }
3445
3446 /* wptr/rptr are in bytes! */
0c45249f
JG		 3447 rptr += 16;
3448 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3449 }
3450 /* make sure wptr hasn't changed while processing */
3451 wptr = r600_get_ih_wptr(rdev);
3452 if (wptr != rdev->ih.wptr)
3453 goto restart_ih;
d4877cf2
AD		 3454 if (queue_hotplug)
3455 queue_work(rdev->wq, &rdev->hotplug_work);
d8f60cfc
AD		 3456 rdev->ih.rptr = rptr;
3457 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3458 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3459 return IRQ_HANDLED;
3460}
3ce0a23d
JG		 3461
3462/*
3463 * Debugfs info
3464 */
3465#if defined(CONFIG_DEBUG_FS)
3466
3467static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 3468{
3ce0a23d
JG		 3469 struct drm_info_node *node = (struct drm_info_node *) m->private;
3470 struct drm_device *dev = node->minor->dev;
3471 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 3472 unsigned count, i, j;
3473
3474 radeon_ring_free_size(rdev);
d6840766 3475 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 3476 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 3477 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3478 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3479 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3480 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 3481 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3482 seq_printf(m, "%u dwords in ring\n", count);
d6840766 3483 i = rdev->cp.rptr;
3ce0a23d 3484 for (j = 0; j <= count; j++) {
3ce0a23d 3485 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 3486 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 3487 }
3488 return 0;
3489}
3490
3491static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3492{
3493 struct drm_info_node *node = (struct drm_info_node *) m->private;
3494 struct drm_device *dev = node->minor->dev;
3495 struct radeon_device *rdev = dev->dev_private;
3496
3497 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3498 DREG32_SYS(m, rdev, VM_L2_STATUS);
3499 return 0;
3500}
3501
3502static struct drm_info_list r600_mc_info_list[] = {
3503 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3504 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3505};
3506#endif
3507
3508int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3509{
3510#if defined(CONFIG_DEBUG_FS)
3511 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3512#else
3513 return 0;
3514#endif
771fe6b9 3515}
062b389c
JG		 3516
3517/**
3518 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3519 * rdev: radeon device structure
3520 * bo: buffer object struct which userspace is waiting for idle
3521 *
3522 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3523 * through ring buffer, this leads to corruption in rendering, see
3524 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3525 * directly perform HDP flush by writing register through MMIO.
3526 */
3527void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3528{
3529 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3530}
kernel source for telekom puls (alcatel/mediatek)