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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include "drmP.h" | |
771fe6b9 | 29 | #include "radeon.h" |
e6990375 | 30 | #include "radeon_asic.h" |
f0ed1f65 JG |
31 | #include "atom.h" |
32 | #include "r520d.h" | |
771fe6b9 | 33 | |
f0ed1f65 | 34 | /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ |
771fe6b9 | 35 | |
f0ed1f65 | 36 | static int r520_mc_wait_for_idle(struct radeon_device *rdev) |
771fe6b9 JG |
37 | { |
38 | unsigned i; | |
39 | uint32_t tmp; | |
40 | ||
41 | for (i = 0; i < rdev->usec_timeout; i++) { | |
42 | /* read MC_STATUS */ | |
43 | tmp = RREG32_MC(R520_MC_STATUS); | |
44 | if (tmp & R520_MC_STATUS_IDLE) { | |
45 | return 0; | |
46 | } | |
47 | DRM_UDELAY(1); | |
48 | } | |
49 | return -1; | |
50 | } | |
51 | ||
f0ed1f65 | 52 | static void r520_gpu_init(struct radeon_device *rdev) |
771fe6b9 JG |
53 | { |
54 | unsigned pipe_select_current, gb_pipe_select, tmp; | |
55 | ||
d39c3b89 | 56 | rv515_vga_render_disable(rdev); |
771fe6b9 JG |
57 | /* |
58 | * DST_PIPE_CONFIG 0x170C | |
59 | * GB_TILE_CONFIG 0x4018 | |
60 | * GB_FIFO_SIZE 0x4024 | |
61 | * GB_PIPE_SELECT 0x402C | |
62 | * GB_PIPE_SELECT2 0x4124 | |
63 | * Z_PIPE_SHIFT 0 | |
64 | * Z_PIPE_MASK 0x000000003 | |
65 | * GB_FIFO_SIZE2 0x4128 | |
66 | * SC_SFIFO_SIZE_SHIFT 0 | |
67 | * SC_SFIFO_SIZE_MASK 0x000000003 | |
68 | * SC_MFIFO_SIZE_SHIFT 2 | |
69 | * SC_MFIFO_SIZE_MASK 0x00000000C | |
70 | * FG_SFIFO_SIZE_SHIFT 4 | |
71 | * FG_SFIFO_SIZE_MASK 0x000000030 | |
72 | * ZB_MFIFO_SIZE_SHIFT 6 | |
73 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 | |
74 | * GA_ENHANCE 0x4274 | |
75 | * SU_REG_DEST 0x42C8 | |
76 | */ | |
77 | /* workaround for RV530 */ | |
78 | if (rdev->family == CHIP_RV530) { | |
771fe6b9 JG |
79 | WREG32(0x4128, 0xFF); |
80 | } | |
81 | r420_pipes_init(rdev); | |
82 | gb_pipe_select = RREG32(0x402C); | |
83 | tmp = RREG32(0x170C); | |
84 | pipe_select_current = (tmp >> 2) & 3; | |
85 | tmp = (1 << pipe_select_current) | | |
86 | (((gb_pipe_select >> 8) & 0xF) << 4); | |
87 | WREG32_PLL(0x000D, tmp); | |
88 | if (r520_mc_wait_for_idle(rdev)) { | |
89 | printk(KERN_WARNING "Failed to wait MC idle while " | |
90 | "programming pipes. Bad things might happen.\n"); | |
91 | } | |
92 | } | |
93 | ||
771fe6b9 JG |
94 | static void r520_vram_get_type(struct radeon_device *rdev) |
95 | { | |
96 | uint32_t tmp; | |
97 | ||
98 | rdev->mc.vram_width = 128; | |
99 | rdev->mc.vram_is_ddr = true; | |
100 | tmp = RREG32_MC(R520_MC_CNTL0); | |
101 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { | |
102 | case 0: | |
103 | rdev->mc.vram_width = 32; | |
104 | break; | |
105 | case 1: | |
106 | rdev->mc.vram_width = 64; | |
107 | break; | |
108 | case 2: | |
109 | rdev->mc.vram_width = 128; | |
110 | break; | |
111 | case 3: | |
112 | rdev->mc.vram_width = 256; | |
113 | break; | |
114 | default: | |
115 | rdev->mc.vram_width = 128; | |
116 | break; | |
117 | } | |
118 | if (tmp & R520_MC_CHANNEL_SIZE) | |
119 | rdev->mc.vram_width *= 2; | |
120 | } | |
121 | ||
d594e46a | 122 | void r520_mc_init(struct radeon_device *rdev) |
771fe6b9 | 123 | { |
c93bb85b | 124 | |
771fe6b9 | 125 | r520_vram_get_type(rdev); |
2a0f8918 | 126 | r100_vram_init_sizes(rdev); |
d594e46a JG |
127 | radeon_vram_location(rdev, &rdev->mc, 0); |
128 | if (!(rdev->flags & RADEON_IS_AGP)) | |
129 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 130 | radeon_update_bandwidth_info(rdev); |
c93bb85b JG |
131 | } |
132 | ||
f0ed1f65 JG |
133 | void r520_mc_program(struct radeon_device *rdev) |
134 | { | |
135 | struct rv515_mc_save save; | |
136 | ||
137 | /* Stops all mc clients */ | |
138 | rv515_mc_stop(rdev, &save); | |
139 | ||
140 | /* Wait for mc idle */ | |
141 | if (r520_mc_wait_for_idle(rdev)) | |
142 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); | |
143 | /* Write VRAM size in case we are limiting it */ | |
144 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
145 | /* Program MC, should be a 32bits limited address space */ | |
146 | WREG32_MC(R_000004_MC_FB_LOCATION, | |
147 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | | |
148 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
149 | WREG32(R_000134_HDP_FB_LOCATION, | |
150 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); | |
151 | if (rdev->flags & RADEON_IS_AGP) { | |
152 | WREG32_MC(R_000005_MC_AGP_LOCATION, | |
153 | S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
154 | S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
155 | WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
156 | WREG32_MC(R_000007_AGP_BASE_2, | |
157 | S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); | |
158 | } else { | |
159 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); | |
160 | WREG32_MC(R_000006_AGP_BASE, 0); | |
161 | WREG32_MC(R_000007_AGP_BASE_2, 0); | |
162 | } | |
163 | ||
164 | rv515_mc_resume(rdev, &save); | |
165 | } | |
166 | ||
167 | static int r520_startup(struct radeon_device *rdev) | |
168 | { | |
169 | int r; | |
170 | ||
171 | r520_mc_program(rdev); | |
172 | /* Resume clock */ | |
173 | rv515_clock_startup(rdev); | |
174 | /* Initialize GPU configuration (# pipes, ...) */ | |
175 | r520_gpu_init(rdev); | |
176 | /* Initialize GART (initialize after TTM so we can allocate | |
177 | * memory through TTM but finalize after TTM) */ | |
178 | if (rdev->flags & RADEON_IS_PCIE) { | |
179 | r = rv370_pcie_gart_enable(rdev); | |
180 | if (r) | |
181 | return r; | |
182 | } | |
183 | /* Enable IRQ */ | |
ac447df4 | 184 | rs600_irq_set(rdev); |
cafe6609 | 185 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
f0ed1f65 JG |
186 | /* 1M ring buffer */ |
187 | r = r100_cp_init(rdev, 1024 * 1024); | |
188 | if (r) { | |
189 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
190 | return r; | |
191 | } | |
192 | r = r100_wb_init(rdev); | |
193 | if (r) | |
194 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
195 | r = r100_ib_init(rdev); | |
196 | if (r) { | |
197 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
198 | return r; | |
199 | } | |
200 | return 0; | |
201 | } | |
202 | ||
203 | int r520_resume(struct radeon_device *rdev) | |
c93bb85b | 204 | { |
f0ed1f65 JG |
205 | /* Make sur GART are not working */ |
206 | if (rdev->flags & RADEON_IS_PCIE) | |
207 | rv370_pcie_gart_disable(rdev); | |
208 | /* Resume clock before doing reset */ | |
209 | rv515_clock_startup(rdev); | |
210 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 211 | if (radeon_asic_reset(rdev)) { |
f0ed1f65 JG |
212 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
213 | RREG32(R_000E40_RBBM_STATUS), | |
214 | RREG32(R_0007C0_CP_STAT)); | |
215 | } | |
216 | /* post */ | |
217 | atom_asic_init(rdev->mode_info.atom_context); | |
218 | /* Resume clock after posting */ | |
219 | rv515_clock_startup(rdev); | |
550e2d92 DA |
220 | /* Initialize surface registers */ |
221 | radeon_surface_init(rdev); | |
f0ed1f65 | 222 | return r520_startup(rdev); |
771fe6b9 | 223 | } |
d39c3b89 JG |
224 | |
225 | int r520_init(struct radeon_device *rdev) | |
226 | { | |
f0ed1f65 JG |
227 | int r; |
228 | ||
f0ed1f65 JG |
229 | /* Initialize scratch registers */ |
230 | radeon_scratch_init(rdev); | |
231 | /* Initialize surface registers */ | |
232 | radeon_surface_init(rdev); | |
233 | /* TODO: disable VGA need to use VGA request */ | |
234 | /* BIOS*/ | |
235 | if (!radeon_get_bios(rdev)) { | |
236 | if (ASIC_IS_AVIVO(rdev)) | |
237 | return -EINVAL; | |
238 | } | |
239 | if (rdev->is_atom_bios) { | |
240 | r = radeon_atombios_init(rdev); | |
241 | if (r) | |
242 | return r; | |
243 | } else { | |
244 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); | |
245 | return -EINVAL; | |
246 | } | |
247 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 248 | if (radeon_asic_reset(rdev)) { |
f0ed1f65 JG |
249 | dev_warn(rdev->dev, |
250 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
251 | RREG32(R_000E40_RBBM_STATUS), | |
252 | RREG32(R_0007C0_CP_STAT)); | |
253 | } | |
254 | /* check if cards are posted or not */ | |
72542d77 DA |
255 | if (radeon_boot_test_post_card(rdev) == false) |
256 | return -EINVAL; | |
257 | ||
f0ed1f65 JG |
258 | if (!radeon_card_posted(rdev) && rdev->bios) { |
259 | DRM_INFO("GPU not posted. posting now...\n"); | |
260 | atom_asic_init(rdev->mode_info.atom_context); | |
261 | } | |
262 | /* Initialize clocks */ | |
263 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
264 | /* initialize AGP */ |
265 | if (rdev->flags & RADEON_IS_AGP) { | |
266 | r = radeon_agp_init(rdev); | |
267 | if (r) { | |
268 | radeon_agp_disable(rdev); | |
269 | } | |
270 | } | |
271 | /* initialize memory controller */ | |
272 | r520_mc_init(rdev); | |
f0ed1f65 JG |
273 | rv515_debugfs(rdev); |
274 | /* Fence driver */ | |
275 | r = radeon_fence_driver_init(rdev); | |
276 | if (r) | |
277 | return r; | |
278 | r = radeon_irq_kms_init(rdev); | |
279 | if (r) | |
280 | return r; | |
281 | /* Memory manager */ | |
4c788679 | 282 | r = radeon_bo_init(rdev); |
f0ed1f65 JG |
283 | if (r) |
284 | return r; | |
285 | r = rv370_pcie_gart_init(rdev); | |
286 | if (r) | |
287 | return r; | |
d39c3b89 | 288 | rv515_set_safe_registers(rdev); |
f0ed1f65 JG |
289 | rdev->accel_working = true; |
290 | r = r520_startup(rdev); | |
291 | if (r) { | |
292 | /* Somethings want wront with the accel init stop accel */ | |
293 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
f0ed1f65 JG |
294 | r100_cp_fini(rdev); |
295 | r100_wb_fini(rdev); | |
296 | r100_ib_fini(rdev); | |
655efd3d | 297 | radeon_irq_kms_fini(rdev); |
f0ed1f65 JG |
298 | rv370_pcie_gart_fini(rdev); |
299 | radeon_agp_fini(rdev); | |
f0ed1f65 JG |
300 | rdev->accel_working = false; |
301 | } | |
d39c3b89 JG |
302 | return 0; |
303 | } |