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drm/radeon: use status regs to determine what to reset (evergreen)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
760285e7 27#include <drm/drmP.h>
bcc1c2a1 28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
760285e7 30#include <drm/radeon_drm.h>
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
4a15903d
AD		 40static const u32 crtc_offsets[6] =
41{
42 EVERGREEN_CRTC0_REGISTER_OFFSET,
43 EVERGREEN_CRTC1_REGISTER_OFFSET,
44 EVERGREEN_CRTC2_REGISTER_OFFSET,
45 EVERGREEN_CRTC3_REGISTER_OFFSET,
46 EVERGREEN_CRTC4_REGISTER_OFFSET,
47 EVERGREEN_CRTC5_REGISTER_OFFSET
48};
49
bcc1c2a1
AD		 50static void evergreen_gpu_init(struct radeon_device *rdev);
51void evergreen_fini(struct radeon_device *rdev);
b07759bf 52void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
1b37078b
AD		 53extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54 int ring, u32 cp_int_cntl);
bcc1c2a1 55
285484e2
JG		 56void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57 unsigned *bankh, unsigned *mtaspect,
58 unsigned *tile_split)
59{
60 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
61 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
62 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
63 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
64 switch (*bankw) {
65 default:
66 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
67 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
68 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
69 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
70 }
71 switch (*bankh) {
72 default:
73 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
74 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
75 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
76 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
77 }
78 switch (*mtaspect) {
79 default:
80 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
81 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
82 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
83 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
84 }
85}
86
d054ac16
AD		 87void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
88{
89 u16 ctl, v;
32195aec 90 int err;
d054ac16 91
32195aec 92 err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
d054ac16
AD		 93 if (err)
94 return;
95
96 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
97
98 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
99 * to avoid hangs or perfomance issues
100 */
101 if ((v == 0) || (v == 6) || (v == 7)) {
102 ctl &= ~PCI_EXP_DEVCTL_READRQ;
103 ctl |= (2 << 12);
32195aec 104 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
d054ac16
AD		 105 }
106}
107
377edc8b
AD		 108/**
109 * dce4_wait_for_vblank - vblank wait asic callback.
110 *
111 * @rdev: radeon_device pointer
112 * @crtc: crtc to wait for vblank on
113 *
114 * Wait for vblank on the requested crtc (evergreen+).
115 */
3ae19b75
AD		 116void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
117{
3ae19b75
AD		 118 int i;
119
4a15903d
AD		 120 if (crtc >= rdev->num_crtc)
121 return;
122
123 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
3ae19b75 124 for (i = 0; i < rdev->usec_timeout; i++) {
4a15903d 125 if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
3ae19b75
AD		 126 break;
127 udelay(1);
128 }
129 for (i = 0; i < rdev->usec_timeout; i++) {
4a15903d 130 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
3ae19b75
AD		 131 break;
132 udelay(1);
133 }
134 }
135}
136
377edc8b
AD		 137/**
138 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
139 *
140 * @rdev: radeon_device pointer
141 * @crtc: crtc to prepare for pageflip on
142 *
143 * Pre-pageflip callback (evergreen+).
144 * Enables the pageflip irq (vblank irq).
145 */
6f34be50
AD		 146void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
147{
6f34be50
AD		 148 /* enable the pflip int */
149 radeon_irq_kms_pflip_irq_get(rdev, crtc);
150}
151
377edc8b
AD		 152/**
153 * evergreen_post_page_flip - pos-pageflip callback.
154 *
155 * @rdev: radeon_device pointer
156 * @crtc: crtc to cleanup pageflip on
157 *
158 * Post-pageflip callback (evergreen+).
159 * Disables the pageflip irq (vblank irq).
160 */
6f34be50
AD		 161void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
162{
163 /* disable the pflip int */
164 radeon_irq_kms_pflip_irq_put(rdev, crtc);
165}
166
377edc8b
AD		 167/**
168 * evergreen_page_flip - pageflip callback.
169 *
170 * @rdev: radeon_device pointer
171 * @crtc_id: crtc to cleanup pageflip on
172 * @crtc_base: new address of the crtc (GPU MC address)
173 *
174 * Does the actual pageflip (evergreen+).
175 * During vblank we take the crtc lock and wait for the update_pending
176 * bit to go high, when it does, we release the lock, and allow the
177 * double buffered update to take place.
178 * Returns the current update pending status.
179 */
6f34be50
AD		 180u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
181{
182 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
183 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 184 int i;
6f34be50
AD		 185
186 /* Lock the graphics update lock */
187 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
188 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
189
190 /* update the scanout addresses */
191 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
192 upper_32_bits(crtc_base));
193 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
194 (u32)crtc_base);
195
196 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
197 upper_32_bits(crtc_base));
198 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
199 (u32)crtc_base);
200
201 /* Wait for update_pending to go high. */
f6496479
AD		 202 for (i = 0; i < rdev->usec_timeout; i++) {
203 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
204 break;
205 udelay(1);
206 }
6f34be50
AD		 207 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
208
209 /* Unlock the lock, so double-buffering can take place inside vblank */
210 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
211 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
212
213 /* Return current update_pending status: */
214 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
215}
216
21a8122a 217/* get temperature in millidegrees */
20d391d7 218int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 219{
1c88d74f
AD		 220 u32 temp, toffset;
221 int actual_temp = 0;
67b3f823
AD		 222
223 if (rdev->family == CHIP_JUNIPER) {
224 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
225 TOFFSET_SHIFT;
226 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
227 TS0_ADC_DOUT_SHIFT;
228
229 if (toffset & 0x100)
230 actual_temp = temp / 2 - (0x200 - toffset);
231 else
232 actual_temp = temp / 2 + toffset;
233
234 actual_temp = actual_temp * 1000;
235
236 } else {
237 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
238 ASIC_T_SHIFT;
239
240 if (temp & 0x400)
241 actual_temp = -256;
242 else if (temp & 0x200)
243 actual_temp = 255;
244 else if (temp & 0x100) {
245 actual_temp = temp & 0x1ff;
246 actual_temp |= ~0x1ff;
247 } else
248 actual_temp = temp & 0xff;
249
250 actual_temp = (actual_temp * 1000) / 2;
251 }
21a8122a 252
67b3f823 253 return actual_temp;
21a8122a
AD		 254}
255
20d391d7 256int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 257{
258 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 259 int actual_temp = temp - 49;
e33df25f
AD		 260
261 return actual_temp * 1000;
262}
263
377edc8b
AD		 264/**
265 * sumo_pm_init_profile - Initialize power profiles callback.
266 *
267 * @rdev: radeon_device pointer
268 *
269 * Initialize the power states used in profile mode
270 * (sumo, trinity, SI).
271 * Used for profile mode only.
272 */
a4c9e2ee
AD		 273void sumo_pm_init_profile(struct radeon_device *rdev)
274{
275 int idx;
276
277 /* default */
278 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
279 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
280 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
281 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
282
283 /* low,mid sh/mh */
284 if (rdev->flags & RADEON_IS_MOBILITY)
285 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
286 else
287 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
288
289 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
290 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
291 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
292 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
293
294 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
295 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
296 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
298
299 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
300 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
301 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
303
304 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
305 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
306 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
308
309 /* high sh/mh */
310 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
315 rdev->pm.power_state[idx].num_clock_modes - 1;
316
317 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
318 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
319 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
321 rdev->pm.power_state[idx].num_clock_modes - 1;
322}
323
27810fb2
AD		 324/**
325 * btc_pm_init_profile - Initialize power profiles callback.
326 *
327 * @rdev: radeon_device pointer
328 *
329 * Initialize the power states used in profile mode
330 * (BTC, cayman).
331 * Used for profile mode only.
332 */
333void btc_pm_init_profile(struct radeon_device *rdev)
334{
335 int idx;
336
337 /* default */
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
340 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
342 /* starting with BTC, there is one state that is used for both
343 * MH and SH. Difference is that we always use the high clock index for
344 * mclk.
345 */
346 if (rdev->flags & RADEON_IS_MOBILITY)
347 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
348 else
349 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
350 /* low sh */
351 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
352 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
353 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
355 /* mid sh */
356 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
357 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
358 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
359 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
360 /* high sh */
361 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
362 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
363 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
364 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
365 /* low mh */
366 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
367 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
368 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
369 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
370 /* mid mh */
371 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
372 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
373 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
374 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
375 /* high mh */
376 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
377 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
378 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
380}
381
377edc8b
AD		 382/**
383 * evergreen_pm_misc - set additional pm hw parameters callback.
384 *
385 * @rdev: radeon_device pointer
386 *
387 * Set non-clock parameters associated with a power state
388 * (voltage, etc.) (evergreen+).
389 */
49e02b73
AD		 390void evergreen_pm_misc(struct radeon_device *rdev)
391{
a081a9d6
RM		 392 int req_ps_idx = rdev->pm.requested_power_state_index;
393 int req_cm_idx = rdev->pm.requested_clock_mode_index;
394 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
395 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 396
2feea49a 397 if (voltage->type == VOLTAGE_SW) {
a377e187
AD		 398 /* 0xff01 is a flag rather then an actual voltage */
399 if (voltage->voltage == 0xff01)
400 return;
2feea49a 401 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 402 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 403 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 404 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
405 }
a377e187
AD		 406 /* 0xff01 is a flag rather then an actual voltage */
407 if (voltage->vddci == 0xff01)
408 return;
2feea49a
AD		 409 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
410 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
411 rdev->pm.current_vddci = voltage->vddci;
412 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 413 }
414 }
49e02b73
AD		 415}
416
377edc8b
AD		 417/**
418 * evergreen_pm_prepare - pre-power state change callback.
419 *
420 * @rdev: radeon_device pointer
421 *
422 * Prepare for a power state change (evergreen+).
423 */
49e02b73
AD		 424void evergreen_pm_prepare(struct radeon_device *rdev)
425{
426 struct drm_device *ddev = rdev->ddev;
427 struct drm_crtc *crtc;
428 struct radeon_crtc *radeon_crtc;
429 u32 tmp;
430
431 /* disable any active CRTCs */
432 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
433 radeon_crtc = to_radeon_crtc(crtc);
434 if (radeon_crtc->enabled) {
435 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
436 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
437 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
438 }
439 }
440}
441
377edc8b
AD		 442/**
443 * evergreen_pm_finish - post-power state change callback.
444 *
445 * @rdev: radeon_device pointer
446 *
447 * Clean up after a power state change (evergreen+).
448 */
49e02b73
AD		 449void evergreen_pm_finish(struct radeon_device *rdev)
450{
451 struct drm_device *ddev = rdev->ddev;
452 struct drm_crtc *crtc;
453 struct radeon_crtc *radeon_crtc;
454 u32 tmp;
455
456 /* enable any active CRTCs */
457 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
458 radeon_crtc = to_radeon_crtc(crtc);
459 if (radeon_crtc->enabled) {
460 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
461 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
462 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
463 }
464 }
465}
466
377edc8b
AD		 467/**
468 * evergreen_hpd_sense - hpd sense callback.
469 *
470 * @rdev: radeon_device pointer
471 * @hpd: hpd (hotplug detect) pin
472 *
473 * Checks if a digital monitor is connected (evergreen+).
474 * Returns true if connected, false if not connected.
475 */
bcc1c2a1
AD		 476bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
477{
478 bool connected = false;
0ca2ab52
AD		 479
480 switch (hpd) {
481 case RADEON_HPD_1:
482 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
483 connected = true;
484 break;
485 case RADEON_HPD_2:
486 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
487 connected = true;
488 break;
489 case RADEON_HPD_3:
490 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
491 connected = true;
492 break;
493 case RADEON_HPD_4:
494 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
495 connected = true;
496 break;
497 case RADEON_HPD_5:
498 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
499 connected = true;
500 break;
501 case RADEON_HPD_6:
502 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
503 connected = true;
504 break;
505 default:
506 break;
507 }
508
bcc1c2a1
AD		 509 return connected;
510}
511
377edc8b
AD		 512/**
513 * evergreen_hpd_set_polarity - hpd set polarity callback.
514 *
515 * @rdev: radeon_device pointer
516 * @hpd: hpd (hotplug detect) pin
517 *
518 * Set the polarity of the hpd pin (evergreen+).
519 */
bcc1c2a1
AD		 520void evergreen_hpd_set_polarity(struct radeon_device *rdev,
521 enum radeon_hpd_id hpd)
522{
0ca2ab52
AD		 523 u32 tmp;
524 bool connected = evergreen_hpd_sense(rdev, hpd);
525
526 switch (hpd) {
527 case RADEON_HPD_1:
528 tmp = RREG32(DC_HPD1_INT_CONTROL);
529 if (connected)
530 tmp &= ~DC_HPDx_INT_POLARITY;
531 else
532 tmp |= DC_HPDx_INT_POLARITY;
533 WREG32(DC_HPD1_INT_CONTROL, tmp);
534 break;
535 case RADEON_HPD_2:
536 tmp = RREG32(DC_HPD2_INT_CONTROL);
537 if (connected)
538 tmp &= ~DC_HPDx_INT_POLARITY;
539 else
540 tmp |= DC_HPDx_INT_POLARITY;
541 WREG32(DC_HPD2_INT_CONTROL, tmp);
542 break;
543 case RADEON_HPD_3:
544 tmp = RREG32(DC_HPD3_INT_CONTROL);
545 if (connected)
546 tmp &= ~DC_HPDx_INT_POLARITY;
547 else
548 tmp |= DC_HPDx_INT_POLARITY;
549 WREG32(DC_HPD3_INT_CONTROL, tmp);
550 break;
551 case RADEON_HPD_4:
552 tmp = RREG32(DC_HPD4_INT_CONTROL);
553 if (connected)
554 tmp &= ~DC_HPDx_INT_POLARITY;
555 else
556 tmp |= DC_HPDx_INT_POLARITY;
557 WREG32(DC_HPD4_INT_CONTROL, tmp);
558 break;
559 case RADEON_HPD_5:
560 tmp = RREG32(DC_HPD5_INT_CONTROL);
561 if (connected)
562 tmp &= ~DC_HPDx_INT_POLARITY;
563 else
564 tmp |= DC_HPDx_INT_POLARITY;
565 WREG32(DC_HPD5_INT_CONTROL, tmp);
566 break;
567 case RADEON_HPD_6:
568 tmp = RREG32(DC_HPD6_INT_CONTROL);
569 if (connected)
570 tmp &= ~DC_HPDx_INT_POLARITY;
571 else
572 tmp |= DC_HPDx_INT_POLARITY;
573 WREG32(DC_HPD6_INT_CONTROL, tmp);
574 break;
575 default:
576 break;
577 }
bcc1c2a1
AD		 578}
579
377edc8b
AD		 580/**
581 * evergreen_hpd_init - hpd setup callback.
582 *
583 * @rdev: radeon_device pointer
584 *
585 * Setup the hpd pins used by the card (evergreen+).
586 * Enable the pin, set the polarity, and enable the hpd interrupts.
587 */
bcc1c2a1
AD		 588void evergreen_hpd_init(struct radeon_device *rdev)
589{
0ca2ab52
AD		 590 struct drm_device *dev = rdev->ddev;
591 struct drm_connector *connector;
fb98257a 592 unsigned enabled = 0;
0ca2ab52
AD		 593 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
594 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 595
0ca2ab52
AD		 596 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
597 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
598 switch (radeon_connector->hpd.hpd) {
599 case RADEON_HPD_1:
600 WREG32(DC_HPD1_CONTROL, tmp);
0ca2ab52
AD		 601 break;
602 case RADEON_HPD_2:
603 WREG32(DC_HPD2_CONTROL, tmp);
0ca2ab52
AD		 604 break;
605 case RADEON_HPD_3:
606 WREG32(DC_HPD3_CONTROL, tmp);
0ca2ab52
AD		 607 break;
608 case RADEON_HPD_4:
609 WREG32(DC_HPD4_CONTROL, tmp);
0ca2ab52
AD		 610 break;
611 case RADEON_HPD_5:
612 WREG32(DC_HPD5_CONTROL, tmp);
0ca2ab52
AD		 613 break;
614 case RADEON_HPD_6:
615 WREG32(DC_HPD6_CONTROL, tmp);
0ca2ab52
AD		 616 break;
617 default:
618 break;
619 }
64912e99 620 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
fb98257a 621 enabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 622 }
fb98257a 623 radeon_irq_kms_enable_hpd(rdev, enabled);
bcc1c2a1
AD		 624}
625
377edc8b
AD		 626/**
627 * evergreen_hpd_fini - hpd tear down callback.
628 *
629 * @rdev: radeon_device pointer
630 *
631 * Tear down the hpd pins used by the card (evergreen+).
632 * Disable the hpd interrupts.
633 */
0ca2ab52 634void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 635{
0ca2ab52
AD		 636 struct drm_device *dev = rdev->ddev;
637 struct drm_connector *connector;
fb98257a 638 unsigned disabled = 0;
0ca2ab52
AD		 639
640 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
641 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
642 switch (radeon_connector->hpd.hpd) {
643 case RADEON_HPD_1:
644 WREG32(DC_HPD1_CONTROL, 0);
0ca2ab52
AD		 645 break;
646 case RADEON_HPD_2:
647 WREG32(DC_HPD2_CONTROL, 0);
0ca2ab52
AD		 648 break;
649 case RADEON_HPD_3:
650 WREG32(DC_HPD3_CONTROL, 0);
0ca2ab52
AD		 651 break;
652 case RADEON_HPD_4:
653 WREG32(DC_HPD4_CONTROL, 0);
0ca2ab52
AD		 654 break;
655 case RADEON_HPD_5:
656 WREG32(DC_HPD5_CONTROL, 0);
0ca2ab52
AD		 657 break;
658 case RADEON_HPD_6:
659 WREG32(DC_HPD6_CONTROL, 0);
0ca2ab52
AD		 660 break;
661 default:
662 break;
663 }
fb98257a 664 disabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 665 }
fb98257a 666 radeon_irq_kms_disable_hpd(rdev, disabled);
bcc1c2a1
AD		 667}
668
f9d9c362
AD		 669/* watermark setup */
670
671static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
672 struct radeon_crtc *radeon_crtc,
673 struct drm_display_mode *mode,
674 struct drm_display_mode *other_mode)
675{
12dfc843 676 u32 tmp;
f9d9c362
AD		 677 /*
678 * Line Buffer Setup
679 * There are 3 line buffers, each one shared by 2 display controllers.
680 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
681 * the display controllers. The paritioning is done via one of four
682 * preset allocations specified in bits 2:0:
683 * first display controller
684 * 0 - first half of lb (3840 * 2)
685 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 686 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 687 * 3 - first 1/4 of lb (1920 * 2)
688 * second display controller
689 * 4 - second half of lb (3840 * 2)
690 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 691 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 692 * 7 - last 1/4 of lb (1920 * 2)
693 */
12dfc843
AD		 694 /* this can get tricky if we have two large displays on a paired group
695 * of crtcs. Ideally for multiple large displays we'd assign them to
696 * non-linked crtcs for maximum line buffer allocation.
697 */
698 if (radeon_crtc->base.enabled && mode) {
699 if (other_mode)
f9d9c362 700 tmp = 0; /* 1/2 */
12dfc843
AD		 701 else
702 tmp = 2; /* whole */
703 } else
704 tmp = 0;
f9d9c362
AD		 705
706 /* second controller of the pair uses second half of the lb */
707 if (radeon_crtc->crtc_id % 2)
708 tmp += 4;
709 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
710
12dfc843
AD		 711 if (radeon_crtc->base.enabled && mode) {
712 switch (tmp) {
713 case 0:
714 case 4:
715 default:
716 if (ASIC_IS_DCE5(rdev))
717 return 4096 * 2;
718 else
719 return 3840 * 2;
720 case 1:
721 case 5:
722 if (ASIC_IS_DCE5(rdev))
723 return 6144 * 2;
724 else
725 return 5760 * 2;
726 case 2:
727 case 6:
728 if (ASIC_IS_DCE5(rdev))
729 return 8192 * 2;
730 else
731 return 7680 * 2;
732 case 3:
733 case 7:
734 if (ASIC_IS_DCE5(rdev))
735 return 2048 * 2;
736 else
737 return 1920 * 2;
738 }
f9d9c362 739 }
12dfc843
AD		 740
741 /* controller not enabled, so no lb used */
742 return 0;
f9d9c362
AD		 743}
744
ca7db22b 745u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
f9d9c362
AD		 746{
747 u32 tmp = RREG32(MC_SHARED_CHMAP);
748
749 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
750 case 0:
751 default:
752 return 1;
753 case 1:
754 return 2;
755 case 2:
756 return 4;
757 case 3:
758 return 8;
759 }
760}
761
762struct evergreen_wm_params {
763 u32 dram_channels; /* number of dram channels */
764 u32 yclk; /* bandwidth per dram data pin in kHz */
765 u32 sclk; /* engine clock in kHz */
766 u32 disp_clk; /* display clock in kHz */
767 u32 src_width; /* viewport width */
768 u32 active_time; /* active display time in ns */
769 u32 blank_time; /* blank time in ns */
770 bool interlaced; /* mode is interlaced */
771 fixed20_12 vsc; /* vertical scale ratio */
772 u32 num_heads; /* number of active crtcs */
773 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
774 u32 lb_size; /* line buffer allocated to pipe */
775 u32 vtaps; /* vertical scaler taps */
776};
777
778static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
779{
780 /* Calculate DRAM Bandwidth and the part allocated to display. */
781 fixed20_12 dram_efficiency; /* 0.7 */
782 fixed20_12 yclk, dram_channels, bandwidth;
783 fixed20_12 a;
784
785 a.full = dfixed_const(1000);
786 yclk.full = dfixed_const(wm->yclk);
787 yclk.full = dfixed_div(yclk, a);
788 dram_channels.full = dfixed_const(wm->dram_channels * 4);
789 a.full = dfixed_const(10);
790 dram_efficiency.full = dfixed_const(7);
791 dram_efficiency.full = dfixed_div(dram_efficiency, a);
792 bandwidth.full = dfixed_mul(dram_channels, yclk);
793 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
794
795 return dfixed_trunc(bandwidth);
796}
797
798static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
799{
800 /* Calculate DRAM Bandwidth and the part allocated to display. */
801 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
802 fixed20_12 yclk, dram_channels, bandwidth;
803 fixed20_12 a;
804
805 a.full = dfixed_const(1000);
806 yclk.full = dfixed_const(wm->yclk);
807 yclk.full = dfixed_div(yclk, a);
808 dram_channels.full = dfixed_const(wm->dram_channels * 4);
809 a.full = dfixed_const(10);
810 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
811 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
812 bandwidth.full = dfixed_mul(dram_channels, yclk);
813 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
814
815 return dfixed_trunc(bandwidth);
816}
817
818static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
819{
820 /* Calculate the display Data return Bandwidth */
821 fixed20_12 return_efficiency; /* 0.8 */
822 fixed20_12 sclk, bandwidth;
823 fixed20_12 a;
824
825 a.full = dfixed_const(1000);
826 sclk.full = dfixed_const(wm->sclk);
827 sclk.full = dfixed_div(sclk, a);
828 a.full = dfixed_const(10);
829 return_efficiency.full = dfixed_const(8);
830 return_efficiency.full = dfixed_div(return_efficiency, a);
831 a.full = dfixed_const(32);
832 bandwidth.full = dfixed_mul(a, sclk);
833 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
834
835 return dfixed_trunc(bandwidth);
836}
837
838static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
839{
840 /* Calculate the DMIF Request Bandwidth */
841 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
842 fixed20_12 disp_clk, bandwidth;
843 fixed20_12 a;
844
845 a.full = dfixed_const(1000);
846 disp_clk.full = dfixed_const(wm->disp_clk);
847 disp_clk.full = dfixed_div(disp_clk, a);
848 a.full = dfixed_const(10);
849 disp_clk_request_efficiency.full = dfixed_const(8);
850 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
851 a.full = dfixed_const(32);
852 bandwidth.full = dfixed_mul(a, disp_clk);
853 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
854
855 return dfixed_trunc(bandwidth);
856}
857
858static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
859{
860 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
861 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
862 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
863 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
864
865 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
866}
867
868static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
869{
870 /* Calculate the display mode Average Bandwidth
871 * DisplayMode should contain the source and destination dimensions,
872 * timing, etc.
873 */
874 fixed20_12 bpp;
875 fixed20_12 line_time;
876 fixed20_12 src_width;
877 fixed20_12 bandwidth;
878 fixed20_12 a;
879
880 a.full = dfixed_const(1000);
881 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
882 line_time.full = dfixed_div(line_time, a);
883 bpp.full = dfixed_const(wm->bytes_per_pixel);
884 src_width.full = dfixed_const(wm->src_width);
885 bandwidth.full = dfixed_mul(src_width, bpp);
886 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
887 bandwidth.full = dfixed_div(bandwidth, line_time);
888
889 return dfixed_trunc(bandwidth);
890}
891
892static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
893{
894 /* First calcualte the latency in ns */
895 u32 mc_latency = 2000; /* 2000 ns. */
896 u32 available_bandwidth = evergreen_available_bandwidth(wm);
897 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
898 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
899 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
900 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
901 (wm->num_heads * cursor_line_pair_return_time);
902 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
903 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
904 fixed20_12 a, b, c;
905
906 if (wm->num_heads == 0)
907 return 0;
908
909 a.full = dfixed_const(2);
910 b.full = dfixed_const(1);
911 if ((wm->vsc.full > a.full) ||
912 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
913 (wm->vtaps >= 5) ||
914 ((wm->vsc.full >= a.full) && wm->interlaced))
915 max_src_lines_per_dst_line = 4;
916 else
917 max_src_lines_per_dst_line = 2;
918
919 a.full = dfixed_const(available_bandwidth);
920 b.full = dfixed_const(wm->num_heads);
921 a.full = dfixed_div(a, b);
922
923 b.full = dfixed_const(1000);
924 c.full = dfixed_const(wm->disp_clk);
925 b.full = dfixed_div(c, b);
926 c.full = dfixed_const(wm->bytes_per_pixel);
927 b.full = dfixed_mul(b, c);
928
929 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
930
931 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
932 b.full = dfixed_const(1000);
933 c.full = dfixed_const(lb_fill_bw);
934 b.full = dfixed_div(c, b);
935 a.full = dfixed_div(a, b);
936 line_fill_time = dfixed_trunc(a);
937
938 if (line_fill_time < wm->active_time)
939 return latency;
940 else
941 return latency + (line_fill_time - wm->active_time);
942
943}
944
945static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
946{
947 if (evergreen_average_bandwidth(wm) <=
948 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
949 return true;
950 else
951 return false;
952};
953
954static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
955{
956 if (evergreen_average_bandwidth(wm) <=
957 (evergreen_available_bandwidth(wm) / wm->num_heads))
958 return true;
959 else
960 return false;
961};
962
963static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
964{
965 u32 lb_partitions = wm->lb_size / wm->src_width;
966 u32 line_time = wm->active_time + wm->blank_time;
967 u32 latency_tolerant_lines;
968 u32 latency_hiding;
969 fixed20_12 a;
970
971 a.full = dfixed_const(1);
972 if (wm->vsc.full > a.full)
973 latency_tolerant_lines = 1;
974 else {
975 if (lb_partitions <= (wm->vtaps + 1))
976 latency_tolerant_lines = 1;
977 else
978 latency_tolerant_lines = 2;
979 }
980
981 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
982
983 if (evergreen_latency_watermark(wm) <= latency_hiding)
984 return true;
985 else
986 return false;
987}
988
989static void evergreen_program_watermarks(struct radeon_device *rdev,
990 struct radeon_crtc *radeon_crtc,
991 u32 lb_size, u32 num_heads)
992{
993 struct drm_display_mode *mode = &radeon_crtc->base.mode;
994 struct evergreen_wm_params wm;
995 u32 pixel_period;
996 u32 line_time = 0;
997 u32 latency_watermark_a = 0, latency_watermark_b = 0;
998 u32 priority_a_mark = 0, priority_b_mark = 0;
999 u32 priority_a_cnt = PRIORITY_OFF;
1000 u32 priority_b_cnt = PRIORITY_OFF;
1001 u32 pipe_offset = radeon_crtc->crtc_id * 16;
1002 u32 tmp, arb_control3;
1003 fixed20_12 a, b, c;
1004
1005 if (radeon_crtc->base.enabled && num_heads && mode) {
1006 pixel_period = 1000000 / (u32)mode->clock;
1007 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1008 priority_a_cnt = 0;
1009 priority_b_cnt = 0;
1010
1011 wm.yclk = rdev->pm.current_mclk * 10;
1012 wm.sclk = rdev->pm.current_sclk * 10;
1013 wm.disp_clk = mode->clock;
1014 wm.src_width = mode->crtc_hdisplay;
1015 wm.active_time = mode->crtc_hdisplay * pixel_period;
1016 wm.blank_time = line_time - wm.active_time;
1017 wm.interlaced = false;
1018 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1019 wm.interlaced = true;
1020 wm.vsc = radeon_crtc->vsc;
1021 wm.vtaps = 1;
1022 if (radeon_crtc->rmx_type != RMX_OFF)
1023 wm.vtaps = 2;
1024 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
1025 wm.lb_size = lb_size;
1026 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
1027 wm.num_heads = num_heads;
1028
1029 /* set for high clocks */
1030 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
1031 /* set for low clocks */
1032 /* wm.yclk = low clk; wm.sclk = low clk */
1033 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
1034
1035 /* possibly force display priority to high */
1036 /* should really do this at mode validation time... */
1037 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
1038 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
1039 !evergreen_check_latency_hiding(&wm) ||
1040 (rdev->disp_priority == 2)) {
92bdfd4a 1041 DRM_DEBUG_KMS("force priority to high\n");
f9d9c362
AD		 1042 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1043 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1044 }
1045
1046 a.full = dfixed_const(1000);
1047 b.full = dfixed_const(mode->clock);
1048 b.full = dfixed_div(b, a);
1049 c.full = dfixed_const(latency_watermark_a);
1050 c.full = dfixed_mul(c, b);
1051 c.full = dfixed_mul(c, radeon_crtc->hsc);
1052 c.full = dfixed_div(c, a);
1053 a.full = dfixed_const(16);
1054 c.full = dfixed_div(c, a);
1055 priority_a_mark = dfixed_trunc(c);
1056 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1057
1058 a.full = dfixed_const(1000);
1059 b.full = dfixed_const(mode->clock);
1060 b.full = dfixed_div(b, a);
1061 c.full = dfixed_const(latency_watermark_b);
1062 c.full = dfixed_mul(c, b);
1063 c.full = dfixed_mul(c, radeon_crtc->hsc);
1064 c.full = dfixed_div(c, a);
1065 a.full = dfixed_const(16);
1066 c.full = dfixed_div(c, a);
1067 priority_b_mark = dfixed_trunc(c);
1068 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1069 }
1070
1071 /* select wm A */
1072 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1073 tmp = arb_control3;
1074 tmp &= ~LATENCY_WATERMARK_MASK(3);
1075 tmp |= LATENCY_WATERMARK_MASK(1);
1076 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1077 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1078 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1079 LATENCY_HIGH_WATERMARK(line_time)));
1080 /* select wm B */
1081 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1082 tmp &= ~LATENCY_WATERMARK_MASK(3);
1083 tmp |= LATENCY_WATERMARK_MASK(2);
1084 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1085 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1086 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1087 LATENCY_HIGH_WATERMARK(line_time)));
1088 /* restore original selection */
1089 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1090
1091 /* write the priority marks */
1092 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1093 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1094
1095}
1096
377edc8b
AD		 1097/**
1098 * evergreen_bandwidth_update - update display watermarks callback.
1099 *
1100 * @rdev: radeon_device pointer
1101 *
1102 * Update the display watermarks based on the requested mode(s)
1103 * (evergreen+).
1104 */
0ca2ab52 1105void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 1106{
f9d9c362
AD		 1107 struct drm_display_mode *mode0 = NULL;
1108 struct drm_display_mode *mode1 = NULL;
1109 u32 num_heads = 0, lb_size;
1110 int i;
1111
1112 radeon_update_display_priority(rdev);
1113
1114 for (i = 0; i < rdev->num_crtc; i++) {
1115 if (rdev->mode_info.crtcs[i]->base.enabled)
1116 num_heads++;
1117 }
1118 for (i = 0; i < rdev->num_crtc; i += 2) {
1119 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1120 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1121 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1122 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1123 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1124 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1125 }
bcc1c2a1
AD		 1126}
1127
377edc8b
AD		 1128/**
1129 * evergreen_mc_wait_for_idle - wait for MC idle callback.
1130 *
1131 * @rdev: radeon_device pointer
1132 *
1133 * Wait for the MC (memory controller) to be idle.
1134 * (evergreen+).
1135 * Returns 0 if the MC is idle, -1 if not.
1136 */
b9952a8a 1137int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 1138{
1139 unsigned i;
1140 u32 tmp;
1141
1142 for (i = 0; i < rdev->usec_timeout; i++) {
1143 /* read MC_STATUS */
1144 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1145 if (!tmp)
1146 return 0;
1147 udelay(1);
1148 }
1149 return -1;
1150}
1151
1152/*
1153 * GART
1154 */
0fcdb61e
AD		 1155void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1156{
1157 unsigned i;
1158 u32 tmp;
1159
6f2f48a9
AD		 1160 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1161
0fcdb61e
AD		 1162 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1163 for (i = 0; i < rdev->usec_timeout; i++) {
1164 /* read MC_STATUS */
1165 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1166 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1167 if (tmp == 2) {
1168 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1169 return;
1170 }
1171 if (tmp) {
1172 return;
1173 }
1174 udelay(1);
1175 }
1176}
1177
1109ca09 1178static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 1179{
1180 u32 tmp;
0fcdb61e 1181 int r;
bcc1c2a1 1182
c9a1be96 1183 if (rdev->gart.robj == NULL) {
bcc1c2a1
AD		 1184 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1185 return -EINVAL;
1186 }
1187 r = radeon_gart_table_vram_pin(rdev);
1188 if (r)
1189 return r;
82568565 1190 radeon_gart_restore(rdev);
bcc1c2a1
AD		 1191 /* Setup L2 cache */
1192 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1193 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1194 EFFECTIVE_L2_QUEUE_SIZE(7));
1195 WREG32(VM_L2_CNTL2, 0);
1196 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1197 /* Setup TLB control */
1198 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1199 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1200 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1201 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 1202 if (rdev->flags & RADEON_IS_IGP) {
1203 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1204 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1205 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1206 } else {
1207 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1208 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1209 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
0b8c30bc
AD		 1210 if ((rdev->family == CHIP_JUNIPER) ||
1211 (rdev->family == CHIP_CYPRESS) ||
1212 (rdev->family == CHIP_HEMLOCK) ||
1213 (rdev->family == CHIP_BARTS))
1214 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
8aeb96f8 1215 }
bcc1c2a1
AD		 1216 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1217 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1218 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1219 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1220 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1221 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1222 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1223 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1224 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1225 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1226 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 1227 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 1228
0fcdb61e 1229 evergreen_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1230 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1231 (unsigned)(rdev->mc.gtt_size >> 20),
1232 (unsigned long long)rdev->gart.table_addr);
bcc1c2a1
AD		 1233 rdev->gart.ready = true;
1234 return 0;
1235}
1236
1109ca09 1237static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
bcc1c2a1
AD		 1238{
1239 u32 tmp;
bcc1c2a1
AD		 1240
1241 /* Disable all tables */
0fcdb61e
AD		 1242 WREG32(VM_CONTEXT0_CNTL, 0);
1243 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1244
1245 /* Setup L2 cache */
1246 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1247 EFFECTIVE_L2_QUEUE_SIZE(7));
1248 WREG32(VM_L2_CNTL2, 0);
1249 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1250 /* Setup TLB control */
1251 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1252 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1253 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1254 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1255 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1256 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1257 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1258 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 1259 radeon_gart_table_vram_unpin(rdev);
bcc1c2a1
AD		 1260}
1261
1109ca09 1262static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
bcc1c2a1
AD		 1263{
1264 evergreen_pcie_gart_disable(rdev);
1265 radeon_gart_table_vram_free(rdev);
1266 radeon_gart_fini(rdev);
1267}
1268
1269
1109ca09 1270static void evergreen_agp_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 1271{
1272 u32 tmp;
bcc1c2a1
AD		 1273
1274 /* Setup L2 cache */
1275 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1276 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1277 EFFECTIVE_L2_QUEUE_SIZE(7));
1278 WREG32(VM_L2_CNTL2, 0);
1279 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1280 /* Setup TLB control */
1281 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1282 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1283 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1284 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1285 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1286 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1287 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1288 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1289 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1290 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1291 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 1292 WREG32(VM_CONTEXT0_CNTL, 0);
1293 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1294}
1295
b9952a8a 1296void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 1297{
62444b74
AD		 1298 u32 crtc_enabled, tmp, frame_count, blackout;
1299 int i, j;
1300
bcc1c2a1
AD		 1301 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1302 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
bcc1c2a1 1303
62444b74 1304 /* disable VGA render */
bcc1c2a1 1305 WREG32(VGA_RENDER_CONTROL, 0);
62444b74
AD		 1306 /* blank the display controllers */
1307 for (i = 0; i < rdev->num_crtc; i++) {
1308 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1309 if (crtc_enabled) {
1310 save->crtc_enabled[i] = true;
1311 if (ASIC_IS_DCE6(rdev)) {
1312 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1313 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1314 radeon_wait_for_vblank(rdev, i);
1315 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
bb588820 1316 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1317 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
bb588820 1318 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1319 }
1320 } else {
1321 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1322 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1323 radeon_wait_for_vblank(rdev, i);
1324 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
bb588820 1325 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1326 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
bb588820 1327 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1328 }
1329 }
1330 /* wait for the next frame */
1331 frame_count = radeon_get_vblank_counter(rdev, i);
1332 for (j = 0; j < rdev->usec_timeout; j++) {
1333 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1334 break;
1335 udelay(1);
1336 }
804cc4a0
AD		 1337 } else {
1338 save->crtc_enabled[i] = false;
62444b74 1339 }
18007401 1340 }
bcc1c2a1 1341
62444b74
AD		 1342 radeon_mc_wait_for_idle(rdev);
1343
1344 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1345 if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1346 /* Block CPU access */
1347 WREG32(BIF_FB_EN, 0);
1348 /* blackout the MC */
1349 blackout &= ~BLACKOUT_MODE_MASK;
1350 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
b7eff394 1351 }
ed39fadd
AD		 1352 /* wait for the MC to settle */
1353 udelay(100);
bcc1c2a1
AD		 1354}
1355
b9952a8a 1356void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 1357{
62444b74
AD		 1358 u32 tmp, frame_count;
1359 int i, j;
18007401 1360
62444b74
AD		 1361 /* update crtc base addresses */
1362 for (i = 0; i < rdev->num_crtc; i++) {
1363 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 1364 upper_32_bits(rdev->mc.vram_start));
62444b74 1365 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 1366 upper_32_bits(rdev->mc.vram_start));
62444b74 1367 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401 1368 (u32)rdev->mc.vram_start);
62444b74 1369 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401
AD		 1370 (u32)rdev->mc.vram_start);
1371 }
bcc1c2a1
AD		 1372 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1373 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
62444b74
AD		 1374
1375 /* unblackout the MC */
1376 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1377 tmp &= ~BLACKOUT_MODE_MASK;
1378 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1379 /* allow CPU access */
1380 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1381
1382 for (i = 0; i < rdev->num_crtc; i++) {
695ddeb4 1383 if (save->crtc_enabled[i]) {
62444b74
AD		 1384 if (ASIC_IS_DCE6(rdev)) {
1385 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1386 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
bb588820 1387 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1388 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
bb588820 1389 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1390 } else {
1391 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1392 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
bb588820 1393 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1394 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
bb588820 1395 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1396 }
1397 /* wait for the next frame */
1398 frame_count = radeon_get_vblank_counter(rdev, i);
1399 for (j = 0; j < rdev->usec_timeout; j++) {
1400 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1401 break;
1402 udelay(1);
1403 }
1404 }
1405 }
1406 /* Unlock vga access */
bcc1c2a1
AD		 1407 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1408 mdelay(1);
bcc1c2a1
AD		 1409 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1410}
1411
755d819e 1412void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 1413{
1414 struct evergreen_mc_save save;
1415 u32 tmp;
1416 int i, j;
1417
1418 /* Initialize HDP */
1419 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1420 WREG32((0x2c14 + j), 0x00000000);
1421 WREG32((0x2c18 + j), 0x00000000);
1422 WREG32((0x2c1c + j), 0x00000000);
1423 WREG32((0x2c20 + j), 0x00000000);
1424 WREG32((0x2c24 + j), 0x00000000);
1425 }
1426 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1427
1428 evergreen_mc_stop(rdev, &save);
1429 if (evergreen_mc_wait_for_idle(rdev)) {
1430 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1431 }
1432 /* Lockout access through VGA aperture*/
1433 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1434 /* Update configuration */
1435 if (rdev->flags & RADEON_IS_AGP) {
1436 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1437 /* VRAM before AGP */
1438 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1439 rdev->mc.vram_start >> 12);
1440 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1441 rdev->mc.gtt_end >> 12);
1442 } else {
1443 /* VRAM after AGP */
1444 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1445 rdev->mc.gtt_start >> 12);
1446 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1447 rdev->mc.vram_end >> 12);
1448 }
1449 } else {
1450 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1451 rdev->mc.vram_start >> 12);
1452 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1453 rdev->mc.vram_end >> 12);
1454 }
3b9832f6 1455 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
05b3ef69
AD		 1456 /* llano/ontario only */
1457 if ((rdev->family == CHIP_PALM) ||
1458 (rdev->family == CHIP_SUMO) ||
1459 (rdev->family == CHIP_SUMO2)) {
b4183e30
AD		 1460 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1461 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1462 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1463 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1464 }
bcc1c2a1
AD		 1465 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1466 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1467 WREG32(MC_VM_FB_LOCATION, tmp);
1468 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 1469 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 1470 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1471 if (rdev->flags & RADEON_IS_AGP) {
1472 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1473 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1474 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1475 } else {
1476 WREG32(MC_VM_AGP_BASE, 0);
1477 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1478 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1479 }
1480 if (evergreen_mc_wait_for_idle(rdev)) {
1481 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1482 }
1483 evergreen_mc_resume(rdev, &save);
1484 /* we need to own VRAM, so turn off the VGA renderer here
1485 * to stop it overwriting our objects */
1486 rv515_vga_render_disable(rdev);
1487}
1488
bcc1c2a1
AD		 1489/*
1490 * CP.
1491 */
12920591
AD		 1492void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1493{
876dc9f3 1494 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 1495 u32 next_rptr;
7b1f2485 1496
12920591 1497 /* set to DX10/11 mode */
e32eb50d
CK		 1498 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1499 radeon_ring_write(ring, 1);
45df6803
CK		 1500
1501 if (ring->rptr_save_reg) {
89d35807 1502 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 1503 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1504 radeon_ring_write(ring, ((ring->rptr_save_reg -
1505 PACKET3_SET_CONFIG_REG_START) >> 2));
1506 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1507 } else if (rdev->wb.enabled) {
1508 next_rptr = ring->wptr + 5 + 4;
1509 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1510 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1511 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1512 radeon_ring_write(ring, next_rptr);
1513 radeon_ring_write(ring, 0);
45df6803
CK		 1514 }
1515
e32eb50d
CK		 1516 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1517 radeon_ring_write(ring,
0f234f5f
AD		 1518#ifdef __BIG_ENDIAN
1519 (2 << 0) |
1520#endif
1521 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 1522 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1523 radeon_ring_write(ring, ib->length_dw);
12920591
AD		 1524}
1525
bcc1c2a1
AD		 1526
1527static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1528{
fe251e2f
AD		 1529 const __be32 *fw_data;
1530 int i;
1531
1532 if (!rdev->me_fw || !rdev->pfp_fw)
1533 return -EINVAL;
bcc1c2a1 1534
fe251e2f 1535 r700_cp_stop(rdev);
0f234f5f
AD		 1536 WREG32(CP_RB_CNTL,
1537#ifdef __BIG_ENDIAN
1538 BUF_SWAP_32BIT |
1539#endif
1540 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 1541
1542 fw_data = (const __be32 *)rdev->pfp_fw->data;
1543 WREG32(CP_PFP_UCODE_ADDR, 0);
1544 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1545 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1546 WREG32(CP_PFP_UCODE_ADDR, 0);
1547
1548 fw_data = (const __be32 *)rdev->me_fw->data;
1549 WREG32(CP_ME_RAM_WADDR, 0);
1550 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1551 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1552
1553 WREG32(CP_PFP_UCODE_ADDR, 0);
1554 WREG32(CP_ME_RAM_WADDR, 0);
1555 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1556 return 0;
1557}
1558
7e7b41d2
AD		 1559static int evergreen_cp_start(struct radeon_device *rdev)
1560{
e32eb50d 1561 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2281a378 1562 int r, i;
7e7b41d2
AD		 1563 uint32_t cp_me;
1564
e32eb50d 1565 r = radeon_ring_lock(rdev, ring, 7);
7e7b41d2
AD		 1566 if (r) {
1567 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1568 return r;
1569 }
e32eb50d
CK		 1570 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1571 radeon_ring_write(ring, 0x1);
1572 radeon_ring_write(ring, 0x0);
1573 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1574 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1575 radeon_ring_write(ring, 0);
1576 radeon_ring_write(ring, 0);
1577 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1578
1579 cp_me = 0xff;
1580 WREG32(CP_ME_CNTL, cp_me);
1581
e32eb50d 1582 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
7e7b41d2
AD		 1583 if (r) {
1584 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1585 return r;
1586 }
2281a378
AD		 1587
1588 /* setup clear context state */
e32eb50d
CK		 1589 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1590 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2281a378
AD		 1591
1592 for (i = 0; i < evergreen_default_size; i++)
e32eb50d 1593 radeon_ring_write(ring, evergreen_default_state[i]);
2281a378 1594
e32eb50d
CK		 1595 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1596 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2281a378
AD		 1597
1598 /* set clear context state */
e32eb50d
CK		 1599 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1600 radeon_ring_write(ring, 0);
2281a378
AD		 1601
1602 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1603 radeon_ring_write(ring, 0xc0026f00);
1604 radeon_ring_write(ring, 0x00000000);
1605 radeon_ring_write(ring, 0x00000000);
1606 radeon_ring_write(ring, 0x00000000);
2281a378
AD		 1607
1608 /* Clear consts */
e32eb50d
CK		 1609 radeon_ring_write(ring, 0xc0036f00);
1610 radeon_ring_write(ring, 0x00000bc4);
1611 radeon_ring_write(ring, 0xffffffff);
1612 radeon_ring_write(ring, 0xffffffff);
1613 radeon_ring_write(ring, 0xffffffff);
2281a378 1614
e32eb50d
CK		 1615 radeon_ring_write(ring, 0xc0026900);
1616 radeon_ring_write(ring, 0x00000316);
1617 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1618 radeon_ring_write(ring, 0x00000010); /* */
18ff84da 1619
e32eb50d 1620 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1621
1622 return 0;
1623}
1624
1109ca09 1625static int evergreen_cp_resume(struct radeon_device *rdev)
fe251e2f 1626{
e32eb50d 1627 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f
AD		 1628 u32 tmp;
1629 u32 rb_bufsz;
1630 int r;
1631
1632 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1633 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1634 SOFT_RESET_PA |
1635 SOFT_RESET_SH |
1636 SOFT_RESET_VGT |
a49a50da 1637 SOFT_RESET_SPI |
fe251e2f
AD		 1638 SOFT_RESET_SX));
1639 RREG32(GRBM_SOFT_RESET);
1640 mdelay(15);
1641 WREG32(GRBM_SOFT_RESET, 0);
1642 RREG32(GRBM_SOFT_RESET);
1643
1644 /* Set ring buffer size */
e32eb50d 1645 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 1646 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1647#ifdef __BIG_ENDIAN
1648 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1649#endif
fe251e2f 1650 WREG32(CP_RB_CNTL, tmp);
15d3332f 1651 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1652 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
fe251e2f
AD		 1653
1654 /* Set the write pointer delay */
1655 WREG32(CP_RB_WPTR_DELAY, 0);
1656
1657 /* Initialize the ring buffer's read and write pointers */
1658 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1659 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1660 ring->wptr = 0;
1661 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1 1662
48fc7f7e 1663 /* set the wb address whether it's enabled or not */
0f234f5f 1664 WREG32(CP_RB_RPTR_ADDR,
0f234f5f 1665 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 1666 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1667 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1668
1669 if (rdev->wb.enabled)
1670 WREG32(SCRATCH_UMSK, 0xff);
1671 else {
1672 tmp |= RB_NO_UPDATE;
1673 WREG32(SCRATCH_UMSK, 0);
1674 }
1675
fe251e2f
AD		 1676 mdelay(1);
1677 WREG32(CP_RB_CNTL, tmp);
1678
e32eb50d 1679 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
fe251e2f
AD		 1680 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1681
e32eb50d 1682 ring->rptr = RREG32(CP_RB_RPTR);
fe251e2f 1683
7e7b41d2 1684 evergreen_cp_start(rdev);
e32eb50d 1685 ring->ready = true;
f712812e 1686 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
fe251e2f 1687 if (r) {
e32eb50d 1688 ring->ready = false;
fe251e2f
AD		 1689 return r;
1690 }
1691 return 0;
1692}
bcc1c2a1
AD		 1693
1694/*
1695 * Core functions
1696 */
bcc1c2a1
AD		 1697static void evergreen_gpu_init(struct radeon_device *rdev)
1698{
416a2bd2 1699 u32 gb_addr_config;
32fcdbf4 1700 u32 mc_shared_chmap, mc_arb_ramcfg;
32fcdbf4
AD		 1701 u32 sx_debug_1;
1702 u32 smx_dc_ctl0;
1703 u32 sq_config;
1704 u32 sq_lds_resource_mgmt;
1705 u32 sq_gpr_resource_mgmt_1;
1706 u32 sq_gpr_resource_mgmt_2;
1707 u32 sq_gpr_resource_mgmt_3;
1708 u32 sq_thread_resource_mgmt;
1709 u32 sq_thread_resource_mgmt_2;
1710 u32 sq_stack_resource_mgmt_1;
1711 u32 sq_stack_resource_mgmt_2;
1712 u32 sq_stack_resource_mgmt_3;
1713 u32 vgt_cache_invalidation;
f25a5c63 1714 u32 hdp_host_path_cntl, tmp;
416a2bd2 1715 u32 disabled_rb_mask;
32fcdbf4
AD		 1716 int i, j, num_shader_engines, ps_thread_count;
1717
1718 switch (rdev->family) {
1719 case CHIP_CYPRESS:
1720 case CHIP_HEMLOCK:
1721 rdev->config.evergreen.num_ses = 2;
1722 rdev->config.evergreen.max_pipes = 4;
1723 rdev->config.evergreen.max_tile_pipes = 8;
1724 rdev->config.evergreen.max_simds = 10;
1725 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1726 rdev->config.evergreen.max_gprs = 256;
1727 rdev->config.evergreen.max_threads = 248;
1728 rdev->config.evergreen.max_gs_threads = 32;
1729 rdev->config.evergreen.max_stack_entries = 512;
1730 rdev->config.evergreen.sx_num_of_sets = 4;
1731 rdev->config.evergreen.sx_max_export_size = 256;
1732 rdev->config.evergreen.sx_max_export_pos_size = 64;
1733 rdev->config.evergreen.sx_max_export_smx_size = 192;
1734 rdev->config.evergreen.max_hw_contexts = 8;
1735 rdev->config.evergreen.sq_num_cf_insts = 2;
1736
1737 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1738 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1739 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1740 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1741 break;
1742 case CHIP_JUNIPER:
1743 rdev->config.evergreen.num_ses = 1;
1744 rdev->config.evergreen.max_pipes = 4;
1745 rdev->config.evergreen.max_tile_pipes = 4;
1746 rdev->config.evergreen.max_simds = 10;
1747 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1748 rdev->config.evergreen.max_gprs = 256;
1749 rdev->config.evergreen.max_threads = 248;
1750 rdev->config.evergreen.max_gs_threads = 32;
1751 rdev->config.evergreen.max_stack_entries = 512;
1752 rdev->config.evergreen.sx_num_of_sets = 4;
1753 rdev->config.evergreen.sx_max_export_size = 256;
1754 rdev->config.evergreen.sx_max_export_pos_size = 64;
1755 rdev->config.evergreen.sx_max_export_smx_size = 192;
1756 rdev->config.evergreen.max_hw_contexts = 8;
1757 rdev->config.evergreen.sq_num_cf_insts = 2;
1758
1759 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1760 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1761 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1762 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1763 break;
1764 case CHIP_REDWOOD:
1765 rdev->config.evergreen.num_ses = 1;
1766 rdev->config.evergreen.max_pipes = 4;
1767 rdev->config.evergreen.max_tile_pipes = 4;
1768 rdev->config.evergreen.max_simds = 5;
1769 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1770 rdev->config.evergreen.max_gprs = 256;
1771 rdev->config.evergreen.max_threads = 248;
1772 rdev->config.evergreen.max_gs_threads = 32;
1773 rdev->config.evergreen.max_stack_entries = 256;
1774 rdev->config.evergreen.sx_num_of_sets = 4;
1775 rdev->config.evergreen.sx_max_export_size = 256;
1776 rdev->config.evergreen.sx_max_export_pos_size = 64;
1777 rdev->config.evergreen.sx_max_export_smx_size = 192;
1778 rdev->config.evergreen.max_hw_contexts = 8;
1779 rdev->config.evergreen.sq_num_cf_insts = 2;
1780
1781 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1782 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1783 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1784 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1785 break;
1786 case CHIP_CEDAR:
1787 default:
1788 rdev->config.evergreen.num_ses = 1;
1789 rdev->config.evergreen.max_pipes = 2;
1790 rdev->config.evergreen.max_tile_pipes = 2;
1791 rdev->config.evergreen.max_simds = 2;
1792 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1793 rdev->config.evergreen.max_gprs = 256;
1794 rdev->config.evergreen.max_threads = 192;
1795 rdev->config.evergreen.max_gs_threads = 16;
1796 rdev->config.evergreen.max_stack_entries = 256;
1797 rdev->config.evergreen.sx_num_of_sets = 4;
1798 rdev->config.evergreen.sx_max_export_size = 128;
1799 rdev->config.evergreen.sx_max_export_pos_size = 32;
1800 rdev->config.evergreen.sx_max_export_smx_size = 96;
1801 rdev->config.evergreen.max_hw_contexts = 4;
1802 rdev->config.evergreen.sq_num_cf_insts = 1;
1803
d5e455e4
AD		 1804 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1805 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1806 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1807 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5e455e4
AD		 1808 break;
1809 case CHIP_PALM:
1810 rdev->config.evergreen.num_ses = 1;
1811 rdev->config.evergreen.max_pipes = 2;
1812 rdev->config.evergreen.max_tile_pipes = 2;
1813 rdev->config.evergreen.max_simds = 2;
1814 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1815 rdev->config.evergreen.max_gprs = 256;
1816 rdev->config.evergreen.max_threads = 192;
1817 rdev->config.evergreen.max_gs_threads = 16;
1818 rdev->config.evergreen.max_stack_entries = 256;
1819 rdev->config.evergreen.sx_num_of_sets = 4;
1820 rdev->config.evergreen.sx_max_export_size = 128;
1821 rdev->config.evergreen.sx_max_export_pos_size = 32;
1822 rdev->config.evergreen.sx_max_export_smx_size = 96;
1823 rdev->config.evergreen.max_hw_contexts = 4;
1824 rdev->config.evergreen.sq_num_cf_insts = 1;
1825
d5c5a72f
AD		 1826 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1827 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1828 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1829 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 1830 break;
1831 case CHIP_SUMO:
1832 rdev->config.evergreen.num_ses = 1;
1833 rdev->config.evergreen.max_pipes = 4;
bd25f078 1834 rdev->config.evergreen.max_tile_pipes = 4;
d5c5a72f
AD		 1835 if (rdev->pdev->device == 0x9648)
1836 rdev->config.evergreen.max_simds = 3;
1837 else if ((rdev->pdev->device == 0x9647) ||
1838 (rdev->pdev->device == 0x964a))
1839 rdev->config.evergreen.max_simds = 4;
1840 else
1841 rdev->config.evergreen.max_simds = 5;
1842 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1843 rdev->config.evergreen.max_gprs = 256;
1844 rdev->config.evergreen.max_threads = 248;
1845 rdev->config.evergreen.max_gs_threads = 32;
1846 rdev->config.evergreen.max_stack_entries = 256;
1847 rdev->config.evergreen.sx_num_of_sets = 4;
1848 rdev->config.evergreen.sx_max_export_size = 256;
1849 rdev->config.evergreen.sx_max_export_pos_size = 64;
1850 rdev->config.evergreen.sx_max_export_smx_size = 192;
1851 rdev->config.evergreen.max_hw_contexts = 8;
1852 rdev->config.evergreen.sq_num_cf_insts = 2;
1853
1854 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1855 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1856 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 1857 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 1858 break;
1859 case CHIP_SUMO2:
1860 rdev->config.evergreen.num_ses = 1;
1861 rdev->config.evergreen.max_pipes = 4;
1862 rdev->config.evergreen.max_tile_pipes = 4;
1863 rdev->config.evergreen.max_simds = 2;
1864 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1865 rdev->config.evergreen.max_gprs = 256;
1866 rdev->config.evergreen.max_threads = 248;
1867 rdev->config.evergreen.max_gs_threads = 32;
1868 rdev->config.evergreen.max_stack_entries = 512;
1869 rdev->config.evergreen.sx_num_of_sets = 4;
1870 rdev->config.evergreen.sx_max_export_size = 256;
1871 rdev->config.evergreen.sx_max_export_pos_size = 64;
1872 rdev->config.evergreen.sx_max_export_smx_size = 192;
1873 rdev->config.evergreen.max_hw_contexts = 8;
1874 rdev->config.evergreen.sq_num_cf_insts = 2;
1875
adb68fa2
AD		 1876 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1877 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1878 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 1879 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1880 break;
1881 case CHIP_BARTS:
1882 rdev->config.evergreen.num_ses = 2;
1883 rdev->config.evergreen.max_pipes = 4;
1884 rdev->config.evergreen.max_tile_pipes = 8;
1885 rdev->config.evergreen.max_simds = 7;
1886 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1887 rdev->config.evergreen.max_gprs = 256;
1888 rdev->config.evergreen.max_threads = 248;
1889 rdev->config.evergreen.max_gs_threads = 32;
1890 rdev->config.evergreen.max_stack_entries = 512;
1891 rdev->config.evergreen.sx_num_of_sets = 4;
1892 rdev->config.evergreen.sx_max_export_size = 256;
1893 rdev->config.evergreen.sx_max_export_pos_size = 64;
1894 rdev->config.evergreen.sx_max_export_smx_size = 192;
1895 rdev->config.evergreen.max_hw_contexts = 8;
1896 rdev->config.evergreen.sq_num_cf_insts = 2;
1897
1898 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1899 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1900 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1901 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1902 break;
1903 case CHIP_TURKS:
1904 rdev->config.evergreen.num_ses = 1;
1905 rdev->config.evergreen.max_pipes = 4;
1906 rdev->config.evergreen.max_tile_pipes = 4;
1907 rdev->config.evergreen.max_simds = 6;
1908 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1909 rdev->config.evergreen.max_gprs = 256;
1910 rdev->config.evergreen.max_threads = 248;
1911 rdev->config.evergreen.max_gs_threads = 32;
1912 rdev->config.evergreen.max_stack_entries = 256;
1913 rdev->config.evergreen.sx_num_of_sets = 4;
1914 rdev->config.evergreen.sx_max_export_size = 256;
1915 rdev->config.evergreen.sx_max_export_pos_size = 64;
1916 rdev->config.evergreen.sx_max_export_smx_size = 192;
1917 rdev->config.evergreen.max_hw_contexts = 8;
1918 rdev->config.evergreen.sq_num_cf_insts = 2;
1919
1920 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1921 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1922 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1923 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1924 break;
1925 case CHIP_CAICOS:
1926 rdev->config.evergreen.num_ses = 1;
bd25f078 1927 rdev->config.evergreen.max_pipes = 2;
adb68fa2
AD		 1928 rdev->config.evergreen.max_tile_pipes = 2;
1929 rdev->config.evergreen.max_simds = 2;
1930 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1931 rdev->config.evergreen.max_gprs = 256;
1932 rdev->config.evergreen.max_threads = 192;
1933 rdev->config.evergreen.max_gs_threads = 16;
1934 rdev->config.evergreen.max_stack_entries = 256;
1935 rdev->config.evergreen.sx_num_of_sets = 4;
1936 rdev->config.evergreen.sx_max_export_size = 128;
1937 rdev->config.evergreen.sx_max_export_pos_size = 32;
1938 rdev->config.evergreen.sx_max_export_smx_size = 96;
1939 rdev->config.evergreen.max_hw_contexts = 4;
1940 rdev->config.evergreen.sq_num_cf_insts = 1;
1941
32fcdbf4
AD		 1942 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1943 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1944 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1945 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1946 break;
1947 }
1948
1949 /* Initialize HDP */
1950 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1951 WREG32((0x2c14 + j), 0x00000000);
1952 WREG32((0x2c18 + j), 0x00000000);
1953 WREG32((0x2c1c + j), 0x00000000);
1954 WREG32((0x2c20 + j), 0x00000000);
1955 WREG32((0x2c24 + j), 0x00000000);
1956 }
1957
1958 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1959
d054ac16
AD		 1960 evergreen_fix_pci_max_read_req_size(rdev);
1961
32fcdbf4 1962 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
05b3ef69
AD		 1963 if ((rdev->family == CHIP_PALM) ||
1964 (rdev->family == CHIP_SUMO) ||
1965 (rdev->family == CHIP_SUMO2))
d9282fca
AD		 1966 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1967 else
1968 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
32fcdbf4 1969
1aa52bd3
AD		 1970 /* setup tiling info dword. gb_addr_config is not adequate since it does
1971 * not have bank info, so create a custom tiling dword.
1972 * bits 3:0 num_pipes
1973 * bits 7:4 num_banks
1974 * bits 11:8 group_size
1975 * bits 15:12 row_size
1976 */
1977 rdev->config.evergreen.tile_config = 0;
1978 switch (rdev->config.evergreen.max_tile_pipes) {
1979 case 1:
1980 default:
1981 rdev->config.evergreen.tile_config |= (0 << 0);
1982 break;
1983 case 2:
1984 rdev->config.evergreen.tile_config |= (1 << 0);
1985 break;
1986 case 4:
1987 rdev->config.evergreen.tile_config |= (2 << 0);
1988 break;
1989 case 8:
1990 rdev->config.evergreen.tile_config |= (3 << 0);
1991 break;
1992 }
d698a34d 1993 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
5bfa4879 1994 if (rdev->flags & RADEON_IS_IGP)
d698a34d 1995 rdev->config.evergreen.tile_config |= 1 << 4;
29d65406 1996 else {
c8d15edc
AD		 1997 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1998 case 0: /* four banks */
29d65406 1999 rdev->config.evergreen.tile_config |= 0 << 4;
c8d15edc
AD		 2000 break;
2001 case 1: /* eight banks */
2002 rdev->config.evergreen.tile_config |= 1 << 4;
2003 break;
2004 case 2: /* sixteen banks */
2005 default:
2006 rdev->config.evergreen.tile_config |= 2 << 4;
2007 break;
2008 }
29d65406 2009 }
416a2bd2 2010 rdev->config.evergreen.tile_config |= 0 << 8;
1aa52bd3
AD		 2011 rdev->config.evergreen.tile_config |=
2012 ((gb_addr_config & 0x30000000) >> 28) << 12;
2013
416a2bd2 2014 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
32fcdbf4 2015
416a2bd2
AD		 2016 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
2017 u32 efuse_straps_4;
2018 u32 efuse_straps_3;
32fcdbf4 2019
416a2bd2
AD		 2020 WREG32(RCU_IND_INDEX, 0x204);
2021 efuse_straps_4 = RREG32(RCU_IND_DATA);
2022 WREG32(RCU_IND_INDEX, 0x203);
2023 efuse_straps_3 = RREG32(RCU_IND_DATA);
2024 tmp = (((efuse_straps_4 & 0xf) << 4) |
2025 ((efuse_straps_3 & 0xf0000000) >> 28));
2026 } else {
2027 tmp = 0;
2028 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
2029 u32 rb_disable_bitmap;
2030
2031 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2032 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2033 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
2034 tmp <<= 4;
2035 tmp |= rb_disable_bitmap;
32fcdbf4 2036 }
416a2bd2
AD		 2037 }
2038 /* enabled rb are just the one not disabled :) */
2039 disabled_rb_mask = tmp;
32fcdbf4 2040
416a2bd2
AD		 2041 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2042 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
32fcdbf4 2043
416a2bd2
AD		 2044 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2045 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2046 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
233d1ad5 2047 WREG32(DMA_TILING_CONFIG, gb_addr_config);
32fcdbf4 2048
f7eb9730
AD		 2049 if ((rdev->config.evergreen.max_backends == 1) &&
2050 (rdev->flags & RADEON_IS_IGP)) {
2051 if ((disabled_rb_mask & 3) == 1) {
2052 /* RB0 disabled, RB1 enabled */
2053 tmp = 0x11111111;
2054 } else {
2055 /* RB1 disabled, RB0 enabled */
2056 tmp = 0x00000000;
2057 }
2058 } else {
2059 tmp = gb_addr_config & NUM_PIPES_MASK;
2060 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2061 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
2062 }
416a2bd2 2063 WREG32(GB_BACKEND_MAP, tmp);
32fcdbf4
AD		 2064
2065 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2066 WREG32(CGTS_TCC_DISABLE, 0);
2067 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2068 WREG32(CGTS_USER_TCC_DISABLE, 0);
2069
2070 /* set HW defaults for 3D engine */
2071 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2072 ROQ_IB2_START(0x2b)));
2073
2074 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2075
2076 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2077 SYNC_GRADIENT |
2078 SYNC_WALKER |
2079 SYNC_ALIGNER));
2080
2081 sx_debug_1 = RREG32(SX_DEBUG_1);
2082 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2083 WREG32(SX_DEBUG_1, sx_debug_1);
2084
2085
2086 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2087 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2088 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2089 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2090
b866d133
AD		 2091 if (rdev->family <= CHIP_SUMO2)
2092 WREG32(SMX_SAR_CTL0, 0x00010000);
2093
32fcdbf4
AD		 2094 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2095 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2096 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2097
2098 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2099 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2100 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2101
2102 WREG32(VGT_NUM_INSTANCES, 1);
2103 WREG32(SPI_CONFIG_CNTL, 0);
2104 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2105 WREG32(CP_PERFMON_CNTL, 0);
2106
2107 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2108 FETCH_FIFO_HIWATER(0x4) |
2109 DONE_FIFO_HIWATER(0xe0) |
2110 ALU_UPDATE_FIFO_HIWATER(0x8)));
2111
2112 sq_config = RREG32(SQ_CONFIG);
2113 sq_config &= ~(PS_PRIO(3) |
2114 VS_PRIO(3) |
2115 GS_PRIO(3) |
2116 ES_PRIO(3));
2117 sq_config |= (VC_ENABLE |
2118 EXPORT_SRC_C |
2119 PS_PRIO(0) |
2120 VS_PRIO(1) |
2121 GS_PRIO(2) |
2122 ES_PRIO(3));
2123
d5e455e4
AD		 2124 switch (rdev->family) {
2125 case CHIP_CEDAR:
2126 case CHIP_PALM:
d5c5a72f
AD		 2127 case CHIP_SUMO:
2128 case CHIP_SUMO2:
adb68fa2 2129 case CHIP_CAICOS:
32fcdbf4
AD		 2130 /* no vertex cache */
2131 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 2132 break;
2133 default:
2134 break;
2135 }
32fcdbf4
AD		 2136
2137 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2138
2139 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2140 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2141 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2142 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2143 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2144 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2145 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2146
d5e455e4
AD		 2147 switch (rdev->family) {
2148 case CHIP_CEDAR:
2149 case CHIP_PALM:
d5c5a72f
AD		 2150 case CHIP_SUMO:
2151 case CHIP_SUMO2:
32fcdbf4 2152 ps_thread_count = 96;
d5e455e4
AD		 2153 break;
2154 default:
32fcdbf4 2155 ps_thread_count = 128;
d5e455e4
AD		 2156 break;
2157 }
32fcdbf4
AD		 2158
2159 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 2160 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2161 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2162 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2163 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2164 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 2165
2166 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2167 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2168 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2169 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2170 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2171 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2172
2173 WREG32(SQ_CONFIG, sq_config);
2174 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2175 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2176 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2177 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2178 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2179 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2180 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2181 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2182 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2183 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2184
2185 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2186 FORCE_EOV_MAX_REZ_CNT(255)));
2187
d5e455e4
AD		 2188 switch (rdev->family) {
2189 case CHIP_CEDAR:
2190 case CHIP_PALM:
d5c5a72f
AD		 2191 case CHIP_SUMO:
2192 case CHIP_SUMO2:
adb68fa2 2193 case CHIP_CAICOS:
32fcdbf4 2194 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 2195 break;
2196 default:
32fcdbf4 2197 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 2198 break;
2199 }
32fcdbf4
AD		 2200 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2201 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2202
2203 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 2204 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 2205 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2206
60a4a3e0
AD		 2207 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2208 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2209
32fcdbf4
AD		 2210 WREG32(CB_PERF_CTR0_SEL_0, 0);
2211 WREG32(CB_PERF_CTR0_SEL_1, 0);
2212 WREG32(CB_PERF_CTR1_SEL_0, 0);
2213 WREG32(CB_PERF_CTR1_SEL_1, 0);
2214 WREG32(CB_PERF_CTR2_SEL_0, 0);
2215 WREG32(CB_PERF_CTR2_SEL_1, 0);
2216 WREG32(CB_PERF_CTR3_SEL_0, 0);
2217 WREG32(CB_PERF_CTR3_SEL_1, 0);
2218
60a4a3e0
AD		 2219 /* clear render buffer base addresses */
2220 WREG32(CB_COLOR0_BASE, 0);
2221 WREG32(CB_COLOR1_BASE, 0);
2222 WREG32(CB_COLOR2_BASE, 0);
2223 WREG32(CB_COLOR3_BASE, 0);
2224 WREG32(CB_COLOR4_BASE, 0);
2225 WREG32(CB_COLOR5_BASE, 0);
2226 WREG32(CB_COLOR6_BASE, 0);
2227 WREG32(CB_COLOR7_BASE, 0);
2228 WREG32(CB_COLOR8_BASE, 0);
2229 WREG32(CB_COLOR9_BASE, 0);
2230 WREG32(CB_COLOR10_BASE, 0);
2231 WREG32(CB_COLOR11_BASE, 0);
2232
2233 /* set the shader const cache sizes to 0 */
2234 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2235 WREG32(i, 0);
2236 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2237 WREG32(i, 0);
2238
f25a5c63
AD		 2239 tmp = RREG32(HDP_MISC_CNTL);
2240 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2241 WREG32(HDP_MISC_CNTL, tmp);
2242
32fcdbf4
AD		 2243 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2244 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2245
2246 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2247
2248 udelay(50);
2249
bcc1c2a1
AD		 2250}
2251
2252int evergreen_mc_init(struct radeon_device *rdev)
2253{
bcc1c2a1
AD		 2254 u32 tmp;
2255 int chansize, numchan;
bcc1c2a1
AD		 2256
2257 /* Get VRAM informations */
2258 rdev->mc.vram_is_ddr = true;
05b3ef69
AD		 2259 if ((rdev->family == CHIP_PALM) ||
2260 (rdev->family == CHIP_SUMO) ||
2261 (rdev->family == CHIP_SUMO2))
8208441b
AD		 2262 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2263 else
2264 tmp = RREG32(MC_ARB_RAMCFG);
bcc1c2a1
AD		 2265 if (tmp & CHANSIZE_OVERRIDE) {
2266 chansize = 16;
2267 } else if (tmp & CHANSIZE_MASK) {
2268 chansize = 64;
2269 } else {
2270 chansize = 32;
2271 }
2272 tmp = RREG32(MC_SHARED_CHMAP);
2273 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2274 case 0:
2275 default:
2276 numchan = 1;
2277 break;
2278 case 1:
2279 numchan = 2;
2280 break;
2281 case 2:
2282 numchan = 4;
2283 break;
2284 case 3:
2285 numchan = 8;
2286 break;
2287 }
2288 rdev->mc.vram_width = numchan * chansize;
2289 /* Could aper size report 0 ? */
01d73a69
JC		 2290 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2291 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2292 /* Setup GPU memory space */
05b3ef69
AD		 2293 if ((rdev->family == CHIP_PALM) ||
2294 (rdev->family == CHIP_SUMO) ||
2295 (rdev->family == CHIP_SUMO2)) {
6eb18f8b
AD		 2296 /* size in bytes on fusion */
2297 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2298 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2299 } else {
05b3ef69 2300 /* size in MB on evergreen/cayman/tn */
6eb18f8b
AD		 2301 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2302 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2303 }
51e5fcd3 2304 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 2305 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2306 radeon_update_bandwidth_info(rdev);
2307
bcc1c2a1
AD		 2308 return 0;
2309}
d594e46a 2310
e32eb50d 2311bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 2312{
17db7042
AD		 2313 u32 srbm_status;
2314 u32 grbm_status;
2315 u32 grbm_status_se0, grbm_status_se1;
17db7042
AD		 2316
2317 srbm_status = RREG32(SRBM_STATUS);
2318 grbm_status = RREG32(GRBM_STATUS);
2319 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2320 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2321 if (!(grbm_status & GUI_ACTIVE)) {
069211e5 2322 radeon_ring_lockup_update(ring);
17db7042
AD		 2323 return false;
2324 }
2325 /* force CP activities */
7b9ef16b 2326 radeon_ring_force_activity(rdev, ring);
069211e5 2327 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 2328}
2329
187e3593 2330void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
bcc1c2a1 2331{
64c56e8c 2332 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
747943ea 2333 RREG32(GRBM_STATUS));
64c56e8c 2334 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
747943ea 2335 RREG32(GRBM_STATUS_SE0));
64c56e8c 2336 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
747943ea 2337 RREG32(GRBM_STATUS_SE1));
64c56e8c 2338 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
747943ea 2339 RREG32(SRBM_STATUS));
a65a4369
AD		 2340 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n",
2341 RREG32(SRBM_STATUS2));
440a7cd8
JG		 2342 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2343 RREG32(CP_STALLED_STAT1));
2344 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2345 RREG32(CP_STALLED_STAT2));
2346 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2347 RREG32(CP_BUSY_STAT));
2348 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2349 RREG32(CP_STAT));
eaaa6983
JG		 2350 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2351 RREG32(DMA_STATUS_REG));
0ecebb9e
AD		 2352}
2353
a65a4369 2354static bool evergreen_is_display_hung(struct radeon_device *rdev)
0ecebb9e 2355{
a65a4369
AD		 2356 u32 crtc_hung = 0;
2357 u32 crtc_status[6];
2358 u32 i, j, tmp;
2359
2360 for (i = 0; i < rdev->num_crtc; i++) {
2361 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
2362 crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2363 crtc_hung |= (1 << i);
2364 }
2365 }
2366
2367 for (j = 0; j < 10; j++) {
2368 for (i = 0; i < rdev->num_crtc; i++) {
2369 if (crtc_hung & (1 << i)) {
2370 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2371 if (tmp != crtc_status[i])
2372 crtc_hung &= ~(1 << i);
2373 }
2374 }
2375 if (crtc_hung == 0)
2376 return false;
2377 udelay(100);
2378 }
2379
2380 return true;
2381}
2382
2383static u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
2384{
2385 u32 reset_mask = 0;
b7630473 2386 u32 tmp;
0ecebb9e 2387
a65a4369
AD		 2388 /* GRBM_STATUS */
2389 tmp = RREG32(GRBM_STATUS);
2390 if (tmp & (PA_BUSY | SC_BUSY |
2391 SH_BUSY | SX_BUSY |
2392 TA_BUSY | VGT_BUSY |
2393 DB_BUSY | CB_BUSY |
2394 SPI_BUSY | VGT_BUSY_NO_DMA))
2395 reset_mask |= RADEON_RESET_GFX;
2396
2397 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2398 CP_BUSY | CP_COHERENCY_BUSY))
2399 reset_mask |= RADEON_RESET_CP;
2400
2401 if (tmp & GRBM_EE_BUSY)
2402 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
19fc42ed 2403
a65a4369
AD		 2404 /* DMA_STATUS_REG */
2405 tmp = RREG32(DMA_STATUS_REG);
2406 if (!(tmp & DMA_IDLE))
2407 reset_mask |= RADEON_RESET_DMA;
2408
2409 /* SRBM_STATUS2 */
2410 tmp = RREG32(SRBM_STATUS2);
2411 if (tmp & DMA_BUSY)
2412 reset_mask |= RADEON_RESET_DMA;
2413
2414 /* SRBM_STATUS */
2415 tmp = RREG32(SRBM_STATUS);
2416 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2417 reset_mask |= RADEON_RESET_RLC;
2418
2419 if (tmp & IH_BUSY)
2420 reset_mask |= RADEON_RESET_IH;
2421
2422 if (tmp & SEM_BUSY)
2423 reset_mask |= RADEON_RESET_SEM;
2424
2425 if (tmp & GRBM_RQ_PENDING)
2426 reset_mask |= RADEON_RESET_GRBM;
2427
2428 if (tmp & VMC_BUSY)
2429 reset_mask |= RADEON_RESET_VMC;
2430
2431 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2432 MCC_BUSY | MCD_BUSY))
2433 reset_mask |= RADEON_RESET_MC;
2434
2435 if (evergreen_is_display_hung(rdev))
2436 reset_mask |= RADEON_RESET_DISPLAY;
2437
2438 /* VM_L2_STATUS */
2439 tmp = RREG32(VM_L2_STATUS);
2440 if (tmp & L2_BUSY)
2441 reset_mask |= RADEON_RESET_VMC;
2442
2443 return reset_mask;
2444}
2445
2446static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2447{
2448 struct evergreen_mc_save save;
2449 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2450 u32 tmp;
19fc42ed 2451
0ecebb9e 2452 if (reset_mask == 0)
a65a4369 2453 return;
0ecebb9e
AD		 2454
2455 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2456
b7630473
AD		 2457 evergreen_print_gpu_status_regs(rdev);
2458
0ecebb9e
AD		 2459 evergreen_mc_stop(rdev, &save);
2460 if (evergreen_mc_wait_for_idle(rdev)) {
2461 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2462 }
2463
b7630473
AD		 2464 /* Disable CP parsing/prefetching */
2465 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2466
2467 if (reset_mask & RADEON_RESET_DMA) {
2468 /* Disable DMA */
2469 tmp = RREG32(DMA_RB_CNTL);
2470 tmp &= ~DMA_RB_ENABLE;
2471 WREG32(DMA_RB_CNTL, tmp);
2472 }
2473
2474 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
2475 grbm_soft_reset |= SOFT_RESET_DB |
2476 SOFT_RESET_CB |
2477 SOFT_RESET_PA |
2478 SOFT_RESET_SC |
2479 SOFT_RESET_SPI |
2480 SOFT_RESET_SX |
2481 SOFT_RESET_SH |
2482 SOFT_RESET_TC |
2483 SOFT_RESET_TA |
2484 SOFT_RESET_VC |
2485 SOFT_RESET_VGT;
2486 }
2487
2488 if (reset_mask & RADEON_RESET_CP) {
2489 grbm_soft_reset |= SOFT_RESET_CP |
2490 SOFT_RESET_VGT;
2491
2492 srbm_soft_reset |= SOFT_RESET_GRBM;
2493 }
0ecebb9e
AD		 2494
2495 if (reset_mask & RADEON_RESET_DMA)
b7630473
AD		 2496 srbm_soft_reset |= SOFT_RESET_DMA;
2497
a65a4369
AD		 2498 if (reset_mask & RADEON_RESET_DISPLAY)
2499 srbm_soft_reset |= SOFT_RESET_DC;
2500
2501 if (reset_mask & RADEON_RESET_RLC)
2502 srbm_soft_reset |= SOFT_RESET_RLC;
2503
2504 if (reset_mask & RADEON_RESET_SEM)
2505 srbm_soft_reset |= SOFT_RESET_SEM;
2506
2507 if (reset_mask & RADEON_RESET_IH)
2508 srbm_soft_reset |= SOFT_RESET_IH;
2509
2510 if (reset_mask & RADEON_RESET_GRBM)
2511 srbm_soft_reset |= SOFT_RESET_GRBM;
2512
2513 if (reset_mask & RADEON_RESET_VMC)
2514 srbm_soft_reset |= SOFT_RESET_VMC;
2515
2516 if (reset_mask & RADEON_RESET_MC)
2517 srbm_soft_reset |= SOFT_RESET_MC;
2518
b7630473
AD		 2519 if (grbm_soft_reset) {
2520 tmp = RREG32(GRBM_SOFT_RESET);
2521 tmp |= grbm_soft_reset;
2522 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2523 WREG32(GRBM_SOFT_RESET, tmp);
2524 tmp = RREG32(GRBM_SOFT_RESET);
2525
2526 udelay(50);
2527
2528 tmp &= ~grbm_soft_reset;
2529 WREG32(GRBM_SOFT_RESET, tmp);
2530 tmp = RREG32(GRBM_SOFT_RESET);
2531 }
2532
2533 if (srbm_soft_reset) {
2534 tmp = RREG32(SRBM_SOFT_RESET);
2535 tmp |= srbm_soft_reset;
2536 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2537 WREG32(SRBM_SOFT_RESET, tmp);
2538 tmp = RREG32(SRBM_SOFT_RESET);
2539
2540 udelay(50);
2541
2542 tmp &= ~srbm_soft_reset;
2543 WREG32(SRBM_SOFT_RESET, tmp);
2544 tmp = RREG32(SRBM_SOFT_RESET);
2545 }
0ecebb9e
AD		 2546
2547 /* Wait a little for things to settle down */
2548 udelay(50);
2549
747943ea 2550 evergreen_mc_resume(rdev, &save);
b7630473
AD		 2551 udelay(50);
2552
b7630473 2553 evergreen_print_gpu_status_regs(rdev);
bcc1c2a1
AD		 2554}
2555
a2d07b74 2556int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2557{
a65a4369
AD		 2558 u32 reset_mask;
2559
2560 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2561
2562 if (reset_mask)
2563 r600_set_bios_scratch_engine_hung(rdev, true);
2564
2565 evergreen_gpu_soft_reset(rdev, reset_mask);
2566
2567 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2568
2569 if (!reset_mask)
2570 r600_set_bios_scratch_engine_hung(rdev, false);
2571
2572 return 0;
747943ea
AD		 2573}
2574
45f9a39b
AD		 2575/* Interrupts */
2576
2577u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2578{
46437057 2579 if (crtc >= rdev->num_crtc)
45f9a39b 2580 return 0;
46437057
AD		 2581 else
2582 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
45f9a39b
AD		 2583}
2584
2585void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2586{
2587 u32 tmp;
2588
1b37078b
AD		 2589 if (rdev->family >= CHIP_CAYMAN) {
2590 cayman_cp_int_cntl_setup(rdev, 0,
2591 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2592 cayman_cp_int_cntl_setup(rdev, 1, 0);
2593 cayman_cp_int_cntl_setup(rdev, 2, 0);
f60cbd11
AD		 2594 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2595 WREG32(CAYMAN_DMA1_CNTL, tmp);
1b37078b
AD		 2596 } else
2597 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
233d1ad5
AD		 2598 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2599 WREG32(DMA_CNTL, tmp);
45f9a39b
AD		 2600 WREG32(GRBM_INT_CNTL, 0);
2601 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2602 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2603 if (rdev->num_crtc >= 4) {
18007401
AD		 2604 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2605 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2606 }
2607 if (rdev->num_crtc >= 6) {
18007401
AD		 2608 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2609 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2610 }
45f9a39b
AD		 2611
2612 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2613 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2614 if (rdev->num_crtc >= 4) {
18007401
AD		 2615 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2616 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2617 }
2618 if (rdev->num_crtc >= 6) {
18007401
AD		 2619 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2620 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2621 }
45f9a39b 2622
05b3ef69
AD		 2623 /* only one DAC on DCE6 */
2624 if (!ASIC_IS_DCE6(rdev))
2625 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
45f9a39b
AD		 2626 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2627
2628 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2629 WREG32(DC_HPD1_INT_CONTROL, tmp);
2630 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2631 WREG32(DC_HPD2_INT_CONTROL, tmp);
2632 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2633 WREG32(DC_HPD3_INT_CONTROL, tmp);
2634 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2635 WREG32(DC_HPD4_INT_CONTROL, tmp);
2636 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2637 WREG32(DC_HPD5_INT_CONTROL, tmp);
2638 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2639 WREG32(DC_HPD6_INT_CONTROL, tmp);
2640
2641}
2642
2643int evergreen_irq_set(struct radeon_device *rdev)
2644{
2645 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1b37078b 2646 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
45f9a39b
AD		 2647 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2648 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2649 u32 grbm_int_cntl = 0;
6f34be50 2650 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
f122c610 2651 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
f60cbd11 2652 u32 dma_cntl, dma_cntl1 = 0;
45f9a39b
AD		 2653
2654 if (!rdev->irq.installed) {
fce7d61b 2655 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2656 return -EINVAL;
2657 }
2658 /* don't enable anything if the ih is disabled */
2659 if (!rdev->ih.enabled) {
2660 r600_disable_interrupts(rdev);
2661 /* force the active interrupt state to all disabled */
2662 evergreen_disable_interrupt_state(rdev);
2663 return 0;
2664 }
2665
2666 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2667 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2668 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2669 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2670 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2671 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2672
f122c610
AD		 2673 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2674 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2675 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2676 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2677 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2678 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2679
233d1ad5
AD		 2680 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2681
1b37078b
AD		 2682 if (rdev->family >= CHIP_CAYMAN) {
2683 /* enable CP interrupts on all rings */
736fc37f 2684 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 2685 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2686 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2687 }
736fc37f 2688 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
1b37078b
AD		 2689 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2690 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2691 }
736fc37f 2692 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
1b37078b
AD		 2693 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2694 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2695 }
2696 } else {
736fc37f 2697 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 2698 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2699 cp_int_cntl |= RB_INT_ENABLE;
2700 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2701 }
45f9a39b 2702 }
1b37078b 2703
233d1ad5
AD		 2704 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
2705 DRM_DEBUG("r600_irq_set: sw int dma\n");
2706 dma_cntl |= TRAP_ENABLE;
2707 }
2708
f60cbd11
AD		 2709 if (rdev->family >= CHIP_CAYMAN) {
2710 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2711 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
2712 DRM_DEBUG("r600_irq_set: sw int dma1\n");
2713 dma_cntl1 |= TRAP_ENABLE;
2714 }
2715 }
2716
6f34be50 2717 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 2718 atomic_read(&rdev->irq.pflip[0])) {
45f9a39b
AD		 2719 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2720 crtc1 |= VBLANK_INT_MASK;
2721 }
6f34be50 2722 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 2723 atomic_read(&rdev->irq.pflip[1])) {
45f9a39b
AD		 2724 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2725 crtc2 |= VBLANK_INT_MASK;
2726 }
6f34be50 2727 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 2728 atomic_read(&rdev->irq.pflip[2])) {
45f9a39b
AD		 2729 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2730 crtc3 |= VBLANK_INT_MASK;
2731 }
6f34be50 2732 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 2733 atomic_read(&rdev->irq.pflip[3])) {
45f9a39b
AD		 2734 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2735 crtc4 |= VBLANK_INT_MASK;
2736 }
6f34be50 2737 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 2738 atomic_read(&rdev->irq.pflip[4])) {
45f9a39b
AD		 2739 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2740 crtc5 |= VBLANK_INT_MASK;
2741 }
6f34be50 2742 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 2743 atomic_read(&rdev->irq.pflip[5])) {
45f9a39b
AD		 2744 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2745 crtc6 |= VBLANK_INT_MASK;
2746 }
2747 if (rdev->irq.hpd[0]) {
2748 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2749 hpd1 |= DC_HPDx_INT_EN;
2750 }
2751 if (rdev->irq.hpd[1]) {
2752 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2753 hpd2 |= DC_HPDx_INT_EN;
2754 }
2755 if (rdev->irq.hpd[2]) {
2756 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2757 hpd3 |= DC_HPDx_INT_EN;
2758 }
2759 if (rdev->irq.hpd[3]) {
2760 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2761 hpd4 |= DC_HPDx_INT_EN;
2762 }
2763 if (rdev->irq.hpd[4]) {
2764 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2765 hpd5 |= DC_HPDx_INT_EN;
2766 }
2767 if (rdev->irq.hpd[5]) {
2768 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2769 hpd6 |= DC_HPDx_INT_EN;
2770 }
f122c610
AD		 2771 if (rdev->irq.afmt[0]) {
2772 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2773 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2774 }
2775 if (rdev->irq.afmt[1]) {
2776 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2777 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2778 }
2779 if (rdev->irq.afmt[2]) {
2780 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2781 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2782 }
2783 if (rdev->irq.afmt[3]) {
2784 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2785 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2786 }
2787 if (rdev->irq.afmt[4]) {
2788 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2789 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2790 }
2791 if (rdev->irq.afmt[5]) {
2792 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2793 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2794 }
45f9a39b 2795
1b37078b
AD		 2796 if (rdev->family >= CHIP_CAYMAN) {
2797 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2798 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2799 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2800 } else
2801 WREG32(CP_INT_CNTL, cp_int_cntl);
233d1ad5
AD		 2802
2803 WREG32(DMA_CNTL, dma_cntl);
2804
f60cbd11
AD		 2805 if (rdev->family >= CHIP_CAYMAN)
2806 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
2807
2031f77c 2808 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2809
2810 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2811 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
b7eff394 2812 if (rdev->num_crtc >= 4) {
18007401
AD		 2813 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2814 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
b7eff394
AD		 2815 }
2816 if (rdev->num_crtc >= 6) {
18007401
AD		 2817 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2818 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2819 }
45f9a39b 2820
6f34be50
AD		 2821 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2822 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
b7eff394
AD		 2823 if (rdev->num_crtc >= 4) {
2824 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2825 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2826 }
2827 if (rdev->num_crtc >= 6) {
2828 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2829 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2830 }
6f34be50 2831
45f9a39b
AD		 2832 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2833 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2834 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2835 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2836 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2837 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2838
f122c610
AD		 2839 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2840 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2841 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2842 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2843 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2844 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2845
bcc1c2a1
AD		 2846 return 0;
2847}
2848
cbdd4501 2849static void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2850{
2851 u32 tmp;
2852
6f34be50
AD		 2853 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2854 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2855 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2856 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2857 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2858 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2859 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2860 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 2861 if (rdev->num_crtc >= 4) {
2862 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2863 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2864 }
2865 if (rdev->num_crtc >= 6) {
2866 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2867 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2868 }
6f34be50 2869
f122c610
AD		 2870 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2871 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2872 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2873 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2874 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2875 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2876
6f34be50
AD		 2877 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2878 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2879 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2880 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6f34be50 2881 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2882 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2883 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b 2884 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6f34be50 2885 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2886 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2887 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2888 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2889
b7eff394
AD		 2890 if (rdev->num_crtc >= 4) {
2891 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2892 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2893 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2894 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2895 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2896 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2897 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2898 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2899 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2900 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2901 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2902 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2903 }
2904
2905 if (rdev->num_crtc >= 6) {
2906 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2907 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2908 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2909 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2910 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2911 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2912 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2913 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2914 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2915 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2916 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2917 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2918 }
45f9a39b 2919
6f34be50 2920 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2921 tmp = RREG32(DC_HPD1_INT_CONTROL);
2922 tmp |= DC_HPDx_INT_ACK;
2923 WREG32(DC_HPD1_INT_CONTROL, tmp);
2924 }
6f34be50 2925 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2926 tmp = RREG32(DC_HPD2_INT_CONTROL);
2927 tmp |= DC_HPDx_INT_ACK;
2928 WREG32(DC_HPD2_INT_CONTROL, tmp);
2929 }
6f34be50 2930 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2931 tmp = RREG32(DC_HPD3_INT_CONTROL);
2932 tmp |= DC_HPDx_INT_ACK;
2933 WREG32(DC_HPD3_INT_CONTROL, tmp);
2934 }
6f34be50 2935 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2936 tmp = RREG32(DC_HPD4_INT_CONTROL);
2937 tmp |= DC_HPDx_INT_ACK;
2938 WREG32(DC_HPD4_INT_CONTROL, tmp);
2939 }
6f34be50 2940 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2941 tmp = RREG32(DC_HPD5_INT_CONTROL);
2942 tmp |= DC_HPDx_INT_ACK;
2943 WREG32(DC_HPD5_INT_CONTROL, tmp);
2944 }
6f34be50 2945 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2946 tmp = RREG32(DC_HPD5_INT_CONTROL);
2947 tmp |= DC_HPDx_INT_ACK;
2948 WREG32(DC_HPD6_INT_CONTROL, tmp);
2949 }
f122c610
AD		 2950 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2951 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2952 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2953 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2954 }
2955 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2956 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2957 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2958 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2959 }
2960 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2961 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2962 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2963 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2964 }
2965 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2966 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2967 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2968 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2969 }
2970 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2971 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2972 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2973 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2974 }
2975 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2976 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2977 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2978 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2979 }
45f9a39b
AD		 2980}
2981
1109ca09 2982static void evergreen_irq_disable(struct radeon_device *rdev)
45f9a39b 2983{
45f9a39b
AD		 2984 r600_disable_interrupts(rdev);
2985 /* Wait and acknowledge irq */
2986 mdelay(1);
6f34be50 2987 evergreen_irq_ack(rdev);
45f9a39b
AD		 2988 evergreen_disable_interrupt_state(rdev);
2989}
2990
755d819e 2991void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 2992{
2993 evergreen_irq_disable(rdev);
2994 r600_rlc_stop(rdev);
2995}
2996
cbdd4501 2997static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
45f9a39b
AD		 2998{
2999 u32 wptr, tmp;
3000
724c80e1 3001 if (rdev->wb.enabled)
204ae24d 3002 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3003 else
3004 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 3005
3006 if (wptr & RB_OVERFLOW) {
3007 /* When a ring buffer overflow happen start parsing interrupt
3008 * from the last not overwritten vector (wptr + 16). Hopefully
3009 * this should allow us to catchup.
3010 */
3011 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3012 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3013 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3014 tmp = RREG32(IH_RB_CNTL);
3015 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3016 WREG32(IH_RB_CNTL, tmp);
3017 }
3018 return (wptr & rdev->ih.ptr_mask);
3019}
3020
3021int evergreen_irq_process(struct radeon_device *rdev)
3022{
682f1a54
DA		 3023 u32 wptr;
3024 u32 rptr;
45f9a39b
AD		 3025 u32 src_id, src_data;
3026 u32 ring_index;
45f9a39b 3027 bool queue_hotplug = false;
f122c610 3028 bool queue_hdmi = false;
45f9a39b 3029
682f1a54 3030 if (!rdev->ih.enabled || rdev->shutdown)
45f9a39b
AD		 3031 return IRQ_NONE;
3032
682f1a54 3033 wptr = evergreen_get_ih_wptr(rdev);
c20dc369
CK		 3034
3035restart_ih:
3036 /* is somebody else already processing irqs? */
3037 if (atomic_xchg(&rdev->ih.lock, 1))
3038 return IRQ_NONE;
3039
682f1a54
DA		 3040 rptr = rdev->ih.rptr;
3041 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
45f9a39b 3042
964f6645
BH		 3043 /* Order reading of wptr vs. reading of IH ring data */
3044 rmb();
3045
45f9a39b 3046 /* display interrupts */
6f34be50 3047 evergreen_irq_ack(rdev);
45f9a39b 3048
45f9a39b
AD		 3049 while (rptr != wptr) {
3050 /* wptr/rptr are in bytes! */
3051 ring_index = rptr / 4;
0f234f5f
AD		 3052 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3053 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 3054
3055 switch (src_id) {
3056 case 1: /* D1 vblank/vline */
3057 switch (src_data) {
3058 case 0: /* D1 vblank */
6f34be50 3059 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3060 if (rdev->irq.crtc_vblank_int[0]) {
3061 drm_handle_vblank(rdev->ddev, 0);
3062 rdev->pm.vblank_sync = true;
3063 wake_up(&rdev->irq.vblank_queue);
3064 }
736fc37f 3065 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 3066 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3067 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 3068 DRM_DEBUG("IH: D1 vblank\n");
3069 }
3070 break;
3071 case 1: /* D1 vline */
6f34be50
AD		 3072 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3073 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 3074 DRM_DEBUG("IH: D1 vline\n");
3075 }
3076 break;
3077 default:
3078 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3079 break;
3080 }
3081 break;
3082 case 2: /* D2 vblank/vline */
3083 switch (src_data) {
3084 case 0: /* D2 vblank */
6f34be50 3085 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3086 if (rdev->irq.crtc_vblank_int[1]) {
3087 drm_handle_vblank(rdev->ddev, 1);
3088 rdev->pm.vblank_sync = true;
3089 wake_up(&rdev->irq.vblank_queue);
3090 }
736fc37f 3091 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 3092 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3093 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 3094 DRM_DEBUG("IH: D2 vblank\n");
3095 }
3096 break;
3097 case 1: /* D2 vline */
6f34be50
AD		 3098 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3099 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 3100 DRM_DEBUG("IH: D2 vline\n");
3101 }
3102 break;
3103 default:
3104 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3105 break;
3106 }
3107 break;
3108 case 3: /* D3 vblank/vline */
3109 switch (src_data) {
3110 case 0: /* D3 vblank */
6f34be50
AD		 3111 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3112 if (rdev->irq.crtc_vblank_int[2]) {
3113 drm_handle_vblank(rdev->ddev, 2);
3114 rdev->pm.vblank_sync = true;
3115 wake_up(&rdev->irq.vblank_queue);
3116 }
736fc37f 3117 if (atomic_read(&rdev->irq.pflip[2]))
6f34be50
AD		 3118 radeon_crtc_handle_flip(rdev, 2);
3119 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 3120 DRM_DEBUG("IH: D3 vblank\n");
3121 }
3122 break;
3123 case 1: /* D3 vline */
6f34be50
AD		 3124 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3125 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 3126 DRM_DEBUG("IH: D3 vline\n");
3127 }
3128 break;
3129 default:
3130 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3131 break;
3132 }
3133 break;
3134 case 4: /* D4 vblank/vline */
3135 switch (src_data) {
3136 case 0: /* D4 vblank */
6f34be50
AD		 3137 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3138 if (rdev->irq.crtc_vblank_int[3]) {
3139 drm_handle_vblank(rdev->ddev, 3);
3140 rdev->pm.vblank_sync = true;
3141 wake_up(&rdev->irq.vblank_queue);
3142 }
736fc37f 3143 if (atomic_read(&rdev->irq.pflip[3]))
6f34be50
AD		 3144 radeon_crtc_handle_flip(rdev, 3);
3145 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 3146 DRM_DEBUG("IH: D4 vblank\n");
3147 }
3148 break;
3149 case 1: /* D4 vline */
6f34be50
AD		 3150 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3151 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 3152 DRM_DEBUG("IH: D4 vline\n");
3153 }
3154 break;
3155 default:
3156 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3157 break;
3158 }
3159 break;
3160 case 5: /* D5 vblank/vline */
3161 switch (src_data) {
3162 case 0: /* D5 vblank */
6f34be50
AD		 3163 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3164 if (rdev->irq.crtc_vblank_int[4]) {
3165 drm_handle_vblank(rdev->ddev, 4);
3166 rdev->pm.vblank_sync = true;
3167 wake_up(&rdev->irq.vblank_queue);
3168 }
736fc37f 3169 if (atomic_read(&rdev->irq.pflip[4]))
6f34be50
AD		 3170 radeon_crtc_handle_flip(rdev, 4);
3171 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 3172 DRM_DEBUG("IH: D5 vblank\n");
3173 }
3174 break;
3175 case 1: /* D5 vline */
6f34be50
AD		 3176 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3177 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 3178 DRM_DEBUG("IH: D5 vline\n");
3179 }
3180 break;
3181 default:
3182 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3183 break;
3184 }
3185 break;
3186 case 6: /* D6 vblank/vline */
3187 switch (src_data) {
3188 case 0: /* D6 vblank */
6f34be50
AD		 3189 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3190 if (rdev->irq.crtc_vblank_int[5]) {
3191 drm_handle_vblank(rdev->ddev, 5);
3192 rdev->pm.vblank_sync = true;
3193 wake_up(&rdev->irq.vblank_queue);
3194 }
736fc37f 3195 if (atomic_read(&rdev->irq.pflip[5]))
6f34be50
AD		 3196 radeon_crtc_handle_flip(rdev, 5);
3197 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 3198 DRM_DEBUG("IH: D6 vblank\n");
3199 }
3200 break;
3201 case 1: /* D6 vline */
6f34be50
AD		 3202 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3203 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 3204 DRM_DEBUG("IH: D6 vline\n");
3205 }
3206 break;
3207 default:
3208 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3209 break;
3210 }
3211 break;
3212 case 42: /* HPD hotplug */
3213 switch (src_data) {
3214 case 0:
6f34be50
AD		 3215 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3216 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 3217 queue_hotplug = true;
3218 DRM_DEBUG("IH: HPD1\n");
3219 }
3220 break;
3221 case 1:
6f34be50
AD		 3222 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3223 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 3224 queue_hotplug = true;
3225 DRM_DEBUG("IH: HPD2\n");
3226 }
3227 break;
3228 case 2:
6f34be50
AD		 3229 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3230 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 3231 queue_hotplug = true;
3232 DRM_DEBUG("IH: HPD3\n");
3233 }
3234 break;
3235 case 3:
6f34be50
AD		 3236 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3237 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 3238 queue_hotplug = true;
3239 DRM_DEBUG("IH: HPD4\n");
3240 }
3241 break;
3242 case 4:
6f34be50
AD		 3243 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3244 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 3245 queue_hotplug = true;
3246 DRM_DEBUG("IH: HPD5\n");
3247 }
3248 break;
3249 case 5:
6f34be50
AD		 3250 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3251 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 3252 queue_hotplug = true;
3253 DRM_DEBUG("IH: HPD6\n");
3254 }
3255 break;
3256 default:
3257 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3258 break;
3259 }
3260 break;
f122c610
AD		 3261 case 44: /* hdmi */
3262 switch (src_data) {
3263 case 0:
3264 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3265 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3266 queue_hdmi = true;
3267 DRM_DEBUG("IH: HDMI0\n");
3268 }
3269 break;
3270 case 1:
3271 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3272 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3273 queue_hdmi = true;
3274 DRM_DEBUG("IH: HDMI1\n");
3275 }
3276 break;
3277 case 2:
3278 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3279 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3280 queue_hdmi = true;
3281 DRM_DEBUG("IH: HDMI2\n");
3282 }
3283 break;
3284 case 3:
3285 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3286 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3287 queue_hdmi = true;
3288 DRM_DEBUG("IH: HDMI3\n");
3289 }
3290 break;
3291 case 4:
3292 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3293 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3294 queue_hdmi = true;
3295 DRM_DEBUG("IH: HDMI4\n");
3296 }
3297 break;
3298 case 5:
3299 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3300 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3301 queue_hdmi = true;
3302 DRM_DEBUG("IH: HDMI5\n");
3303 }
3304 break;
3305 default:
3306 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3307 break;
3308 }
3309 break;
ae133a11
CK		 3310 case 146:
3311 case 147:
3312 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3313 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3314 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3315 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3316 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3317 /* reset addr and status */
3318 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3319 break;
45f9a39b
AD		 3320 case 176: /* CP_INT in ring buffer */
3321 case 177: /* CP_INT in IB1 */
3322 case 178: /* CP_INT in IB2 */
3323 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3324 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b
AD		 3325 break;
3326 case 181: /* CP EOP event */
3327 DRM_DEBUG("IH: CP EOP\n");
1b37078b
AD		 3328 if (rdev->family >= CHIP_CAYMAN) {
3329 switch (src_data) {
3330 case 0:
3331 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3332 break;
3333 case 1:
3334 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3335 break;
3336 case 2:
3337 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3338 break;
3339 }
3340 } else
3341 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b 3342 break;
233d1ad5
AD		 3343 case 224: /* DMA trap event */
3344 DRM_DEBUG("IH: DMA trap\n");
3345 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3346 break;
2031f77c 3347 case 233: /* GUI IDLE */
303c805c 3348 DRM_DEBUG("IH: GUI idle\n");
2031f77c 3349 break;
f60cbd11
AD		 3350 case 244: /* DMA trap event */
3351 if (rdev->family >= CHIP_CAYMAN) {
3352 DRM_DEBUG("IH: DMA1 trap\n");
3353 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
3354 }
3355 break;
45f9a39b
AD		 3356 default:
3357 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3358 break;
3359 }
3360
3361 /* wptr/rptr are in bytes! */
3362 rptr += 16;
3363 rptr &= rdev->ih.ptr_mask;
3364 }
45f9a39b 3365 if (queue_hotplug)
32c87fca 3366 schedule_work(&rdev->hotplug_work);
f122c610
AD		 3367 if (queue_hdmi)
3368 schedule_work(&rdev->audio_work);
45f9a39b
AD		 3369 rdev->ih.rptr = rptr;
3370 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 3371 atomic_set(&rdev->ih.lock, 0);
3372
3373 /* make sure wptr hasn't changed while processing */
3374 wptr = evergreen_get_ih_wptr(rdev);
3375 if (wptr != rptr)
3376 goto restart_ih;
3377
45f9a39b
AD		 3378 return IRQ_HANDLED;
3379}
3380
233d1ad5
AD		 3381/**
3382 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
3383 *
3384 * @rdev: radeon_device pointer
3385 * @fence: radeon fence object
3386 *
3387 * Add a DMA fence packet to the ring to write
3388 * the fence seq number and DMA trap packet to generate
3389 * an interrupt if needed (evergreen-SI).
3390 */
3391void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
3392 struct radeon_fence *fence)
3393{
3394 struct radeon_ring *ring = &rdev->ring[fence->ring];
3395 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3396 /* write the fence */
0fcb6155 3397 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
233d1ad5
AD		 3398 radeon_ring_write(ring, addr & 0xfffffffc);
3399 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3400 radeon_ring_write(ring, fence->seq);
3401 /* generate an interrupt */
0fcb6155 3402 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
233d1ad5 3403 /* flush HDP */
0fcb6155 3404 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
4b681c28 3405 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
233d1ad5
AD		 3406 radeon_ring_write(ring, 1);
3407}
3408
3409/**
3410 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
3411 *
3412 * @rdev: radeon_device pointer
3413 * @ib: IB object to schedule
3414 *
3415 * Schedule an IB in the DMA ring (evergreen).
3416 */
3417void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
3418 struct radeon_ib *ib)
3419{
3420 struct radeon_ring *ring = &rdev->ring[ib->ring];
3421
3422 if (rdev->wb.enabled) {
3423 u32 next_rptr = ring->wptr + 4;
3424 while ((next_rptr & 7) != 5)
3425 next_rptr++;
3426 next_rptr += 3;
0fcb6155 3427 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
233d1ad5
AD		 3428 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3429 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3430 radeon_ring_write(ring, next_rptr);
3431 }
3432
3433 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3434 * Pad as necessary with NOPs.
3435 */
3436 while ((ring->wptr & 7) != 5)
0fcb6155
JG		 3437 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
3438 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
233d1ad5
AD		 3439 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3440 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3441
3442}
3443
3444/**
3445 * evergreen_copy_dma - copy pages using the DMA engine
3446 *
3447 * @rdev: radeon_device pointer
3448 * @src_offset: src GPU address
3449 * @dst_offset: dst GPU address
3450 * @num_gpu_pages: number of GPU pages to xfer
3451 * @fence: radeon fence object
3452 *
3453 * Copy GPU paging using the DMA engine (evergreen-cayman).
3454 * Used by the radeon ttm implementation to move pages if
3455 * registered as the asic copy callback.
3456 */
3457int evergreen_copy_dma(struct radeon_device *rdev,
3458 uint64_t src_offset, uint64_t dst_offset,
3459 unsigned num_gpu_pages,
3460 struct radeon_fence **fence)
3461{
3462 struct radeon_semaphore *sem = NULL;
3463 int ring_index = rdev->asic->copy.dma_ring_index;
3464 struct radeon_ring *ring = &rdev->ring[ring_index];
3465 u32 size_in_dw, cur_size_in_dw;
3466 int i, num_loops;
3467 int r = 0;
3468
3469 r = radeon_semaphore_create(rdev, &sem);
3470 if (r) {
3471 DRM_ERROR("radeon: moving bo (%d).\n", r);
3472 return r;
3473 }
3474
3475 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3476 num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
3477 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
3478 if (r) {
3479 DRM_ERROR("radeon: moving bo (%d).\n", r);
3480 radeon_semaphore_free(rdev, &sem, NULL);
3481 return r;
3482 }
3483
3484 if (radeon_fence_need_sync(*fence, ring->idx)) {
3485 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3486 ring->idx);
3487 radeon_fence_note_sync(*fence, ring->idx);
3488 } else {
3489 radeon_semaphore_free(rdev, &sem, NULL);
3490 }
3491
3492 for (i = 0; i < num_loops; i++) {
3493 cur_size_in_dw = size_in_dw;
3494 if (cur_size_in_dw > 0xFFFFF)
3495 cur_size_in_dw = 0xFFFFF;
3496 size_in_dw -= cur_size_in_dw;
0fcb6155 3497 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
233d1ad5
AD		 3498 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3499 radeon_ring_write(ring, src_offset & 0xfffffffc);
3500 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3501 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
3502 src_offset += cur_size_in_dw * 4;
3503 dst_offset += cur_size_in_dw * 4;
3504 }
3505
3506 r = radeon_fence_emit(rdev, fence, ring->idx);
3507 if (r) {
3508 radeon_ring_unlock_undo(rdev, ring);
3509 return r;
3510 }
3511
3512 radeon_ring_unlock_commit(rdev, ring);
3513 radeon_semaphore_free(rdev, &sem, *fence);
3514
3515 return r;
3516}
3517
bcc1c2a1
AD		 3518static int evergreen_startup(struct radeon_device *rdev)
3519{
e32eb50d 3520 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
bcc1c2a1
AD		 3521 int r;
3522
9e46a48d 3523 /* enable pcie gen2 link */
cd54033a 3524 evergreen_pcie_gen2_enable(rdev);
9e46a48d 3525
0af62b01
AD		 3526 if (ASIC_IS_DCE5(rdev)) {
3527 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3528 r = ni_init_microcode(rdev);
3529 if (r) {
3530 DRM_ERROR("Failed to load firmware!\n");
3531 return r;
3532 }
3533 }
755d819e 3534 r = ni_mc_load_microcode(rdev);
bcc1c2a1 3535 if (r) {
0af62b01 3536 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 3537 return r;
3538 }
0af62b01
AD		 3539 } else {
3540 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3541 r = r600_init_microcode(rdev);
3542 if (r) {
3543 DRM_ERROR("Failed to load firmware!\n");
3544 return r;
3545 }
3546 }
bcc1c2a1 3547 }
fe251e2f 3548
16cdf04d
AD		 3549 r = r600_vram_scratch_init(rdev);
3550 if (r)
3551 return r;
3552
bcc1c2a1 3553 evergreen_mc_program(rdev);
bcc1c2a1 3554 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 3555 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 3556 } else {
3557 r = evergreen_pcie_gart_enable(rdev);
3558 if (r)
3559 return r;
3560 }
bcc1c2a1 3561 evergreen_gpu_init(rdev);
bcc1c2a1 3562
d7ccd8fc 3563 r = evergreen_blit_init(rdev);
bcc1c2a1 3564 if (r) {
fb3d9e97 3565 r600_blit_fini(rdev);
27cd7769 3566 rdev->asic->copy.copy = NULL;
d7ccd8fc 3567 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 3568 }
3569
724c80e1
AD		 3570 /* allocate wb buffer */
3571 r = radeon_wb_init(rdev);
3572 if (r)
3573 return r;
3574
30eb77f4
JG		 3575 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3576 if (r) {
3577 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3578 return r;
3579 }
3580
233d1ad5
AD		 3581 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3582 if (r) {
3583 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3584 return r;
3585 }
3586
bcc1c2a1
AD		 3587 /* Enable IRQ */
3588 r = r600_irq_init(rdev);
3589 if (r) {
3590 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3591 radeon_irq_kms_fini(rdev);
3592 return r;
3593 }
45f9a39b 3594 evergreen_irq_set(rdev);
bcc1c2a1 3595
e32eb50d 3596 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 3597 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3598 0, 0xfffff, RADEON_CP_PACKET2);
bcc1c2a1
AD		 3599 if (r)
3600 return r;
233d1ad5
AD		 3601
3602 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3603 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3604 DMA_RB_RPTR, DMA_RB_WPTR,
0fcb6155 3605 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
233d1ad5
AD		 3606 if (r)
3607 return r;
3608
bcc1c2a1
AD		 3609 r = evergreen_cp_load_microcode(rdev);
3610 if (r)
3611 return r;
fe251e2f 3612 r = evergreen_cp_resume(rdev);
233d1ad5
AD		 3613 if (r)
3614 return r;
3615 r = r600_dma_resume(rdev);
bcc1c2a1
AD		 3616 if (r)
3617 return r;
fe251e2f 3618
2898c348
CK		 3619 r = radeon_ib_pool_init(rdev);
3620 if (r) {
3621 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3622 return r;
2898c348 3623 }
b15ba512 3624
69d2ae57
RM		 3625 r = r600_audio_init(rdev);
3626 if (r) {
3627 DRM_ERROR("radeon: audio init failed\n");
b15ba512
JG		 3628 return r;
3629 }
3630
bcc1c2a1
AD		 3631 return 0;
3632}
3633
3634int evergreen_resume(struct radeon_device *rdev)
3635{
3636 int r;
3637
86f5c9ed
AD		 3638 /* reset the asic, the gfx blocks are often in a bad state
3639 * after the driver is unloaded or after a resume
3640 */
3641 if (radeon_asic_reset(rdev))
3642 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 3643 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3644 * posting will perform necessary task to bring back GPU into good
3645 * shape.
3646 */
3647 /* post card */
3648 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1 3649
b15ba512 3650 rdev->accel_working = true;
bcc1c2a1
AD		 3651 r = evergreen_startup(rdev);
3652 if (r) {
755d819e 3653 DRM_ERROR("evergreen startup failed on resume\n");
6b7746e8 3654 rdev->accel_working = false;
bcc1c2a1
AD		 3655 return r;
3656 }
fe251e2f 3657
bcc1c2a1
AD		 3658 return r;
3659
3660}
3661
3662int evergreen_suspend(struct radeon_device *rdev)
3663{
69d2ae57 3664 r600_audio_fini(rdev);
bcc1c2a1 3665 r700_cp_stop(rdev);
233d1ad5 3666 r600_dma_stop(rdev);
45f9a39b 3667 evergreen_irq_suspend(rdev);
724c80e1 3668 radeon_wb_disable(rdev);
bcc1c2a1 3669 evergreen_pcie_gart_disable(rdev);
d7ccd8fc
AD		 3670
3671 return 0;
3672}
3673
bcc1c2a1
AD		 3674/* Plan is to move initialization in that function and use
3675 * helper function so that radeon_device_init pretty much
3676 * do nothing more than calling asic specific function. This
3677 * should also allow to remove a bunch of callback function
3678 * like vram_info.
3679 */
3680int evergreen_init(struct radeon_device *rdev)
3681{
3682 int r;
3683
bcc1c2a1
AD		 3684 /* Read BIOS */
3685 if (!radeon_get_bios(rdev)) {
3686 if (ASIC_IS_AVIVO(rdev))
3687 return -EINVAL;
3688 }
3689 /* Must be an ATOMBIOS */
3690 if (!rdev->is_atom_bios) {
755d819e 3691 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 3692 return -EINVAL;
3693 }
3694 r = radeon_atombios_init(rdev);
3695 if (r)
3696 return r;
86f5c9ed
AD		 3697 /* reset the asic, the gfx blocks are often in a bad state
3698 * after the driver is unloaded or after a resume
3699 */
3700 if (radeon_asic_reset(rdev))
3701 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 3702 /* Post card if necessary */
fd909c37 3703 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 3704 if (!rdev->bios) {
3705 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3706 return -EINVAL;
3707 }
3708 DRM_INFO("GPU not posted. posting now...\n");
3709 atom_asic_init(rdev->mode_info.atom_context);
3710 }
3711 /* Initialize scratch registers */
3712 r600_scratch_init(rdev);
3713 /* Initialize surface registers */
3714 radeon_surface_init(rdev);
3715 /* Initialize clocks */
3716 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 3717 /* Fence driver */
3718 r = radeon_fence_driver_init(rdev);
3719 if (r)
3720 return r;
d594e46a
JG		 3721 /* initialize AGP */
3722 if (rdev->flags & RADEON_IS_AGP) {
3723 r = radeon_agp_init(rdev);
3724 if (r)
3725 radeon_agp_disable(rdev);
3726 }
3727 /* initialize memory controller */
bcc1c2a1
AD		 3728 r = evergreen_mc_init(rdev);
3729 if (r)
3730 return r;
3731 /* Memory manager */
3732 r = radeon_bo_init(rdev);
3733 if (r)
3734 return r;
45f9a39b 3735
bcc1c2a1
AD		 3736 r = radeon_irq_kms_init(rdev);
3737 if (r)
3738 return r;
3739
e32eb50d
CK		 3740 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3741 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
bcc1c2a1 3742
233d1ad5
AD		 3743 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3744 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3745
bcc1c2a1
AD		 3746 rdev->ih.ring_obj = NULL;
3747 r600_ih_ring_init(rdev, 64 * 1024);
3748
3749 r = r600_pcie_gart_init(rdev);
3750 if (r)
3751 return r;
0fcdb61e 3752
148a03bc 3753 rdev->accel_working = true;
bcc1c2a1
AD		 3754 r = evergreen_startup(rdev);
3755 if (r) {
fe251e2f
AD		 3756 dev_err(rdev->dev, "disabling GPU acceleration\n");
3757 r700_cp_fini(rdev);
233d1ad5 3758 r600_dma_fini(rdev);
fe251e2f 3759 r600_irq_fini(rdev);
724c80e1 3760 radeon_wb_fini(rdev);
2898c348 3761 radeon_ib_pool_fini(rdev);
fe251e2f 3762 radeon_irq_kms_fini(rdev);
0fcdb61e 3763 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3764 rdev->accel_working = false;
3765 }
77e00f2e
AD		 3766
3767 /* Don't start up if the MC ucode is missing on BTC parts.
3768 * The default clocks and voltages before the MC ucode
3769 * is loaded are not suffient for advanced operations.
3770 */
3771 if (ASIC_IS_DCE5(rdev)) {
3772 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3773 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3774 return -EINVAL;
3775 }
3776 }
3777
bcc1c2a1
AD		 3778 return 0;
3779}
3780
3781void evergreen_fini(struct radeon_device *rdev)
3782{
69d2ae57 3783 r600_audio_fini(rdev);
fb3d9e97 3784 r600_blit_fini(rdev);
45f9a39b 3785 r700_cp_fini(rdev);
233d1ad5 3786 r600_dma_fini(rdev);
bcc1c2a1 3787 r600_irq_fini(rdev);
724c80e1 3788 radeon_wb_fini(rdev);
2898c348 3789 radeon_ib_pool_fini(rdev);
bcc1c2a1 3790 radeon_irq_kms_fini(rdev);
bcc1c2a1 3791 evergreen_pcie_gart_fini(rdev);
16cdf04d 3792 r600_vram_scratch_fini(rdev);
bcc1c2a1
AD		 3793 radeon_gem_fini(rdev);
3794 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3795 radeon_agp_fini(rdev);
3796 radeon_bo_fini(rdev);
3797 radeon_atombios_fini(rdev);
3798 kfree(rdev->bios);
3799 rdev->bios = NULL;
bcc1c2a1 3800}
9e46a48d 3801
b07759bf 3802void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
9e46a48d 3803{
197bbb3d
DA		 3804 u32 link_width_cntl, speed_cntl, mask;
3805 int ret;
9e46a48d 3806
d42dd579
AD		 3807 if (radeon_pcie_gen2 == 0)
3808 return;
3809
9e46a48d
AD		 3810 if (rdev->flags & RADEON_IS_IGP)
3811 return;
3812
3813 if (!(rdev->flags & RADEON_IS_PCIE))
3814 return;
3815
3816 /* x2 cards have a special sequence */
3817 if (ASIC_IS_X2(rdev))
3818 return;
3819
197bbb3d
DA		 3820 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3821 if (ret != 0)
3822 return;
3823
3824 if (!(mask & DRM_PCIE_SPEED_50))
3825 return;
3826
3691feea
AD		 3827 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3828 if (speed_cntl & LC_CURRENT_DATA_RATE) {
3829 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3830 return;
3831 }
3832
197bbb3d
DA		 3833 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3834
9e46a48d
AD		 3835 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3836 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3837
3838 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3839 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3840 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3841
3842 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3843 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3844 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3845
3846 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3847 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3848 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3849
3850 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3851 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3852 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3853
3854 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3855 speed_cntl |= LC_GEN2_EN_STRAP;
3856 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3857
3858 } else {
3859 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3860 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3861 if (1)
3862 link_width_cntl |= LC_UPCONFIGURE_DIS;
3863 else
3864 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3865 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3866 }
3867}
kernel source for telekom puls (alcatel/mediatek)