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Merge branch 'timer/cleanup' into late/mvebu2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
760285e7 27#include <drm/drmP.h>
bcc1c2a1 28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
760285e7 30#include <drm/radeon_drm.h>
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
4a15903d
AD		 40static const u32 crtc_offsets[6] =
41{
42 EVERGREEN_CRTC0_REGISTER_OFFSET,
43 EVERGREEN_CRTC1_REGISTER_OFFSET,
44 EVERGREEN_CRTC2_REGISTER_OFFSET,
45 EVERGREEN_CRTC3_REGISTER_OFFSET,
46 EVERGREEN_CRTC4_REGISTER_OFFSET,
47 EVERGREEN_CRTC5_REGISTER_OFFSET
48};
49
bcc1c2a1
AD		 50static void evergreen_gpu_init(struct radeon_device *rdev);
51void evergreen_fini(struct radeon_device *rdev);
b07759bf 52void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
1b37078b
AD		 53extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54 int ring, u32 cp_int_cntl);
bcc1c2a1 55
285484e2
JG		 56void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57 unsigned *bankh, unsigned *mtaspect,
58 unsigned *tile_split)
59{
60 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
61 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
62 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
63 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
64 switch (*bankw) {
65 default:
66 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
67 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
68 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
69 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
70 }
71 switch (*bankh) {
72 default:
73 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
74 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
75 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
76 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
77 }
78 switch (*mtaspect) {
79 default:
80 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
81 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
82 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
83 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
84 }
85}
86
d054ac16
AD		 87void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
88{
89 u16 ctl, v;
32195aec 90 int err;
d054ac16 91
32195aec 92 err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
d054ac16
AD		 93 if (err)
94 return;
95
96 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
97
98 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
99 * to avoid hangs or perfomance issues
100 */
101 if ((v == 0) || (v == 6) || (v == 7)) {
102 ctl &= ~PCI_EXP_DEVCTL_READRQ;
103 ctl |= (2 << 12);
32195aec 104 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
d054ac16
AD		 105 }
106}
107
377edc8b
AD		 108/**
109 * dce4_wait_for_vblank - vblank wait asic callback.
110 *
111 * @rdev: radeon_device pointer
112 * @crtc: crtc to wait for vblank on
113 *
114 * Wait for vblank on the requested crtc (evergreen+).
115 */
3ae19b75
AD		 116void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
117{
3ae19b75
AD		 118 int i;
119
4a15903d
AD		 120 if (crtc >= rdev->num_crtc)
121 return;
122
123 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
3ae19b75 124 for (i = 0; i < rdev->usec_timeout; i++) {
4a15903d 125 if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
3ae19b75
AD		 126 break;
127 udelay(1);
128 }
129 for (i = 0; i < rdev->usec_timeout; i++) {
4a15903d 130 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
3ae19b75
AD		 131 break;
132 udelay(1);
133 }
134 }
135}
136
377edc8b
AD		 137/**
138 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
139 *
140 * @rdev: radeon_device pointer
141 * @crtc: crtc to prepare for pageflip on
142 *
143 * Pre-pageflip callback (evergreen+).
144 * Enables the pageflip irq (vblank irq).
145 */
6f34be50
AD		 146void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
147{
6f34be50
AD		 148 /* enable the pflip int */
149 radeon_irq_kms_pflip_irq_get(rdev, crtc);
150}
151
377edc8b
AD		 152/**
153 * evergreen_post_page_flip - pos-pageflip callback.
154 *
155 * @rdev: radeon_device pointer
156 * @crtc: crtc to cleanup pageflip on
157 *
158 * Post-pageflip callback (evergreen+).
159 * Disables the pageflip irq (vblank irq).
160 */
6f34be50
AD		 161void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
162{
163 /* disable the pflip int */
164 radeon_irq_kms_pflip_irq_put(rdev, crtc);
165}
166
377edc8b
AD		 167/**
168 * evergreen_page_flip - pageflip callback.
169 *
170 * @rdev: radeon_device pointer
171 * @crtc_id: crtc to cleanup pageflip on
172 * @crtc_base: new address of the crtc (GPU MC address)
173 *
174 * Does the actual pageflip (evergreen+).
175 * During vblank we take the crtc lock and wait for the update_pending
176 * bit to go high, when it does, we release the lock, and allow the
177 * double buffered update to take place.
178 * Returns the current update pending status.
179 */
6f34be50
AD		 180u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
181{
182 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
183 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 184 int i;
6f34be50
AD		 185
186 /* Lock the graphics update lock */
187 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
188 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
189
190 /* update the scanout addresses */
191 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
192 upper_32_bits(crtc_base));
193 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
194 (u32)crtc_base);
195
196 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
197 upper_32_bits(crtc_base));
198 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
199 (u32)crtc_base);
200
201 /* Wait for update_pending to go high. */
f6496479
AD		 202 for (i = 0; i < rdev->usec_timeout; i++) {
203 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
204 break;
205 udelay(1);
206 }
6f34be50
AD		 207 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
208
209 /* Unlock the lock, so double-buffering can take place inside vblank */
210 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
211 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
212
213 /* Return current update_pending status: */
214 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
215}
216
21a8122a 217/* get temperature in millidegrees */
20d391d7 218int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 219{
1c88d74f
AD		 220 u32 temp, toffset;
221 int actual_temp = 0;
67b3f823
AD		 222
223 if (rdev->family == CHIP_JUNIPER) {
224 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
225 TOFFSET_SHIFT;
226 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
227 TS0_ADC_DOUT_SHIFT;
228
229 if (toffset & 0x100)
230 actual_temp = temp / 2 - (0x200 - toffset);
231 else
232 actual_temp = temp / 2 + toffset;
233
234 actual_temp = actual_temp * 1000;
235
236 } else {
237 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
238 ASIC_T_SHIFT;
239
240 if (temp & 0x400)
241 actual_temp = -256;
242 else if (temp & 0x200)
243 actual_temp = 255;
244 else if (temp & 0x100) {
245 actual_temp = temp & 0x1ff;
246 actual_temp |= ~0x1ff;
247 } else
248 actual_temp = temp & 0xff;
249
250 actual_temp = (actual_temp * 1000) / 2;
251 }
21a8122a 252
67b3f823 253 return actual_temp;
21a8122a
AD		 254}
255
20d391d7 256int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 257{
258 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 259 int actual_temp = temp - 49;
e33df25f
AD		 260
261 return actual_temp * 1000;
262}
263
377edc8b
AD		 264/**
265 * sumo_pm_init_profile - Initialize power profiles callback.
266 *
267 * @rdev: radeon_device pointer
268 *
269 * Initialize the power states used in profile mode
270 * (sumo, trinity, SI).
271 * Used for profile mode only.
272 */
a4c9e2ee
AD		 273void sumo_pm_init_profile(struct radeon_device *rdev)
274{
275 int idx;
276
277 /* default */
278 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
279 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
280 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
281 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
282
283 /* low,mid sh/mh */
284 if (rdev->flags & RADEON_IS_MOBILITY)
285 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
286 else
287 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
288
289 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
290 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
291 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
292 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
293
294 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
295 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
296 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
298
299 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
300 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
301 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
303
304 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
305 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
306 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
308
309 /* high sh/mh */
310 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
315 rdev->pm.power_state[idx].num_clock_modes - 1;
316
317 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
318 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
319 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
321 rdev->pm.power_state[idx].num_clock_modes - 1;
322}
323
27810fb2
AD		 324/**
325 * btc_pm_init_profile - Initialize power profiles callback.
326 *
327 * @rdev: radeon_device pointer
328 *
329 * Initialize the power states used in profile mode
330 * (BTC, cayman).
331 * Used for profile mode only.
332 */
333void btc_pm_init_profile(struct radeon_device *rdev)
334{
335 int idx;
336
337 /* default */
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
340 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
342 /* starting with BTC, there is one state that is used for both
343 * MH and SH. Difference is that we always use the high clock index for
344 * mclk.
345 */
346 if (rdev->flags & RADEON_IS_MOBILITY)
347 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
348 else
349 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
350 /* low sh */
351 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
352 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
353 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
355 /* mid sh */
356 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
357 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
358 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
359 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
360 /* high sh */
361 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
362 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
363 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
364 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
365 /* low mh */
366 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
367 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
368 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
369 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
370 /* mid mh */
371 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
372 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
373 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
374 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
375 /* high mh */
376 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
377 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
378 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
380}
381
377edc8b
AD		 382/**
383 * evergreen_pm_misc - set additional pm hw parameters callback.
384 *
385 * @rdev: radeon_device pointer
386 *
387 * Set non-clock parameters associated with a power state
388 * (voltage, etc.) (evergreen+).
389 */
49e02b73
AD		 390void evergreen_pm_misc(struct radeon_device *rdev)
391{
a081a9d6
RM		 392 int req_ps_idx = rdev->pm.requested_power_state_index;
393 int req_cm_idx = rdev->pm.requested_clock_mode_index;
394 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
395 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 396
2feea49a 397 if (voltage->type == VOLTAGE_SW) {
a377e187
AD		 398 /* 0xff01 is a flag rather then an actual voltage */
399 if (voltage->voltage == 0xff01)
400 return;
2feea49a 401 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 402 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 403 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 404 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
405 }
a377e187
AD		 406 /* 0xff01 is a flag rather then an actual voltage */
407 if (voltage->vddci == 0xff01)
408 return;
2feea49a
AD		 409 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
410 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
411 rdev->pm.current_vddci = voltage->vddci;
412 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 413 }
414 }
49e02b73
AD		 415}
416
377edc8b
AD		 417/**
418 * evergreen_pm_prepare - pre-power state change callback.
419 *
420 * @rdev: radeon_device pointer
421 *
422 * Prepare for a power state change (evergreen+).
423 */
49e02b73
AD		 424void evergreen_pm_prepare(struct radeon_device *rdev)
425{
426 struct drm_device *ddev = rdev->ddev;
427 struct drm_crtc *crtc;
428 struct radeon_crtc *radeon_crtc;
429 u32 tmp;
430
431 /* disable any active CRTCs */
432 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
433 radeon_crtc = to_radeon_crtc(crtc);
434 if (radeon_crtc->enabled) {
435 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
436 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
437 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
438 }
439 }
440}
441
377edc8b
AD		 442/**
443 * evergreen_pm_finish - post-power state change callback.
444 *
445 * @rdev: radeon_device pointer
446 *
447 * Clean up after a power state change (evergreen+).
448 */
49e02b73
AD		 449void evergreen_pm_finish(struct radeon_device *rdev)
450{
451 struct drm_device *ddev = rdev->ddev;
452 struct drm_crtc *crtc;
453 struct radeon_crtc *radeon_crtc;
454 u32 tmp;
455
456 /* enable any active CRTCs */
457 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
458 radeon_crtc = to_radeon_crtc(crtc);
459 if (radeon_crtc->enabled) {
460 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
461 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
462 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
463 }
464 }
465}
466
377edc8b
AD		 467/**
468 * evergreen_hpd_sense - hpd sense callback.
469 *
470 * @rdev: radeon_device pointer
471 * @hpd: hpd (hotplug detect) pin
472 *
473 * Checks if a digital monitor is connected (evergreen+).
474 * Returns true if connected, false if not connected.
475 */
bcc1c2a1
AD		 476bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
477{
478 bool connected = false;
0ca2ab52
AD		 479
480 switch (hpd) {
481 case RADEON_HPD_1:
482 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
483 connected = true;
484 break;
485 case RADEON_HPD_2:
486 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
487 connected = true;
488 break;
489 case RADEON_HPD_3:
490 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
491 connected = true;
492 break;
493 case RADEON_HPD_4:
494 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
495 connected = true;
496 break;
497 case RADEON_HPD_5:
498 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
499 connected = true;
500 break;
501 case RADEON_HPD_6:
502 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
503 connected = true;
504 break;
505 default:
506 break;
507 }
508
bcc1c2a1
AD		 509 return connected;
510}
511
377edc8b
AD		 512/**
513 * evergreen_hpd_set_polarity - hpd set polarity callback.
514 *
515 * @rdev: radeon_device pointer
516 * @hpd: hpd (hotplug detect) pin
517 *
518 * Set the polarity of the hpd pin (evergreen+).
519 */
bcc1c2a1
AD		 520void evergreen_hpd_set_polarity(struct radeon_device *rdev,
521 enum radeon_hpd_id hpd)
522{
0ca2ab52
AD		 523 u32 tmp;
524 bool connected = evergreen_hpd_sense(rdev, hpd);
525
526 switch (hpd) {
527 case RADEON_HPD_1:
528 tmp = RREG32(DC_HPD1_INT_CONTROL);
529 if (connected)
530 tmp &= ~DC_HPDx_INT_POLARITY;
531 else
532 tmp |= DC_HPDx_INT_POLARITY;
533 WREG32(DC_HPD1_INT_CONTROL, tmp);
534 break;
535 case RADEON_HPD_2:
536 tmp = RREG32(DC_HPD2_INT_CONTROL);
537 if (connected)
538 tmp &= ~DC_HPDx_INT_POLARITY;
539 else
540 tmp |= DC_HPDx_INT_POLARITY;
541 WREG32(DC_HPD2_INT_CONTROL, tmp);
542 break;
543 case RADEON_HPD_3:
544 tmp = RREG32(DC_HPD3_INT_CONTROL);
545 if (connected)
546 tmp &= ~DC_HPDx_INT_POLARITY;
547 else
548 tmp |= DC_HPDx_INT_POLARITY;
549 WREG32(DC_HPD3_INT_CONTROL, tmp);
550 break;
551 case RADEON_HPD_4:
552 tmp = RREG32(DC_HPD4_INT_CONTROL);
553 if (connected)
554 tmp &= ~DC_HPDx_INT_POLARITY;
555 else
556 tmp |= DC_HPDx_INT_POLARITY;
557 WREG32(DC_HPD4_INT_CONTROL, tmp);
558 break;
559 case RADEON_HPD_5:
560 tmp = RREG32(DC_HPD5_INT_CONTROL);
561 if (connected)
562 tmp &= ~DC_HPDx_INT_POLARITY;
563 else
564 tmp |= DC_HPDx_INT_POLARITY;
565 WREG32(DC_HPD5_INT_CONTROL, tmp);
566 break;
567 case RADEON_HPD_6:
568 tmp = RREG32(DC_HPD6_INT_CONTROL);
569 if (connected)
570 tmp &= ~DC_HPDx_INT_POLARITY;
571 else
572 tmp |= DC_HPDx_INT_POLARITY;
573 WREG32(DC_HPD6_INT_CONTROL, tmp);
574 break;
575 default:
576 break;
577 }
bcc1c2a1
AD		 578}
579
377edc8b
AD		 580/**
581 * evergreen_hpd_init - hpd setup callback.
582 *
583 * @rdev: radeon_device pointer
584 *
585 * Setup the hpd pins used by the card (evergreen+).
586 * Enable the pin, set the polarity, and enable the hpd interrupts.
587 */
bcc1c2a1
AD		 588void evergreen_hpd_init(struct radeon_device *rdev)
589{
0ca2ab52
AD		 590 struct drm_device *dev = rdev->ddev;
591 struct drm_connector *connector;
fb98257a 592 unsigned enabled = 0;
0ca2ab52
AD		 593 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
594 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 595
0ca2ab52
AD		 596 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
597 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
598 switch (radeon_connector->hpd.hpd) {
599 case RADEON_HPD_1:
600 WREG32(DC_HPD1_CONTROL, tmp);
0ca2ab52
AD		 601 break;
602 case RADEON_HPD_2:
603 WREG32(DC_HPD2_CONTROL, tmp);
0ca2ab52
AD		 604 break;
605 case RADEON_HPD_3:
606 WREG32(DC_HPD3_CONTROL, tmp);
0ca2ab52
AD		 607 break;
608 case RADEON_HPD_4:
609 WREG32(DC_HPD4_CONTROL, tmp);
0ca2ab52
AD		 610 break;
611 case RADEON_HPD_5:
612 WREG32(DC_HPD5_CONTROL, tmp);
0ca2ab52
AD		 613 break;
614 case RADEON_HPD_6:
615 WREG32(DC_HPD6_CONTROL, tmp);
0ca2ab52
AD		 616 break;
617 default:
618 break;
619 }
64912e99 620 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
fb98257a 621 enabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 622 }
fb98257a 623 radeon_irq_kms_enable_hpd(rdev, enabled);
bcc1c2a1
AD		 624}
625
377edc8b
AD		 626/**
627 * evergreen_hpd_fini - hpd tear down callback.
628 *
629 * @rdev: radeon_device pointer
630 *
631 * Tear down the hpd pins used by the card (evergreen+).
632 * Disable the hpd interrupts.
633 */
0ca2ab52 634void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 635{
0ca2ab52
AD		 636 struct drm_device *dev = rdev->ddev;
637 struct drm_connector *connector;
fb98257a 638 unsigned disabled = 0;
0ca2ab52
AD		 639
640 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
641 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
642 switch (radeon_connector->hpd.hpd) {
643 case RADEON_HPD_1:
644 WREG32(DC_HPD1_CONTROL, 0);
0ca2ab52
AD		 645 break;
646 case RADEON_HPD_2:
647 WREG32(DC_HPD2_CONTROL, 0);
0ca2ab52
AD		 648 break;
649 case RADEON_HPD_3:
650 WREG32(DC_HPD3_CONTROL, 0);
0ca2ab52
AD		 651 break;
652 case RADEON_HPD_4:
653 WREG32(DC_HPD4_CONTROL, 0);
0ca2ab52
AD		 654 break;
655 case RADEON_HPD_5:
656 WREG32(DC_HPD5_CONTROL, 0);
0ca2ab52
AD		 657 break;
658 case RADEON_HPD_6:
659 WREG32(DC_HPD6_CONTROL, 0);
0ca2ab52
AD		 660 break;
661 default:
662 break;
663 }
fb98257a 664 disabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 665 }
fb98257a 666 radeon_irq_kms_disable_hpd(rdev, disabled);
bcc1c2a1
AD		 667}
668
f9d9c362
AD		 669/* watermark setup */
670
671static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
672 struct radeon_crtc *radeon_crtc,
673 struct drm_display_mode *mode,
674 struct drm_display_mode *other_mode)
675{
12dfc843 676 u32 tmp;
f9d9c362
AD		 677 /*
678 * Line Buffer Setup
679 * There are 3 line buffers, each one shared by 2 display controllers.
680 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
681 * the display controllers. The paritioning is done via one of four
682 * preset allocations specified in bits 2:0:
683 * first display controller
684 * 0 - first half of lb (3840 * 2)
685 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 686 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 687 * 3 - first 1/4 of lb (1920 * 2)
688 * second display controller
689 * 4 - second half of lb (3840 * 2)
690 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 691 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 692 * 7 - last 1/4 of lb (1920 * 2)
693 */
12dfc843
AD		 694 /* this can get tricky if we have two large displays on a paired group
695 * of crtcs. Ideally for multiple large displays we'd assign them to
696 * non-linked crtcs for maximum line buffer allocation.
697 */
698 if (radeon_crtc->base.enabled && mode) {
699 if (other_mode)
f9d9c362 700 tmp = 0; /* 1/2 */
12dfc843
AD		 701 else
702 tmp = 2; /* whole */
703 } else
704 tmp = 0;
f9d9c362
AD		 705
706 /* second controller of the pair uses second half of the lb */
707 if (radeon_crtc->crtc_id % 2)
708 tmp += 4;
709 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
710
12dfc843
AD		 711 if (radeon_crtc->base.enabled && mode) {
712 switch (tmp) {
713 case 0:
714 case 4:
715 default:
716 if (ASIC_IS_DCE5(rdev))
717 return 4096 * 2;
718 else
719 return 3840 * 2;
720 case 1:
721 case 5:
722 if (ASIC_IS_DCE5(rdev))
723 return 6144 * 2;
724 else
725 return 5760 * 2;
726 case 2:
727 case 6:
728 if (ASIC_IS_DCE5(rdev))
729 return 8192 * 2;
730 else
731 return 7680 * 2;
732 case 3:
733 case 7:
734 if (ASIC_IS_DCE5(rdev))
735 return 2048 * 2;
736 else
737 return 1920 * 2;
738 }
f9d9c362 739 }
12dfc843
AD		 740
741 /* controller not enabled, so no lb used */
742 return 0;
f9d9c362
AD		 743}
744
ca7db22b 745u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
f9d9c362
AD		 746{
747 u32 tmp = RREG32(MC_SHARED_CHMAP);
748
749 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
750 case 0:
751 default:
752 return 1;
753 case 1:
754 return 2;
755 case 2:
756 return 4;
757 case 3:
758 return 8;
759 }
760}
761
762struct evergreen_wm_params {
763 u32 dram_channels; /* number of dram channels */
764 u32 yclk; /* bandwidth per dram data pin in kHz */
765 u32 sclk; /* engine clock in kHz */
766 u32 disp_clk; /* display clock in kHz */
767 u32 src_width; /* viewport width */
768 u32 active_time; /* active display time in ns */
769 u32 blank_time; /* blank time in ns */
770 bool interlaced; /* mode is interlaced */
771 fixed20_12 vsc; /* vertical scale ratio */
772 u32 num_heads; /* number of active crtcs */
773 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
774 u32 lb_size; /* line buffer allocated to pipe */
775 u32 vtaps; /* vertical scaler taps */
776};
777
778static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
779{
780 /* Calculate DRAM Bandwidth and the part allocated to display. */
781 fixed20_12 dram_efficiency; /* 0.7 */
782 fixed20_12 yclk, dram_channels, bandwidth;
783 fixed20_12 a;
784
785 a.full = dfixed_const(1000);
786 yclk.full = dfixed_const(wm->yclk);
787 yclk.full = dfixed_div(yclk, a);
788 dram_channels.full = dfixed_const(wm->dram_channels * 4);
789 a.full = dfixed_const(10);
790 dram_efficiency.full = dfixed_const(7);
791 dram_efficiency.full = dfixed_div(dram_efficiency, a);
792 bandwidth.full = dfixed_mul(dram_channels, yclk);
793 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
794
795 return dfixed_trunc(bandwidth);
796}
797
798static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
799{
800 /* Calculate DRAM Bandwidth and the part allocated to display. */
801 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
802 fixed20_12 yclk, dram_channels, bandwidth;
803 fixed20_12 a;
804
805 a.full = dfixed_const(1000);
806 yclk.full = dfixed_const(wm->yclk);
807 yclk.full = dfixed_div(yclk, a);
808 dram_channels.full = dfixed_const(wm->dram_channels * 4);
809 a.full = dfixed_const(10);
810 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
811 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
812 bandwidth.full = dfixed_mul(dram_channels, yclk);
813 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
814
815 return dfixed_trunc(bandwidth);
816}
817
818static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
819{
820 /* Calculate the display Data return Bandwidth */
821 fixed20_12 return_efficiency; /* 0.8 */
822 fixed20_12 sclk, bandwidth;
823 fixed20_12 a;
824
825 a.full = dfixed_const(1000);
826 sclk.full = dfixed_const(wm->sclk);
827 sclk.full = dfixed_div(sclk, a);
828 a.full = dfixed_const(10);
829 return_efficiency.full = dfixed_const(8);
830 return_efficiency.full = dfixed_div(return_efficiency, a);
831 a.full = dfixed_const(32);
832 bandwidth.full = dfixed_mul(a, sclk);
833 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
834
835 return dfixed_trunc(bandwidth);
836}
837
838static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
839{
840 /* Calculate the DMIF Request Bandwidth */
841 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
842 fixed20_12 disp_clk, bandwidth;
843 fixed20_12 a;
844
845 a.full = dfixed_const(1000);
846 disp_clk.full = dfixed_const(wm->disp_clk);
847 disp_clk.full = dfixed_div(disp_clk, a);
848 a.full = dfixed_const(10);
849 disp_clk_request_efficiency.full = dfixed_const(8);
850 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
851 a.full = dfixed_const(32);
852 bandwidth.full = dfixed_mul(a, disp_clk);
853 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
854
855 return dfixed_trunc(bandwidth);
856}
857
858static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
859{
860 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
861 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
862 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
863 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
864
865 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
866}
867
868static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
869{
870 /* Calculate the display mode Average Bandwidth
871 * DisplayMode should contain the source and destination dimensions,
872 * timing, etc.
873 */
874 fixed20_12 bpp;
875 fixed20_12 line_time;
876 fixed20_12 src_width;
877 fixed20_12 bandwidth;
878 fixed20_12 a;
879
880 a.full = dfixed_const(1000);
881 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
882 line_time.full = dfixed_div(line_time, a);
883 bpp.full = dfixed_const(wm->bytes_per_pixel);
884 src_width.full = dfixed_const(wm->src_width);
885 bandwidth.full = dfixed_mul(src_width, bpp);
886 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
887 bandwidth.full = dfixed_div(bandwidth, line_time);
888
889 return dfixed_trunc(bandwidth);
890}
891
892static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
893{
894 /* First calcualte the latency in ns */
895 u32 mc_latency = 2000; /* 2000 ns. */
896 u32 available_bandwidth = evergreen_available_bandwidth(wm);
897 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
898 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
899 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
900 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
901 (wm->num_heads * cursor_line_pair_return_time);
902 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
903 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
904 fixed20_12 a, b, c;
905
906 if (wm->num_heads == 0)
907 return 0;
908
909 a.full = dfixed_const(2);
910 b.full = dfixed_const(1);
911 if ((wm->vsc.full > a.full) ||
912 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
913 (wm->vtaps >= 5) ||
914 ((wm->vsc.full >= a.full) && wm->interlaced))
915 max_src_lines_per_dst_line = 4;
916 else
917 max_src_lines_per_dst_line = 2;
918
919 a.full = dfixed_const(available_bandwidth);
920 b.full = dfixed_const(wm->num_heads);
921 a.full = dfixed_div(a, b);
922
923 b.full = dfixed_const(1000);
924 c.full = dfixed_const(wm->disp_clk);
925 b.full = dfixed_div(c, b);
926 c.full = dfixed_const(wm->bytes_per_pixel);
927 b.full = dfixed_mul(b, c);
928
929 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
930
931 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
932 b.full = dfixed_const(1000);
933 c.full = dfixed_const(lb_fill_bw);
934 b.full = dfixed_div(c, b);
935 a.full = dfixed_div(a, b);
936 line_fill_time = dfixed_trunc(a);
937
938 if (line_fill_time < wm->active_time)
939 return latency;
940 else
941 return latency + (line_fill_time - wm->active_time);
942
943}
944
945static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
946{
947 if (evergreen_average_bandwidth(wm) <=
948 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
949 return true;
950 else
951 return false;
952};
953
954static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
955{
956 if (evergreen_average_bandwidth(wm) <=
957 (evergreen_available_bandwidth(wm) / wm->num_heads))
958 return true;
959 else
960 return false;
961};
962
963static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
964{
965 u32 lb_partitions = wm->lb_size / wm->src_width;
966 u32 line_time = wm->active_time + wm->blank_time;
967 u32 latency_tolerant_lines;
968 u32 latency_hiding;
969 fixed20_12 a;
970
971 a.full = dfixed_const(1);
972 if (wm->vsc.full > a.full)
973 latency_tolerant_lines = 1;
974 else {
975 if (lb_partitions <= (wm->vtaps + 1))
976 latency_tolerant_lines = 1;
977 else
978 latency_tolerant_lines = 2;
979 }
980
981 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
982
983 if (evergreen_latency_watermark(wm) <= latency_hiding)
984 return true;
985 else
986 return false;
987}
988
989static void evergreen_program_watermarks(struct radeon_device *rdev,
990 struct radeon_crtc *radeon_crtc,
991 u32 lb_size, u32 num_heads)
992{
993 struct drm_display_mode *mode = &radeon_crtc->base.mode;
994 struct evergreen_wm_params wm;
995 u32 pixel_period;
996 u32 line_time = 0;
997 u32 latency_watermark_a = 0, latency_watermark_b = 0;
998 u32 priority_a_mark = 0, priority_b_mark = 0;
999 u32 priority_a_cnt = PRIORITY_OFF;
1000 u32 priority_b_cnt = PRIORITY_OFF;
1001 u32 pipe_offset = radeon_crtc->crtc_id * 16;
1002 u32 tmp, arb_control3;
1003 fixed20_12 a, b, c;
1004
1005 if (radeon_crtc->base.enabled && num_heads && mode) {
1006 pixel_period = 1000000 / (u32)mode->clock;
1007 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1008 priority_a_cnt = 0;
1009 priority_b_cnt = 0;
1010
1011 wm.yclk = rdev->pm.current_mclk * 10;
1012 wm.sclk = rdev->pm.current_sclk * 10;
1013 wm.disp_clk = mode->clock;
1014 wm.src_width = mode->crtc_hdisplay;
1015 wm.active_time = mode->crtc_hdisplay * pixel_period;
1016 wm.blank_time = line_time - wm.active_time;
1017 wm.interlaced = false;
1018 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1019 wm.interlaced = true;
1020 wm.vsc = radeon_crtc->vsc;
1021 wm.vtaps = 1;
1022 if (radeon_crtc->rmx_type != RMX_OFF)
1023 wm.vtaps = 2;
1024 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
1025 wm.lb_size = lb_size;
1026 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
1027 wm.num_heads = num_heads;
1028
1029 /* set for high clocks */
1030 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
1031 /* set for low clocks */
1032 /* wm.yclk = low clk; wm.sclk = low clk */
1033 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
1034
1035 /* possibly force display priority to high */
1036 /* should really do this at mode validation time... */
1037 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
1038 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
1039 !evergreen_check_latency_hiding(&wm) ||
1040 (rdev->disp_priority == 2)) {
92bdfd4a 1041 DRM_DEBUG_KMS("force priority to high\n");
f9d9c362
AD		 1042 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1043 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1044 }
1045
1046 a.full = dfixed_const(1000);
1047 b.full = dfixed_const(mode->clock);
1048 b.full = dfixed_div(b, a);
1049 c.full = dfixed_const(latency_watermark_a);
1050 c.full = dfixed_mul(c, b);
1051 c.full = dfixed_mul(c, radeon_crtc->hsc);
1052 c.full = dfixed_div(c, a);
1053 a.full = dfixed_const(16);
1054 c.full = dfixed_div(c, a);
1055 priority_a_mark = dfixed_trunc(c);
1056 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1057
1058 a.full = dfixed_const(1000);
1059 b.full = dfixed_const(mode->clock);
1060 b.full = dfixed_div(b, a);
1061 c.full = dfixed_const(latency_watermark_b);
1062 c.full = dfixed_mul(c, b);
1063 c.full = dfixed_mul(c, radeon_crtc->hsc);
1064 c.full = dfixed_div(c, a);
1065 a.full = dfixed_const(16);
1066 c.full = dfixed_div(c, a);
1067 priority_b_mark = dfixed_trunc(c);
1068 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1069 }
1070
1071 /* select wm A */
1072 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1073 tmp = arb_control3;
1074 tmp &= ~LATENCY_WATERMARK_MASK(3);
1075 tmp |= LATENCY_WATERMARK_MASK(1);
1076 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1077 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1078 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1079 LATENCY_HIGH_WATERMARK(line_time)));
1080 /* select wm B */
1081 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1082 tmp &= ~LATENCY_WATERMARK_MASK(3);
1083 tmp |= LATENCY_WATERMARK_MASK(2);
1084 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1085 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1086 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1087 LATENCY_HIGH_WATERMARK(line_time)));
1088 /* restore original selection */
1089 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1090
1091 /* write the priority marks */
1092 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1093 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1094
1095}
1096
377edc8b
AD		 1097/**
1098 * evergreen_bandwidth_update - update display watermarks callback.
1099 *
1100 * @rdev: radeon_device pointer
1101 *
1102 * Update the display watermarks based on the requested mode(s)
1103 * (evergreen+).
1104 */
0ca2ab52 1105void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 1106{
f9d9c362
AD		 1107 struct drm_display_mode *mode0 = NULL;
1108 struct drm_display_mode *mode1 = NULL;
1109 u32 num_heads = 0, lb_size;
1110 int i;
1111
1112 radeon_update_display_priority(rdev);
1113
1114 for (i = 0; i < rdev->num_crtc; i++) {
1115 if (rdev->mode_info.crtcs[i]->base.enabled)
1116 num_heads++;
1117 }
1118 for (i = 0; i < rdev->num_crtc; i += 2) {
1119 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1120 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1121 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1122 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1123 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1124 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1125 }
bcc1c2a1
AD		 1126}
1127
377edc8b
AD		 1128/**
1129 * evergreen_mc_wait_for_idle - wait for MC idle callback.
1130 *
1131 * @rdev: radeon_device pointer
1132 *
1133 * Wait for the MC (memory controller) to be idle.
1134 * (evergreen+).
1135 * Returns 0 if the MC is idle, -1 if not.
1136 */
b9952a8a 1137int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 1138{
1139 unsigned i;
1140 u32 tmp;
1141
1142 for (i = 0; i < rdev->usec_timeout; i++) {
1143 /* read MC_STATUS */
1144 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1145 if (!tmp)
1146 return 0;
1147 udelay(1);
1148 }
1149 return -1;
1150}
1151
1152/*
1153 * GART
1154 */
0fcdb61e
AD		 1155void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1156{
1157 unsigned i;
1158 u32 tmp;
1159
6f2f48a9
AD		 1160 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1161
0fcdb61e
AD		 1162 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1163 for (i = 0; i < rdev->usec_timeout; i++) {
1164 /* read MC_STATUS */
1165 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1166 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1167 if (tmp == 2) {
1168 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1169 return;
1170 }
1171 if (tmp) {
1172 return;
1173 }
1174 udelay(1);
1175 }
1176}
1177
1109ca09 1178static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 1179{
1180 u32 tmp;
0fcdb61e 1181 int r;
bcc1c2a1 1182
c9a1be96 1183 if (rdev->gart.robj == NULL) {
bcc1c2a1
AD		 1184 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1185 return -EINVAL;
1186 }
1187 r = radeon_gart_table_vram_pin(rdev);
1188 if (r)
1189 return r;
82568565 1190 radeon_gart_restore(rdev);
bcc1c2a1
AD		 1191 /* Setup L2 cache */
1192 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1193 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1194 EFFECTIVE_L2_QUEUE_SIZE(7));
1195 WREG32(VM_L2_CNTL2, 0);
1196 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1197 /* Setup TLB control */
1198 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1199 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1200 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1201 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 1202 if (rdev->flags & RADEON_IS_IGP) {
1203 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1204 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1205 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1206 } else {
1207 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1208 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1209 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
0b8c30bc
AD		 1210 if ((rdev->family == CHIP_JUNIPER) ||
1211 (rdev->family == CHIP_CYPRESS) ||
1212 (rdev->family == CHIP_HEMLOCK) ||
1213 (rdev->family == CHIP_BARTS))
1214 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
8aeb96f8 1215 }
bcc1c2a1
AD		 1216 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1217 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1218 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1219 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1220 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1221 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1222 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1223 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1224 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1225 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1226 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 1227 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 1228
0fcdb61e 1229 evergreen_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1230 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1231 (unsigned)(rdev->mc.gtt_size >> 20),
1232 (unsigned long long)rdev->gart.table_addr);
bcc1c2a1
AD		 1233 rdev->gart.ready = true;
1234 return 0;
1235}
1236
1109ca09 1237static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
bcc1c2a1
AD		 1238{
1239 u32 tmp;
bcc1c2a1
AD		 1240
1241 /* Disable all tables */
0fcdb61e
AD		 1242 WREG32(VM_CONTEXT0_CNTL, 0);
1243 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1244
1245 /* Setup L2 cache */
1246 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1247 EFFECTIVE_L2_QUEUE_SIZE(7));
1248 WREG32(VM_L2_CNTL2, 0);
1249 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1250 /* Setup TLB control */
1251 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1252 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1253 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1254 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1255 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1256 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1257 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1258 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 1259 radeon_gart_table_vram_unpin(rdev);
bcc1c2a1
AD		 1260}
1261
1109ca09 1262static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
bcc1c2a1
AD		 1263{
1264 evergreen_pcie_gart_disable(rdev);
1265 radeon_gart_table_vram_free(rdev);
1266 radeon_gart_fini(rdev);
1267}
1268
1269
1109ca09 1270static void evergreen_agp_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 1271{
1272 u32 tmp;
bcc1c2a1
AD		 1273
1274 /* Setup L2 cache */
1275 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1276 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1277 EFFECTIVE_L2_QUEUE_SIZE(7));
1278 WREG32(VM_L2_CNTL2, 0);
1279 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1280 /* Setup TLB control */
1281 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1282 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1283 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1284 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1285 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1286 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1287 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1288 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1289 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1290 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1291 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 1292 WREG32(VM_CONTEXT0_CNTL, 0);
1293 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1294}
1295
b9952a8a 1296void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 1297{
62444b74
AD		 1298 u32 crtc_enabled, tmp, frame_count, blackout;
1299 int i, j;
1300
bcc1c2a1
AD		 1301 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1302 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
bcc1c2a1 1303
62444b74 1304 /* disable VGA render */
bcc1c2a1 1305 WREG32(VGA_RENDER_CONTROL, 0);
62444b74
AD		 1306 /* blank the display controllers */
1307 for (i = 0; i < rdev->num_crtc; i++) {
1308 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1309 if (crtc_enabled) {
1310 save->crtc_enabled[i] = true;
1311 if (ASIC_IS_DCE6(rdev)) {
1312 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1313 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1314 radeon_wait_for_vblank(rdev, i);
1315 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1316 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1317 }
1318 } else {
1319 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1320 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1321 radeon_wait_for_vblank(rdev, i);
1322 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1323 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1324 }
1325 }
1326 /* wait for the next frame */
1327 frame_count = radeon_get_vblank_counter(rdev, i);
1328 for (j = 0; j < rdev->usec_timeout; j++) {
1329 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1330 break;
1331 udelay(1);
1332 }
804cc4a0
AD		 1333 } else {
1334 save->crtc_enabled[i] = false;
62444b74 1335 }
18007401 1336 }
bcc1c2a1 1337
62444b74
AD		 1338 radeon_mc_wait_for_idle(rdev);
1339
1340 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1341 if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1342 /* Block CPU access */
1343 WREG32(BIF_FB_EN, 0);
1344 /* blackout the MC */
1345 blackout &= ~BLACKOUT_MODE_MASK;
1346 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
b7eff394 1347 }
bcc1c2a1
AD		 1348}
1349
b9952a8a 1350void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 1351{
62444b74
AD		 1352 u32 tmp, frame_count;
1353 int i, j;
18007401 1354
62444b74
AD		 1355 /* update crtc base addresses */
1356 for (i = 0; i < rdev->num_crtc; i++) {
1357 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 1358 upper_32_bits(rdev->mc.vram_start));
62444b74 1359 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 1360 upper_32_bits(rdev->mc.vram_start));
62444b74 1361 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401 1362 (u32)rdev->mc.vram_start);
62444b74 1363 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401
AD		 1364 (u32)rdev->mc.vram_start);
1365 }
bcc1c2a1
AD		 1366 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1367 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
62444b74
AD		 1368
1369 /* unblackout the MC */
1370 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1371 tmp &= ~BLACKOUT_MODE_MASK;
1372 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1373 /* allow CPU access */
1374 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1375
1376 for (i = 0; i < rdev->num_crtc; i++) {
695ddeb4 1377 if (save->crtc_enabled[i]) {
62444b74
AD		 1378 if (ASIC_IS_DCE6(rdev)) {
1379 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1380 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1381 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1382 } else {
1383 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1384 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1385 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1386 }
1387 /* wait for the next frame */
1388 frame_count = radeon_get_vblank_counter(rdev, i);
1389 for (j = 0; j < rdev->usec_timeout; j++) {
1390 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1391 break;
1392 udelay(1);
1393 }
1394 }
1395 }
1396 /* Unlock vga access */
bcc1c2a1
AD		 1397 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1398 mdelay(1);
bcc1c2a1
AD		 1399 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1400}
1401
755d819e 1402void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 1403{
1404 struct evergreen_mc_save save;
1405 u32 tmp;
1406 int i, j;
1407
1408 /* Initialize HDP */
1409 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1410 WREG32((0x2c14 + j), 0x00000000);
1411 WREG32((0x2c18 + j), 0x00000000);
1412 WREG32((0x2c1c + j), 0x00000000);
1413 WREG32((0x2c20 + j), 0x00000000);
1414 WREG32((0x2c24 + j), 0x00000000);
1415 }
1416 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1417
1418 evergreen_mc_stop(rdev, &save);
1419 if (evergreen_mc_wait_for_idle(rdev)) {
1420 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1421 }
1422 /* Lockout access through VGA aperture*/
1423 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1424 /* Update configuration */
1425 if (rdev->flags & RADEON_IS_AGP) {
1426 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1427 /* VRAM before AGP */
1428 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1429 rdev->mc.vram_start >> 12);
1430 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1431 rdev->mc.gtt_end >> 12);
1432 } else {
1433 /* VRAM after AGP */
1434 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1435 rdev->mc.gtt_start >> 12);
1436 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1437 rdev->mc.vram_end >> 12);
1438 }
1439 } else {
1440 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1441 rdev->mc.vram_start >> 12);
1442 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1443 rdev->mc.vram_end >> 12);
1444 }
3b9832f6 1445 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
05b3ef69
AD		 1446 /* llano/ontario only */
1447 if ((rdev->family == CHIP_PALM) ||
1448 (rdev->family == CHIP_SUMO) ||
1449 (rdev->family == CHIP_SUMO2)) {
b4183e30
AD		 1450 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1451 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1452 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1453 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1454 }
bcc1c2a1
AD		 1455 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1456 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1457 WREG32(MC_VM_FB_LOCATION, tmp);
1458 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 1459 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 1460 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1461 if (rdev->flags & RADEON_IS_AGP) {
1462 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1463 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1464 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1465 } else {
1466 WREG32(MC_VM_AGP_BASE, 0);
1467 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1468 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1469 }
1470 if (evergreen_mc_wait_for_idle(rdev)) {
1471 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1472 }
1473 evergreen_mc_resume(rdev, &save);
1474 /* we need to own VRAM, so turn off the VGA renderer here
1475 * to stop it overwriting our objects */
1476 rv515_vga_render_disable(rdev);
1477}
1478
bcc1c2a1
AD		 1479/*
1480 * CP.
1481 */
12920591
AD		 1482void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1483{
876dc9f3 1484 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 1485 u32 next_rptr;
7b1f2485 1486
12920591 1487 /* set to DX10/11 mode */
e32eb50d
CK		 1488 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1489 radeon_ring_write(ring, 1);
45df6803
CK		 1490
1491 if (ring->rptr_save_reg) {
89d35807 1492 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 1493 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1494 radeon_ring_write(ring, ((ring->rptr_save_reg -
1495 PACKET3_SET_CONFIG_REG_START) >> 2));
1496 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1497 } else if (rdev->wb.enabled) {
1498 next_rptr = ring->wptr + 5 + 4;
1499 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1500 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1501 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1502 radeon_ring_write(ring, next_rptr);
1503 radeon_ring_write(ring, 0);
45df6803
CK		 1504 }
1505
e32eb50d
CK		 1506 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1507 radeon_ring_write(ring,
0f234f5f
AD		 1508#ifdef __BIG_ENDIAN
1509 (2 << 0) |
1510#endif
1511 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 1512 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1513 radeon_ring_write(ring, ib->length_dw);
12920591
AD		 1514}
1515
bcc1c2a1
AD		 1516
1517static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1518{
fe251e2f
AD		 1519 const __be32 *fw_data;
1520 int i;
1521
1522 if (!rdev->me_fw || !rdev->pfp_fw)
1523 return -EINVAL;
bcc1c2a1 1524
fe251e2f 1525 r700_cp_stop(rdev);
0f234f5f
AD		 1526 WREG32(CP_RB_CNTL,
1527#ifdef __BIG_ENDIAN
1528 BUF_SWAP_32BIT |
1529#endif
1530 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 1531
1532 fw_data = (const __be32 *)rdev->pfp_fw->data;
1533 WREG32(CP_PFP_UCODE_ADDR, 0);
1534 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1535 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1536 WREG32(CP_PFP_UCODE_ADDR, 0);
1537
1538 fw_data = (const __be32 *)rdev->me_fw->data;
1539 WREG32(CP_ME_RAM_WADDR, 0);
1540 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1541 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1542
1543 WREG32(CP_PFP_UCODE_ADDR, 0);
1544 WREG32(CP_ME_RAM_WADDR, 0);
1545 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1546 return 0;
1547}
1548
7e7b41d2
AD		 1549static int evergreen_cp_start(struct radeon_device *rdev)
1550{
e32eb50d 1551 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2281a378 1552 int r, i;
7e7b41d2
AD		 1553 uint32_t cp_me;
1554
e32eb50d 1555 r = radeon_ring_lock(rdev, ring, 7);
7e7b41d2
AD		 1556 if (r) {
1557 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1558 return r;
1559 }
e32eb50d
CK		 1560 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1561 radeon_ring_write(ring, 0x1);
1562 radeon_ring_write(ring, 0x0);
1563 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1564 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1565 radeon_ring_write(ring, 0);
1566 radeon_ring_write(ring, 0);
1567 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1568
1569 cp_me = 0xff;
1570 WREG32(CP_ME_CNTL, cp_me);
1571
e32eb50d 1572 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
7e7b41d2
AD		 1573 if (r) {
1574 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1575 return r;
1576 }
2281a378
AD		 1577
1578 /* setup clear context state */
e32eb50d
CK		 1579 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1580 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2281a378
AD		 1581
1582 for (i = 0; i < evergreen_default_size; i++)
e32eb50d 1583 radeon_ring_write(ring, evergreen_default_state[i]);
2281a378 1584
e32eb50d
CK		 1585 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1586 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2281a378
AD		 1587
1588 /* set clear context state */
e32eb50d
CK		 1589 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1590 radeon_ring_write(ring, 0);
2281a378
AD		 1591
1592 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1593 radeon_ring_write(ring, 0xc0026f00);
1594 radeon_ring_write(ring, 0x00000000);
1595 radeon_ring_write(ring, 0x00000000);
1596 radeon_ring_write(ring, 0x00000000);
2281a378
AD		 1597
1598 /* Clear consts */
e32eb50d
CK		 1599 radeon_ring_write(ring, 0xc0036f00);
1600 radeon_ring_write(ring, 0x00000bc4);
1601 radeon_ring_write(ring, 0xffffffff);
1602 radeon_ring_write(ring, 0xffffffff);
1603 radeon_ring_write(ring, 0xffffffff);
2281a378 1604
e32eb50d
CK		 1605 radeon_ring_write(ring, 0xc0026900);
1606 radeon_ring_write(ring, 0x00000316);
1607 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1608 radeon_ring_write(ring, 0x00000010); /* */
18ff84da 1609
e32eb50d 1610 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1611
1612 return 0;
1613}
1614
1109ca09 1615static int evergreen_cp_resume(struct radeon_device *rdev)
fe251e2f 1616{
e32eb50d 1617 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f
AD		 1618 u32 tmp;
1619 u32 rb_bufsz;
1620 int r;
1621
1622 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1623 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1624 SOFT_RESET_PA |
1625 SOFT_RESET_SH |
1626 SOFT_RESET_VGT |
a49a50da 1627 SOFT_RESET_SPI |
fe251e2f
AD		 1628 SOFT_RESET_SX));
1629 RREG32(GRBM_SOFT_RESET);
1630 mdelay(15);
1631 WREG32(GRBM_SOFT_RESET, 0);
1632 RREG32(GRBM_SOFT_RESET);
1633
1634 /* Set ring buffer size */
e32eb50d 1635 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 1636 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1637#ifdef __BIG_ENDIAN
1638 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1639#endif
fe251e2f 1640 WREG32(CP_RB_CNTL, tmp);
15d3332f 1641 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1642 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
fe251e2f
AD		 1643
1644 /* Set the write pointer delay */
1645 WREG32(CP_RB_WPTR_DELAY, 0);
1646
1647 /* Initialize the ring buffer's read and write pointers */
1648 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1649 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1650 ring->wptr = 0;
1651 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1 1652
48fc7f7e 1653 /* set the wb address whether it's enabled or not */
0f234f5f 1654 WREG32(CP_RB_RPTR_ADDR,
0f234f5f 1655 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 1656 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1657 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1658
1659 if (rdev->wb.enabled)
1660 WREG32(SCRATCH_UMSK, 0xff);
1661 else {
1662 tmp |= RB_NO_UPDATE;
1663 WREG32(SCRATCH_UMSK, 0);
1664 }
1665
fe251e2f
AD		 1666 mdelay(1);
1667 WREG32(CP_RB_CNTL, tmp);
1668
e32eb50d 1669 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
fe251e2f
AD		 1670 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1671
e32eb50d 1672 ring->rptr = RREG32(CP_RB_RPTR);
fe251e2f 1673
7e7b41d2 1674 evergreen_cp_start(rdev);
e32eb50d 1675 ring->ready = true;
f712812e 1676 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
fe251e2f 1677 if (r) {
e32eb50d 1678 ring->ready = false;
fe251e2f
AD		 1679 return r;
1680 }
1681 return 0;
1682}
bcc1c2a1
AD		 1683
1684/*
1685 * Core functions
1686 */
bcc1c2a1
AD		 1687static void evergreen_gpu_init(struct radeon_device *rdev)
1688{
416a2bd2 1689 u32 gb_addr_config;
32fcdbf4 1690 u32 mc_shared_chmap, mc_arb_ramcfg;
32fcdbf4
AD		 1691 u32 sx_debug_1;
1692 u32 smx_dc_ctl0;
1693 u32 sq_config;
1694 u32 sq_lds_resource_mgmt;
1695 u32 sq_gpr_resource_mgmt_1;
1696 u32 sq_gpr_resource_mgmt_2;
1697 u32 sq_gpr_resource_mgmt_3;
1698 u32 sq_thread_resource_mgmt;
1699 u32 sq_thread_resource_mgmt_2;
1700 u32 sq_stack_resource_mgmt_1;
1701 u32 sq_stack_resource_mgmt_2;
1702 u32 sq_stack_resource_mgmt_3;
1703 u32 vgt_cache_invalidation;
f25a5c63 1704 u32 hdp_host_path_cntl, tmp;
416a2bd2 1705 u32 disabled_rb_mask;
32fcdbf4
AD		 1706 int i, j, num_shader_engines, ps_thread_count;
1707
1708 switch (rdev->family) {
1709 case CHIP_CYPRESS:
1710 case CHIP_HEMLOCK:
1711 rdev->config.evergreen.num_ses = 2;
1712 rdev->config.evergreen.max_pipes = 4;
1713 rdev->config.evergreen.max_tile_pipes = 8;
1714 rdev->config.evergreen.max_simds = 10;
1715 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1716 rdev->config.evergreen.max_gprs = 256;
1717 rdev->config.evergreen.max_threads = 248;
1718 rdev->config.evergreen.max_gs_threads = 32;
1719 rdev->config.evergreen.max_stack_entries = 512;
1720 rdev->config.evergreen.sx_num_of_sets = 4;
1721 rdev->config.evergreen.sx_max_export_size = 256;
1722 rdev->config.evergreen.sx_max_export_pos_size = 64;
1723 rdev->config.evergreen.sx_max_export_smx_size = 192;
1724 rdev->config.evergreen.max_hw_contexts = 8;
1725 rdev->config.evergreen.sq_num_cf_insts = 2;
1726
1727 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1728 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1729 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1730 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1731 break;
1732 case CHIP_JUNIPER:
1733 rdev->config.evergreen.num_ses = 1;
1734 rdev->config.evergreen.max_pipes = 4;
1735 rdev->config.evergreen.max_tile_pipes = 4;
1736 rdev->config.evergreen.max_simds = 10;
1737 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1738 rdev->config.evergreen.max_gprs = 256;
1739 rdev->config.evergreen.max_threads = 248;
1740 rdev->config.evergreen.max_gs_threads = 32;
1741 rdev->config.evergreen.max_stack_entries = 512;
1742 rdev->config.evergreen.sx_num_of_sets = 4;
1743 rdev->config.evergreen.sx_max_export_size = 256;
1744 rdev->config.evergreen.sx_max_export_pos_size = 64;
1745 rdev->config.evergreen.sx_max_export_smx_size = 192;
1746 rdev->config.evergreen.max_hw_contexts = 8;
1747 rdev->config.evergreen.sq_num_cf_insts = 2;
1748
1749 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1750 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1751 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1752 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1753 break;
1754 case CHIP_REDWOOD:
1755 rdev->config.evergreen.num_ses = 1;
1756 rdev->config.evergreen.max_pipes = 4;
1757 rdev->config.evergreen.max_tile_pipes = 4;
1758 rdev->config.evergreen.max_simds = 5;
1759 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1760 rdev->config.evergreen.max_gprs = 256;
1761 rdev->config.evergreen.max_threads = 248;
1762 rdev->config.evergreen.max_gs_threads = 32;
1763 rdev->config.evergreen.max_stack_entries = 256;
1764 rdev->config.evergreen.sx_num_of_sets = 4;
1765 rdev->config.evergreen.sx_max_export_size = 256;
1766 rdev->config.evergreen.sx_max_export_pos_size = 64;
1767 rdev->config.evergreen.sx_max_export_smx_size = 192;
1768 rdev->config.evergreen.max_hw_contexts = 8;
1769 rdev->config.evergreen.sq_num_cf_insts = 2;
1770
1771 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1772 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1773 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1774 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1775 break;
1776 case CHIP_CEDAR:
1777 default:
1778 rdev->config.evergreen.num_ses = 1;
1779 rdev->config.evergreen.max_pipes = 2;
1780 rdev->config.evergreen.max_tile_pipes = 2;
1781 rdev->config.evergreen.max_simds = 2;
1782 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1783 rdev->config.evergreen.max_gprs = 256;
1784 rdev->config.evergreen.max_threads = 192;
1785 rdev->config.evergreen.max_gs_threads = 16;
1786 rdev->config.evergreen.max_stack_entries = 256;
1787 rdev->config.evergreen.sx_num_of_sets = 4;
1788 rdev->config.evergreen.sx_max_export_size = 128;
1789 rdev->config.evergreen.sx_max_export_pos_size = 32;
1790 rdev->config.evergreen.sx_max_export_smx_size = 96;
1791 rdev->config.evergreen.max_hw_contexts = 4;
1792 rdev->config.evergreen.sq_num_cf_insts = 1;
1793
d5e455e4
AD		 1794 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1795 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1796 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1797 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5e455e4
AD		 1798 break;
1799 case CHIP_PALM:
1800 rdev->config.evergreen.num_ses = 1;
1801 rdev->config.evergreen.max_pipes = 2;
1802 rdev->config.evergreen.max_tile_pipes = 2;
1803 rdev->config.evergreen.max_simds = 2;
1804 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1805 rdev->config.evergreen.max_gprs = 256;
1806 rdev->config.evergreen.max_threads = 192;
1807 rdev->config.evergreen.max_gs_threads = 16;
1808 rdev->config.evergreen.max_stack_entries = 256;
1809 rdev->config.evergreen.sx_num_of_sets = 4;
1810 rdev->config.evergreen.sx_max_export_size = 128;
1811 rdev->config.evergreen.sx_max_export_pos_size = 32;
1812 rdev->config.evergreen.sx_max_export_smx_size = 96;
1813 rdev->config.evergreen.max_hw_contexts = 4;
1814 rdev->config.evergreen.sq_num_cf_insts = 1;
1815
d5c5a72f
AD		 1816 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1817 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1818 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1819 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 1820 break;
1821 case CHIP_SUMO:
1822 rdev->config.evergreen.num_ses = 1;
1823 rdev->config.evergreen.max_pipes = 4;
bd25f078 1824 rdev->config.evergreen.max_tile_pipes = 4;
d5c5a72f
AD		 1825 if (rdev->pdev->device == 0x9648)
1826 rdev->config.evergreen.max_simds = 3;
1827 else if ((rdev->pdev->device == 0x9647) ||
1828 (rdev->pdev->device == 0x964a))
1829 rdev->config.evergreen.max_simds = 4;
1830 else
1831 rdev->config.evergreen.max_simds = 5;
1832 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1833 rdev->config.evergreen.max_gprs = 256;
1834 rdev->config.evergreen.max_threads = 248;
1835 rdev->config.evergreen.max_gs_threads = 32;
1836 rdev->config.evergreen.max_stack_entries = 256;
1837 rdev->config.evergreen.sx_num_of_sets = 4;
1838 rdev->config.evergreen.sx_max_export_size = 256;
1839 rdev->config.evergreen.sx_max_export_pos_size = 64;
1840 rdev->config.evergreen.sx_max_export_smx_size = 192;
1841 rdev->config.evergreen.max_hw_contexts = 8;
1842 rdev->config.evergreen.sq_num_cf_insts = 2;
1843
1844 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1845 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1846 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 1847 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 1848 break;
1849 case CHIP_SUMO2:
1850 rdev->config.evergreen.num_ses = 1;
1851 rdev->config.evergreen.max_pipes = 4;
1852 rdev->config.evergreen.max_tile_pipes = 4;
1853 rdev->config.evergreen.max_simds = 2;
1854 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1855 rdev->config.evergreen.max_gprs = 256;
1856 rdev->config.evergreen.max_threads = 248;
1857 rdev->config.evergreen.max_gs_threads = 32;
1858 rdev->config.evergreen.max_stack_entries = 512;
1859 rdev->config.evergreen.sx_num_of_sets = 4;
1860 rdev->config.evergreen.sx_max_export_size = 256;
1861 rdev->config.evergreen.sx_max_export_pos_size = 64;
1862 rdev->config.evergreen.sx_max_export_smx_size = 192;
1863 rdev->config.evergreen.max_hw_contexts = 8;
1864 rdev->config.evergreen.sq_num_cf_insts = 2;
1865
adb68fa2
AD		 1866 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1867 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1868 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 1869 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1870 break;
1871 case CHIP_BARTS:
1872 rdev->config.evergreen.num_ses = 2;
1873 rdev->config.evergreen.max_pipes = 4;
1874 rdev->config.evergreen.max_tile_pipes = 8;
1875 rdev->config.evergreen.max_simds = 7;
1876 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1877 rdev->config.evergreen.max_gprs = 256;
1878 rdev->config.evergreen.max_threads = 248;
1879 rdev->config.evergreen.max_gs_threads = 32;
1880 rdev->config.evergreen.max_stack_entries = 512;
1881 rdev->config.evergreen.sx_num_of_sets = 4;
1882 rdev->config.evergreen.sx_max_export_size = 256;
1883 rdev->config.evergreen.sx_max_export_pos_size = 64;
1884 rdev->config.evergreen.sx_max_export_smx_size = 192;
1885 rdev->config.evergreen.max_hw_contexts = 8;
1886 rdev->config.evergreen.sq_num_cf_insts = 2;
1887
1888 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1889 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1890 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1891 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1892 break;
1893 case CHIP_TURKS:
1894 rdev->config.evergreen.num_ses = 1;
1895 rdev->config.evergreen.max_pipes = 4;
1896 rdev->config.evergreen.max_tile_pipes = 4;
1897 rdev->config.evergreen.max_simds = 6;
1898 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1899 rdev->config.evergreen.max_gprs = 256;
1900 rdev->config.evergreen.max_threads = 248;
1901 rdev->config.evergreen.max_gs_threads = 32;
1902 rdev->config.evergreen.max_stack_entries = 256;
1903 rdev->config.evergreen.sx_num_of_sets = 4;
1904 rdev->config.evergreen.sx_max_export_size = 256;
1905 rdev->config.evergreen.sx_max_export_pos_size = 64;
1906 rdev->config.evergreen.sx_max_export_smx_size = 192;
1907 rdev->config.evergreen.max_hw_contexts = 8;
1908 rdev->config.evergreen.sq_num_cf_insts = 2;
1909
1910 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1911 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1912 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1913 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1914 break;
1915 case CHIP_CAICOS:
1916 rdev->config.evergreen.num_ses = 1;
bd25f078 1917 rdev->config.evergreen.max_pipes = 2;
adb68fa2
AD		 1918 rdev->config.evergreen.max_tile_pipes = 2;
1919 rdev->config.evergreen.max_simds = 2;
1920 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1921 rdev->config.evergreen.max_gprs = 256;
1922 rdev->config.evergreen.max_threads = 192;
1923 rdev->config.evergreen.max_gs_threads = 16;
1924 rdev->config.evergreen.max_stack_entries = 256;
1925 rdev->config.evergreen.sx_num_of_sets = 4;
1926 rdev->config.evergreen.sx_max_export_size = 128;
1927 rdev->config.evergreen.sx_max_export_pos_size = 32;
1928 rdev->config.evergreen.sx_max_export_smx_size = 96;
1929 rdev->config.evergreen.max_hw_contexts = 4;
1930 rdev->config.evergreen.sq_num_cf_insts = 1;
1931
32fcdbf4
AD		 1932 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1933 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1934 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1935 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1936 break;
1937 }
1938
1939 /* Initialize HDP */
1940 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1941 WREG32((0x2c14 + j), 0x00000000);
1942 WREG32((0x2c18 + j), 0x00000000);
1943 WREG32((0x2c1c + j), 0x00000000);
1944 WREG32((0x2c20 + j), 0x00000000);
1945 WREG32((0x2c24 + j), 0x00000000);
1946 }
1947
1948 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1949
d054ac16
AD		 1950 evergreen_fix_pci_max_read_req_size(rdev);
1951
32fcdbf4 1952 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
05b3ef69
AD		 1953 if ((rdev->family == CHIP_PALM) ||
1954 (rdev->family == CHIP_SUMO) ||
1955 (rdev->family == CHIP_SUMO2))
d9282fca
AD		 1956 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1957 else
1958 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
32fcdbf4 1959
1aa52bd3
AD		 1960 /* setup tiling info dword. gb_addr_config is not adequate since it does
1961 * not have bank info, so create a custom tiling dword.
1962 * bits 3:0 num_pipes
1963 * bits 7:4 num_banks
1964 * bits 11:8 group_size
1965 * bits 15:12 row_size
1966 */
1967 rdev->config.evergreen.tile_config = 0;
1968 switch (rdev->config.evergreen.max_tile_pipes) {
1969 case 1:
1970 default:
1971 rdev->config.evergreen.tile_config |= (0 << 0);
1972 break;
1973 case 2:
1974 rdev->config.evergreen.tile_config |= (1 << 0);
1975 break;
1976 case 4:
1977 rdev->config.evergreen.tile_config |= (2 << 0);
1978 break;
1979 case 8:
1980 rdev->config.evergreen.tile_config |= (3 << 0);
1981 break;
1982 }
d698a34d 1983 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
5bfa4879 1984 if (rdev->flags & RADEON_IS_IGP)
d698a34d 1985 rdev->config.evergreen.tile_config |= 1 << 4;
29d65406 1986 else {
c8d15edc
AD		 1987 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1988 case 0: /* four banks */
29d65406 1989 rdev->config.evergreen.tile_config |= 0 << 4;
c8d15edc
AD		 1990 break;
1991 case 1: /* eight banks */
1992 rdev->config.evergreen.tile_config |= 1 << 4;
1993 break;
1994 case 2: /* sixteen banks */
1995 default:
1996 rdev->config.evergreen.tile_config |= 2 << 4;
1997 break;
1998 }
29d65406 1999 }
416a2bd2 2000 rdev->config.evergreen.tile_config |= 0 << 8;
1aa52bd3
AD		 2001 rdev->config.evergreen.tile_config |=
2002 ((gb_addr_config & 0x30000000) >> 28) << 12;
2003
416a2bd2 2004 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
32fcdbf4 2005
416a2bd2
AD		 2006 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
2007 u32 efuse_straps_4;
2008 u32 efuse_straps_3;
32fcdbf4 2009
416a2bd2
AD		 2010 WREG32(RCU_IND_INDEX, 0x204);
2011 efuse_straps_4 = RREG32(RCU_IND_DATA);
2012 WREG32(RCU_IND_INDEX, 0x203);
2013 efuse_straps_3 = RREG32(RCU_IND_DATA);
2014 tmp = (((efuse_straps_4 & 0xf) << 4) |
2015 ((efuse_straps_3 & 0xf0000000) >> 28));
2016 } else {
2017 tmp = 0;
2018 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
2019 u32 rb_disable_bitmap;
2020
2021 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2022 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2023 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
2024 tmp <<= 4;
2025 tmp |= rb_disable_bitmap;
32fcdbf4 2026 }
416a2bd2
AD		 2027 }
2028 /* enabled rb are just the one not disabled :) */
2029 disabled_rb_mask = tmp;
32fcdbf4 2030
416a2bd2
AD		 2031 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2032 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
32fcdbf4 2033
416a2bd2
AD		 2034 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2035 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2036 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
233d1ad5 2037 WREG32(DMA_TILING_CONFIG, gb_addr_config);
32fcdbf4 2038
416a2bd2
AD		 2039 tmp = gb_addr_config & NUM_PIPES_MASK;
2040 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2041 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
2042 WREG32(GB_BACKEND_MAP, tmp);
32fcdbf4
AD		 2043
2044 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2045 WREG32(CGTS_TCC_DISABLE, 0);
2046 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2047 WREG32(CGTS_USER_TCC_DISABLE, 0);
2048
2049 /* set HW defaults for 3D engine */
2050 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2051 ROQ_IB2_START(0x2b)));
2052
2053 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2054
2055 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2056 SYNC_GRADIENT |
2057 SYNC_WALKER |
2058 SYNC_ALIGNER));
2059
2060 sx_debug_1 = RREG32(SX_DEBUG_1);
2061 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2062 WREG32(SX_DEBUG_1, sx_debug_1);
2063
2064
2065 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2066 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2067 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2068 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2069
b866d133
AD		 2070 if (rdev->family <= CHIP_SUMO2)
2071 WREG32(SMX_SAR_CTL0, 0x00010000);
2072
32fcdbf4
AD		 2073 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2074 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2075 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2076
2077 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2078 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2079 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2080
2081 WREG32(VGT_NUM_INSTANCES, 1);
2082 WREG32(SPI_CONFIG_CNTL, 0);
2083 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2084 WREG32(CP_PERFMON_CNTL, 0);
2085
2086 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2087 FETCH_FIFO_HIWATER(0x4) |
2088 DONE_FIFO_HIWATER(0xe0) |
2089 ALU_UPDATE_FIFO_HIWATER(0x8)));
2090
2091 sq_config = RREG32(SQ_CONFIG);
2092 sq_config &= ~(PS_PRIO(3) |
2093 VS_PRIO(3) |
2094 GS_PRIO(3) |
2095 ES_PRIO(3));
2096 sq_config |= (VC_ENABLE |
2097 EXPORT_SRC_C |
2098 PS_PRIO(0) |
2099 VS_PRIO(1) |
2100 GS_PRIO(2) |
2101 ES_PRIO(3));
2102
d5e455e4
AD		 2103 switch (rdev->family) {
2104 case CHIP_CEDAR:
2105 case CHIP_PALM:
d5c5a72f
AD		 2106 case CHIP_SUMO:
2107 case CHIP_SUMO2:
adb68fa2 2108 case CHIP_CAICOS:
32fcdbf4
AD		 2109 /* no vertex cache */
2110 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 2111 break;
2112 default:
2113 break;
2114 }
32fcdbf4
AD		 2115
2116 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2117
2118 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2119 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2120 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2121 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2122 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2123 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2124 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2125
d5e455e4
AD		 2126 switch (rdev->family) {
2127 case CHIP_CEDAR:
2128 case CHIP_PALM:
d5c5a72f
AD		 2129 case CHIP_SUMO:
2130 case CHIP_SUMO2:
32fcdbf4 2131 ps_thread_count = 96;
d5e455e4
AD		 2132 break;
2133 default:
32fcdbf4 2134 ps_thread_count = 128;
d5e455e4
AD		 2135 break;
2136 }
32fcdbf4
AD		 2137
2138 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 2139 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2140 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2141 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2142 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2143 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 2144
2145 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2146 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2147 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2148 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2149 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2150 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2151
2152 WREG32(SQ_CONFIG, sq_config);
2153 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2154 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2155 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2156 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2157 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2158 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2159 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2160 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2161 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2162 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2163
2164 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2165 FORCE_EOV_MAX_REZ_CNT(255)));
2166
d5e455e4
AD		 2167 switch (rdev->family) {
2168 case CHIP_CEDAR:
2169 case CHIP_PALM:
d5c5a72f
AD		 2170 case CHIP_SUMO:
2171 case CHIP_SUMO2:
adb68fa2 2172 case CHIP_CAICOS:
32fcdbf4 2173 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 2174 break;
2175 default:
32fcdbf4 2176 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 2177 break;
2178 }
32fcdbf4
AD		 2179 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2180 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2181
2182 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 2183 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 2184 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2185
60a4a3e0
AD		 2186 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2187 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2188
32fcdbf4
AD		 2189 WREG32(CB_PERF_CTR0_SEL_0, 0);
2190 WREG32(CB_PERF_CTR0_SEL_1, 0);
2191 WREG32(CB_PERF_CTR1_SEL_0, 0);
2192 WREG32(CB_PERF_CTR1_SEL_1, 0);
2193 WREG32(CB_PERF_CTR2_SEL_0, 0);
2194 WREG32(CB_PERF_CTR2_SEL_1, 0);
2195 WREG32(CB_PERF_CTR3_SEL_0, 0);
2196 WREG32(CB_PERF_CTR3_SEL_1, 0);
2197
60a4a3e0
AD		 2198 /* clear render buffer base addresses */
2199 WREG32(CB_COLOR0_BASE, 0);
2200 WREG32(CB_COLOR1_BASE, 0);
2201 WREG32(CB_COLOR2_BASE, 0);
2202 WREG32(CB_COLOR3_BASE, 0);
2203 WREG32(CB_COLOR4_BASE, 0);
2204 WREG32(CB_COLOR5_BASE, 0);
2205 WREG32(CB_COLOR6_BASE, 0);
2206 WREG32(CB_COLOR7_BASE, 0);
2207 WREG32(CB_COLOR8_BASE, 0);
2208 WREG32(CB_COLOR9_BASE, 0);
2209 WREG32(CB_COLOR10_BASE, 0);
2210 WREG32(CB_COLOR11_BASE, 0);
2211
2212 /* set the shader const cache sizes to 0 */
2213 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2214 WREG32(i, 0);
2215 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2216 WREG32(i, 0);
2217
f25a5c63
AD		 2218 tmp = RREG32(HDP_MISC_CNTL);
2219 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2220 WREG32(HDP_MISC_CNTL, tmp);
2221
32fcdbf4
AD		 2222 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2223 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2224
2225 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2226
2227 udelay(50);
2228
bcc1c2a1
AD		 2229}
2230
2231int evergreen_mc_init(struct radeon_device *rdev)
2232{
bcc1c2a1
AD		 2233 u32 tmp;
2234 int chansize, numchan;
bcc1c2a1
AD		 2235
2236 /* Get VRAM informations */
2237 rdev->mc.vram_is_ddr = true;
05b3ef69
AD		 2238 if ((rdev->family == CHIP_PALM) ||
2239 (rdev->family == CHIP_SUMO) ||
2240 (rdev->family == CHIP_SUMO2))
8208441b
AD		 2241 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2242 else
2243 tmp = RREG32(MC_ARB_RAMCFG);
bcc1c2a1
AD		 2244 if (tmp & CHANSIZE_OVERRIDE) {
2245 chansize = 16;
2246 } else if (tmp & CHANSIZE_MASK) {
2247 chansize = 64;
2248 } else {
2249 chansize = 32;
2250 }
2251 tmp = RREG32(MC_SHARED_CHMAP);
2252 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2253 case 0:
2254 default:
2255 numchan = 1;
2256 break;
2257 case 1:
2258 numchan = 2;
2259 break;
2260 case 2:
2261 numchan = 4;
2262 break;
2263 case 3:
2264 numchan = 8;
2265 break;
2266 }
2267 rdev->mc.vram_width = numchan * chansize;
2268 /* Could aper size report 0 ? */
01d73a69
JC		 2269 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2270 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2271 /* Setup GPU memory space */
05b3ef69
AD		 2272 if ((rdev->family == CHIP_PALM) ||
2273 (rdev->family == CHIP_SUMO) ||
2274 (rdev->family == CHIP_SUMO2)) {
6eb18f8b
AD		 2275 /* size in bytes on fusion */
2276 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2277 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2278 } else {
05b3ef69 2279 /* size in MB on evergreen/cayman/tn */
6eb18f8b
AD		 2280 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2281 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2282 }
51e5fcd3 2283 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 2284 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2285 radeon_update_bandwidth_info(rdev);
2286
bcc1c2a1
AD		 2287 return 0;
2288}
d594e46a 2289
e32eb50d 2290bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 2291{
17db7042
AD		 2292 u32 srbm_status;
2293 u32 grbm_status;
2294 u32 grbm_status_se0, grbm_status_se1;
17db7042
AD		 2295
2296 srbm_status = RREG32(SRBM_STATUS);
2297 grbm_status = RREG32(GRBM_STATUS);
2298 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2299 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2300 if (!(grbm_status & GUI_ACTIVE)) {
069211e5 2301 radeon_ring_lockup_update(ring);
17db7042
AD		 2302 return false;
2303 }
2304 /* force CP activities */
7b9ef16b 2305 radeon_ring_force_activity(rdev, ring);
069211e5 2306 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 2307}
2308
0ecebb9e 2309static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
bcc1c2a1 2310{
0ecebb9e 2311 u32 grbm_reset = 0;
747943ea 2312
8d96fe93 2313 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
0ecebb9e 2314 return;
8d96fe93 2315
64c56e8c 2316 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
747943ea 2317 RREG32(GRBM_STATUS));
64c56e8c 2318 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
747943ea 2319 RREG32(GRBM_STATUS_SE0));
64c56e8c 2320 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
747943ea 2321 RREG32(GRBM_STATUS_SE1));
64c56e8c 2322 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
747943ea 2323 RREG32(SRBM_STATUS));
440a7cd8
JG		 2324 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2325 RREG32(CP_STALLED_STAT1));
2326 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2327 RREG32(CP_STALLED_STAT2));
2328 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2329 RREG32(CP_BUSY_STAT));
2330 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2331 RREG32(CP_STAT));
64c56e8c 2332
747943ea
AD		 2333 /* Disable CP parsing/prefetching */
2334 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2335
2336 /* reset all the gfx blocks */
2337 grbm_reset = (SOFT_RESET_CP |
2338 SOFT_RESET_CB |
2339 SOFT_RESET_DB |
2340 SOFT_RESET_PA |
2341 SOFT_RESET_SC |
2342 SOFT_RESET_SPI |
2343 SOFT_RESET_SH |
2344 SOFT_RESET_SX |
2345 SOFT_RESET_TC |
2346 SOFT_RESET_TA |
2347 SOFT_RESET_VC |
2348 SOFT_RESET_VGT);
2349
2350 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2351 WREG32(GRBM_SOFT_RESET, grbm_reset);
2352 (void)RREG32(GRBM_SOFT_RESET);
2353 udelay(50);
2354 WREG32(GRBM_SOFT_RESET, 0);
2355 (void)RREG32(GRBM_SOFT_RESET);
0ecebb9e 2356
64c56e8c 2357 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
747943ea 2358 RREG32(GRBM_STATUS));
64c56e8c 2359 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
747943ea 2360 RREG32(GRBM_STATUS_SE0));
64c56e8c 2361 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
747943ea 2362 RREG32(GRBM_STATUS_SE1));
64c56e8c 2363 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
747943ea 2364 RREG32(SRBM_STATUS));
440a7cd8
JG		 2365 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2366 RREG32(CP_STALLED_STAT1));
2367 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2368 RREG32(CP_STALLED_STAT2));
2369 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2370 RREG32(CP_BUSY_STAT));
2371 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2372 RREG32(CP_STAT));
0ecebb9e
AD		 2373}
2374
2375static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)
2376{
2377 u32 tmp;
2378
2379 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2380 return;
2381
2382 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2383 RREG32(DMA_STATUS_REG));
2384
2385 /* Disable DMA */
2386 tmp = RREG32(DMA_RB_CNTL);
2387 tmp &= ~DMA_RB_ENABLE;
2388 WREG32(DMA_RB_CNTL, tmp);
2389
2390 /* Reset dma */
2391 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2392 RREG32(SRBM_SOFT_RESET);
2393 udelay(50);
2394 WREG32(SRBM_SOFT_RESET, 0);
2395
eaaa6983
JG		 2396 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2397 RREG32(DMA_STATUS_REG));
0ecebb9e
AD		 2398}
2399
2400static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2401{
2402 struct evergreen_mc_save save;
2403
19fc42ed
AD		 2404 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2405 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
2406
2407 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2408 reset_mask &= ~RADEON_RESET_DMA;
2409
0ecebb9e
AD		 2410 if (reset_mask == 0)
2411 return 0;
2412
2413 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2414
2415 evergreen_mc_stop(rdev, &save);
2416 if (evergreen_mc_wait_for_idle(rdev)) {
2417 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2418 }
2419
2420 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
2421 evergreen_gpu_soft_reset_gfx(rdev);
2422
2423 if (reset_mask & RADEON_RESET_DMA)
2424 evergreen_gpu_soft_reset_dma(rdev);
2425
2426 /* Wait a little for things to settle down */
2427 udelay(50);
2428
747943ea 2429 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2430 return 0;
2431}
2432
a2d07b74 2433int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2434{
0ecebb9e
AD		 2435 return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
2436 RADEON_RESET_COMPUTE |
2437 RADEON_RESET_DMA));
747943ea
AD		 2438}
2439
45f9a39b
AD		 2440/* Interrupts */
2441
2442u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2443{
46437057 2444 if (crtc >= rdev->num_crtc)
45f9a39b 2445 return 0;
46437057
AD		 2446 else
2447 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
45f9a39b
AD		 2448}
2449
2450void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2451{
2452 u32 tmp;
2453
1b37078b
AD		 2454 if (rdev->family >= CHIP_CAYMAN) {
2455 cayman_cp_int_cntl_setup(rdev, 0,
2456 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2457 cayman_cp_int_cntl_setup(rdev, 1, 0);
2458 cayman_cp_int_cntl_setup(rdev, 2, 0);
f60cbd11
AD		 2459 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2460 WREG32(CAYMAN_DMA1_CNTL, tmp);
1b37078b
AD		 2461 } else
2462 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
233d1ad5
AD		 2463 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2464 WREG32(DMA_CNTL, tmp);
45f9a39b
AD		 2465 WREG32(GRBM_INT_CNTL, 0);
2466 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2467 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2468 if (rdev->num_crtc >= 4) {
18007401
AD		 2469 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2470 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2471 }
2472 if (rdev->num_crtc >= 6) {
18007401
AD		 2473 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2474 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2475 }
45f9a39b
AD		 2476
2477 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2478 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2479 if (rdev->num_crtc >= 4) {
18007401
AD		 2480 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2481 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2482 }
2483 if (rdev->num_crtc >= 6) {
18007401
AD		 2484 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2485 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2486 }
45f9a39b 2487
05b3ef69
AD		 2488 /* only one DAC on DCE6 */
2489 if (!ASIC_IS_DCE6(rdev))
2490 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
45f9a39b
AD		 2491 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2492
2493 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2494 WREG32(DC_HPD1_INT_CONTROL, tmp);
2495 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2496 WREG32(DC_HPD2_INT_CONTROL, tmp);
2497 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2498 WREG32(DC_HPD3_INT_CONTROL, tmp);
2499 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2500 WREG32(DC_HPD4_INT_CONTROL, tmp);
2501 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2502 WREG32(DC_HPD5_INT_CONTROL, tmp);
2503 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2504 WREG32(DC_HPD6_INT_CONTROL, tmp);
2505
2506}
2507
2508int evergreen_irq_set(struct radeon_device *rdev)
2509{
2510 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1b37078b 2511 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
45f9a39b
AD		 2512 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2513 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2514 u32 grbm_int_cntl = 0;
6f34be50 2515 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
f122c610 2516 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
f60cbd11 2517 u32 dma_cntl, dma_cntl1 = 0;
45f9a39b
AD		 2518
2519 if (!rdev->irq.installed) {
fce7d61b 2520 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2521 return -EINVAL;
2522 }
2523 /* don't enable anything if the ih is disabled */
2524 if (!rdev->ih.enabled) {
2525 r600_disable_interrupts(rdev);
2526 /* force the active interrupt state to all disabled */
2527 evergreen_disable_interrupt_state(rdev);
2528 return 0;
2529 }
2530
2531 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2532 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2533 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2534 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2535 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2536 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2537
f122c610
AD		 2538 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2539 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2540 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2541 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2542 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2543 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2544
233d1ad5
AD		 2545 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2546
1b37078b
AD		 2547 if (rdev->family >= CHIP_CAYMAN) {
2548 /* enable CP interrupts on all rings */
736fc37f 2549 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 2550 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2551 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2552 }
736fc37f 2553 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
1b37078b
AD		 2554 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2555 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2556 }
736fc37f 2557 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
1b37078b
AD		 2558 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2559 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2560 }
2561 } else {
736fc37f 2562 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 2563 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2564 cp_int_cntl |= RB_INT_ENABLE;
2565 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2566 }
45f9a39b 2567 }
1b37078b 2568
233d1ad5
AD		 2569 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
2570 DRM_DEBUG("r600_irq_set: sw int dma\n");
2571 dma_cntl |= TRAP_ENABLE;
2572 }
2573
f60cbd11
AD		 2574 if (rdev->family >= CHIP_CAYMAN) {
2575 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2576 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
2577 DRM_DEBUG("r600_irq_set: sw int dma1\n");
2578 dma_cntl1 |= TRAP_ENABLE;
2579 }
2580 }
2581
6f34be50 2582 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 2583 atomic_read(&rdev->irq.pflip[0])) {
45f9a39b
AD		 2584 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2585 crtc1 |= VBLANK_INT_MASK;
2586 }
6f34be50 2587 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 2588 atomic_read(&rdev->irq.pflip[1])) {
45f9a39b
AD		 2589 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2590 crtc2 |= VBLANK_INT_MASK;
2591 }
6f34be50 2592 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 2593 atomic_read(&rdev->irq.pflip[2])) {
45f9a39b
AD		 2594 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2595 crtc3 |= VBLANK_INT_MASK;
2596 }
6f34be50 2597 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 2598 atomic_read(&rdev->irq.pflip[3])) {
45f9a39b
AD		 2599 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2600 crtc4 |= VBLANK_INT_MASK;
2601 }
6f34be50 2602 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 2603 atomic_read(&rdev->irq.pflip[4])) {
45f9a39b
AD		 2604 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2605 crtc5 |= VBLANK_INT_MASK;
2606 }
6f34be50 2607 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 2608 atomic_read(&rdev->irq.pflip[5])) {
45f9a39b
AD		 2609 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2610 crtc6 |= VBLANK_INT_MASK;
2611 }
2612 if (rdev->irq.hpd[0]) {
2613 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2614 hpd1 |= DC_HPDx_INT_EN;
2615 }
2616 if (rdev->irq.hpd[1]) {
2617 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2618 hpd2 |= DC_HPDx_INT_EN;
2619 }
2620 if (rdev->irq.hpd[2]) {
2621 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2622 hpd3 |= DC_HPDx_INT_EN;
2623 }
2624 if (rdev->irq.hpd[3]) {
2625 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2626 hpd4 |= DC_HPDx_INT_EN;
2627 }
2628 if (rdev->irq.hpd[4]) {
2629 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2630 hpd5 |= DC_HPDx_INT_EN;
2631 }
2632 if (rdev->irq.hpd[5]) {
2633 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2634 hpd6 |= DC_HPDx_INT_EN;
2635 }
f122c610
AD		 2636 if (rdev->irq.afmt[0]) {
2637 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2638 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2639 }
2640 if (rdev->irq.afmt[1]) {
2641 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2642 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2643 }
2644 if (rdev->irq.afmt[2]) {
2645 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2646 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2647 }
2648 if (rdev->irq.afmt[3]) {
2649 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2650 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2651 }
2652 if (rdev->irq.afmt[4]) {
2653 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2654 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2655 }
2656 if (rdev->irq.afmt[5]) {
2657 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2658 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2659 }
45f9a39b 2660
1b37078b
AD		 2661 if (rdev->family >= CHIP_CAYMAN) {
2662 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2663 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2664 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2665 } else
2666 WREG32(CP_INT_CNTL, cp_int_cntl);
233d1ad5
AD		 2667
2668 WREG32(DMA_CNTL, dma_cntl);
2669
f60cbd11
AD		 2670 if (rdev->family >= CHIP_CAYMAN)
2671 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
2672
2031f77c 2673 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2674
2675 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2676 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
b7eff394 2677 if (rdev->num_crtc >= 4) {
18007401
AD		 2678 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2679 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
b7eff394
AD		 2680 }
2681 if (rdev->num_crtc >= 6) {
18007401
AD		 2682 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2683 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2684 }
45f9a39b 2685
6f34be50
AD		 2686 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2687 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
b7eff394
AD		 2688 if (rdev->num_crtc >= 4) {
2689 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2690 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2691 }
2692 if (rdev->num_crtc >= 6) {
2693 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2694 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2695 }
6f34be50 2696
45f9a39b
AD		 2697 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2698 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2699 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2700 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2701 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2702 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2703
f122c610
AD		 2704 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2705 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2706 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2707 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2708 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2709 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2710
bcc1c2a1
AD		 2711 return 0;
2712}
2713
cbdd4501 2714static void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2715{
2716 u32 tmp;
2717
6f34be50
AD		 2718 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2719 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2720 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2721 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2722 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2723 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2724 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2725 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 2726 if (rdev->num_crtc >= 4) {
2727 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2728 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2729 }
2730 if (rdev->num_crtc >= 6) {
2731 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2732 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2733 }
6f34be50 2734
f122c610
AD		 2735 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2736 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2737 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2738 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2739 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2740 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2741
6f34be50
AD		 2742 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2743 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2744 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2745 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6f34be50 2746 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2747 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2748 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b 2749 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6f34be50 2750 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2751 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2752 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2753 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2754
b7eff394
AD		 2755 if (rdev->num_crtc >= 4) {
2756 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2757 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2758 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2759 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2760 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2761 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2762 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2763 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2764 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2765 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2766 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2767 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2768 }
2769
2770 if (rdev->num_crtc >= 6) {
2771 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2772 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2773 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2774 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2775 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2776 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2777 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2778 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2779 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2780 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2781 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2782 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2783 }
45f9a39b 2784
6f34be50 2785 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2786 tmp = RREG32(DC_HPD1_INT_CONTROL);
2787 tmp |= DC_HPDx_INT_ACK;
2788 WREG32(DC_HPD1_INT_CONTROL, tmp);
2789 }
6f34be50 2790 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2791 tmp = RREG32(DC_HPD2_INT_CONTROL);
2792 tmp |= DC_HPDx_INT_ACK;
2793 WREG32(DC_HPD2_INT_CONTROL, tmp);
2794 }
6f34be50 2795 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2796 tmp = RREG32(DC_HPD3_INT_CONTROL);
2797 tmp |= DC_HPDx_INT_ACK;
2798 WREG32(DC_HPD3_INT_CONTROL, tmp);
2799 }
6f34be50 2800 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2801 tmp = RREG32(DC_HPD4_INT_CONTROL);
2802 tmp |= DC_HPDx_INT_ACK;
2803 WREG32(DC_HPD4_INT_CONTROL, tmp);
2804 }
6f34be50 2805 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2806 tmp = RREG32(DC_HPD5_INT_CONTROL);
2807 tmp |= DC_HPDx_INT_ACK;
2808 WREG32(DC_HPD5_INT_CONTROL, tmp);
2809 }
6f34be50 2810 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2811 tmp = RREG32(DC_HPD5_INT_CONTROL);
2812 tmp |= DC_HPDx_INT_ACK;
2813 WREG32(DC_HPD6_INT_CONTROL, tmp);
2814 }
f122c610
AD		 2815 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2816 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2817 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2818 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2819 }
2820 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2821 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2822 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2823 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2824 }
2825 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2826 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2827 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2828 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2829 }
2830 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2831 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2832 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2833 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2834 }
2835 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2836 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2837 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2838 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2839 }
2840 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2841 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2842 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2843 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2844 }
45f9a39b
AD		 2845}
2846
1109ca09 2847static void evergreen_irq_disable(struct radeon_device *rdev)
45f9a39b 2848{
45f9a39b
AD		 2849 r600_disable_interrupts(rdev);
2850 /* Wait and acknowledge irq */
2851 mdelay(1);
6f34be50 2852 evergreen_irq_ack(rdev);
45f9a39b
AD		 2853 evergreen_disable_interrupt_state(rdev);
2854}
2855
755d819e 2856void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 2857{
2858 evergreen_irq_disable(rdev);
2859 r600_rlc_stop(rdev);
2860}
2861
cbdd4501 2862static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
45f9a39b
AD		 2863{
2864 u32 wptr, tmp;
2865
724c80e1 2866 if (rdev->wb.enabled)
204ae24d 2867 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 2868 else
2869 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2870
2871 if (wptr & RB_OVERFLOW) {
2872 /* When a ring buffer overflow happen start parsing interrupt
2873 * from the last not overwritten vector (wptr + 16). Hopefully
2874 * this should allow us to catchup.
2875 */
2876 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2877 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2878 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2879 tmp = RREG32(IH_RB_CNTL);
2880 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2881 WREG32(IH_RB_CNTL, tmp);
2882 }
2883 return (wptr & rdev->ih.ptr_mask);
2884}
2885
2886int evergreen_irq_process(struct radeon_device *rdev)
2887{
682f1a54
DA		 2888 u32 wptr;
2889 u32 rptr;
45f9a39b
AD		 2890 u32 src_id, src_data;
2891 u32 ring_index;
45f9a39b 2892 bool queue_hotplug = false;
f122c610 2893 bool queue_hdmi = false;
45f9a39b 2894
682f1a54 2895 if (!rdev->ih.enabled || rdev->shutdown)
45f9a39b
AD		 2896 return IRQ_NONE;
2897
682f1a54 2898 wptr = evergreen_get_ih_wptr(rdev);
c20dc369
CK		 2899
2900restart_ih:
2901 /* is somebody else already processing irqs? */
2902 if (atomic_xchg(&rdev->ih.lock, 1))
2903 return IRQ_NONE;
2904
682f1a54
DA		 2905 rptr = rdev->ih.rptr;
2906 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
45f9a39b 2907
964f6645
BH		 2908 /* Order reading of wptr vs. reading of IH ring data */
2909 rmb();
2910
45f9a39b 2911 /* display interrupts */
6f34be50 2912 evergreen_irq_ack(rdev);
45f9a39b 2913
45f9a39b
AD		 2914 while (rptr != wptr) {
2915 /* wptr/rptr are in bytes! */
2916 ring_index = rptr / 4;
0f234f5f
AD		 2917 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2918 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 2919
2920 switch (src_id) {
2921 case 1: /* D1 vblank/vline */
2922 switch (src_data) {
2923 case 0: /* D1 vblank */
6f34be50 2924 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 2925 if (rdev->irq.crtc_vblank_int[0]) {
2926 drm_handle_vblank(rdev->ddev, 0);
2927 rdev->pm.vblank_sync = true;
2928 wake_up(&rdev->irq.vblank_queue);
2929 }
736fc37f 2930 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 2931 radeon_crtc_handle_flip(rdev, 0);
6f34be50 2932 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 2933 DRM_DEBUG("IH: D1 vblank\n");
2934 }
2935 break;
2936 case 1: /* D1 vline */
6f34be50
AD		 2937 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2938 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 2939 DRM_DEBUG("IH: D1 vline\n");
2940 }
2941 break;
2942 default:
2943 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2944 break;
2945 }
2946 break;
2947 case 2: /* D2 vblank/vline */
2948 switch (src_data) {
2949 case 0: /* D2 vblank */
6f34be50 2950 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 2951 if (rdev->irq.crtc_vblank_int[1]) {
2952 drm_handle_vblank(rdev->ddev, 1);
2953 rdev->pm.vblank_sync = true;
2954 wake_up(&rdev->irq.vblank_queue);
2955 }
736fc37f 2956 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 2957 radeon_crtc_handle_flip(rdev, 1);
6f34be50 2958 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 2959 DRM_DEBUG("IH: D2 vblank\n");
2960 }
2961 break;
2962 case 1: /* D2 vline */
6f34be50
AD		 2963 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2964 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 2965 DRM_DEBUG("IH: D2 vline\n");
2966 }
2967 break;
2968 default:
2969 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2970 break;
2971 }
2972 break;
2973 case 3: /* D3 vblank/vline */
2974 switch (src_data) {
2975 case 0: /* D3 vblank */
6f34be50
AD		 2976 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2977 if (rdev->irq.crtc_vblank_int[2]) {
2978 drm_handle_vblank(rdev->ddev, 2);
2979 rdev->pm.vblank_sync = true;
2980 wake_up(&rdev->irq.vblank_queue);
2981 }
736fc37f 2982 if (atomic_read(&rdev->irq.pflip[2]))
6f34be50
AD		 2983 radeon_crtc_handle_flip(rdev, 2);
2984 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 2985 DRM_DEBUG("IH: D3 vblank\n");
2986 }
2987 break;
2988 case 1: /* D3 vline */
6f34be50
AD		 2989 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2990 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 2991 DRM_DEBUG("IH: D3 vline\n");
2992 }
2993 break;
2994 default:
2995 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2996 break;
2997 }
2998 break;
2999 case 4: /* D4 vblank/vline */
3000 switch (src_data) {
3001 case 0: /* D4 vblank */
6f34be50
AD		 3002 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3003 if (rdev->irq.crtc_vblank_int[3]) {
3004 drm_handle_vblank(rdev->ddev, 3);
3005 rdev->pm.vblank_sync = true;
3006 wake_up(&rdev->irq.vblank_queue);
3007 }
736fc37f 3008 if (atomic_read(&rdev->irq.pflip[3]))
6f34be50
AD		 3009 radeon_crtc_handle_flip(rdev, 3);
3010 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 3011 DRM_DEBUG("IH: D4 vblank\n");
3012 }
3013 break;
3014 case 1: /* D4 vline */
6f34be50
AD		 3015 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3016 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 3017 DRM_DEBUG("IH: D4 vline\n");
3018 }
3019 break;
3020 default:
3021 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3022 break;
3023 }
3024 break;
3025 case 5: /* D5 vblank/vline */
3026 switch (src_data) {
3027 case 0: /* D5 vblank */
6f34be50
AD		 3028 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3029 if (rdev->irq.crtc_vblank_int[4]) {
3030 drm_handle_vblank(rdev->ddev, 4);
3031 rdev->pm.vblank_sync = true;
3032 wake_up(&rdev->irq.vblank_queue);
3033 }
736fc37f 3034 if (atomic_read(&rdev->irq.pflip[4]))
6f34be50
AD		 3035 radeon_crtc_handle_flip(rdev, 4);
3036 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 3037 DRM_DEBUG("IH: D5 vblank\n");
3038 }
3039 break;
3040 case 1: /* D5 vline */
6f34be50
AD		 3041 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3042 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 3043 DRM_DEBUG("IH: D5 vline\n");
3044 }
3045 break;
3046 default:
3047 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3048 break;
3049 }
3050 break;
3051 case 6: /* D6 vblank/vline */
3052 switch (src_data) {
3053 case 0: /* D6 vblank */
6f34be50
AD		 3054 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3055 if (rdev->irq.crtc_vblank_int[5]) {
3056 drm_handle_vblank(rdev->ddev, 5);
3057 rdev->pm.vblank_sync = true;
3058 wake_up(&rdev->irq.vblank_queue);
3059 }
736fc37f 3060 if (atomic_read(&rdev->irq.pflip[5]))
6f34be50
AD		 3061 radeon_crtc_handle_flip(rdev, 5);
3062 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 3063 DRM_DEBUG("IH: D6 vblank\n");
3064 }
3065 break;
3066 case 1: /* D6 vline */
6f34be50
AD		 3067 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3068 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 3069 DRM_DEBUG("IH: D6 vline\n");
3070 }
3071 break;
3072 default:
3073 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3074 break;
3075 }
3076 break;
3077 case 42: /* HPD hotplug */
3078 switch (src_data) {
3079 case 0:
6f34be50
AD		 3080 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3081 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 3082 queue_hotplug = true;
3083 DRM_DEBUG("IH: HPD1\n");
3084 }
3085 break;
3086 case 1:
6f34be50
AD		 3087 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3088 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 3089 queue_hotplug = true;
3090 DRM_DEBUG("IH: HPD2\n");
3091 }
3092 break;
3093 case 2:
6f34be50
AD		 3094 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3095 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 3096 queue_hotplug = true;
3097 DRM_DEBUG("IH: HPD3\n");
3098 }
3099 break;
3100 case 3:
6f34be50
AD		 3101 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3102 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 3103 queue_hotplug = true;
3104 DRM_DEBUG("IH: HPD4\n");
3105 }
3106 break;
3107 case 4:
6f34be50
AD		 3108 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3109 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 3110 queue_hotplug = true;
3111 DRM_DEBUG("IH: HPD5\n");
3112 }
3113 break;
3114 case 5:
6f34be50
AD		 3115 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3116 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 3117 queue_hotplug = true;
3118 DRM_DEBUG("IH: HPD6\n");
3119 }
3120 break;
3121 default:
3122 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3123 break;
3124 }
3125 break;
f122c610
AD		 3126 case 44: /* hdmi */
3127 switch (src_data) {
3128 case 0:
3129 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3130 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3131 queue_hdmi = true;
3132 DRM_DEBUG("IH: HDMI0\n");
3133 }
3134 break;
3135 case 1:
3136 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3137 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3138 queue_hdmi = true;
3139 DRM_DEBUG("IH: HDMI1\n");
3140 }
3141 break;
3142 case 2:
3143 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3144 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3145 queue_hdmi = true;
3146 DRM_DEBUG("IH: HDMI2\n");
3147 }
3148 break;
3149 case 3:
3150 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3151 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3152 queue_hdmi = true;
3153 DRM_DEBUG("IH: HDMI3\n");
3154 }
3155 break;
3156 case 4:
3157 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3158 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3159 queue_hdmi = true;
3160 DRM_DEBUG("IH: HDMI4\n");
3161 }
3162 break;
3163 case 5:
3164 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3165 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3166 queue_hdmi = true;
3167 DRM_DEBUG("IH: HDMI5\n");
3168 }
3169 break;
3170 default:
3171 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3172 break;
3173 }
3174 break;
ae133a11
CK		 3175 case 146:
3176 case 147:
3177 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3178 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3179 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3180 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3181 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3182 /* reset addr and status */
3183 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3184 break;
45f9a39b
AD		 3185 case 176: /* CP_INT in ring buffer */
3186 case 177: /* CP_INT in IB1 */
3187 case 178: /* CP_INT in IB2 */
3188 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3189 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b
AD		 3190 break;
3191 case 181: /* CP EOP event */
3192 DRM_DEBUG("IH: CP EOP\n");
1b37078b
AD		 3193 if (rdev->family >= CHIP_CAYMAN) {
3194 switch (src_data) {
3195 case 0:
3196 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3197 break;
3198 case 1:
3199 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3200 break;
3201 case 2:
3202 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3203 break;
3204 }
3205 } else
3206 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b 3207 break;
233d1ad5
AD		 3208 case 224: /* DMA trap event */
3209 DRM_DEBUG("IH: DMA trap\n");
3210 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3211 break;
2031f77c 3212 case 233: /* GUI IDLE */
303c805c 3213 DRM_DEBUG("IH: GUI idle\n");
2031f77c 3214 break;
f60cbd11
AD		 3215 case 244: /* DMA trap event */
3216 if (rdev->family >= CHIP_CAYMAN) {
3217 DRM_DEBUG("IH: DMA1 trap\n");
3218 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
3219 }
3220 break;
45f9a39b
AD		 3221 default:
3222 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3223 break;
3224 }
3225
3226 /* wptr/rptr are in bytes! */
3227 rptr += 16;
3228 rptr &= rdev->ih.ptr_mask;
3229 }
45f9a39b 3230 if (queue_hotplug)
32c87fca 3231 schedule_work(&rdev->hotplug_work);
f122c610
AD		 3232 if (queue_hdmi)
3233 schedule_work(&rdev->audio_work);
45f9a39b
AD		 3234 rdev->ih.rptr = rptr;
3235 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 3236 atomic_set(&rdev->ih.lock, 0);
3237
3238 /* make sure wptr hasn't changed while processing */
3239 wptr = evergreen_get_ih_wptr(rdev);
3240 if (wptr != rptr)
3241 goto restart_ih;
3242
45f9a39b
AD		 3243 return IRQ_HANDLED;
3244}
3245
233d1ad5
AD		 3246/**
3247 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
3248 *
3249 * @rdev: radeon_device pointer
3250 * @fence: radeon fence object
3251 *
3252 * Add a DMA fence packet to the ring to write
3253 * the fence seq number and DMA trap packet to generate
3254 * an interrupt if needed (evergreen-SI).
3255 */
3256void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
3257 struct radeon_fence *fence)
3258{
3259 struct radeon_ring *ring = &rdev->ring[fence->ring];
3260 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3261 /* write the fence */
3262 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
3263 radeon_ring_write(ring, addr & 0xfffffffc);
3264 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3265 radeon_ring_write(ring, fence->seq);
3266 /* generate an interrupt */
3267 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
3268 /* flush HDP */
3269 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
4b681c28 3270 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
233d1ad5
AD		 3271 radeon_ring_write(ring, 1);
3272}
3273
3274/**
3275 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
3276 *
3277 * @rdev: radeon_device pointer
3278 * @ib: IB object to schedule
3279 *
3280 * Schedule an IB in the DMA ring (evergreen).
3281 */
3282void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
3283 struct radeon_ib *ib)
3284{
3285 struct radeon_ring *ring = &rdev->ring[ib->ring];
3286
3287 if (rdev->wb.enabled) {
3288 u32 next_rptr = ring->wptr + 4;
3289 while ((next_rptr & 7) != 5)
3290 next_rptr++;
3291 next_rptr += 3;
3292 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3293 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3294 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3295 radeon_ring_write(ring, next_rptr);
3296 }
3297
3298 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3299 * Pad as necessary with NOPs.
3300 */
3301 while ((ring->wptr & 7) != 5)
3302 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3303 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3304 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3305 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3306
3307}
3308
3309/**
3310 * evergreen_copy_dma - copy pages using the DMA engine
3311 *
3312 * @rdev: radeon_device pointer
3313 * @src_offset: src GPU address
3314 * @dst_offset: dst GPU address
3315 * @num_gpu_pages: number of GPU pages to xfer
3316 * @fence: radeon fence object
3317 *
3318 * Copy GPU paging using the DMA engine (evergreen-cayman).
3319 * Used by the radeon ttm implementation to move pages if
3320 * registered as the asic copy callback.
3321 */
3322int evergreen_copy_dma(struct radeon_device *rdev,
3323 uint64_t src_offset, uint64_t dst_offset,
3324 unsigned num_gpu_pages,
3325 struct radeon_fence **fence)
3326{
3327 struct radeon_semaphore *sem = NULL;
3328 int ring_index = rdev->asic->copy.dma_ring_index;
3329 struct radeon_ring *ring = &rdev->ring[ring_index];
3330 u32 size_in_dw, cur_size_in_dw;
3331 int i, num_loops;
3332 int r = 0;
3333
3334 r = radeon_semaphore_create(rdev, &sem);
3335 if (r) {
3336 DRM_ERROR("radeon: moving bo (%d).\n", r);
3337 return r;
3338 }
3339
3340 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3341 num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
3342 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
3343 if (r) {
3344 DRM_ERROR("radeon: moving bo (%d).\n", r);
3345 radeon_semaphore_free(rdev, &sem, NULL);
3346 return r;
3347 }
3348
3349 if (radeon_fence_need_sync(*fence, ring->idx)) {
3350 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3351 ring->idx);
3352 radeon_fence_note_sync(*fence, ring->idx);
3353 } else {
3354 radeon_semaphore_free(rdev, &sem, NULL);
3355 }
3356
3357 for (i = 0; i < num_loops; i++) {
3358 cur_size_in_dw = size_in_dw;
3359 if (cur_size_in_dw > 0xFFFFF)
3360 cur_size_in_dw = 0xFFFFF;
3361 size_in_dw -= cur_size_in_dw;
3362 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
3363 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3364 radeon_ring_write(ring, src_offset & 0xfffffffc);
3365 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3366 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
3367 src_offset += cur_size_in_dw * 4;
3368 dst_offset += cur_size_in_dw * 4;
3369 }
3370
3371 r = radeon_fence_emit(rdev, fence, ring->idx);
3372 if (r) {
3373 radeon_ring_unlock_undo(rdev, ring);
3374 return r;
3375 }
3376
3377 radeon_ring_unlock_commit(rdev, ring);
3378 radeon_semaphore_free(rdev, &sem, *fence);
3379
3380 return r;
3381}
3382
bcc1c2a1
AD		 3383static int evergreen_startup(struct radeon_device *rdev)
3384{
e32eb50d 3385 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
bcc1c2a1
AD		 3386 int r;
3387
9e46a48d 3388 /* enable pcie gen2 link */
cd54033a 3389 evergreen_pcie_gen2_enable(rdev);
9e46a48d 3390
0af62b01
AD		 3391 if (ASIC_IS_DCE5(rdev)) {
3392 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3393 r = ni_init_microcode(rdev);
3394 if (r) {
3395 DRM_ERROR("Failed to load firmware!\n");
3396 return r;
3397 }
3398 }
755d819e 3399 r = ni_mc_load_microcode(rdev);
bcc1c2a1 3400 if (r) {
0af62b01 3401 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 3402 return r;
3403 }
0af62b01
AD		 3404 } else {
3405 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3406 r = r600_init_microcode(rdev);
3407 if (r) {
3408 DRM_ERROR("Failed to load firmware!\n");
3409 return r;
3410 }
3411 }
bcc1c2a1 3412 }
fe251e2f 3413
16cdf04d
AD		 3414 r = r600_vram_scratch_init(rdev);
3415 if (r)
3416 return r;
3417
bcc1c2a1 3418 evergreen_mc_program(rdev);
bcc1c2a1 3419 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 3420 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 3421 } else {
3422 r = evergreen_pcie_gart_enable(rdev);
3423 if (r)
3424 return r;
3425 }
bcc1c2a1 3426 evergreen_gpu_init(rdev);
bcc1c2a1 3427
d7ccd8fc 3428 r = evergreen_blit_init(rdev);
bcc1c2a1 3429 if (r) {
fb3d9e97 3430 r600_blit_fini(rdev);
27cd7769 3431 rdev->asic->copy.copy = NULL;
d7ccd8fc 3432 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 3433 }
3434
724c80e1
AD		 3435 /* allocate wb buffer */
3436 r = radeon_wb_init(rdev);
3437 if (r)
3438 return r;
3439
30eb77f4
JG		 3440 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3441 if (r) {
3442 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3443 return r;
3444 }
3445
233d1ad5
AD		 3446 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3447 if (r) {
3448 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3449 return r;
3450 }
3451
bcc1c2a1
AD		 3452 /* Enable IRQ */
3453 r = r600_irq_init(rdev);
3454 if (r) {
3455 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3456 radeon_irq_kms_fini(rdev);
3457 return r;
3458 }
45f9a39b 3459 evergreen_irq_set(rdev);
bcc1c2a1 3460
e32eb50d 3461 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 3462 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3463 0, 0xfffff, RADEON_CP_PACKET2);
bcc1c2a1
AD		 3464 if (r)
3465 return r;
233d1ad5
AD		 3466
3467 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3468 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3469 DMA_RB_RPTR, DMA_RB_WPTR,
3470 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3471 if (r)
3472 return r;
3473
bcc1c2a1
AD		 3474 r = evergreen_cp_load_microcode(rdev);
3475 if (r)
3476 return r;
fe251e2f 3477 r = evergreen_cp_resume(rdev);
233d1ad5
AD		 3478 if (r)
3479 return r;
3480 r = r600_dma_resume(rdev);
bcc1c2a1
AD		 3481 if (r)
3482 return r;
fe251e2f 3483
2898c348
CK		 3484 r = radeon_ib_pool_init(rdev);
3485 if (r) {
3486 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3487 return r;
2898c348 3488 }
b15ba512 3489
69d2ae57
RM		 3490 r = r600_audio_init(rdev);
3491 if (r) {
3492 DRM_ERROR("radeon: audio init failed\n");
b15ba512
JG		 3493 return r;
3494 }
3495
bcc1c2a1
AD		 3496 return 0;
3497}
3498
3499int evergreen_resume(struct radeon_device *rdev)
3500{
3501 int r;
3502
86f5c9ed
AD		 3503 /* reset the asic, the gfx blocks are often in a bad state
3504 * after the driver is unloaded or after a resume
3505 */
3506 if (radeon_asic_reset(rdev))
3507 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 3508 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3509 * posting will perform necessary task to bring back GPU into good
3510 * shape.
3511 */
3512 /* post card */
3513 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1 3514
b15ba512 3515 rdev->accel_working = true;
bcc1c2a1
AD		 3516 r = evergreen_startup(rdev);
3517 if (r) {
755d819e 3518 DRM_ERROR("evergreen startup failed on resume\n");
6b7746e8 3519 rdev->accel_working = false;
bcc1c2a1
AD		 3520 return r;
3521 }
fe251e2f 3522
bcc1c2a1
AD		 3523 return r;
3524
3525}
3526
3527int evergreen_suspend(struct radeon_device *rdev)
3528{
69d2ae57 3529 r600_audio_fini(rdev);
bcc1c2a1 3530 r700_cp_stop(rdev);
233d1ad5 3531 r600_dma_stop(rdev);
45f9a39b 3532 evergreen_irq_suspend(rdev);
724c80e1 3533 radeon_wb_disable(rdev);
bcc1c2a1 3534 evergreen_pcie_gart_disable(rdev);
d7ccd8fc
AD		 3535
3536 return 0;
3537}
3538
bcc1c2a1
AD		 3539/* Plan is to move initialization in that function and use
3540 * helper function so that radeon_device_init pretty much
3541 * do nothing more than calling asic specific function. This
3542 * should also allow to remove a bunch of callback function
3543 * like vram_info.
3544 */
3545int evergreen_init(struct radeon_device *rdev)
3546{
3547 int r;
3548
bcc1c2a1
AD		 3549 /* Read BIOS */
3550 if (!radeon_get_bios(rdev)) {
3551 if (ASIC_IS_AVIVO(rdev))
3552 return -EINVAL;
3553 }
3554 /* Must be an ATOMBIOS */
3555 if (!rdev->is_atom_bios) {
755d819e 3556 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 3557 return -EINVAL;
3558 }
3559 r = radeon_atombios_init(rdev);
3560 if (r)
3561 return r;
86f5c9ed
AD		 3562 /* reset the asic, the gfx blocks are often in a bad state
3563 * after the driver is unloaded or after a resume
3564 */
3565 if (radeon_asic_reset(rdev))
3566 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 3567 /* Post card if necessary */
fd909c37 3568 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 3569 if (!rdev->bios) {
3570 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3571 return -EINVAL;
3572 }
3573 DRM_INFO("GPU not posted. posting now...\n");
3574 atom_asic_init(rdev->mode_info.atom_context);
3575 }
3576 /* Initialize scratch registers */
3577 r600_scratch_init(rdev);
3578 /* Initialize surface registers */
3579 radeon_surface_init(rdev);
3580 /* Initialize clocks */
3581 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 3582 /* Fence driver */
3583 r = radeon_fence_driver_init(rdev);
3584 if (r)
3585 return r;
d594e46a
JG		 3586 /* initialize AGP */
3587 if (rdev->flags & RADEON_IS_AGP) {
3588 r = radeon_agp_init(rdev);
3589 if (r)
3590 radeon_agp_disable(rdev);
3591 }
3592 /* initialize memory controller */
bcc1c2a1
AD		 3593 r = evergreen_mc_init(rdev);
3594 if (r)
3595 return r;
3596 /* Memory manager */
3597 r = radeon_bo_init(rdev);
3598 if (r)
3599 return r;
45f9a39b 3600
bcc1c2a1
AD		 3601 r = radeon_irq_kms_init(rdev);
3602 if (r)
3603 return r;
3604
e32eb50d
CK		 3605 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3606 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
bcc1c2a1 3607
233d1ad5
AD		 3608 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3609 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3610
bcc1c2a1
AD		 3611 rdev->ih.ring_obj = NULL;
3612 r600_ih_ring_init(rdev, 64 * 1024);
3613
3614 r = r600_pcie_gart_init(rdev);
3615 if (r)
3616 return r;
0fcdb61e 3617
148a03bc 3618 rdev->accel_working = true;
bcc1c2a1
AD		 3619 r = evergreen_startup(rdev);
3620 if (r) {
fe251e2f
AD		 3621 dev_err(rdev->dev, "disabling GPU acceleration\n");
3622 r700_cp_fini(rdev);
233d1ad5 3623 r600_dma_fini(rdev);
fe251e2f 3624 r600_irq_fini(rdev);
724c80e1 3625 radeon_wb_fini(rdev);
2898c348 3626 radeon_ib_pool_fini(rdev);
fe251e2f 3627 radeon_irq_kms_fini(rdev);
0fcdb61e 3628 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3629 rdev->accel_working = false;
3630 }
77e00f2e
AD		 3631
3632 /* Don't start up if the MC ucode is missing on BTC parts.
3633 * The default clocks and voltages before the MC ucode
3634 * is loaded are not suffient for advanced operations.
3635 */
3636 if (ASIC_IS_DCE5(rdev)) {
3637 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3638 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3639 return -EINVAL;
3640 }
3641 }
3642
bcc1c2a1
AD		 3643 return 0;
3644}
3645
3646void evergreen_fini(struct radeon_device *rdev)
3647{
69d2ae57 3648 r600_audio_fini(rdev);
fb3d9e97 3649 r600_blit_fini(rdev);
45f9a39b 3650 r700_cp_fini(rdev);
233d1ad5 3651 r600_dma_fini(rdev);
bcc1c2a1 3652 r600_irq_fini(rdev);
724c80e1 3653 radeon_wb_fini(rdev);
2898c348 3654 radeon_ib_pool_fini(rdev);
bcc1c2a1 3655 radeon_irq_kms_fini(rdev);
bcc1c2a1 3656 evergreen_pcie_gart_fini(rdev);
16cdf04d 3657 r600_vram_scratch_fini(rdev);
bcc1c2a1
AD		 3658 radeon_gem_fini(rdev);
3659 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3660 radeon_agp_fini(rdev);
3661 radeon_bo_fini(rdev);
3662 radeon_atombios_fini(rdev);
3663 kfree(rdev->bios);
3664 rdev->bios = NULL;
bcc1c2a1 3665}
9e46a48d 3666
b07759bf 3667void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
9e46a48d 3668{
197bbb3d
DA		 3669 u32 link_width_cntl, speed_cntl, mask;
3670 int ret;
9e46a48d 3671
d42dd579
AD		 3672 if (radeon_pcie_gen2 == 0)
3673 return;
3674
9e46a48d
AD		 3675 if (rdev->flags & RADEON_IS_IGP)
3676 return;
3677
3678 if (!(rdev->flags & RADEON_IS_PCIE))
3679 return;
3680
3681 /* x2 cards have a special sequence */
3682 if (ASIC_IS_X2(rdev))
3683 return;
3684
197bbb3d
DA		 3685 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3686 if (ret != 0)
3687 return;
3688
3689 if (!(mask & DRM_PCIE_SPEED_50))
3690 return;
3691
3691feea
AD		 3692 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3693 if (speed_cntl & LC_CURRENT_DATA_RATE) {
3694 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3695 return;
3696 }
3697
197bbb3d
DA		 3698 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3699
9e46a48d
AD		 3700 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3701 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3702
3703 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3704 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3705 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3706
3707 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3708 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3709 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3710
3711 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3712 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3713 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3714
3715 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3716 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3717 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3718
3719 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3720 speed_cntl |= LC_GEN2_EN_STRAP;
3721 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3722
3723 } else {
3724 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3725 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3726 if (1)
3727 link_width_cntl |= LC_UPCONFIGURE_DIS;
3728 else
3729 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3730 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3731 }
3732}
kernel source for telekom puls (alcatel/mediatek)