Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include <drm/drmP.h> | |
27 | #include <drm/drm_crtc_helper.h> | |
28 | #include <drm/radeon_drm.h> | |
68adac5e | 29 | #include <drm/drm_fixed.h> |
771fe6b9 JG |
30 | #include "radeon.h" |
31 | #include "atom.h" | |
32 | #include "atom-bits.h" | |
33 | ||
c93bb85b JG |
34 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
35 | struct drm_display_mode *mode, | |
36 | struct drm_display_mode *adjusted_mode) | |
37 | { | |
38 | struct drm_device *dev = crtc->dev; | |
39 | struct radeon_device *rdev = dev->dev_private; | |
40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
41 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; | |
42 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); | |
43 | int a1, a2; | |
44 | ||
45 | memset(&args, 0, sizeof(args)); | |
46 | ||
c93bb85b JG |
47 | args.ucCRTC = radeon_crtc->crtc_id; |
48 | ||
49 | switch (radeon_crtc->rmx_type) { | |
50 | case RMX_CENTER: | |
4589433c CC |
51 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
52 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); | |
53 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); | |
54 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); | |
c93bb85b JG |
55 | break; |
56 | case RMX_ASPECT: | |
57 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; | |
58 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; | |
59 | ||
60 | if (a1 > a2) { | |
4589433c CC |
61 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
62 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); | |
c93bb85b | 63 | } else if (a2 > a1) { |
942b0e95 AD |
64 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
65 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); | |
c93bb85b | 66 | } |
c93bb85b JG |
67 | break; |
68 | case RMX_FULL: | |
69 | default: | |
4589433c CC |
70 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
71 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); | |
72 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); | |
73 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); | |
c93bb85b JG |
74 | break; |
75 | } | |
5b1714d3 | 76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
c93bb85b JG |
77 | } |
78 | ||
79 | static void atombios_scaler_setup(struct drm_crtc *crtc) | |
80 | { | |
81 | struct drm_device *dev = crtc->dev; | |
82 | struct radeon_device *rdev = dev->dev_private; | |
83 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
84 | ENABLE_SCALER_PS_ALLOCATION args; | |
85 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); | |
5df3196b AD |
86 | struct radeon_encoder *radeon_encoder = |
87 | to_radeon_encoder(radeon_crtc->encoder); | |
c93bb85b JG |
88 | /* fixme - fill in enc_priv for atom dac */ |
89 | enum radeon_tv_std tv_std = TV_STD_NTSC; | |
4ce001ab | 90 | bool is_tv = false, is_cv = false; |
c93bb85b JG |
91 | |
92 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) | |
93 | return; | |
94 | ||
5df3196b AD |
95 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
96 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; | |
97 | tv_std = tv_dac->tv_std; | |
98 | is_tv = true; | |
4ce001ab DA |
99 | } |
100 | ||
c93bb85b JG |
101 | memset(&args, 0, sizeof(args)); |
102 | ||
103 | args.ucScaler = radeon_crtc->crtc_id; | |
104 | ||
4ce001ab | 105 | if (is_tv) { |
c93bb85b JG |
106 | switch (tv_std) { |
107 | case TV_STD_NTSC: | |
108 | default: | |
109 | args.ucTVStandard = ATOM_TV_NTSC; | |
110 | break; | |
111 | case TV_STD_PAL: | |
112 | args.ucTVStandard = ATOM_TV_PAL; | |
113 | break; | |
114 | case TV_STD_PAL_M: | |
115 | args.ucTVStandard = ATOM_TV_PALM; | |
116 | break; | |
117 | case TV_STD_PAL_60: | |
118 | args.ucTVStandard = ATOM_TV_PAL60; | |
119 | break; | |
120 | case TV_STD_NTSC_J: | |
121 | args.ucTVStandard = ATOM_TV_NTSCJ; | |
122 | break; | |
123 | case TV_STD_SCART_PAL: | |
124 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ | |
125 | break; | |
126 | case TV_STD_SECAM: | |
127 | args.ucTVStandard = ATOM_TV_SECAM; | |
128 | break; | |
129 | case TV_STD_PAL_CN: | |
130 | args.ucTVStandard = ATOM_TV_PALCN; | |
131 | break; | |
132 | } | |
133 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | |
4ce001ab | 134 | } else if (is_cv) { |
c93bb85b JG |
135 | args.ucTVStandard = ATOM_TV_CV; |
136 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; | |
137 | } else { | |
138 | switch (radeon_crtc->rmx_type) { | |
139 | case RMX_FULL: | |
140 | args.ucEnable = ATOM_SCALER_EXPANSION; | |
141 | break; | |
142 | case RMX_CENTER: | |
143 | args.ucEnable = ATOM_SCALER_CENTER; | |
144 | break; | |
145 | case RMX_ASPECT: | |
146 | args.ucEnable = ATOM_SCALER_EXPANSION; | |
147 | break; | |
148 | default: | |
149 | if (ASIC_IS_AVIVO(rdev)) | |
150 | args.ucEnable = ATOM_SCALER_DISABLE; | |
151 | else | |
152 | args.ucEnable = ATOM_SCALER_CENTER; | |
153 | break; | |
154 | } | |
155 | } | |
156 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
4ce001ab DA |
157 | if ((is_tv || is_cv) |
158 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { | |
159 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); | |
c93bb85b JG |
160 | } |
161 | } | |
162 | ||
771fe6b9 JG |
163 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
164 | { | |
165 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
166 | struct drm_device *dev = crtc->dev; | |
167 | struct radeon_device *rdev = dev->dev_private; | |
168 | int index = | |
169 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); | |
170 | ENABLE_CRTC_PS_ALLOCATION args; | |
171 | ||
172 | memset(&args, 0, sizeof(args)); | |
173 | ||
174 | args.ucCRTC = radeon_crtc->crtc_id; | |
175 | args.ucEnable = lock; | |
176 | ||
177 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
178 | } | |
179 | ||
180 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) | |
181 | { | |
182 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
183 | struct drm_device *dev = crtc->dev; | |
184 | struct radeon_device *rdev = dev->dev_private; | |
185 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); | |
186 | ENABLE_CRTC_PS_ALLOCATION args; | |
187 | ||
188 | memset(&args, 0, sizeof(args)); | |
189 | ||
190 | args.ucCRTC = radeon_crtc->crtc_id; | |
191 | args.ucEnable = state; | |
192 | ||
193 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
194 | } | |
195 | ||
196 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) | |
197 | { | |
198 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
199 | struct drm_device *dev = crtc->dev; | |
200 | struct radeon_device *rdev = dev->dev_private; | |
201 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); | |
202 | ENABLE_CRTC_PS_ALLOCATION args; | |
203 | ||
204 | memset(&args, 0, sizeof(args)); | |
205 | ||
206 | args.ucCRTC = radeon_crtc->crtc_id; | |
207 | args.ucEnable = state; | |
208 | ||
209 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
210 | } | |
211 | ||
212 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) | |
213 | { | |
214 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
215 | struct drm_device *dev = crtc->dev; | |
216 | struct radeon_device *rdev = dev->dev_private; | |
217 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); | |
218 | BLANK_CRTC_PS_ALLOCATION args; | |
219 | ||
220 | memset(&args, 0, sizeof(args)); | |
221 | ||
222 | args.ucCRTC = radeon_crtc->crtc_id; | |
223 | args.ucBlanking = state; | |
224 | ||
225 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
226 | } | |
227 | ||
fef9f91f AD |
228 | static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) |
229 | { | |
230 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
231 | struct drm_device *dev = crtc->dev; | |
232 | struct radeon_device *rdev = dev->dev_private; | |
233 | int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); | |
234 | ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; | |
235 | ||
236 | memset(&args, 0, sizeof(args)); | |
237 | ||
238 | args.ucDispPipeId = radeon_crtc->crtc_id; | |
239 | args.ucEnable = state; | |
240 | ||
241 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
242 | } | |
243 | ||
771fe6b9 JG |
244 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
245 | { | |
246 | struct drm_device *dev = crtc->dev; | |
247 | struct radeon_device *rdev = dev->dev_private; | |
500b7587 | 248 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
249 | |
250 | switch (mode) { | |
251 | case DRM_MODE_DPMS_ON: | |
d7311171 AD |
252 | radeon_crtc->enabled = true; |
253 | /* adjust pm to dpms changes BEFORE enabling crtcs */ | |
254 | radeon_pm_compute_clocks(rdev); | |
37b4390e | 255 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
79f17c64 | 256 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
37b4390e AD |
257 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
258 | atombios_blank_crtc(crtc, ATOM_DISABLE); | |
45f9a39b | 259 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
e5b91efc MD |
260 | /* Make sure vblank interrupt is still enabled if needed */ |
261 | radeon_irq_set(rdev); | |
500b7587 | 262 | radeon_crtc_load_lut(crtc); |
771fe6b9 JG |
263 | break; |
264 | case DRM_MODE_DPMS_STANDBY: | |
265 | case DRM_MODE_DPMS_SUSPEND: | |
266 | case DRM_MODE_DPMS_OFF: | |
45f9a39b | 267 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
a93f344d AD |
268 | if (radeon_crtc->enabled) |
269 | atombios_blank_crtc(crtc, ATOM_ENABLE); | |
79f17c64 | 270 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
37b4390e AD |
271 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
272 | atombios_enable_crtc(crtc, ATOM_DISABLE); | |
a48b9b4e | 273 | radeon_crtc->enabled = false; |
d7311171 AD |
274 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
275 | radeon_pm_compute_clocks(rdev); | |
771fe6b9 JG |
276 | break; |
277 | } | |
771fe6b9 JG |
278 | } |
279 | ||
280 | static void | |
281 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, | |
5a9bcacc | 282 | struct drm_display_mode *mode) |
771fe6b9 | 283 | { |
5a9bcacc | 284 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
285 | struct drm_device *dev = crtc->dev; |
286 | struct radeon_device *rdev = dev->dev_private; | |
5a9bcacc | 287 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
771fe6b9 | 288 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
5a9bcacc | 289 | u16 misc = 0; |
771fe6b9 | 290 | |
5a9bcacc | 291 | memset(&args, 0, sizeof(args)); |
5b1714d3 | 292 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); |
5a9bcacc | 293 | args.usH_Blanking_Time = |
5b1714d3 AD |
294 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); |
295 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); | |
5a9bcacc | 296 | args.usV_Blanking_Time = |
5b1714d3 | 297 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); |
5a9bcacc | 298 | args.usH_SyncOffset = |
5b1714d3 | 299 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); |
5a9bcacc AD |
300 | args.usH_SyncWidth = |
301 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); | |
302 | args.usV_SyncOffset = | |
5b1714d3 | 303 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); |
5a9bcacc AD |
304 | args.usV_SyncWidth = |
305 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); | |
5b1714d3 AD |
306 | args.ucH_Border = radeon_crtc->h_border; |
307 | args.ucV_Border = radeon_crtc->v_border; | |
5a9bcacc AD |
308 | |
309 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
310 | misc |= ATOM_VSYNC_POLARITY; | |
311 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
312 | misc |= ATOM_HSYNC_POLARITY; | |
313 | if (mode->flags & DRM_MODE_FLAG_CSYNC) | |
314 | misc |= ATOM_COMPOSITESYNC; | |
315 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
316 | misc |= ATOM_INTERLACE; | |
2b239a97 | 317 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
5a9bcacc | 318 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
2b239a97 AD |
319 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
320 | misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; | |
5a9bcacc AD |
321 | |
322 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); | |
323 | args.ucCRTC = radeon_crtc->crtc_id; | |
771fe6b9 | 324 | |
5a9bcacc | 325 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
771fe6b9 JG |
326 | } |
327 | ||
5a9bcacc AD |
328 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
329 | struct drm_display_mode *mode) | |
771fe6b9 | 330 | { |
5a9bcacc | 331 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
332 | struct drm_device *dev = crtc->dev; |
333 | struct radeon_device *rdev = dev->dev_private; | |
5a9bcacc | 334 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
771fe6b9 | 335 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
5a9bcacc | 336 | u16 misc = 0; |
771fe6b9 | 337 | |
5a9bcacc AD |
338 | memset(&args, 0, sizeof(args)); |
339 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); | |
340 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); | |
341 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); | |
342 | args.usH_SyncWidth = | |
343 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); | |
344 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); | |
345 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); | |
346 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); | |
347 | args.usV_SyncWidth = | |
348 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); | |
349 | ||
54bfe496 AD |
350 | args.ucOverscanRight = radeon_crtc->h_border; |
351 | args.ucOverscanLeft = radeon_crtc->h_border; | |
352 | args.ucOverscanBottom = radeon_crtc->v_border; | |
353 | args.ucOverscanTop = radeon_crtc->v_border; | |
354 | ||
5a9bcacc AD |
355 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
356 | misc |= ATOM_VSYNC_POLARITY; | |
357 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
358 | misc |= ATOM_HSYNC_POLARITY; | |
359 | if (mode->flags & DRM_MODE_FLAG_CSYNC) | |
360 | misc |= ATOM_COMPOSITESYNC; | |
361 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
362 | misc |= ATOM_INTERLACE; | |
2b239a97 | 363 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
5a9bcacc | 364 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
2b239a97 AD |
365 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
366 | misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; | |
5a9bcacc AD |
367 | |
368 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); | |
369 | args.ucCRTC = radeon_crtc->crtc_id; | |
771fe6b9 | 370 | |
5a9bcacc | 371 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
771fe6b9 JG |
372 | } |
373 | ||
3fa47d9e | 374 | static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) |
b792210e | 375 | { |
b792210e AD |
376 | u32 ss_cntl; |
377 | ||
378 | if (ASIC_IS_DCE4(rdev)) { | |
3fa47d9e | 379 | switch (pll_id) { |
b792210e AD |
380 | case ATOM_PPLL1: |
381 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); | |
382 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; | |
383 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); | |
384 | break; | |
385 | case ATOM_PPLL2: | |
386 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); | |
387 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; | |
388 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); | |
389 | break; | |
390 | case ATOM_DCPLL: | |
391 | case ATOM_PPLL_INVALID: | |
392 | return; | |
393 | } | |
394 | } else if (ASIC_IS_AVIVO(rdev)) { | |
3fa47d9e | 395 | switch (pll_id) { |
b792210e AD |
396 | case ATOM_PPLL1: |
397 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); | |
398 | ss_cntl &= ~1; | |
399 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); | |
400 | break; | |
401 | case ATOM_PPLL2: | |
402 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); | |
403 | ss_cntl &= ~1; | |
404 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); | |
405 | break; | |
406 | case ATOM_DCPLL: | |
407 | case ATOM_PPLL_INVALID: | |
408 | return; | |
409 | } | |
410 | } | |
411 | } | |
412 | ||
413 | ||
26b9fc3a | 414 | union atom_enable_ss { |
ba032a58 AD |
415 | ENABLE_LVDS_SS_PARAMETERS lvds_ss; |
416 | ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; | |
26b9fc3a | 417 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
ba032a58 | 418 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; |
a572eaa3 | 419 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; |
26b9fc3a AD |
420 | }; |
421 | ||
3fa47d9e | 422 | static void atombios_crtc_program_ss(struct radeon_device *rdev, |
ba032a58 AD |
423 | int enable, |
424 | int pll_id, | |
5efcc76c | 425 | int crtc_id, |
ba032a58 | 426 | struct radeon_atom_ss *ss) |
ebbe1cb9 | 427 | { |
5efcc76c | 428 | unsigned i; |
ebbe1cb9 | 429 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
26b9fc3a | 430 | union atom_enable_ss args; |
ebbe1cb9 | 431 | |
5efcc76c | 432 | if (!enable) { |
53176706 | 433 | for (i = 0; i < rdev->num_crtc; i++) { |
5efcc76c JG |
434 | if (rdev->mode_info.crtcs[i] && |
435 | rdev->mode_info.crtcs[i]->enabled && | |
436 | i != crtc_id && | |
437 | pll_id == rdev->mode_info.crtcs[i]->pll_id) { | |
438 | /* one other crtc is using this pll don't turn | |
439 | * off spread spectrum as it might turn off | |
440 | * display on active crtc | |
441 | */ | |
442 | return; | |
443 | } | |
444 | } | |
445 | } | |
446 | ||
ba032a58 | 447 | memset(&args, 0, sizeof(args)); |
bcc1c2a1 | 448 | |
a572eaa3 | 449 | if (ASIC_IS_DCE5(rdev)) { |
4589433c | 450 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
8e8e523d | 451 | args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
a572eaa3 AD |
452 | switch (pll_id) { |
453 | case ATOM_PPLL1: | |
454 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; | |
a572eaa3 AD |
455 | break; |
456 | case ATOM_PPLL2: | |
457 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; | |
a572eaa3 AD |
458 | break; |
459 | case ATOM_DCPLL: | |
460 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; | |
a572eaa3 AD |
461 | break; |
462 | case ATOM_PPLL_INVALID: | |
463 | return; | |
464 | } | |
f312f093 AD |
465 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
466 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); | |
d0ae3e89 | 467 | args.v3.ucEnable = enable; |
0671bdd7 | 468 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) |
8e8e523d | 469 | args.v3.ucEnable = ATOM_DISABLE; |
a572eaa3 | 470 | } else if (ASIC_IS_DCE4(rdev)) { |
ba032a58 | 471 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
8e8e523d | 472 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
473 | switch (pll_id) { |
474 | case ATOM_PPLL1: | |
475 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; | |
ba032a58 AD |
476 | break; |
477 | case ATOM_PPLL2: | |
478 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; | |
ebbe1cb9 | 479 | break; |
ba032a58 AD |
480 | case ATOM_DCPLL: |
481 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; | |
ba032a58 AD |
482 | break; |
483 | case ATOM_PPLL_INVALID: | |
484 | return; | |
ebbe1cb9 | 485 | } |
f312f093 AD |
486 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
487 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); | |
ba032a58 | 488 | args.v2.ucEnable = enable; |
09cc6506 | 489 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) |
8e8e523d | 490 | args.v2.ucEnable = ATOM_DISABLE; |
ba032a58 AD |
491 | } else if (ASIC_IS_DCE3(rdev)) { |
492 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); | |
8e8e523d | 493 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
494 | args.v1.ucSpreadSpectrumStep = ss->step; |
495 | args.v1.ucSpreadSpectrumDelay = ss->delay; | |
496 | args.v1.ucSpreadSpectrumRange = ss->range; | |
497 | args.v1.ucPpll = pll_id; | |
498 | args.v1.ucEnable = enable; | |
499 | } else if (ASIC_IS_AVIVO(rdev)) { | |
8e8e523d AD |
500 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
501 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { | |
3fa47d9e | 502 | atombios_disable_ss(rdev, pll_id); |
ba032a58 AD |
503 | return; |
504 | } | |
505 | args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); | |
8e8e523d | 506 | args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
507 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
508 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; | |
509 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; | |
510 | args.lvds_ss_2.ucEnable = enable; | |
ebbe1cb9 | 511 | } else { |
8e8e523d AD |
512 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
513 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { | |
3fa47d9e | 514 | atombios_disable_ss(rdev, pll_id); |
ba032a58 AD |
515 | return; |
516 | } | |
517 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); | |
8e8e523d | 518 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
ba032a58 AD |
519 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; |
520 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; | |
521 | args.lvds_ss.ucEnable = enable; | |
ebbe1cb9 | 522 | } |
26b9fc3a | 523 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
ebbe1cb9 AD |
524 | } |
525 | ||
4eaeca33 AD |
526 | union adjust_pixel_clock { |
527 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; | |
bcc1c2a1 | 528 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
4eaeca33 AD |
529 | }; |
530 | ||
531 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |
19eca43e | 532 | struct drm_display_mode *mode) |
771fe6b9 | 533 | { |
19eca43e | 534 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
771fe6b9 JG |
535 | struct drm_device *dev = crtc->dev; |
536 | struct radeon_device *rdev = dev->dev_private; | |
5df3196b AD |
537 | struct drm_encoder *encoder = radeon_crtc->encoder; |
538 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
539 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
4eaeca33 | 540 | u32 adjusted_clock = mode->clock; |
5df3196b | 541 | int encoder_mode = atombios_get_encoder_mode(encoder); |
fbee67a6 | 542 | u32 dp_clock = mode->clock; |
5df3196b AD |
543 | int bpc = radeon_get_monitor_bpc(connector); |
544 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); | |
fc10332b | 545 | |
4eaeca33 | 546 | /* reset the pll flags */ |
19eca43e | 547 | radeon_crtc->pll_flags = 0; |
771fe6b9 JG |
548 | |
549 | if (ASIC_IS_AVIVO(rdev)) { | |
eb1300bc AD |
550 | if ((rdev->family == CHIP_RS600) || |
551 | (rdev->family == CHIP_RS690) || | |
552 | (rdev->family == CHIP_RS740)) | |
19eca43e AD |
553 | radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
554 | RADEON_PLL_PREFER_CLOSEST_LOWER); | |
5480f727 DA |
555 | |
556 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ | |
19eca43e | 557 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
5480f727 | 558 | else |
19eca43e | 559 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
9bb09fa1 | 560 | |
5785e53f | 561 | if (rdev->family < CHIP_RV770) |
19eca43e | 562 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
37d4174d AD |
563 | /* use frac fb div on APUs */ |
564 | if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) | |
19eca43e | 565 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
41167828 AD |
566 | /* use frac fb div on RS780/RS880 */ |
567 | if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) | |
568 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; | |
a02dc74b AD |
569 | if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) |
570 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; | |
5480f727 | 571 | } else { |
19eca43e | 572 | radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; |
771fe6b9 | 573 | |
5480f727 | 574 | if (mode->clock > 200000) /* range limits??? */ |
19eca43e | 575 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
5480f727 | 576 | else |
19eca43e | 577 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
5480f727 DA |
578 | } |
579 | ||
5df3196b AD |
580 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
581 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { | |
582 | if (connector) { | |
583 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
584 | struct radeon_connector_atom_dig *dig_connector = | |
585 | radeon_connector->con_priv; | |
5b40ddf8 | 586 | |
5df3196b AD |
587 | dp_clock = dig_connector->dp_clock; |
588 | } | |
589 | } | |
5b40ddf8 | 590 | |
5df3196b AD |
591 | /* use recommended ref_div for ss */ |
592 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
593 | if (radeon_crtc->ss_enabled) { | |
594 | if (radeon_crtc->ss.refdiv) { | |
595 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; | |
596 | radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; | |
597 | if (ASIC_IS_AVIVO(rdev)) | |
598 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; | |
771fe6b9 | 599 | } |
771fe6b9 JG |
600 | } |
601 | } | |
602 | ||
5df3196b AD |
603 | if (ASIC_IS_AVIVO(rdev)) { |
604 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ | |
605 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) | |
606 | adjusted_clock = mode->clock * 2; | |
607 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) | |
608 | radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; | |
609 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) | |
610 | radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; | |
611 | } else { | |
612 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) | |
613 | radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; | |
614 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) | |
615 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; | |
616 | } | |
617 | ||
2606c886 AD |
618 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
619 | * accordingly based on the encoder/transmitter to work around | |
620 | * special hw requirements. | |
621 | */ | |
622 | if (ASIC_IS_DCE3(rdev)) { | |
4eaeca33 | 623 | union adjust_pixel_clock args; |
4eaeca33 AD |
624 | u8 frev, crev; |
625 | int index; | |
2606c886 | 626 | |
2606c886 | 627 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
a084e6ee AD |
628 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
629 | &crev)) | |
630 | return adjusted_clock; | |
4eaeca33 AD |
631 | |
632 | memset(&args, 0, sizeof(args)); | |
633 | ||
634 | switch (frev) { | |
635 | case 1: | |
636 | switch (crev) { | |
637 | case 1: | |
638 | case 2: | |
639 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); | |
640 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; | |
bcc1c2a1 | 641 | args.v1.ucEncodeMode = encoder_mode; |
19eca43e | 642 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
fbee67a6 AD |
643 | args.v1.ucConfig |= |
644 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; | |
4eaeca33 AD |
645 | |
646 | atom_execute_table(rdev->mode_info.atom_context, | |
647 | index, (uint32_t *)&args); | |
648 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; | |
649 | break; | |
bcc1c2a1 AD |
650 | case 3: |
651 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); | |
652 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; | |
653 | args.v3.sInput.ucEncodeMode = encoder_mode; | |
654 | args.v3.sInput.ucDispPllConfig = 0; | |
19eca43e | 655 | if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) |
b526ce22 AD |
656 | args.v3.sInput.ucDispPllConfig |= |
657 | DISPPLL_CONFIG_SS_ENABLE; | |
996d5c59 | 658 | if (ENCODER_MODE_IS_DP(encoder_mode)) { |
b4f15f80 AD |
659 | args.v3.sInput.ucDispPllConfig |= |
660 | DISPPLL_CONFIG_COHERENT_MODE; | |
661 | /* 16200 or 27000 */ | |
662 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | |
663 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
bcc1c2a1 | 664 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
b4f15f80 AD |
665 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) |
666 | /* deep color support */ | |
667 | args.v3.sInput.usPixelClock = | |
668 | cpu_to_le16((mode->clock * bpc / 8) / 10); | |
669 | if (dig->coherent_mode) | |
bcc1c2a1 AD |
670 | args.v3.sInput.ucDispPllConfig |= |
671 | DISPPLL_CONFIG_COHERENT_MODE; | |
9aa59993 | 672 | if (is_duallink) |
bcc1c2a1 | 673 | args.v3.sInput.ucDispPllConfig |= |
b4f15f80 | 674 | DISPPLL_CONFIG_DUAL_LINK; |
bcc1c2a1 | 675 | } |
1d33e1fc AD |
676 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
677 | ENCODER_OBJECT_ID_NONE) | |
678 | args.v3.sInput.ucExtTransmitterID = | |
679 | radeon_encoder_get_dp_bridge_encoder_id(encoder); | |
680 | else | |
cc9f67a0 AD |
681 | args.v3.sInput.ucExtTransmitterID = 0; |
682 | ||
bcc1c2a1 AD |
683 | atom_execute_table(rdev->mode_info.atom_context, |
684 | index, (uint32_t *)&args); | |
685 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; | |
686 | if (args.v3.sOutput.ucRefDiv) { | |
19eca43e AD |
687 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
688 | radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; | |
689 | radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; | |
bcc1c2a1 AD |
690 | } |
691 | if (args.v3.sOutput.ucPostDiv) { | |
19eca43e AD |
692 | radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
693 | radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; | |
694 | radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; | |
bcc1c2a1 AD |
695 | } |
696 | break; | |
4eaeca33 AD |
697 | default: |
698 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
699 | return adjusted_clock; | |
700 | } | |
701 | break; | |
702 | default: | |
703 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
704 | return adjusted_clock; | |
705 | } | |
d56ef9c8 | 706 | } |
4eaeca33 AD |
707 | return adjusted_clock; |
708 | } | |
709 | ||
710 | union set_pixel_clock { | |
711 | SET_PIXEL_CLOCK_PS_ALLOCATION base; | |
712 | PIXEL_CLOCK_PARAMETERS v1; | |
713 | PIXEL_CLOCK_PARAMETERS_V2 v2; | |
714 | PIXEL_CLOCK_PARAMETERS_V3 v3; | |
bcc1c2a1 | 715 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
f82b3ddc | 716 | PIXEL_CLOCK_PARAMETERS_V6 v6; |
4eaeca33 AD |
717 | }; |
718 | ||
f82b3ddc AD |
719 | /* on DCE5, make sure the voltage is high enough to support the |
720 | * required disp clk. | |
721 | */ | |
f3f1f03e | 722 | static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, |
f82b3ddc | 723 | u32 dispclk) |
bcc1c2a1 | 724 | { |
bcc1c2a1 AD |
725 | u8 frev, crev; |
726 | int index; | |
727 | union set_pixel_clock args; | |
728 | ||
729 | memset(&args, 0, sizeof(args)); | |
730 | ||
731 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); | |
a084e6ee AD |
732 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
733 | &crev)) | |
734 | return; | |
bcc1c2a1 AD |
735 | |
736 | switch (frev) { | |
737 | case 1: | |
738 | switch (crev) { | |
739 | case 5: | |
740 | /* if the default dcpll clock is specified, | |
741 | * SetPixelClock provides the dividers | |
742 | */ | |
743 | args.v5.ucCRTC = ATOM_CRTC_INVALID; | |
4589433c | 744 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
bcc1c2a1 AD |
745 | args.v5.ucPpll = ATOM_DCPLL; |
746 | break; | |
f82b3ddc AD |
747 | case 6: |
748 | /* if the default dcpll clock is specified, | |
749 | * SetPixelClock provides the dividers | |
750 | */ | |
265aa6c8 | 751 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
729b95ef AD |
752 | if (ASIC_IS_DCE61(rdev)) |
753 | args.v6.ucPpll = ATOM_EXT_PLL1; | |
754 | else if (ASIC_IS_DCE6(rdev)) | |
f3f1f03e AD |
755 | args.v6.ucPpll = ATOM_PPLL0; |
756 | else | |
757 | args.v6.ucPpll = ATOM_DCPLL; | |
f82b3ddc | 758 | break; |
bcc1c2a1 AD |
759 | default: |
760 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
761 | return; | |
762 | } | |
763 | break; | |
764 | default: | |
765 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
766 | return; | |
767 | } | |
768 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
769 | } | |
770 | ||
37f9003b | 771 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
f1bece7f | 772 | u32 crtc_id, |
37f9003b AD |
773 | int pll_id, |
774 | u32 encoder_mode, | |
775 | u32 encoder_id, | |
776 | u32 clock, | |
777 | u32 ref_div, | |
778 | u32 fb_div, | |
779 | u32 frac_fb_div, | |
df271bec | 780 | u32 post_div, |
8e8e523d AD |
781 | int bpc, |
782 | bool ss_enabled, | |
783 | struct radeon_atom_ss *ss) | |
4eaeca33 | 784 | { |
4eaeca33 AD |
785 | struct drm_device *dev = crtc->dev; |
786 | struct radeon_device *rdev = dev->dev_private; | |
4eaeca33 | 787 | u8 frev, crev; |
37f9003b | 788 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
4eaeca33 | 789 | union set_pixel_clock args; |
4eaeca33 AD |
790 | |
791 | memset(&args, 0, sizeof(args)); | |
792 | ||
a084e6ee AD |
793 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
794 | &crev)) | |
795 | return; | |
771fe6b9 JG |
796 | |
797 | switch (frev) { | |
798 | case 1: | |
799 | switch (crev) { | |
800 | case 1: | |
37f9003b AD |
801 | if (clock == ATOM_DISABLE) |
802 | return; | |
803 | args.v1.usPixelClock = cpu_to_le16(clock / 10); | |
4eaeca33 AD |
804 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
805 | args.v1.usFbDiv = cpu_to_le16(fb_div); | |
806 | args.v1.ucFracFbDiv = frac_fb_div; | |
807 | args.v1.ucPostDiv = post_div; | |
37f9003b AD |
808 | args.v1.ucPpll = pll_id; |
809 | args.v1.ucCRTC = crtc_id; | |
4eaeca33 | 810 | args.v1.ucRefDivSrc = 1; |
771fe6b9 JG |
811 | break; |
812 | case 2: | |
37f9003b | 813 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
4eaeca33 AD |
814 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
815 | args.v2.usFbDiv = cpu_to_le16(fb_div); | |
816 | args.v2.ucFracFbDiv = frac_fb_div; | |
817 | args.v2.ucPostDiv = post_div; | |
37f9003b AD |
818 | args.v2.ucPpll = pll_id; |
819 | args.v2.ucCRTC = crtc_id; | |
4eaeca33 | 820 | args.v2.ucRefDivSrc = 1; |
771fe6b9 JG |
821 | break; |
822 | case 3: | |
37f9003b | 823 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
4eaeca33 AD |
824 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
825 | args.v3.usFbDiv = cpu_to_le16(fb_div); | |
826 | args.v3.ucFracFbDiv = frac_fb_div; | |
827 | args.v3.ucPostDiv = post_div; | |
37f9003b | 828 | args.v3.ucPpll = pll_id; |
e729586e AD |
829 | if (crtc_id == ATOM_CRTC2) |
830 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; | |
831 | else | |
832 | args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; | |
6f15c506 AD |
833 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
834 | args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; | |
37f9003b | 835 | args.v3.ucTransmitterId = encoder_id; |
bcc1c2a1 AD |
836 | args.v3.ucEncoderMode = encoder_mode; |
837 | break; | |
838 | case 5: | |
37f9003b AD |
839 | args.v5.ucCRTC = crtc_id; |
840 | args.v5.usPixelClock = cpu_to_le16(clock / 10); | |
bcc1c2a1 AD |
841 | args.v5.ucRefDiv = ref_div; |
842 | args.v5.usFbDiv = cpu_to_le16(fb_div); | |
843 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); | |
844 | args.v5.ucPostDiv = post_div; | |
845 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ | |
8e8e523d AD |
846 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
847 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; | |
59dbea87 AD |
848 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
849 | switch (bpc) { | |
850 | case 8: | |
851 | default: | |
852 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; | |
853 | break; | |
854 | case 10: | |
855 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; | |
856 | break; | |
857 | } | |
df271bec | 858 | } |
37f9003b | 859 | args.v5.ucTransmitterID = encoder_id; |
bcc1c2a1 | 860 | args.v5.ucEncoderMode = encoder_mode; |
37f9003b | 861 | args.v5.ucPpll = pll_id; |
771fe6b9 | 862 | break; |
f82b3ddc | 863 | case 6: |
f1bece7f | 864 | args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); |
f82b3ddc AD |
865 | args.v6.ucRefDiv = ref_div; |
866 | args.v6.usFbDiv = cpu_to_le16(fb_div); | |
867 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); | |
868 | args.v6.ucPostDiv = post_div; | |
869 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ | |
8e8e523d AD |
870 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
871 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; | |
59dbea87 AD |
872 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { |
873 | switch (bpc) { | |
874 | case 8: | |
875 | default: | |
876 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; | |
877 | break; | |
878 | case 10: | |
879 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; | |
880 | break; | |
881 | case 12: | |
882 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; | |
883 | break; | |
884 | case 16: | |
885 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; | |
886 | break; | |
887 | } | |
df271bec | 888 | } |
f82b3ddc AD |
889 | args.v6.ucTransmitterID = encoder_id; |
890 | args.v6.ucEncoderMode = encoder_mode; | |
891 | args.v6.ucPpll = pll_id; | |
892 | break; | |
771fe6b9 JG |
893 | default: |
894 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
895 | return; | |
896 | } | |
897 | break; | |
898 | default: | |
899 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); | |
900 | return; | |
901 | } | |
902 | ||
771fe6b9 JG |
903 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
904 | } | |
905 | ||
19eca43e | 906 | static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
37f9003b AD |
907 | { |
908 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
909 | struct drm_device *dev = crtc->dev; | |
910 | struct radeon_device *rdev = dev->dev_private; | |
5df3196b AD |
911 | struct radeon_encoder *radeon_encoder = |
912 | to_radeon_encoder(radeon_crtc->encoder); | |
913 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); | |
19eca43e AD |
914 | |
915 | radeon_crtc->bpc = 8; | |
916 | radeon_crtc->ss_enabled = false; | |
37f9003b | 917 | |
700698e7 | 918 | if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
5df3196b | 919 | (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { |
ba032a58 AD |
920 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
921 | struct drm_connector *connector = | |
5df3196b | 922 | radeon_get_connector_for_encoder(radeon_crtc->encoder); |
ba032a58 AD |
923 | struct radeon_connector *radeon_connector = |
924 | to_radeon_connector(connector); | |
925 | struct radeon_connector_atom_dig *dig_connector = | |
926 | radeon_connector->con_priv; | |
927 | int dp_clock; | |
19eca43e | 928 | radeon_crtc->bpc = radeon_get_monitor_bpc(connector); |
ba032a58 AD |
929 | |
930 | switch (encoder_mode) { | |
996d5c59 | 931 | case ATOM_ENCODER_MODE_DP_MST: |
ba032a58 AD |
932 | case ATOM_ENCODER_MODE_DP: |
933 | /* DP/eDP */ | |
934 | dp_clock = dig_connector->dp_clock / 10; | |
2307790f | 935 | if (ASIC_IS_DCE4(rdev)) |
19eca43e AD |
936 | radeon_crtc->ss_enabled = |
937 | radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, | |
2307790f AD |
938 | ASIC_INTERNAL_SS_ON_DP, |
939 | dp_clock); | |
940 | else { | |
941 | if (dp_clock == 16200) { | |
19eca43e AD |
942 | radeon_crtc->ss_enabled = |
943 | radeon_atombios_get_ppll_ss_info(rdev, | |
944 | &radeon_crtc->ss, | |
2307790f | 945 | ATOM_DP_SS_ID2); |
19eca43e AD |
946 | if (!radeon_crtc->ss_enabled) |
947 | radeon_crtc->ss_enabled = | |
948 | radeon_atombios_get_ppll_ss_info(rdev, | |
949 | &radeon_crtc->ss, | |
2307790f | 950 | ATOM_DP_SS_ID1); |
9b0b183e | 951 | } else { |
19eca43e AD |
952 | radeon_crtc->ss_enabled = |
953 | radeon_atombios_get_ppll_ss_info(rdev, | |
954 | &radeon_crtc->ss, | |
2307790f | 955 | ATOM_DP_SS_ID1); |
9b0b183e AD |
956 | } |
957 | /* disable spread spectrum on DCE3 DP */ | |
958 | radeon_crtc->ss_enabled = false; | |
ba032a58 AD |
959 | } |
960 | break; | |
961 | case ATOM_ENCODER_MODE_LVDS: | |
962 | if (ASIC_IS_DCE4(rdev)) | |
19eca43e AD |
963 | radeon_crtc->ss_enabled = |
964 | radeon_atombios_get_asic_ss_info(rdev, | |
965 | &radeon_crtc->ss, | |
966 | dig->lcd_ss_id, | |
967 | mode->clock / 10); | |
ba032a58 | 968 | else |
19eca43e AD |
969 | radeon_crtc->ss_enabled = |
970 | radeon_atombios_get_ppll_ss_info(rdev, | |
971 | &radeon_crtc->ss, | |
972 | dig->lcd_ss_id); | |
ba032a58 AD |
973 | break; |
974 | case ATOM_ENCODER_MODE_DVI: | |
975 | if (ASIC_IS_DCE4(rdev)) | |
19eca43e AD |
976 | radeon_crtc->ss_enabled = |
977 | radeon_atombios_get_asic_ss_info(rdev, | |
978 | &radeon_crtc->ss, | |
ba032a58 AD |
979 | ASIC_INTERNAL_SS_ON_TMDS, |
980 | mode->clock / 10); | |
981 | break; | |
982 | case ATOM_ENCODER_MODE_HDMI: | |
983 | if (ASIC_IS_DCE4(rdev)) | |
19eca43e AD |
984 | radeon_crtc->ss_enabled = |
985 | radeon_atombios_get_asic_ss_info(rdev, | |
986 | &radeon_crtc->ss, | |
ba032a58 AD |
987 | ASIC_INTERNAL_SS_ON_HDMI, |
988 | mode->clock / 10); | |
989 | break; | |
990 | default: | |
991 | break; | |
992 | } | |
993 | } | |
994 | ||
37f9003b | 995 | /* adjust pixel clock as needed */ |
19eca43e AD |
996 | radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); |
997 | ||
998 | return true; | |
999 | } | |
1000 | ||
1001 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) | |
1002 | { | |
1003 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1004 | struct drm_device *dev = crtc->dev; | |
1005 | struct radeon_device *rdev = dev->dev_private; | |
5df3196b AD |
1006 | struct radeon_encoder *radeon_encoder = |
1007 | to_radeon_encoder(radeon_crtc->encoder); | |
19eca43e AD |
1008 | u32 pll_clock = mode->clock; |
1009 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; | |
1010 | struct radeon_pll *pll; | |
5df3196b | 1011 | int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); |
19eca43e AD |
1012 | |
1013 | switch (radeon_crtc->pll_id) { | |
1014 | case ATOM_PPLL1: | |
1015 | pll = &rdev->clock.p1pll; | |
1016 | break; | |
1017 | case ATOM_PPLL2: | |
1018 | pll = &rdev->clock.p2pll; | |
1019 | break; | |
1020 | case ATOM_DCPLL: | |
1021 | case ATOM_PPLL_INVALID: | |
1022 | default: | |
1023 | pll = &rdev->clock.dcpll; | |
1024 | break; | |
1025 | } | |
1026 | ||
1027 | /* update pll params */ | |
1028 | pll->flags = radeon_crtc->pll_flags; | |
1029 | pll->reference_div = radeon_crtc->pll_reference_div; | |
1030 | pll->post_div = radeon_crtc->pll_post_div; | |
37f9003b | 1031 | |
64146f8b AD |
1032 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
1033 | /* TV seems to prefer the legacy algo on some boards */ | |
19eca43e AD |
1034 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1035 | &fb_div, &frac_fb_div, &ref_div, &post_div); | |
64146f8b | 1036 | else if (ASIC_IS_AVIVO(rdev)) |
19eca43e AD |
1037 | radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1038 | &fb_div, &frac_fb_div, &ref_div, &post_div); | |
619efb10 | 1039 | else |
19eca43e AD |
1040 | radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, |
1041 | &fb_div, &frac_fb_div, &ref_div, &post_div); | |
37f9003b | 1042 | |
19eca43e AD |
1043 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, |
1044 | radeon_crtc->crtc_id, &radeon_crtc->ss); | |
ba032a58 | 1045 | |
37f9003b AD |
1046 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
1047 | encoder_mode, radeon_encoder->encoder_id, mode->clock, | |
19eca43e AD |
1048 | ref_div, fb_div, frac_fb_div, post_div, |
1049 | radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); | |
37f9003b | 1050 | |
19eca43e | 1051 | if (radeon_crtc->ss_enabled) { |
ba032a58 AD |
1052 | /* calculate ss amount and step size */ |
1053 | if (ASIC_IS_DCE4(rdev)) { | |
1054 | u32 step_size; | |
19eca43e AD |
1055 | u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; |
1056 | radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; | |
1057 | radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & | |
ba032a58 | 1058 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
19eca43e AD |
1059 | if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
1060 | step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / | |
ba032a58 AD |
1061 | (125 * 25 * pll->reference_freq / 100); |
1062 | else | |
19eca43e | 1063 | step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / |
ba032a58 | 1064 | (125 * 25 * pll->reference_freq / 100); |
19eca43e | 1065 | radeon_crtc->ss.step = step_size; |
ba032a58 AD |
1066 | } |
1067 | ||
19eca43e AD |
1068 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, |
1069 | radeon_crtc->crtc_id, &radeon_crtc->ss); | |
ba032a58 | 1070 | } |
37f9003b AD |
1071 | } |
1072 | ||
c9417bdd AD |
1073 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
1074 | struct drm_framebuffer *fb, | |
1075 | int x, int y, int atomic) | |
bcc1c2a1 AD |
1076 | { |
1077 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1078 | struct drm_device *dev = crtc->dev; | |
1079 | struct radeon_device *rdev = dev->dev_private; | |
1080 | struct radeon_framebuffer *radeon_fb; | |
4dd19b0d | 1081 | struct drm_framebuffer *target_fb; |
bcc1c2a1 AD |
1082 | struct drm_gem_object *obj; |
1083 | struct radeon_bo *rbo; | |
1084 | uint64_t fb_location; | |
1085 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; | |
285484e2 | 1086 | unsigned bankw, bankh, mtaspect, tile_split; |
fa6bee46 | 1087 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
adcfde51 | 1088 | u32 tmp, viewport_w, viewport_h; |
bcc1c2a1 AD |
1089 | int r; |
1090 | ||
1091 | /* no fb bound */ | |
4dd19b0d | 1092 | if (!atomic && !crtc->fb) { |
d9fdaafb | 1093 | DRM_DEBUG_KMS("No FB bound\n"); |
bcc1c2a1 AD |
1094 | return 0; |
1095 | } | |
1096 | ||
4dd19b0d CB |
1097 | if (atomic) { |
1098 | radeon_fb = to_radeon_framebuffer(fb); | |
1099 | target_fb = fb; | |
1100 | } | |
1101 | else { | |
1102 | radeon_fb = to_radeon_framebuffer(crtc->fb); | |
1103 | target_fb = crtc->fb; | |
1104 | } | |
bcc1c2a1 | 1105 | |
4dd19b0d CB |
1106 | /* If atomic, assume fb object is pinned & idle & fenced and |
1107 | * just update base pointers | |
1108 | */ | |
bcc1c2a1 | 1109 | obj = radeon_fb->obj; |
7e4d15d9 | 1110 | rbo = gem_to_radeon_bo(obj); |
bcc1c2a1 AD |
1111 | r = radeon_bo_reserve(rbo, false); |
1112 | if (unlikely(r != 0)) | |
1113 | return r; | |
4dd19b0d CB |
1114 | |
1115 | if (atomic) | |
1116 | fb_location = radeon_bo_gpu_offset(rbo); | |
1117 | else { | |
1118 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); | |
1119 | if (unlikely(r != 0)) { | |
1120 | radeon_bo_unreserve(rbo); | |
1121 | return -EINVAL; | |
1122 | } | |
bcc1c2a1 | 1123 | } |
4dd19b0d | 1124 | |
bcc1c2a1 AD |
1125 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1126 | radeon_bo_unreserve(rbo); | |
1127 | ||
4dd19b0d | 1128 | switch (target_fb->bits_per_pixel) { |
bcc1c2a1 AD |
1129 | case 8: |
1130 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | | |
1131 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); | |
1132 | break; | |
1133 | case 15: | |
1134 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | |
1135 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); | |
1136 | break; | |
1137 | case 16: | |
1138 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | | |
1139 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); | |
fa6bee46 AD |
1140 | #ifdef __BIG_ENDIAN |
1141 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); | |
1142 | #endif | |
bcc1c2a1 AD |
1143 | break; |
1144 | case 24: | |
1145 | case 32: | |
1146 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | | |
1147 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); | |
fa6bee46 AD |
1148 | #ifdef __BIG_ENDIAN |
1149 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); | |
1150 | #endif | |
bcc1c2a1 AD |
1151 | break; |
1152 | default: | |
1153 | DRM_ERROR("Unsupported screen depth %d\n", | |
4dd19b0d | 1154 | target_fb->bits_per_pixel); |
bcc1c2a1 AD |
1155 | return -EINVAL; |
1156 | } | |
1157 | ||
392e3722 | 1158 | if (tiling_flags & RADEON_TILING_MACRO) { |
b7019b2f AD |
1159 | if (rdev->family >= CHIP_TAHITI) |
1160 | tmp = rdev->config.si.tile_config; | |
1161 | else if (rdev->family >= CHIP_CAYMAN) | |
392e3722 AD |
1162 | tmp = rdev->config.cayman.tile_config; |
1163 | else | |
1164 | tmp = rdev->config.evergreen.tile_config; | |
1165 | ||
1166 | switch ((tmp & 0xf0) >> 4) { | |
1167 | case 0: /* 4 banks */ | |
1168 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); | |
1169 | break; | |
1170 | case 1: /* 8 banks */ | |
1171 | default: | |
1172 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); | |
1173 | break; | |
1174 | case 2: /* 16 banks */ | |
1175 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); | |
1176 | break; | |
1177 | } | |
1178 | ||
97d66328 | 1179 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
285484e2 JG |
1180 | |
1181 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); | |
1182 | fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); | |
1183 | fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); | |
1184 | fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); | |
1185 | fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); | |
392e3722 | 1186 | } else if (tiling_flags & RADEON_TILING_MICRO) |
97d66328 AD |
1187 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
1188 | ||
b7019b2f AD |
1189 | if ((rdev->family == CHIP_TAHITI) || |
1190 | (rdev->family == CHIP_PITCAIRN)) | |
1191 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); | |
9c74433b AD |
1192 | else if ((rdev->family == CHIP_VERDE) || |
1193 | (rdev->family == CHIP_OLAND) || | |
1194 | (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ | |
b7019b2f AD |
1195 | fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); |
1196 | ||
bcc1c2a1 AD |
1197 | switch (radeon_crtc->crtc_id) { |
1198 | case 0: | |
1199 | WREG32(AVIVO_D1VGA_CONTROL, 0); | |
1200 | break; | |
1201 | case 1: | |
1202 | WREG32(AVIVO_D2VGA_CONTROL, 0); | |
1203 | break; | |
1204 | case 2: | |
1205 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); | |
1206 | break; | |
1207 | case 3: | |
1208 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); | |
1209 | break; | |
1210 | case 4: | |
1211 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); | |
1212 | break; | |
1213 | case 5: | |
1214 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); | |
1215 | break; | |
1216 | default: | |
1217 | break; | |
1218 | } | |
1219 | ||
1220 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
1221 | upper_32_bits(fb_location)); | |
1222 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, | |
1223 | upper_32_bits(fb_location)); | |
1224 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
1225 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); | |
1226 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, | |
1227 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); | |
1228 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); | |
fa6bee46 | 1229 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
bcc1c2a1 AD |
1230 | |
1231 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); | |
1232 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); | |
1233 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); | |
1234 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); | |
4dd19b0d CB |
1235 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1236 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); | |
bcc1c2a1 | 1237 | |
01f2c773 | 1238 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
bcc1c2a1 AD |
1239 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1240 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); | |
1241 | ||
1242 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, | |
1b619250 | 1243 | target_fb->height); |
bcc1c2a1 AD |
1244 | x &= ~3; |
1245 | y &= ~1; | |
1246 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, | |
1247 | (x << 16) | y); | |
adcfde51 AD |
1248 | viewport_w = crtc->mode.hdisplay; |
1249 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; | |
bcc1c2a1 | 1250 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
adcfde51 | 1251 | (viewport_w << 16) | viewport_h); |
bcc1c2a1 | 1252 | |
fb9674bd AD |
1253 | /* pageflip setup */ |
1254 | /* make sure flip is at vb rather than hb */ | |
1255 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); | |
1256 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; | |
1257 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); | |
1258 | ||
1259 | /* set pageflip to happen anywhere in vblank interval */ | |
1260 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); | |
1261 | ||
4dd19b0d CB |
1262 | if (!atomic && fb && fb != crtc->fb) { |
1263 | radeon_fb = to_radeon_framebuffer(fb); | |
7e4d15d9 | 1264 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
bcc1c2a1 AD |
1265 | r = radeon_bo_reserve(rbo, false); |
1266 | if (unlikely(r != 0)) | |
1267 | return r; | |
1268 | radeon_bo_unpin(rbo); | |
1269 | radeon_bo_unreserve(rbo); | |
1270 | } | |
1271 | ||
1272 | /* Bytes per pixel may have changed */ | |
1273 | radeon_bandwidth_update(rdev); | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
4dd19b0d CB |
1278 | static int avivo_crtc_do_set_base(struct drm_crtc *crtc, |
1279 | struct drm_framebuffer *fb, | |
1280 | int x, int y, int atomic) | |
771fe6b9 JG |
1281 | { |
1282 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1283 | struct drm_device *dev = crtc->dev; | |
1284 | struct radeon_device *rdev = dev->dev_private; | |
1285 | struct radeon_framebuffer *radeon_fb; | |
1286 | struct drm_gem_object *obj; | |
4c788679 | 1287 | struct radeon_bo *rbo; |
4dd19b0d | 1288 | struct drm_framebuffer *target_fb; |
771fe6b9 | 1289 | uint64_t fb_location; |
e024e110 | 1290 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
fa6bee46 | 1291 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
adcfde51 | 1292 | u32 tmp, viewport_w, viewport_h; |
4c788679 | 1293 | int r; |
771fe6b9 | 1294 | |
2de3b484 | 1295 | /* no fb bound */ |
4dd19b0d | 1296 | if (!atomic && !crtc->fb) { |
d9fdaafb | 1297 | DRM_DEBUG_KMS("No FB bound\n"); |
2de3b484 JG |
1298 | return 0; |
1299 | } | |
771fe6b9 | 1300 | |
4dd19b0d CB |
1301 | if (atomic) { |
1302 | radeon_fb = to_radeon_framebuffer(fb); | |
1303 | target_fb = fb; | |
1304 | } | |
1305 | else { | |
1306 | radeon_fb = to_radeon_framebuffer(crtc->fb); | |
1307 | target_fb = crtc->fb; | |
1308 | } | |
771fe6b9 JG |
1309 | |
1310 | obj = radeon_fb->obj; | |
7e4d15d9 | 1311 | rbo = gem_to_radeon_bo(obj); |
4c788679 JG |
1312 | r = radeon_bo_reserve(rbo, false); |
1313 | if (unlikely(r != 0)) | |
1314 | return r; | |
4dd19b0d CB |
1315 | |
1316 | /* If atomic, assume fb object is pinned & idle & fenced and | |
1317 | * just update base pointers | |
1318 | */ | |
1319 | if (atomic) | |
1320 | fb_location = radeon_bo_gpu_offset(rbo); | |
1321 | else { | |
1322 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); | |
1323 | if (unlikely(r != 0)) { | |
1324 | radeon_bo_unreserve(rbo); | |
1325 | return -EINVAL; | |
1326 | } | |
771fe6b9 | 1327 | } |
4c788679 JG |
1328 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
1329 | radeon_bo_unreserve(rbo); | |
771fe6b9 | 1330 | |
4dd19b0d | 1331 | switch (target_fb->bits_per_pixel) { |
41456df2 DA |
1332 | case 8: |
1333 | fb_format = | |
1334 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | | |
1335 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; | |
1336 | break; | |
771fe6b9 JG |
1337 | case 15: |
1338 | fb_format = | |
1339 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | | |
1340 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; | |
1341 | break; | |
1342 | case 16: | |
1343 | fb_format = | |
1344 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | | |
1345 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; | |
fa6bee46 AD |
1346 | #ifdef __BIG_ENDIAN |
1347 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; | |
1348 | #endif | |
771fe6b9 JG |
1349 | break; |
1350 | case 24: | |
1351 | case 32: | |
1352 | fb_format = | |
1353 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | | |
1354 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; | |
fa6bee46 AD |
1355 | #ifdef __BIG_ENDIAN |
1356 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; | |
1357 | #endif | |
771fe6b9 JG |
1358 | break; |
1359 | default: | |
1360 | DRM_ERROR("Unsupported screen depth %d\n", | |
4dd19b0d | 1361 | target_fb->bits_per_pixel); |
771fe6b9 JG |
1362 | return -EINVAL; |
1363 | } | |
1364 | ||
40c4ac1c AD |
1365 | if (rdev->family >= CHIP_R600) { |
1366 | if (tiling_flags & RADEON_TILING_MACRO) | |
1367 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; | |
1368 | else if (tiling_flags & RADEON_TILING_MICRO) | |
1369 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; | |
1370 | } else { | |
1371 | if (tiling_flags & RADEON_TILING_MACRO) | |
1372 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; | |
cf2f05d3 | 1373 | |
40c4ac1c AD |
1374 | if (tiling_flags & RADEON_TILING_MICRO) |
1375 | fb_format |= AVIVO_D1GRPH_TILED; | |
1376 | } | |
e024e110 | 1377 | |
771fe6b9 JG |
1378 | if (radeon_crtc->crtc_id == 0) |
1379 | WREG32(AVIVO_D1VGA_CONTROL, 0); | |
1380 | else | |
1381 | WREG32(AVIVO_D2VGA_CONTROL, 0); | |
c290dadf AD |
1382 | |
1383 | if (rdev->family >= CHIP_RV770) { | |
1384 | if (radeon_crtc->crtc_id) { | |
95347871 AD |
1385 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1386 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); | |
c290dadf | 1387 | } else { |
95347871 AD |
1388 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
1389 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); | |
c290dadf AD |
1390 | } |
1391 | } | |
771fe6b9 JG |
1392 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
1393 | (u32) fb_location); | |
1394 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + | |
1395 | radeon_crtc->crtc_offset, (u32) fb_location); | |
1396 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); | |
fa6bee46 AD |
1397 | if (rdev->family >= CHIP_R600) |
1398 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); | |
771fe6b9 JG |
1399 | |
1400 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); | |
1401 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); | |
1402 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); | |
1403 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); | |
4dd19b0d CB |
1404 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
1405 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); | |
771fe6b9 | 1406 | |
01f2c773 | 1407 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
771fe6b9 JG |
1408 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
1409 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); | |
1410 | ||
1411 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, | |
1b619250 | 1412 | target_fb->height); |
771fe6b9 JG |
1413 | x &= ~3; |
1414 | y &= ~1; | |
1415 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, | |
1416 | (x << 16) | y); | |
adcfde51 AD |
1417 | viewport_w = crtc->mode.hdisplay; |
1418 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; | |
771fe6b9 | 1419 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
adcfde51 | 1420 | (viewport_w << 16) | viewport_h); |
771fe6b9 | 1421 | |
fb9674bd AD |
1422 | /* pageflip setup */ |
1423 | /* make sure flip is at vb rather than hb */ | |
1424 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); | |
1425 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; | |
1426 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); | |
1427 | ||
1428 | /* set pageflip to happen anywhere in vblank interval */ | |
1429 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); | |
1430 | ||
4dd19b0d CB |
1431 | if (!atomic && fb && fb != crtc->fb) { |
1432 | radeon_fb = to_radeon_framebuffer(fb); | |
7e4d15d9 | 1433 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
4c788679 JG |
1434 | r = radeon_bo_reserve(rbo, false); |
1435 | if (unlikely(r != 0)) | |
1436 | return r; | |
1437 | radeon_bo_unpin(rbo); | |
1438 | radeon_bo_unreserve(rbo); | |
771fe6b9 | 1439 | } |
f30f37de MD |
1440 | |
1441 | /* Bytes per pixel may have changed */ | |
1442 | radeon_bandwidth_update(rdev); | |
1443 | ||
771fe6b9 JG |
1444 | return 0; |
1445 | } | |
1446 | ||
54f088a9 AD |
1447 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
1448 | struct drm_framebuffer *old_fb) | |
1449 | { | |
1450 | struct drm_device *dev = crtc->dev; | |
1451 | struct radeon_device *rdev = dev->dev_private; | |
1452 | ||
bcc1c2a1 | 1453 | if (ASIC_IS_DCE4(rdev)) |
c9417bdd | 1454 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
4dd19b0d CB |
1455 | else if (ASIC_IS_AVIVO(rdev)) |
1456 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
1457 | else | |
1458 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
1459 | } | |
1460 | ||
1461 | int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, | |
1462 | struct drm_framebuffer *fb, | |
21c74a8e | 1463 | int x, int y, enum mode_set_atomic state) |
4dd19b0d CB |
1464 | { |
1465 | struct drm_device *dev = crtc->dev; | |
1466 | struct radeon_device *rdev = dev->dev_private; | |
1467 | ||
1468 | if (ASIC_IS_DCE4(rdev)) | |
c9417bdd | 1469 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
bcc1c2a1 | 1470 | else if (ASIC_IS_AVIVO(rdev)) |
4dd19b0d | 1471 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
54f088a9 | 1472 | else |
4dd19b0d | 1473 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
54f088a9 AD |
1474 | } |
1475 | ||
615e0cb6 AD |
1476 | /* properly set additional regs when using atombios */ |
1477 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) | |
1478 | { | |
1479 | struct drm_device *dev = crtc->dev; | |
1480 | struct radeon_device *rdev = dev->dev_private; | |
1481 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1482 | u32 disp_merge_cntl; | |
1483 | ||
1484 | switch (radeon_crtc->crtc_id) { | |
1485 | case 0: | |
1486 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); | |
1487 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; | |
1488 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); | |
1489 | break; | |
1490 | case 1: | |
1491 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); | |
1492 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; | |
1493 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); | |
1494 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); | |
1495 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); | |
1496 | break; | |
1497 | } | |
1498 | } | |
1499 | ||
f3dd8508 AD |
1500 | /** |
1501 | * radeon_get_pll_use_mask - look up a mask of which pplls are in use | |
1502 | * | |
1503 | * @crtc: drm crtc | |
1504 | * | |
1505 | * Returns the mask of which PPLLs (Pixel PLLs) are in use. | |
1506 | */ | |
1507 | static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) | |
1508 | { | |
1509 | struct drm_device *dev = crtc->dev; | |
1510 | struct drm_crtc *test_crtc; | |
57b35e29 | 1511 | struct radeon_crtc *test_radeon_crtc; |
f3dd8508 AD |
1512 | u32 pll_in_use = 0; |
1513 | ||
1514 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { | |
1515 | if (crtc == test_crtc) | |
1516 | continue; | |
1517 | ||
57b35e29 AD |
1518 | test_radeon_crtc = to_radeon_crtc(test_crtc); |
1519 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) | |
1520 | pll_in_use |= (1 << test_radeon_crtc->pll_id); | |
f3dd8508 AD |
1521 | } |
1522 | return pll_in_use; | |
1523 | } | |
1524 | ||
1525 | /** | |
1526 | * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP | |
1527 | * | |
1528 | * @crtc: drm crtc | |
1529 | * | |
1530 | * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is | |
1531 | * also in DP mode. For DP, a single PPLL can be used for all DP | |
1532 | * crtcs/encoders. | |
1533 | */ | |
1534 | static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) | |
1535 | { | |
1536 | struct drm_device *dev = crtc->dev; | |
57b35e29 | 1537 | struct drm_crtc *test_crtc; |
5df3196b | 1538 | struct radeon_crtc *test_radeon_crtc; |
f3dd8508 | 1539 | |
57b35e29 AD |
1540 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1541 | if (crtc == test_crtc) | |
1542 | continue; | |
1543 | test_radeon_crtc = to_radeon_crtc(test_crtc); | |
1544 | if (test_radeon_crtc->encoder && | |
1545 | ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { | |
1546 | /* for DP use the same PLL for all */ | |
1547 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) | |
1548 | return test_radeon_crtc->pll_id; | |
f3dd8508 AD |
1549 | } |
1550 | } | |
1551 | return ATOM_PPLL_INVALID; | |
1552 | } | |
1553 | ||
2f454cf1 AD |
1554 | /** |
1555 | * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc | |
1556 | * | |
1557 | * @crtc: drm crtc | |
1558 | * @encoder: drm encoder | |
1559 | * | |
1560 | * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can | |
1561 | * be shared (i.e., same clock). | |
1562 | */ | |
5df3196b | 1563 | static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) |
2f454cf1 | 1564 | { |
5df3196b | 1565 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
2f454cf1 | 1566 | struct drm_device *dev = crtc->dev; |
9642ac0e | 1567 | struct drm_crtc *test_crtc; |
5df3196b | 1568 | struct radeon_crtc *test_radeon_crtc; |
9642ac0e | 1569 | u32 adjusted_clock, test_adjusted_clock; |
2f454cf1 | 1570 | |
9642ac0e AD |
1571 | adjusted_clock = radeon_crtc->adjusted_clock; |
1572 | ||
1573 | if (adjusted_clock == 0) | |
1574 | return ATOM_PPLL_INVALID; | |
2f454cf1 | 1575 | |
57b35e29 AD |
1576 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
1577 | if (crtc == test_crtc) | |
1578 | continue; | |
1579 | test_radeon_crtc = to_radeon_crtc(test_crtc); | |
1580 | if (test_radeon_crtc->encoder && | |
1581 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { | |
1582 | /* check if we are already driving this connector with another crtc */ | |
1583 | if (test_radeon_crtc->connector == radeon_crtc->connector) { | |
1584 | /* if we are, return that pll */ | |
1585 | if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) | |
5df3196b | 1586 | return test_radeon_crtc->pll_id; |
2f454cf1 | 1587 | } |
57b35e29 AD |
1588 | /* for non-DP check the clock */ |
1589 | test_adjusted_clock = test_radeon_crtc->adjusted_clock; | |
1590 | if ((crtc->mode.clock == test_crtc->mode.clock) && | |
1591 | (adjusted_clock == test_adjusted_clock) && | |
1592 | (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && | |
1593 | (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) | |
1594 | return test_radeon_crtc->pll_id; | |
2f454cf1 AD |
1595 | } |
1596 | } | |
1597 | return ATOM_PPLL_INVALID; | |
1598 | } | |
1599 | ||
f3dd8508 AD |
1600 | /** |
1601 | * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. | |
1602 | * | |
1603 | * @crtc: drm crtc | |
1604 | * | |
1605 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors | |
1606 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP | |
1607 | * monitors a dedicated PPLL must be used. If a particular board has | |
1608 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming | |
1609 | * as there is no need to program the PLL itself. If we are not able to | |
1610 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to | |
1611 | * avoid messing up an existing monitor. | |
1612 | * | |
1613 | * Asic specific PLL information | |
1614 | * | |
1615 | * DCE 6.1 | |
1616 | * - PPLL2 is only available to UNIPHYA (both DP and non-DP) | |
1617 | * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) | |
1618 | * | |
1619 | * DCE 6.0 | |
1620 | * - PPLL0 is available to all UNIPHY (DP only) | |
1621 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC | |
1622 | * | |
1623 | * DCE 5.0 | |
1624 | * - DCPLL is available to all UNIPHY (DP only) | |
1625 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC | |
1626 | * | |
1627 | * DCE 3.0/4.0/4.1 | |
1628 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC | |
1629 | * | |
1630 | */ | |
bcc1c2a1 AD |
1631 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
1632 | { | |
5df3196b | 1633 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
bcc1c2a1 AD |
1634 | struct drm_device *dev = crtc->dev; |
1635 | struct radeon_device *rdev = dev->dev_private; | |
5df3196b AD |
1636 | struct radeon_encoder *radeon_encoder = |
1637 | to_radeon_encoder(radeon_crtc->encoder); | |
f3dd8508 AD |
1638 | u32 pll_in_use; |
1639 | int pll; | |
bcc1c2a1 | 1640 | |
24e1f794 | 1641 | if (ASIC_IS_DCE61(rdev)) { |
5df3196b AD |
1642 | struct radeon_encoder_atom_dig *dig = |
1643 | radeon_encoder->enc_priv; | |
1644 | ||
1645 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && | |
1646 | (dig->linkb == false)) | |
1647 | /* UNIPHY A uses PPLL2 */ | |
1648 | return ATOM_PPLL2; | |
1649 | else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { | |
1650 | /* UNIPHY B/C/D/E/F */ | |
1651 | if (rdev->clock.dp_extclk) | |
1652 | /* skip PPLL programming if using ext clock */ | |
1653 | return ATOM_PPLL_INVALID; | |
1654 | else { | |
1655 | /* use the same PPLL for all DP monitors */ | |
1656 | pll = radeon_get_shared_dp_ppll(crtc); | |
1657 | if (pll != ATOM_PPLL_INVALID) | |
1658 | return pll; | |
24e1f794 | 1659 | } |
5df3196b AD |
1660 | } else { |
1661 | /* use the same PPLL for all monitors with the same clock */ | |
1662 | pll = radeon_get_shared_nondp_ppll(crtc); | |
1663 | if (pll != ATOM_PPLL_INVALID) | |
1664 | return pll; | |
24e1f794 AD |
1665 | } |
1666 | /* UNIPHY B/C/D/E/F */ | |
f3dd8508 AD |
1667 | pll_in_use = radeon_get_pll_use_mask(crtc); |
1668 | if (!(pll_in_use & (1 << ATOM_PPLL0))) | |
24e1f794 | 1669 | return ATOM_PPLL0; |
f3dd8508 AD |
1670 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
1671 | return ATOM_PPLL1; | |
1672 | DRM_ERROR("unable to allocate a PPLL\n"); | |
1673 | return ATOM_PPLL_INVALID; | |
b4cd4961 AD |
1674 | } else if (ASIC_IS_DCE41(rdev)) { |
1675 | /* Don't share PLLs on DCE4.1 chips */ | |
1676 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { | |
1677 | if (rdev->clock.dp_extclk) | |
1678 | /* skip PPLL programming if using ext clock */ | |
1679 | return ATOM_PPLL_INVALID; | |
1680 | } | |
1681 | pll_in_use = radeon_get_pll_use_mask(crtc); | |
1682 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | |
1683 | return ATOM_PPLL1; | |
1684 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | |
1685 | return ATOM_PPLL2; | |
1686 | DRM_ERROR("unable to allocate a PPLL\n"); | |
1687 | return ATOM_PPLL_INVALID; | |
24e1f794 | 1688 | } else if (ASIC_IS_DCE4(rdev)) { |
5df3196b AD |
1689 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1690 | * depending on the asic: | |
1691 | * DCE4: PPLL or ext clock | |
1692 | * DCE5: PPLL, DCPLL, or ext clock | |
1693 | * DCE6: PPLL, PPLL0, or ext clock | |
1694 | * | |
1695 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip | |
1696 | * PPLL/DCPLL programming and only program the DP DTO for the | |
1697 | * crtc virtual pixel clock. | |
1698 | */ | |
1699 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { | |
1700 | if (rdev->clock.dp_extclk) | |
1701 | /* skip PPLL programming if using ext clock */ | |
1702 | return ATOM_PPLL_INVALID; | |
1703 | else if (ASIC_IS_DCE6(rdev)) | |
1704 | /* use PPLL0 for all DP */ | |
1705 | return ATOM_PPLL0; | |
1706 | else if (ASIC_IS_DCE5(rdev)) | |
1707 | /* use DCPLL for all DP */ | |
1708 | return ATOM_DCPLL; | |
1709 | else { | |
1710 | /* use the same PPLL for all DP monitors */ | |
1711 | pll = radeon_get_shared_dp_ppll(crtc); | |
1712 | if (pll != ATOM_PPLL_INVALID) | |
1713 | return pll; | |
bcc1c2a1 | 1714 | } |
b4cd4961 | 1715 | } else { |
5df3196b AD |
1716 | /* use the same PPLL for all monitors with the same clock */ |
1717 | pll = radeon_get_shared_nondp_ppll(crtc); | |
1718 | if (pll != ATOM_PPLL_INVALID) | |
1719 | return pll; | |
bcc1c2a1 | 1720 | } |
f3dd8508 AD |
1721 | /* all other cases */ |
1722 | pll_in_use = radeon_get_pll_use_mask(crtc); | |
f3dd8508 | 1723 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
bcc1c2a1 | 1724 | return ATOM_PPLL1; |
29dbe3bc AD |
1725 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
1726 | return ATOM_PPLL2; | |
f3dd8508 AD |
1727 | DRM_ERROR("unable to allocate a PPLL\n"); |
1728 | return ATOM_PPLL_INVALID; | |
1e4db5f2 AD |
1729 | } else { |
1730 | /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ | |
fc58acdb JG |
1731 | /* some atombios (observed in some DCE2/DCE3) code have a bug, |
1732 | * the matching btw pll and crtc is done through | |
1733 | * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the | |
1734 | * pll (1 or 2) to select which register to write. ie if using | |
1735 | * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 | |
1736 | * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to | |
1737 | * choose which value to write. Which is reverse order from | |
1738 | * register logic. So only case that works is when pllid is | |
1739 | * same as crtcid or when both pll and crtc are enabled and | |
1740 | * both use same clock. | |
1741 | * | |
1742 | * So just return crtc id as if crtc and pll were hard linked | |
1743 | * together even if they aren't | |
1744 | */ | |
1e4db5f2 | 1745 | return radeon_crtc->crtc_id; |
2f454cf1 | 1746 | } |
bcc1c2a1 AD |
1747 | } |
1748 | ||
f3f1f03e | 1749 | void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
3fa47d9e AD |
1750 | { |
1751 | /* always set DCPLL */ | |
f3f1f03e AD |
1752 | if (ASIC_IS_DCE6(rdev)) |
1753 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); | |
1754 | else if (ASIC_IS_DCE4(rdev)) { | |
3fa47d9e AD |
1755 | struct radeon_atom_ss ss; |
1756 | bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, | |
1757 | ASIC_INTERNAL_SS_ON_DCPLL, | |
1758 | rdev->clock.default_dispclk); | |
1759 | if (ss_enabled) | |
5efcc76c | 1760 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); |
3fa47d9e | 1761 | /* XXX: DCE5, make sure voltage, dispclk is high enough */ |
f3f1f03e | 1762 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
3fa47d9e | 1763 | if (ss_enabled) |
5efcc76c | 1764 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); |
3fa47d9e AD |
1765 | } |
1766 | ||
1767 | } | |
1768 | ||
771fe6b9 JG |
1769 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
1770 | struct drm_display_mode *mode, | |
1771 | struct drm_display_mode *adjusted_mode, | |
1772 | int x, int y, struct drm_framebuffer *old_fb) | |
1773 | { | |
1774 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
1775 | struct drm_device *dev = crtc->dev; | |
1776 | struct radeon_device *rdev = dev->dev_private; | |
5df3196b AD |
1777 | struct radeon_encoder *radeon_encoder = |
1778 | to_radeon_encoder(radeon_crtc->encoder); | |
54bfe496 | 1779 | bool is_tvcv = false; |
771fe6b9 | 1780 | |
5df3196b AD |
1781 | if (radeon_encoder->active_device & |
1782 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) | |
1783 | is_tvcv = true; | |
771fe6b9 JG |
1784 | |
1785 | atombios_crtc_set_pll(crtc, adjusted_mode); | |
771fe6b9 | 1786 | |
54bfe496 | 1787 | if (ASIC_IS_DCE4(rdev)) |
bcc1c2a1 | 1788 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
54bfe496 AD |
1789 | else if (ASIC_IS_AVIVO(rdev)) { |
1790 | if (is_tvcv) | |
1791 | atombios_crtc_set_timing(crtc, adjusted_mode); | |
1792 | else | |
1793 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); | |
1794 | } else { | |
bcc1c2a1 | 1795 | atombios_crtc_set_timing(crtc, adjusted_mode); |
5a9bcacc AD |
1796 | if (radeon_crtc->crtc_id == 0) |
1797 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); | |
615e0cb6 | 1798 | radeon_legacy_atom_fixup(crtc); |
771fe6b9 | 1799 | } |
bcc1c2a1 | 1800 | atombios_crtc_set_base(crtc, x, y, old_fb); |
c93bb85b JG |
1801 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
1802 | atombios_scaler_setup(crtc); | |
771fe6b9 JG |
1803 | return 0; |
1804 | } | |
1805 | ||
1806 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, | |
e811f5ae | 1807 | const struct drm_display_mode *mode, |
771fe6b9 JG |
1808 | struct drm_display_mode *adjusted_mode) |
1809 | { | |
5df3196b AD |
1810 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
1811 | struct drm_device *dev = crtc->dev; | |
1812 | struct drm_encoder *encoder; | |
1813 | ||
1814 | /* assign the encoder to the radeon crtc to avoid repeated lookups later */ | |
1815 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1816 | if (encoder->crtc == crtc) { | |
1817 | radeon_crtc->encoder = encoder; | |
57b35e29 | 1818 | radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); |
5df3196b AD |
1819 | break; |
1820 | } | |
1821 | } | |
57b35e29 AD |
1822 | if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { |
1823 | radeon_crtc->encoder = NULL; | |
1824 | radeon_crtc->connector = NULL; | |
5df3196b | 1825 | return false; |
57b35e29 | 1826 | } |
c93bb85b JG |
1827 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
1828 | return false; | |
19eca43e AD |
1829 | if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
1830 | return false; | |
c0fd0834 AD |
1831 | /* pick pll */ |
1832 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); | |
1833 | /* if we can't get a PPLL for a non-DP encoder, fail */ | |
1834 | if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && | |
1835 | !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) | |
1836 | return false; | |
1837 | ||
771fe6b9 JG |
1838 | return true; |
1839 | } | |
1840 | ||
1841 | static void atombios_crtc_prepare(struct drm_crtc *crtc) | |
1842 | { | |
6c0ae2ab AD |
1843 | struct drm_device *dev = crtc->dev; |
1844 | struct radeon_device *rdev = dev->dev_private; | |
267364ac | 1845 | |
6c0ae2ab AD |
1846 | /* disable crtc pair power gating before programming */ |
1847 | if (ASIC_IS_DCE6(rdev)) | |
1848 | atombios_powergate_crtc(crtc, ATOM_DISABLE); | |
1849 | ||
37b4390e | 1850 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
a348c84d | 1851 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
771fe6b9 JG |
1852 | } |
1853 | ||
1854 | static void atombios_crtc_commit(struct drm_crtc *crtc) | |
1855 | { | |
1856 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); | |
37b4390e | 1857 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
771fe6b9 JG |
1858 | } |
1859 | ||
37f9003b AD |
1860 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
1861 | { | |
1862 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); | |
64199870 AD |
1863 | struct drm_device *dev = crtc->dev; |
1864 | struct radeon_device *rdev = dev->dev_private; | |
8e8e523d | 1865 | struct radeon_atom_ss ss; |
4e58591c | 1866 | int i; |
8e8e523d | 1867 | |
37f9003b | 1868 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
0e3d50bf AD |
1869 | if (ASIC_IS_DCE6(rdev)) |
1870 | atombios_powergate_crtc(crtc, ATOM_ENABLE); | |
37f9003b | 1871 | |
4e58591c AD |
1872 | for (i = 0; i < rdev->num_crtc; i++) { |
1873 | if (rdev->mode_info.crtcs[i] && | |
1874 | rdev->mode_info.crtcs[i]->enabled && | |
1875 | i != radeon_crtc->crtc_id && | |
1876 | radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { | |
1877 | /* one other crtc is using this pll don't turn | |
1878 | * off the pll | |
1879 | */ | |
1880 | goto done; | |
1881 | } | |
1882 | } | |
1883 | ||
37f9003b AD |
1884 | switch (radeon_crtc->pll_id) { |
1885 | case ATOM_PPLL1: | |
1886 | case ATOM_PPLL2: | |
1887 | /* disable the ppll */ | |
1888 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, | |
8e8e523d | 1889 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
37f9003b | 1890 | break; |
64199870 AD |
1891 | case ATOM_PPLL0: |
1892 | /* disable the ppll */ | |
1893 | if (ASIC_IS_DCE61(rdev)) | |
1894 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, | |
1895 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); | |
1896 | break; | |
37f9003b AD |
1897 | default: |
1898 | break; | |
1899 | } | |
4e58591c | 1900 | done: |
f3dd8508 | 1901 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
9642ac0e | 1902 | radeon_crtc->adjusted_clock = 0; |
5df3196b | 1903 | radeon_crtc->encoder = NULL; |
57b35e29 | 1904 | radeon_crtc->connector = NULL; |
37f9003b AD |
1905 | } |
1906 | ||
771fe6b9 JG |
1907 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
1908 | .dpms = atombios_crtc_dpms, | |
1909 | .mode_fixup = atombios_crtc_mode_fixup, | |
1910 | .mode_set = atombios_crtc_mode_set, | |
1911 | .mode_set_base = atombios_crtc_set_base, | |
4dd19b0d | 1912 | .mode_set_base_atomic = atombios_crtc_set_base_atomic, |
771fe6b9 JG |
1913 | .prepare = atombios_crtc_prepare, |
1914 | .commit = atombios_crtc_commit, | |
068143d3 | 1915 | .load_lut = radeon_crtc_load_lut, |
37f9003b | 1916 | .disable = atombios_crtc_disable, |
771fe6b9 JG |
1917 | }; |
1918 | ||
1919 | void radeon_atombios_init_crtc(struct drm_device *dev, | |
1920 | struct radeon_crtc *radeon_crtc) | |
1921 | { | |
bcc1c2a1 AD |
1922 | struct radeon_device *rdev = dev->dev_private; |
1923 | ||
1924 | if (ASIC_IS_DCE4(rdev)) { | |
1925 | switch (radeon_crtc->crtc_id) { | |
1926 | case 0: | |
1927 | default: | |
12d7798f | 1928 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
bcc1c2a1 AD |
1929 | break; |
1930 | case 1: | |
12d7798f | 1931 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
bcc1c2a1 AD |
1932 | break; |
1933 | case 2: | |
12d7798f | 1934 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
bcc1c2a1 AD |
1935 | break; |
1936 | case 3: | |
12d7798f | 1937 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
bcc1c2a1 AD |
1938 | break; |
1939 | case 4: | |
12d7798f | 1940 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
bcc1c2a1 AD |
1941 | break; |
1942 | case 5: | |
12d7798f | 1943 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
bcc1c2a1 AD |
1944 | break; |
1945 | } | |
1946 | } else { | |
1947 | if (radeon_crtc->crtc_id == 1) | |
1948 | radeon_crtc->crtc_offset = | |
1949 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; | |
1950 | else | |
1951 | radeon_crtc->crtc_offset = 0; | |
1952 | } | |
f3dd8508 | 1953 | radeon_crtc->pll_id = ATOM_PPLL_INVALID; |
9642ac0e | 1954 | radeon_crtc->adjusted_clock = 0; |
5df3196b | 1955 | radeon_crtc->encoder = NULL; |
57b35e29 | 1956 | radeon_crtc->connector = NULL; |
771fe6b9 JG |
1957 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
1958 | } |