[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nvc0_instmem.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <drm/drmP.h>

#include "nouveau_drv.h"
#include "nouveau_vm.h"

struct nvc0_instmem_priv {
	struct nouveau_gpuobj  *bar1_pgd;
	struct nouveau_channel *bar1;
	struct nouveau_gpuobj  *bar3_pgd;
	struct nouveau_channel *bar3;
};

int
nvc0_instmem_suspend(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	dev_priv->ramin_available = false;
	return 0;
}

void
nvc0_instmem_resume(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_instmem_priv *priv = dev_priv->engine.instmem.priv;

	nv_mask(dev, 0x100c80, 0x00000001, 0x00000000);
	nv_wr32(dev, 0x001704, 0x80000000 | priv->bar1->ramin->vinst >> 12);
	nv_wr32(dev, 0x001714, 0xc0000000 | priv->bar3->ramin->vinst >> 12);
	dev_priv->ramin_available = true;
}

static void
nvc0_channel_del(struct nouveau_channel **pchan)
{
	struct nouveau_channel *chan;

	chan = *pchan;
	*pchan = NULL;
	if (!chan)
		return;

	nouveau_vm_ref(NULL, &chan->vm, NULL);
	if (drm_mm_initialized(&chan->ramin_heap))
		drm_mm_takedown(&chan->ramin_heap);
	nouveau_gpuobj_ref(NULL, &chan->ramin);
	kfree(chan);
}

static int
nvc0_channel_new(struct drm_device *dev, u32 size, struct nouveau_vm *vm,
		 struct nouveau_channel **pchan,
		 struct nouveau_gpuobj *pgd, u64 vm_size)
{
	struct nouveau_channel *chan;
	int ret;

	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
	if (!chan)
		return -ENOMEM;
	chan->dev = dev;

	ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
	if (ret) {
		nvc0_channel_del(&chan);
		return ret;
	}

	ret = drm_mm_init(&chan->ramin_heap, 0x1000, size - 0x1000);
	if (ret) {
		nvc0_channel_del(&chan);
		return ret;
	}

	ret = nouveau_vm_ref(vm, &chan->vm, NULL);
	if (ret) {
		nvc0_channel_del(&chan);
		return ret;
	}

	nv_wo32(chan->ramin, 0x0200, lower_32_bits(pgd->vinst));
	nv_wo32(chan->ramin, 0x0204, upper_32_bits(pgd->vinst));
	nv_wo32(chan->ramin, 0x0208, lower_32_bits(vm_size - 1));
	nv_wo32(chan->ramin, 0x020c, upper_32_bits(vm_size - 1));

	*pchan = chan;
	return 0;
}

int
nvc0_instmem_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	struct pci_dev *pdev = dev->pdev;
	struct nvc0_instmem_priv *priv;
	struct nouveau_vm *vm = NULL;
	int ret;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;
	pinstmem->priv = priv;

	/* BAR3 VM */
	ret = nouveau_vm_new(dev, 0, pci_resource_len(pdev, 3), 0,
			     &dev_priv->bar3_vm);
	if (ret)
		goto error;

	ret = nouveau_gpuobj_new(dev, NULL,
				 (pci_resource_len(pdev, 3) >> 12) * 8, 0,
				 NVOBJ_FLAG_DONT_MAP |
				 NVOBJ_FLAG_ZERO_ALLOC,
				 &dev_priv->bar3_vm->pgt[0].obj[0]);
	if (ret)
		goto error;
	dev_priv->bar3_vm->pgt[0].refcount[0] = 1;

	nv50_instmem_map(dev_priv->bar3_vm->pgt[0].obj[0]);

	ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 4096,
				 NVOBJ_FLAG_ZERO_ALLOC, &priv->bar3_pgd);
	if (ret)
		goto error;

	ret = nouveau_vm_ref(dev_priv->bar3_vm, &vm, priv->bar3_pgd);
	if (ret)
		goto error;
	nouveau_vm_ref(NULL, &vm, NULL);

	ret = nvc0_channel_new(dev, 8192, dev_priv->bar3_vm, &priv->bar3,
			       priv->bar3_pgd, pci_resource_len(dev->pdev, 3));
	if (ret)
		goto error;

	/* BAR1 VM */
	ret = nouveau_vm_new(dev, 0, pci_resource_len(pdev, 1), 0, &vm);
	if (ret)
		goto error;

	ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 4096,
				 NVOBJ_FLAG_ZERO_ALLOC, &priv->bar1_pgd);
	if (ret)
		goto error;

	ret = nouveau_vm_ref(vm, &dev_priv->bar1_vm, priv->bar1_pgd);
	if (ret)
		goto error;
	nouveau_vm_ref(NULL, &vm, NULL);

	ret = nvc0_channel_new(dev, 8192, dev_priv->bar1_vm, &priv->bar1,
			       priv->bar1_pgd, pci_resource_len(dev->pdev, 1));
	if (ret)
		goto error;

	/* channel vm */
	ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
			     &dev_priv->chan_vm);
	if (ret)
		goto error;

	nvc0_instmem_resume(dev);
	return 0;
error:
	nvc0_instmem_takedown(dev);
	return ret;
}

void
nvc0_instmem_takedown(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nvc0_instmem_priv *priv = dev_priv->engine.instmem.priv;
	struct nouveau_vm *vm = NULL;

	nvc0_instmem_suspend(dev);

	nv_wr32(dev, 0x1704, 0x00000000);
	nv_wr32(dev, 0x1714, 0x00000000);

	nouveau_vm_ref(NULL, &dev_priv->chan_vm, NULL);

	nvc0_channel_del(&priv->bar1);
	nouveau_vm_ref(NULL, &dev_priv->bar1_vm, priv->bar1_pgd);
	nouveau_gpuobj_ref(NULL, &priv->bar1_pgd);

	nvc0_channel_del(&priv->bar3);
	nouveau_vm_ref(dev_priv->bar3_vm, &vm, NULL);
	nouveau_vm_ref(NULL, &vm, priv->bar3_pgd);
	nouveau_gpuobj_ref(NULL, &priv->bar3_pgd);
	nouveau_gpuobj_ref(NULL, &dev_priv->bar3_vm->pgt[0].obj[0]);
	nouveau_vm_ref(NULL, &dev_priv->bar3_vm, NULL);

	dev_priv->engine.instmem.priv = NULL;
	kfree(priv);
}
Commit	Line	Data
4b223eef BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
760285e7	25	#include <drm/drmP.h>
4b223eef BS	26
4b223eef BS	27	#include "nouveau_drv.h"
8984e046	28	#include "nouveau_vm.h"
4b223eef	29
8984e046 BS	30	struct nvc0_instmem_priv {
	31	struct nouveau_gpuobj *bar1_pgd;
	32	struct nouveau_channel *bar1;
	33	struct nouveau_gpuobj *bar3_pgd;
	34	struct nouveau_channel *bar3;
e41115d0 BS	35	};
e41115d0 BS	36
4b223eef	37	int
8984e046	38	nvc0_instmem_suspend(struct drm_device *dev)
4b223eef	39	{
8984e046	40	struct drm_nouveau_private *dev_priv = dev->dev_private;
68b83a93	41
8984e046	42	dev_priv->ramin_available = false;
4b223eef BS	43	return 0;
	44	}
	45
	46	void
8984e046	47	nvc0_instmem_resume(struct drm_device *dev)
4b223eef	48	{
8984e046 BS	49	struct drm_nouveau_private *dev_priv = dev->dev_private;
8984e046 BS	50	struct nvc0_instmem_priv *priv = dev_priv->engine.instmem.priv;
e41115d0	51
8984e046 BS	52	nv_mask(dev, 0x100c80, 0x00000001, 0x00000000);
	53	nv_wr32(dev, 0x001704, 0x80000000 \| priv->bar1->ramin->vinst >> 12);
	54	nv_wr32(dev, 0x001714, 0xc0000000 \| priv->bar3->ramin->vinst >> 12);
	55	dev_priv->ramin_available = true;
4b223eef BS	56	}
4b223eef BS	57
8984e046 BS	58	static void
8984e046 BS	59	nvc0_channel_del(struct nouveau_channel **pchan)
4b223eef	60	{
8984e046	61	struct nouveau_channel *chan;
68b83a93	62
8984e046 BS	63	chan = *pchan;
	64	*pchan = NULL;
	65	if (!chan)
	66	return;
68b83a93	67
8984e046	68	nouveau_vm_ref(NULL, &chan->vm, NULL);
31a5b8ce	69	if (drm_mm_initialized(&chan->ramin_heap))
8984e046 BS	70	drm_mm_takedown(&chan->ramin_heap);
	71	nouveau_gpuobj_ref(NULL, &chan->ramin);
	72	kfree(chan);
4b223eef BS	73	}
4b223eef BS	74
8984e046 BS	75	static int
	76	nvc0_channel_new(struct drm_device dev, u32 size, struct nouveau_vm vm,
	77	struct nouveau_channel **pchan,
	78	struct nouveau_gpuobj *pgd, u64 vm_size)
4b223eef	79	{
8984e046 BS	80	struct nouveau_channel *chan;
8984e046 BS	81	int ret;
e41115d0	82
8984e046 BS	83	chan = kzalloc(sizeof(*chan), GFP_KERNEL);
	84	if (!chan)
	85	return -ENOMEM;
	86	chan->dev = dev;
68b83a93	87
8984e046 BS	88	ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin);
	89	if (ret) {
	90	nvc0_channel_del(&chan);
	91	return ret;
	92	}
68b83a93	93
8984e046 BS	94	ret = drm_mm_init(&chan->ramin_heap, 0x1000, size - 0x1000);
	95	if (ret) {
	96	nvc0_channel_del(&chan);
	97	return ret;
68b83a93	98	}
68b83a93	99
8984e046 BS	100	ret = nouveau_vm_ref(vm, &chan->vm, NULL);
	101	if (ret) {
	102	nvc0_channel_del(&chan);
	103	return ret;
	104	}
4b223eef	105
8984e046 BS	106	nv_wo32(chan->ramin, 0x0200, lower_32_bits(pgd->vinst));
	107	nv_wo32(chan->ramin, 0x0204, upper_32_bits(pgd->vinst));
	108	nv_wo32(chan->ramin, 0x0208, lower_32_bits(vm_size - 1));
	109	nv_wo32(chan->ramin, 0x020c, upper_32_bits(vm_size - 1));
	110
	111	*pchan = chan;
	112	return 0;
4b223eef BS	113	}
	114
	115	int
8984e046	116	nvc0_instmem_init(struct drm_device *dev)
4b223eef	117	{
147cad09	118	struct drm_nouveau_private *dev_priv = dev->dev_private;
8984e046 BS	119	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	120	struct pci_dev *pdev = dev->pdev;
	121	struct nvc0_instmem_priv *priv;
	122	struct nouveau_vm *vm = NULL;
	123	int ret;
147cad09	124
8984e046 BS	125	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
8984e046 BS	126	if (!priv)
147cad09	127	return -ENOMEM;
8984e046 BS	128	pinstmem->priv = priv;
	129
	130	/* BAR3 VM */
	131	ret = nouveau_vm_new(dev, 0, pci_resource_len(pdev, 3), 0,
	132	&dev_priv->bar3_vm);
	133	if (ret)
	134	goto error;
	135
	136	ret = nouveau_gpuobj_new(dev, NULL,
	137	(pci_resource_len(pdev, 3) >> 12) * 8, 0,
	138	NVOBJ_FLAG_DONT_MAP \|
	139	NVOBJ_FLAG_ZERO_ALLOC,
	140	&dev_priv->bar3_vm->pgt[0].obj[0]);
	141	if (ret)
	142	goto error;
	143	dev_priv->bar3_vm->pgt[0].refcount[0] = 1;
	144
	145	nv50_instmem_map(dev_priv->bar3_vm->pgt[0].obj[0]);
	146
	147	ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 4096,
	148	NVOBJ_FLAG_ZERO_ALLOC, &priv->bar3_pgd);
	149	if (ret)
	150	goto error;
	151
	152	ret = nouveau_vm_ref(dev_priv->bar3_vm, &vm, priv->bar3_pgd);
	153	if (ret)
	154	goto error;
	155	nouveau_vm_ref(NULL, &vm, NULL);
	156
	157	ret = nvc0_channel_new(dev, 8192, dev_priv->bar3_vm, &priv->bar3,
	158	priv->bar3_pgd, pci_resource_len(dev->pdev, 3));
	159	if (ret)
	160	goto error;
	161
	162	/* BAR1 VM */
	163	ret = nouveau_vm_new(dev, 0, pci_resource_len(pdev, 1), 0, &vm);
	164	if (ret)
	165	goto error;
	166
	167	ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 4096,
	168	NVOBJ_FLAG_ZERO_ALLOC, &priv->bar1_pgd);
	169	if (ret)
	170	goto error;
	171
	172	ret = nouveau_vm_ref(vm, &dev_priv->bar1_vm, priv->bar1_pgd);
	173	if (ret)
	174	goto error;
	175	nouveau_vm_ref(NULL, &vm, NULL);
	176
	177	ret = nvc0_channel_new(dev, 8192, dev_priv->bar1_vm, &priv->bar1,
	178	priv->bar1_pgd, pci_resource_len(dev->pdev, 1));
	179	if (ret)
	180	goto error;
	181
99805566	182	/* channel vm */
5de8037a BS	183	ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
5de8037a BS	184	&dev_priv->chan_vm);
99805566 BS	185	if (ret)
	186	goto error;
	187
8984e046	188	nvc0_instmem_resume(dev);
4b223eef	189	return 0;
8984e046 BS	190	error:
	191	nvc0_instmem_takedown(dev);
	192	return ret;
4b223eef BS	193	}
	194
	195	void
8984e046	196	nvc0_instmem_takedown(struct drm_device *dev)
4b223eef	197	{
68b83a93	198	struct drm_nouveau_private *dev_priv = dev->dev_private;
8984e046 BS	199	struct nvc0_instmem_priv *priv = dev_priv->engine.instmem.priv;
8984e046 BS	200	struct nouveau_vm *vm = NULL;
68b83a93	201
8984e046	202	nvc0_instmem_suspend(dev);
68b83a93	203
8984e046 BS	204	nv_wr32(dev, 0x1704, 0x00000000);
8984e046 BS	205	nv_wr32(dev, 0x1714, 0x00000000);
68b83a93	206
5de8037a	207	nouveau_vm_ref(NULL, &dev_priv->chan_vm, NULL);
99805566	208
8984e046 BS	209	nvc0_channel_del(&priv->bar1);
	210	nouveau_vm_ref(NULL, &dev_priv->bar1_vm, priv->bar1_pgd);
	211	nouveau_gpuobj_ref(NULL, &priv->bar1_pgd);
68b83a93	212
8984e046 BS	213	nvc0_channel_del(&priv->bar3);
	214	nouveau_vm_ref(dev_priv->bar3_vm, &vm, NULL);
	215	nouveau_vm_ref(NULL, &vm, priv->bar3_pgd);
	216	nouveau_gpuobj_ref(NULL, &priv->bar3_pgd);
	217	nouveau_gpuobj_ref(NULL, &dev_priv->bar3_vm->pgt[0].obj[0]);
	218	nouveau_vm_ref(NULL, &dev_priv->bar3_vm, NULL);
4b223eef	219
8984e046 BS	220	dev_priv->engine.instmem.priv = NULL;
8984e046 BS	221	kfree(priv);
4b223eef BS	222	}
4b223eef BS	223