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drm/nvc0: implement support for copy engines
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nvc0_graph.c
CommitLineData
4b223eef
BS		 1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
966a5b7d
BS		 25#include <linux/firmware.h>
26
4b223eef
BS		 27#include "drmP.h"
28
29#include "nouveau_drv.h"
966a5b7d
BS		 30#include "nouveau_mm.h"
31#include "nvc0_graph.h"
32
7a45cd19
BS		 33static int
34nvc0_graph_load_context(struct nouveau_channel *chan)
35{
36 struct drm_device *dev = chan->dev;
37
38 nv_wr32(dev, 0x409840, 0x00000030);
39 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
40 nv_wr32(dev, 0x409504, 0x00000003);
41 if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
42 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
43
44 return 0;
45}
46
47static int
48nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
49{
50 nv_wr32(dev, 0x409840, 0x00000003);
51 nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
52 nv_wr32(dev, 0x409504, 0x00000009);
53 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
54 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
55 return -EBUSY;
56 }
57
58 return 0;
59}
60
966a5b7d
BS		 61static int
62nvc0_graph_construct_context(struct nouveau_channel *chan)
63{
64 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
7a45cd19
BS		 65 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
66 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
966a5b7d
BS		 67 struct drm_device *dev = chan->dev;
68 int ret, i;
69 u32 *ctx;
70
71 ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
72 if (!ctx)
73 return -ENOMEM;
74
75 nvc0_graph_load_context(chan);
76
77 nv_wo32(grch->grctx, 0x1c, 1);
78 nv_wo32(grch->grctx, 0x20, 0);
79 nv_wo32(grch->grctx, 0x28, 0);
80 nv_wo32(grch->grctx, 0x2c, 0);
81 dev_priv->engine.instmem.flush(dev);
82
83 ret = nvc0_grctx_generate(chan);
84 if (ret) {
85 kfree(ctx);
86 return ret;
87 }
88
89 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
90 if (ret) {
91 kfree(ctx);
92 return ret;
93 }
94
95 for (i = 0; i < priv->grctx_size; i += 4)
96 ctx[i / 4] = nv_ro32(grch->grctx, i);
97
98 priv->grctx_vals = ctx;
99 return 0;
100}
101
102static int
103nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
104{
7a45cd19
BS		 105 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
106 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
966a5b7d
BS		 107 struct drm_device *dev = chan->dev;
108 int i = 0, gpc, tp, ret;
109 u32 magic;
110
111 ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM,
112 &grch->unk408004);
113 if (ret)
114 return ret;
115
116 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM,
117 &grch->unk40800c);
118 if (ret)
119 return ret;
120
c906ca0f
BS		 121 ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096,
122 NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
966a5b7d
BS		 123 &grch->unk418810);
124 if (ret)
125 return ret;
126
127 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM,
128 &grch->mmio);
129 if (ret)
130 return ret;
131
132
133 nv_wo32(grch->mmio, i++ * 4, 0x00408004);
134 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
135 nv_wo32(grch->mmio, i++ * 4, 0x00408008);
136 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
137
138 nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
139 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
140 nv_wo32(grch->mmio, i++ * 4, 0x00408010);
141 nv_wo32(grch->mmio, i++ * 4, 0x80000000);
142
143 nv_wo32(grch->mmio, i++ * 4, 0x00418810);
144 nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12);
145 nv_wo32(grch->mmio, i++ * 4, 0x00419848);
146 nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12);
147
148 nv_wo32(grch->mmio, i++ * 4, 0x00419004);
149 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
150 nv_wo32(grch->mmio, i++ * 4, 0x00419008);
151 nv_wo32(grch->mmio, i++ * 4, 0x00000000);
152
153 nv_wo32(grch->mmio, i++ * 4, 0x00418808);
154 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
155 nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
156 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
157
158 magic = 0x02180000;
159 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
160 nv_wo32(grch->mmio, i++ * 4, magic);
161 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
162 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x02fc) {
163 u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
164 nv_wo32(grch->mmio, i++ * 4, reg);
165 nv_wo32(grch->mmio, i++ * 4, magic);
166 }
167 }
168
169 grch->mmio_nr = i / 2;
170 return 0;
171}
172
7a45cd19
BS		 173static int
174nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
4b223eef 175{
7a45cd19
BS		 176 struct drm_device *dev = chan->dev;
177 struct drm_nouveau_private *dev_priv = dev->dev_private;
966a5b7d 178 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
7a45cd19 179 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
966a5b7d 180 struct nvc0_graph_chan *grch;
966a5b7d
BS		 181 struct nouveau_gpuobj *grctx;
182 int ret, i;
183
7a45cd19
BS		 184 grch = kzalloc(sizeof(*grch), GFP_KERNEL);
185 if (!grch)
966a5b7d 186 return -ENOMEM;
7a45cd19 187 chan->engctx[NVOBJ_ENGINE_GR] = grch;
966a5b7d
BS		 188
189 ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256,
190 NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
191 &grch->grctx);
192 if (ret)
193 goto error;
966a5b7d
BS		 194 grctx = grch->grctx;
195
196 ret = nvc0_graph_create_context_mmio_list(chan);
197 if (ret)
198 goto error;
199
200 nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4);
201 nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst));
202 pinstmem->flush(dev);
203
204 if (!priv->grctx_vals) {
205 ret = nvc0_graph_construct_context(chan);
206 if (ret)
207 goto error;
208 }
209
210 for (i = 0; i < priv->grctx_size; i += 4)
211 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
212
71298e2f
EV		 213 nv_wo32(grctx, 0xf4, 0);
214 nv_wo32(grctx, 0xf8, 0);
215 nv_wo32(grctx, 0x10, grch->mmio_nr);
216 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
217 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
218 nv_wo32(grctx, 0x1c, 1);
219 nv_wo32(grctx, 0x20, 0);
220 nv_wo32(grctx, 0x28, 0);
221 nv_wo32(grctx, 0x2c, 0);
966a5b7d 222 pinstmem->flush(dev);
4b223eef 223 return 0;
966a5b7d
BS		 224
225error:
7a45cd19 226 priv->base.context_del(chan, engine);
966a5b7d 227 return ret;
4b223eef
BS		 228}
229
7a45cd19
BS		 230static void
231nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
4b223eef 232{
7a45cd19 233 struct nvc0_graph_chan *grch = chan->engctx[engine];
966a5b7d
BS		 234
235 nouveau_gpuobj_ref(NULL, &grch->mmio);
236 nouveau_gpuobj_ref(NULL, &grch->unk418810);
237 nouveau_gpuobj_ref(NULL, &grch->unk40800c);
238 nouveau_gpuobj_ref(NULL, &grch->unk408004);
239 nouveau_gpuobj_ref(NULL, &grch->grctx);
7a45cd19 240 chan->engctx[engine] = NULL;
4b223eef
BS		 241}
242
7a45cd19
BS		 243static int
244nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
245 u32 handle, u16 class)
4b223eef 246{
966a5b7d
BS		 247 return 0;
248}
249
250static int
7a45cd19 251nvc0_graph_fini(struct drm_device *dev, int engine)
966a5b7d 252{
7a45cd19
BS		 253 u32 inst = nv_rd32(dev, 0x409b00);
254 if (inst & 0x80000000) {
255 inst &= 0x0fffffff;
256 nvc0_graph_unload_context_to(dev, (u64)inst << 12);
966a5b7d
BS		 257 }
258
4b223eef
BS		 259 return 0;
260}
261
bd2f2037
BS		 262static int
263nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
264 u32 class, u32 mthd, u32 data)
265{
266 nouveau_finish_page_flip(chan, NULL);
267 return 0;
268}
269
966a5b7d
BS		 270static void
271nvc0_graph_init_obj418880(struct drm_device *dev)
272{
7a45cd19 273 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
966a5b7d
BS		 274 int i;
275
276 nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
277 nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
278 for (i = 0; i < 4; i++)
279 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
280 nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
281 nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
282}
283
284static void
285nvc0_graph_init_regs(struct drm_device *dev)
286{
287 nv_wr32(dev, 0x400080, 0x003083c2);
288 nv_wr32(dev, 0x400088, 0x00006fe7);
289 nv_wr32(dev, 0x40008c, 0x00000000);
290 nv_wr32(dev, 0x400090, 0x00000030);
291 nv_wr32(dev, 0x40013c, 0x013901f7);
292 nv_wr32(dev, 0x400140, 0x00000100);
293 nv_wr32(dev, 0x400144, 0x00000000);
294 nv_wr32(dev, 0x400148, 0x00000110);
295 nv_wr32(dev, 0x400138, 0x00000000);
296 nv_wr32(dev, 0x400130, 0x00000000);
297 nv_wr32(dev, 0x400134, 0x00000000);
298 nv_wr32(dev, 0x400124, 0x00000002);
299}
300
301static void
302nvc0_graph_init_gpc_0(struct drm_device *dev)
303{
7a45cd19 304 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
966a5b7d 305 int gpc;
f212949c
EV		 306
307 /*
308 * TP ROP UNKVAL(magic_not_rop_nr)
309 * 450: 4/0/0/0 2 3
310 * 460: 3/4/0/0 4 1
311 * 465: 3/4/4/0 4 7
312 * 470: 3/3/4/4 5 5
313 * 480: 3/4/4/4 6 6
314
315 * magicgpc918
316 * 450: 00200000 00000000001000000000000000000000
317 * 460: 00124925 00000000000100100100100100100101
318 * 465: 000ba2e9 00000000000010111010001011101001
319 * 470: 00092493 00000000000010010010010010010011
320 * 480: 00088889 00000000000010001000100010001001
321
322 * filled values up to tp_total, remainder 0
323 * 450: 00003210 00000000 00000000 00000000
324 * 460: 02321100 00000000 00000000 00000000
325 * 465: 22111000 00000233 00000000 00000000
326 * 470: 11110000 00233222 00000000 00000000
327 * 480: 11110000 03332222 00000000 00000000
328 */
329
966a5b7d
BS		 330 nv_wr32(dev, GPC_BCAST(0x0980), priv->magicgpc980[0]);
331 nv_wr32(dev, GPC_BCAST(0x0984), priv->magicgpc980[1]);
332 nv_wr32(dev, GPC_BCAST(0x0988), priv->magicgpc980[2]);
333 nv_wr32(dev, GPC_BCAST(0x098c), priv->magicgpc980[3]);
334
335 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
336 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
337 priv->tp_nr[gpc]);
338 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
339 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918);
340 }
341
342 nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918);
343 nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr);
344}
345
346static void
347nvc0_graph_init_units(struct drm_device *dev)
348{
349 nv_wr32(dev, 0x409c24, 0x000f0000);
350 nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
351 nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
352 nv_wr32(dev, 0x408030, 0xc0000000);
353 nv_wr32(dev, 0x40601c, 0xc0000000);
354 nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
355 nv_wr32(dev, 0x406018, 0xc0000000);
356 nv_wr32(dev, 0x405840, 0xc0000000);
357 nv_wr32(dev, 0x405844, 0x00ffffff);
358 nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
359 nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
360}
361
362static void
363nvc0_graph_init_gpc_1(struct drm_device *dev)
364{
7a45cd19 365 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
966a5b7d
BS		 366 int gpc, tp;
367
368 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
369 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
370 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
371 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
372 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
373 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
374 nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
375 nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
376 nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
377 nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
378 nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
0f1cb203
BS		 379 nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
380 nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
966a5b7d
BS		 381 }
382 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
383 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
384 }
385}
386
387static void
388nvc0_graph_init_rop(struct drm_device *dev)
389{
7a45cd19 390 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
966a5b7d
BS		 391 int rop;
392
393 for (rop = 0; rop < priv->rop_nr; rop++) {
394 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
395 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
396 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
397 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
398 }
399}
400
401static int
402nvc0_fuc_load_fw(struct drm_device *dev, u32 fuc_base,
403 const char *code_fw, const char *data_fw)
404{
405 const struct firmware *fw;
406 char name[32];
407 int ret, i;
408
409 snprintf(name, sizeof(name), "nouveau/%s", data_fw);
410 ret = request_firmware(&fw, name, &dev->pdev->dev);
411 if (ret) {
412 NV_ERROR(dev, "failed to load %s\n", data_fw);
413 return ret;
414 }
415
416 nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
417 for (i = 0; i < fw->size / 4; i++)
418 nv_wr32(dev, fuc_base + 0x01c4, ((u32 *)fw->data)[i]);
419 release_firmware(fw);
420
421 snprintf(name, sizeof(name), "nouveau/%s", code_fw);
422 ret = request_firmware(&fw, name, &dev->pdev->dev);
423 if (ret) {
424 NV_ERROR(dev, "failed to load %s\n", code_fw);
425 return ret;
426 }
427
428 nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
429 for (i = 0; i < fw->size / 4; i++) {
430 if ((i & 0x3f) == 0)
431 nv_wr32(dev, fuc_base + 0x0188, i >> 6);
432 nv_wr32(dev, fuc_base + 0x0184, ((u32 *)fw->data)[i]);
433 }
434 release_firmware(fw);
435
436 return 0;
437}
438
439static int
440nvc0_graph_init_ctxctl(struct drm_device *dev)
441{
7a45cd19 442 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
966a5b7d
BS		 443 u32 r000260;
444 int ret;
445
446 /* load fuc microcode */
447 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
448 ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d");
449 if (ret == 0)
eeb9cc01 450 ret = nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad");
966a5b7d
BS		 451 nv_wr32(dev, 0x000260, r000260);
452
453 if (ret)
454 return ret;
455
456 /* start both of them running */
457 nv_wr32(dev, 0x409840, 0xffffffff);
458 nv_wr32(dev, 0x41a10c, 0x00000000);
459 nv_wr32(dev, 0x40910c, 0x00000000);
460 nv_wr32(dev, 0x41a100, 0x00000002);
461 nv_wr32(dev, 0x409100, 0x00000002);
462 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
463 NV_INFO(dev, "0x409800 wait failed\n");
464
465 nv_wr32(dev, 0x409840, 0xffffffff);
466 nv_wr32(dev, 0x409500, 0x7fffffff);
467 nv_wr32(dev, 0x409504, 0x00000021);
468
469 nv_wr32(dev, 0x409840, 0xffffffff);
470 nv_wr32(dev, 0x409500, 0x00000000);
471 nv_wr32(dev, 0x409504, 0x00000010);
472 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
473 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
474 return -EBUSY;
475 }
476 priv->grctx_size = nv_rd32(dev, 0x409800);
477
478 nv_wr32(dev, 0x409840, 0xffffffff);
479 nv_wr32(dev, 0x409500, 0x00000000);
480 nv_wr32(dev, 0x409504, 0x00000016);
481 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
482 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
483 return -EBUSY;
484 }
485
486 nv_wr32(dev, 0x409840, 0xffffffff);
487 nv_wr32(dev, 0x409500, 0x00000000);
488 nv_wr32(dev, 0x409504, 0x00000025);
489 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
490 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
491 return -EBUSY;
492 }
493
494 return 0;
4b223eef
BS		 495}
496
7a45cd19
BS		 497static int
498nvc0_graph_init(struct drm_device *dev, int engine)
4b223eef 499{
966a5b7d
BS		 500 int ret;
501
966a5b7d
BS		 502 nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
503 nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
504
966a5b7d
BS		 505 nvc0_graph_init_obj418880(dev);
506 nvc0_graph_init_regs(dev);
f212949c 507 /*nvc0_graph_init_unitplemented_magics(dev);*/
966a5b7d 508 nvc0_graph_init_gpc_0(dev);
f212949c 509 /*nvc0_graph_init_unitplemented_c242(dev);*/
966a5b7d
BS		 510
511 nv_wr32(dev, 0x400500, 0x00010001);
512 nv_wr32(dev, 0x400100, 0xffffffff);
513 nv_wr32(dev, 0x40013c, 0xffffffff);
514
515 nvc0_graph_init_units(dev);
516 nvc0_graph_init_gpc_1(dev);
517 nvc0_graph_init_rop(dev);
518
519 nv_wr32(dev, 0x400108, 0xffffffff);
520 nv_wr32(dev, 0x400138, 0xffffffff);
521 nv_wr32(dev, 0x400118, 0xffffffff);
522 nv_wr32(dev, 0x400130, 0xffffffff);
523 nv_wr32(dev, 0x40011c, 0xffffffff);
524 nv_wr32(dev, 0x400134, 0xffffffff);
525 nv_wr32(dev, 0x400054, 0x34ce3464);
526
527 ret = nvc0_graph_init_ctxctl(dev);
a82dd49f
BS		 528 if (ret)
529 return ret;
530
4b223eef
BS		 531 return 0;
532}
533
d5a27370 534int
966a5b7d
BS		 535nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
536{
537 struct drm_nouveau_private *dev_priv = dev->dev_private;
538 struct nouveau_channel *chan;
539 unsigned long flags;
540 int i;
541
542 spin_lock_irqsave(&dev_priv->channels.lock, flags);
543 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
544 chan = dev_priv->channels.ptr[i];
545 if (!chan || !chan->ramin)
546 continue;
547
548 if (inst == chan->ramin->vinst)
549 break;
550 }
551 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
552 return i;
553}
554
555static void
556nvc0_graph_isr(struct drm_device *dev)
557{
558 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
559 u32 chid = nvc0_graph_isr_chid(dev, inst);
560 u32 stat = nv_rd32(dev, 0x400100);
561 u32 addr = nv_rd32(dev, 0x400704);
562 u32 mthd = (addr & 0x00003ffc);
563 u32 subc = (addr & 0x00070000) >> 16;
564 u32 data = nv_rd32(dev, 0x400708);
565 u32 code = nv_rd32(dev, 0x400110);
566 u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
567
568 if (stat & 0x00000010) {
bd2f2037
BS		 569 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
570 NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
571 "subc %d class 0x%04x mthd 0x%04x "
572 "data 0x%08x\n",
573 chid, inst, subc, class, mthd, data);
574 }
966a5b7d
BS		 575 nv_wr32(dev, 0x400100, 0x00000010);
576 stat &= ~0x00000010;
577 }
578
eae5e7f3
BS		 579 if (stat & 0x00000020) {
580 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
581 "class 0x%04x mthd 0x%04x data 0x%08x\n",
582 chid, inst, subc, class, mthd, data);
583 nv_wr32(dev, 0x400100, 0x00000020);
584 stat &= ~0x00000020;
585 }
586
966a5b7d
BS		 587 if (stat & 0x00100000) {
588 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
6effe393 589 nouveau_enum_print(nv50_data_error_names, code);
966a5b7d
BS		 590 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
591 "mthd 0x%04x data 0x%08x\n",
592 chid, inst, subc, class, mthd, data);
593 nv_wr32(dev, 0x400100, 0x00100000);
594 stat &= ~0x00100000;
595 }
596
eae5e7f3
BS		 597 if (stat & 0x00200000) {
598 u32 trap = nv_rd32(dev, 0x400108);
599 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
600 nv_wr32(dev, 0x400108, trap);
601 nv_wr32(dev, 0x400100, 0x00200000);
602 stat &= ~0x00200000;
603 }
604
966a5b7d
BS		 605 if (stat & 0x00080000) {
606 u32 ustat = nv_rd32(dev, 0x409c18);
607
608 NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat);
609
610 nv_wr32(dev, 0x409c20, ustat);
611 nv_wr32(dev, 0x400100, 0x00080000);
612 stat &= ~0x00080000;
613 }
614
615 if (stat) {
616 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
617 nv_wr32(dev, 0x400100, stat);
618 }
619
620 nv_wr32(dev, 0x400500, 0x00010001);
621}
51f73d64
BS		 622
623static void
624nvc0_runk140_isr(struct drm_device *dev)
625{
626 u32 units = nv_rd32(dev, 0x00017c) & 0x1f;
627
628 while (units) {
629 u32 unit = ffs(units) - 1;
630 u32 reg = 0x140000 + unit * 0x2000;
631 u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0);
632 u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0);
633
634 NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1);
635 units &= ~(1 << unit);
636 }
637}
7a45cd19
BS		 638
639static void
640nvc0_graph_destroy(struct drm_device *dev, int engine)
641{
642 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
643
644 nouveau_irq_unregister(dev, 12);
645 nouveau_irq_unregister(dev, 25);
646
647 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
648 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
649
650 if (priv->grctx_vals)
651 kfree(priv->grctx_vals);
652
653 NVOBJ_ENGINE_DEL(dev, GR);
654 kfree(priv);
655}
656
657int
658nvc0_graph_create(struct drm_device *dev)
659{
660 struct drm_nouveau_private *dev_priv = dev->dev_private;
661 struct nvc0_graph_priv *priv;
662 int ret, gpc, i;
663
a82dd49f
BS		 664 switch (dev_priv->chipset) {
665 case 0xc0:
666 case 0xc3:
667 case 0xc4:
668 break;
669 default:
670 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
671 return 0;
672 }
673
7a45cd19
BS		 674 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
675 if (!priv)
676 return -ENOMEM;
677
678 priv->base.destroy = nvc0_graph_destroy;
679 priv->base.init = nvc0_graph_init;
680 priv->base.fini = nvc0_graph_fini;
681 priv->base.context_new = nvc0_graph_context_new;
682 priv->base.context_del = nvc0_graph_context_del;
683 priv->base.object_new = nvc0_graph_object_new;
684
685 NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
686 nouveau_irq_register(dev, 12, nvc0_graph_isr);
687 nouveau_irq_register(dev, 25, nvc0_runk140_isr);
688
689 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
690 if (ret)
691 goto error;
692
693 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
694 if (ret)
695 goto error;
696
697 for (i = 0; i < 0x1000; i += 4) {
698 nv_wo32(priv->unk4188b4, i, 0x00000010);
699 nv_wo32(priv->unk4188b8, i, 0x00000010);
700 }
701
702 priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
703 priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
704 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
705 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
706 priv->tp_total += priv->tp_nr[gpc];
707 }
708
709 /*XXX: these need figuring out... */
710 switch (dev_priv->chipset) {
711 case 0xc0:
712 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
713 priv->magic_not_rop_nr = 0x07;
714 /* filled values up to tp_total, the rest 0 */
715 priv->magicgpc980[0] = 0x22111000;
716 priv->magicgpc980[1] = 0x00000233;
717 priv->magicgpc980[2] = 0x00000000;
718 priv->magicgpc980[3] = 0x00000000;
719 priv->magicgpc918 = 0x000ba2e9;
720 } else
721 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
722 priv->magic_not_rop_nr = 0x05;
723 priv->magicgpc980[0] = 0x11110000;
724 priv->magicgpc980[1] = 0x00233222;
725 priv->magicgpc980[2] = 0x00000000;
726 priv->magicgpc980[3] = 0x00000000;
727 priv->magicgpc918 = 0x00092493;
728 } else
729 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
730 priv->magic_not_rop_nr = 0x06;
731 priv->magicgpc980[0] = 0x11110000;
732 priv->magicgpc980[1] = 0x03332222;
733 priv->magicgpc980[2] = 0x00000000;
734 priv->magicgpc980[3] = 0x00000000;
735 priv->magicgpc918 = 0x00088889;
736 }
737 break;
738 case 0xc3: /* 450, 4/0/0/0, 2 */
739 priv->magic_not_rop_nr = 0x03;
740 priv->magicgpc980[0] = 0x00003210;
741 priv->magicgpc980[1] = 0x00000000;
742 priv->magicgpc980[2] = 0x00000000;
743 priv->magicgpc980[3] = 0x00000000;
744 priv->magicgpc918 = 0x00200000;
745 break;
746 case 0xc4: /* 460, 3/4/0/0, 4 */
747 priv->magic_not_rop_nr = 0x01;
748 priv->magicgpc980[0] = 0x02321100;
749 priv->magicgpc980[1] = 0x00000000;
750 priv->magicgpc980[2] = 0x00000000;
751 priv->magicgpc980[3] = 0x00000000;
752 priv->magicgpc918 = 0x00124925;
753 break;
754 }
755
756 if (!priv->magic_not_rop_nr) {
757 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
758 priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
759 priv->tp_nr[3], priv->rop_nr);
760 /* use 0xc3's values... */
761 priv->magic_not_rop_nr = 0x03;
762 priv->magicgpc980[0] = 0x00003210;
763 priv->magicgpc980[1] = 0x00000000;
764 priv->magicgpc980[2] = 0x00000000;
765 priv->magicgpc980[3] = 0x00000000;
766 priv->magicgpc918 = 0x00200000;
767 }
768
769 NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
770 NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
771 NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
772 NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
773 NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
774 return 0;
775
776error:
777 nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
778 return ret;
779}
kernel source for telekom puls (alcatel/mediatek)