Commit | Line | Data |
---|---|---|
fade7ad5 BS |
1 | /* |
2 | * Copyright 2010 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
760285e7 | 25 | #include <drm/drmP.h> |
77145f1c | 26 | #include "nouveau_drm.h" |
fade7ad5 BS |
27 | #include "nouveau_bios.h" |
28 | #include "nouveau_pm.h" | |
29 | ||
77145f1c BS |
30 | #include <subdev/bios/pll.h> |
31 | #include <subdev/bios.h> | |
32 | #include <subdev/clock.h> | |
33 | #include <subdev/timer.h> | |
34 | #include <subdev/fb.h> | |
35 | ||
ca94a71f | 36 | static u32 read_clk(struct drm_device *, int, bool); |
cec2a270 | 37 | static u32 read_pll(struct drm_device *, int, u32); |
3b0582d3 BS |
38 | |
39 | static u32 | |
ca94a71f BS |
40 | read_vco(struct drm_device *dev, int clk) |
41 | { | |
77145f1c BS |
42 | struct nouveau_device *device = nouveau_dev(dev); |
43 | u32 sctl = nv_rd32(device, 0x4120 + (clk * 4)); | |
ca94a71f | 44 | if ((sctl & 0x00000030) != 0x00000030) |
cec2a270 BS |
45 | return read_pll(dev, 0x41, 0x00e820); |
46 | return read_pll(dev, 0x42, 0x00e8a0); | |
ca94a71f BS |
47 | } |
48 | ||
49 | static u32 | |
50 | read_clk(struct drm_device *dev, int clk, bool ignore_en) | |
3b0582d3 | 51 | { |
77145f1c BS |
52 | struct nouveau_device *device = nouveau_dev(dev); |
53 | struct nouveau_drm *drm = nouveau_drm(dev); | |
3b0582d3 BS |
54 | u32 sctl, sdiv, sclk; |
55 | ||
64e740bb | 56 | /* refclk for the 0xe8xx plls is a fixed frequency */ |
378f85ed | 57 | if (clk >= 0x40) { |
77145f1c | 58 | if (nv_device(drm->device)->chipset == 0xaf) { |
378f85ed | 59 | /* no joke.. seriously.. sigh.. */ |
77145f1c | 60 | return nv_rd32(device, 0x00471c) * 1000; |
378f85ed BS |
61 | } |
62 | ||
77145f1c | 63 | return device->crystal; |
378f85ed | 64 | } |
3b0582d3 | 65 | |
77145f1c | 66 | sctl = nv_rd32(device, 0x4120 + (clk * 4)); |
ca94a71f BS |
67 | if (!ignore_en && !(sctl & 0x00000100)) |
68 | return 0; | |
69 | ||
70 | switch (sctl & 0x00003000) { | |
71 | case 0x00000000: | |
77145f1c | 72 | return device->crystal; |
ca94a71f | 73 | case 0x00002000: |
3b0582d3 BS |
74 | if (sctl & 0x00000040) |
75 | return 108000; | |
76 | return 100000; | |
ca94a71f BS |
77 | case 0x00003000: |
78 | sclk = read_vco(dev, clk); | |
3b0582d3 | 79 | sdiv = ((sctl & 0x003f0000) >> 16) + 2; |
3b0582d3 BS |
80 | return (sclk * 2) / sdiv; |
81 | default: | |
82 | return 0; | |
83 | } | |
84 | } | |
85 | ||
86 | static u32 | |
cec2a270 | 87 | read_pll(struct drm_device *dev, int clk, u32 pll) |
3b0582d3 | 88 | { |
77145f1c BS |
89 | struct nouveau_device *device = nouveau_dev(dev); |
90 | u32 ctrl = nv_rd32(device, pll + 0); | |
93e692dc | 91 | u32 sclk = 0, P = 1, N = 1, M = 1; |
3b0582d3 BS |
92 | |
93 | if (!(ctrl & 0x00000008)) { | |
93e692dc | 94 | if (ctrl & 0x00000001) { |
77145f1c | 95 | u32 coef = nv_rd32(device, pll + 4); |
93e692dc BS |
96 | M = (coef & 0x000000ff) >> 0; |
97 | N = (coef & 0x0000ff00) >> 8; | |
98 | P = (coef & 0x003f0000) >> 16; | |
cec2a270 | 99 | |
93e692dc BS |
100 | /* no post-divider on these.. */ |
101 | if ((pll & 0x00ff00) == 0x00e800) | |
102 | P = 1; | |
3b0582d3 | 103 | |
93e692dc BS |
104 | sclk = read_clk(dev, 0x00 + clk, false); |
105 | } | |
3b0582d3 | 106 | } else { |
ca94a71f | 107 | sclk = read_clk(dev, 0x10 + clk, false); |
3b0582d3 BS |
108 | } |
109 | ||
074e747a BS |
110 | if (M * P) |
111 | return sclk * N / (M * P); | |
112 | return 0; | |
3b0582d3 | 113 | } |
fade7ad5 | 114 | |
ca94a71f BS |
115 | struct creg { |
116 | u32 clk; | |
117 | u32 pll; | |
fade7ad5 BS |
118 | }; |
119 | ||
215f902e | 120 | static int |
cec2a270 | 121 | calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg) |
215f902e | 122 | { |
77145f1c BS |
123 | struct nouveau_drm *drm = nouveau_drm(dev); |
124 | struct nouveau_device *device = nouveau_dev(dev); | |
125 | struct nouveau_bios *bios = nouveau_bios(device); | |
70790f4f | 126 | struct nvbios_pll limits; |
ca94a71f BS |
127 | u32 oclk, sclk, sdiv; |
128 | int P, N, M, diff; | |
129 | int ret; | |
130 | ||
131 | reg->pll = 0; | |
132 | reg->clk = 0; | |
cec2a270 | 133 | if (!khz) { |
77145f1c | 134 | NV_DEBUG(drm, "no clock for 0x%04x/0x%02x\n", pll, clk); |
cec2a270 BS |
135 | return 0; |
136 | } | |
ca94a71f BS |
137 | |
138 | switch (khz) { | |
139 | case 27000: | |
140 | reg->clk = 0x00000100; | |
141 | return khz; | |
142 | case 100000: | |
143 | reg->clk = 0x00002100; | |
144 | return khz; | |
145 | case 108000: | |
146 | reg->clk = 0x00002140; | |
147 | return khz; | |
148 | default: | |
149 | sclk = read_vco(dev, clk); | |
150 | sdiv = min((sclk * 2) / (khz - 2999), (u32)65); | |
cec2a270 BS |
151 | /* if the clock has a PLL attached, and we can get a within |
152 | * [-2, 3) MHz of a divider, we'll disable the PLL and use | |
153 | * the divider instead. | |
154 | * | |
155 | * divider can go as low as 2, limited here because NVIDIA | |
156 | * and the VBIOS on my NVA8 seem to prefer using the PLL | |
157 | * for 810MHz - is there a good reason? | |
158 | */ | |
ca94a71f BS |
159 | if (sdiv > 4) { |
160 | oclk = (sclk * 2) / sdiv; | |
161 | diff = khz - oclk; | |
162 | if (!pll || (diff >= -2000 && diff < 3000)) { | |
163 | reg->clk = (((sdiv - 2) << 16) | 0x00003100); | |
164 | return oclk; | |
165 | } | |
166 | } | |
cec2a270 BS |
167 | |
168 | if (!pll) { | |
77145f1c | 169 | NV_ERROR(drm, "bad freq %02x: %d %d\n", clk, khz, sclk); |
cec2a270 BS |
170 | return -ERANGE; |
171 | } | |
172 | ||
ca94a71f | 173 | break; |
215f902e BS |
174 | } |
175 | ||
77145f1c | 176 | ret = nvbios_pll_parse(bios, pll, &limits); |
ca94a71f BS |
177 | if (ret) |
178 | return ret; | |
179 | ||
180 | limits.refclk = read_clk(dev, clk - 0x10, true); | |
181 | if (!limits.refclk) | |
182 | return -EINVAL; | |
183 | ||
184 | ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P); | |
185 | if (ret >= 0) { | |
77145f1c | 186 | reg->clk = nv_rd32(device, 0x4120 + (clk * 4)); |
ca94a71f BS |
187 | reg->pll = (P << 16) | (N << 8) | M; |
188 | } | |
77145f1c | 189 | |
ca94a71f | 190 | return ret; |
215f902e BS |
191 | } |
192 | ||
cec2a270 BS |
193 | static void |
194 | prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg) | |
195 | { | |
77145f1c BS |
196 | struct nouveau_device *device = nouveau_dev(dev); |
197 | struct nouveau_drm *drm = nouveau_drm(dev); | |
cec2a270 BS |
198 | const u32 src0 = 0x004120 + (clk * 4); |
199 | const u32 src1 = 0x004160 + (clk * 4); | |
200 | const u32 ctrl = pll + 0; | |
201 | const u32 coef = pll + 4; | |
cec2a270 BS |
202 | |
203 | if (!reg->clk && !reg->pll) { | |
77145f1c | 204 | NV_DEBUG(drm, "no clock for %02x\n", clk); |
cec2a270 BS |
205 | return; |
206 | } | |
207 | ||
cec2a270 | 208 | if (reg->pll) { |
77145f1c BS |
209 | nv_mask(device, src0, 0x00000101, 0x00000101); |
210 | nv_wr32(device, coef, reg->pll); | |
211 | nv_mask(device, ctrl, 0x00000015, 0x00000015); | |
212 | nv_mask(device, ctrl, 0x00000010, 0x00000000); | |
213 | nv_wait(device, ctrl, 0x00020000, 0x00020000); | |
214 | nv_mask(device, ctrl, 0x00000010, 0x00000010); | |
215 | nv_mask(device, ctrl, 0x00000008, 0x00000000); | |
216 | nv_mask(device, src1, 0x00000100, 0x00000000); | |
217 | nv_mask(device, src1, 0x00000001, 0x00000000); | |
cec2a270 | 218 | } else { |
77145f1c BS |
219 | nv_mask(device, src1, 0x003f3141, 0x00000101 | reg->clk); |
220 | nv_mask(device, ctrl, 0x00000018, 0x00000018); | |
074e747a | 221 | udelay(20); |
77145f1c BS |
222 | nv_mask(device, ctrl, 0x00000001, 0x00000000); |
223 | nv_mask(device, src0, 0x00000100, 0x00000000); | |
224 | nv_mask(device, src0, 0x00000001, 0x00000000); | |
cec2a270 BS |
225 | } |
226 | } | |
227 | ||
228 | static void | |
229 | prog_clk(struct drm_device *dev, int clk, struct creg *reg) | |
230 | { | |
77145f1c BS |
231 | struct nouveau_device *device = nouveau_dev(dev); |
232 | struct nouveau_drm *drm = nouveau_drm(dev); | |
233 | ||
cec2a270 | 234 | if (!reg->clk) { |
77145f1c | 235 | NV_DEBUG(drm, "no clock for %02x\n", clk); |
cec2a270 BS |
236 | return; |
237 | } | |
238 | ||
77145f1c | 239 | nv_mask(device, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk); |
cec2a270 BS |
240 | } |
241 | ||
fade7ad5 | 242 | int |
ca94a71f | 243 | nva3_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) |
fade7ad5 | 244 | { |
cec2a270 BS |
245 | perflvl->core = read_pll(dev, 0x00, 0x4200); |
246 | perflvl->shader = read_pll(dev, 0x01, 0x4220); | |
247 | perflvl->memory = read_pll(dev, 0x02, 0x4000); | |
4fd2847e BS |
248 | perflvl->unka0 = read_clk(dev, 0x20, false); |
249 | perflvl->vdec = read_clk(dev, 0x21, false); | |
9698b9a6 BS |
250 | perflvl->daemon = read_clk(dev, 0x25, false); |
251 | perflvl->copy = perflvl->core; | |
ca94a71f | 252 | return 0; |
fade7ad5 BS |
253 | } |
254 | ||
ca94a71f | 255 | struct nva3_pm_state { |
65115bb0 | 256 | struct nouveau_pm_level *perflvl; |
001a3990 | 257 | |
ca94a71f BS |
258 | struct creg nclk; |
259 | struct creg sclk; | |
4fd2847e BS |
260 | struct creg vdec; |
261 | struct creg unka0; | |
001a3990 BS |
262 | |
263 | struct creg mclk; | |
264 | u8 *rammap; | |
265 | u8 rammap_ver; | |
266 | u8 rammap_len; | |
267 | u8 *ramcfg; | |
268 | u8 ramcfg_len; | |
19a1e477 BS |
269 | u32 r004018; |
270 | u32 r100760; | |
ca94a71f BS |
271 | }; |
272 | ||
fade7ad5 | 273 | void * |
ca94a71f | 274 | nva3_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) |
fade7ad5 | 275 | { |
ca94a71f | 276 | struct nva3_pm_state *info; |
001a3990 | 277 | u8 ramcfg_cnt; |
ca94a71f | 278 | int ret; |
fade7ad5 | 279 | |
ca94a71f BS |
280 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
281 | if (!info) | |
282 | return ERR_PTR(-ENOMEM); | |
283 | ||
cec2a270 | 284 | ret = calc_clk(dev, 0x10, 0x4200, perflvl->core, &info->nclk); |
dac55b58 | 285 | if (ret < 0) |
ca94a71f | 286 | goto out; |
dac55b58 | 287 | |
cec2a270 | 288 | ret = calc_clk(dev, 0x11, 0x4220, perflvl->shader, &info->sclk); |
ca94a71f BS |
289 | if (ret < 0) |
290 | goto out; | |
dac55b58 | 291 | |
cec2a270 | 292 | ret = calc_clk(dev, 0x12, 0x4000, perflvl->memory, &info->mclk); |
ca94a71f BS |
293 | if (ret < 0) |
294 | goto out; | |
dac55b58 | 295 | |
cec2a270 | 296 | ret = calc_clk(dev, 0x20, 0x0000, perflvl->unka0, &info->unka0); |
4fd2847e BS |
297 | if (ret < 0) |
298 | goto out; | |
299 | ||
cec2a270 | 300 | ret = calc_clk(dev, 0x21, 0x0000, perflvl->vdec, &info->vdec); |
4fd2847e BS |
301 | if (ret < 0) |
302 | goto out; | |
303 | ||
001a3990 BS |
304 | info->rammap = nouveau_perf_rammap(dev, perflvl->memory, |
305 | &info->rammap_ver, | |
306 | &info->rammap_len, | |
307 | &ramcfg_cnt, &info->ramcfg_len); | |
308 | if (info->rammap_ver != 0x10 || info->rammap_len < 5) | |
309 | info->rammap = NULL; | |
310 | ||
311 | info->ramcfg = nouveau_perf_ramcfg(dev, perflvl->memory, | |
312 | &info->rammap_ver, | |
313 | &info->ramcfg_len); | |
314 | if (info->rammap_ver != 0x10) | |
315 | info->ramcfg = NULL; | |
316 | ||
65115bb0 | 317 | info->perflvl = perflvl; |
ca94a71f BS |
318 | out: |
319 | if (ret < 0) { | |
320 | kfree(info); | |
321 | info = ERR_PTR(ret); | |
fade7ad5 | 322 | } |
ca94a71f BS |
323 | return info; |
324 | } | |
fade7ad5 | 325 | |
d0f67a48 BS |
326 | static bool |
327 | nva3_pm_grcp_idle(void *data) | |
328 | { | |
329 | struct drm_device *dev = data; | |
77145f1c | 330 | struct nouveau_device *device = nouveau_dev(dev); |
d0f67a48 | 331 | |
77145f1c | 332 | if (!(nv_rd32(device, 0x400304) & 0x00000001)) |
d0f67a48 | 333 | return true; |
77145f1c | 334 | if (nv_rd32(device, 0x400308) == 0x0050001c) |
d0f67a48 BS |
335 | return true; |
336 | return false; | |
337 | } | |
338 | ||
65115bb0 BS |
339 | static void |
340 | mclk_precharge(struct nouveau_mem_exec_func *exec) | |
341 | { | |
77145f1c BS |
342 | struct nouveau_device *device = nouveau_dev(exec->dev); |
343 | nv_wr32(device, 0x1002d4, 0x00000001); | |
65115bb0 BS |
344 | } |
345 | ||
346 | static void | |
347 | mclk_refresh(struct nouveau_mem_exec_func *exec) | |
348 | { | |
77145f1c BS |
349 | struct nouveau_device *device = nouveau_dev(exec->dev); |
350 | nv_wr32(device, 0x1002d0, 0x00000001); | |
65115bb0 BS |
351 | } |
352 | ||
353 | static void | |
354 | mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable) | |
355 | { | |
77145f1c BS |
356 | struct nouveau_device *device = nouveau_dev(exec->dev); |
357 | nv_wr32(device, 0x100210, enable ? 0x80000000 : 0x00000000); | |
65115bb0 BS |
358 | } |
359 | ||
360 | static void | |
361 | mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable) | |
362 | { | |
77145f1c BS |
363 | struct nouveau_device *device = nouveau_dev(exec->dev); |
364 | nv_wr32(device, 0x1002dc, enable ? 0x00000001 : 0x00000000); | |
65115bb0 BS |
365 | } |
366 | ||
367 | static void | |
368 | mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec) | |
369 | { | |
77145f1c BS |
370 | struct nouveau_device *device = nouveau_dev(exec->dev); |
371 | volatile u32 post = nv_rd32(device, 0); (void)post; | |
65115bb0 BS |
372 | udelay((nsec + 500) / 1000); |
373 | } | |
374 | ||
375 | static u32 | |
376 | mclk_mrg(struct nouveau_mem_exec_func *exec, int mr) | |
377 | { | |
77145f1c | 378 | struct nouveau_device *device = nouveau_dev(exec->dev); |
65115bb0 | 379 | if (mr <= 1) |
77145f1c | 380 | return nv_rd32(device, 0x1002c0 + ((mr - 0) * 4)); |
65115bb0 | 381 | if (mr <= 3) |
77145f1c | 382 | return nv_rd32(device, 0x1002e0 + ((mr - 2) * 4)); |
65115bb0 BS |
383 | return 0; |
384 | } | |
385 | ||
386 | static void | |
387 | mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data) | |
388 | { | |
77145f1c BS |
389 | struct nouveau_device *device = nouveau_dev(exec->dev); |
390 | struct nouveau_fb *pfb = nouveau_fb(device); | |
65115bb0 | 391 | if (mr <= 1) { |
77145f1c BS |
392 | if (pfb->ram.ranks > 1) |
393 | nv_wr32(device, 0x1002c8 + ((mr - 0) * 4), data); | |
394 | nv_wr32(device, 0x1002c0 + ((mr - 0) * 4), data); | |
65115bb0 BS |
395 | } else |
396 | if (mr <= 3) { | |
77145f1c BS |
397 | if (pfb->ram.ranks > 1) |
398 | nv_wr32(device, 0x1002e8 + ((mr - 2) * 4), data); | |
399 | nv_wr32(device, 0x1002e0 + ((mr - 2) * 4), data); | |
65115bb0 BS |
400 | } |
401 | } | |
402 | ||
403 | static void | |
404 | mclk_clock_set(struct nouveau_mem_exec_func *exec) | |
405 | { | |
77145f1c | 406 | struct nouveau_device *device = nouveau_dev(exec->dev); |
27740383 | 407 | struct nva3_pm_state *info = exec->priv; |
5f54d29e | 408 | u32 ctrl; |
65115bb0 | 409 | |
77145f1c | 410 | ctrl = nv_rd32(device, 0x004000); |
5f54d29e | 411 | if (!(ctrl & 0x00000008) && info->mclk.pll) { |
77145f1c BS |
412 | nv_wr32(device, 0x004000, (ctrl |= 0x00000008)); |
413 | nv_mask(device, 0x1110e0, 0x00088000, 0x00088000); | |
414 | nv_wr32(device, 0x004018, 0x00001000); | |
415 | nv_wr32(device, 0x004000, (ctrl &= ~0x00000001)); | |
416 | nv_wr32(device, 0x004004, info->mclk.pll); | |
417 | nv_wr32(device, 0x004000, (ctrl |= 0x00000001)); | |
5f54d29e | 418 | udelay(64); |
77145f1c | 419 | nv_wr32(device, 0x004018, 0x00005000 | info->r004018); |
5f54d29e BS |
420 | udelay(20); |
421 | } else | |
4719b55b | 422 | if (!info->mclk.pll) { |
77145f1c BS |
423 | nv_mask(device, 0x004168, 0x003f3040, info->mclk.clk); |
424 | nv_wr32(device, 0x004000, (ctrl |= 0x00000008)); | |
425 | nv_mask(device, 0x1110e0, 0x00088000, 0x00088000); | |
426 | nv_wr32(device, 0x004018, 0x0000d000 | info->r004018); | |
4719b55b | 427 | } |
27740383 | 428 | |
001a3990 BS |
429 | if (info->rammap) { |
430 | if (info->ramcfg && (info->rammap[4] & 0x08)) { | |
431 | u32 unk5a0 = (ROM16(info->ramcfg[5]) << 8) | | |
432 | info->ramcfg[5]; | |
433 | u32 unk5a4 = ROM16(info->ramcfg[7]); | |
434 | u32 unk804 = (info->ramcfg[9] & 0xf0) << 16 | | |
435 | (info->ramcfg[3] & 0x0f) << 16 | | |
436 | (info->ramcfg[9] & 0x0f) | | |
27740383 | 437 | 0x80000000; |
77145f1c BS |
438 | nv_wr32(device, 0x1005a0, unk5a0); |
439 | nv_wr32(device, 0x1005a4, unk5a4); | |
440 | nv_wr32(device, 0x10f804, unk804); | |
441 | nv_mask(device, 0x10053c, 0x00001000, 0x00000000); | |
27740383 | 442 | } else { |
77145f1c BS |
443 | nv_mask(device, 0x10053c, 0x00001000, 0x00001000); |
444 | nv_mask(device, 0x10f804, 0x80000000, 0x00000000); | |
445 | nv_mask(device, 0x100760, 0x22222222, info->r100760); | |
446 | nv_mask(device, 0x1007a0, 0x22222222, info->r100760); | |
447 | nv_mask(device, 0x1007e0, 0x22222222, info->r100760); | |
27740383 BS |
448 | } |
449 | } | |
4719b55b BS |
450 | |
451 | if (info->mclk.pll) { | |
77145f1c BS |
452 | nv_mask(device, 0x1110e0, 0x00088000, 0x00011000); |
453 | nv_wr32(device, 0x004000, (ctrl &= ~0x00000008)); | |
4719b55b | 454 | } |
65115bb0 BS |
455 | } |
456 | ||
457 | static void | |
458 | mclk_timing_set(struct nouveau_mem_exec_func *exec) | |
459 | { | |
77145f1c | 460 | struct nouveau_device *device = nouveau_dev(exec->dev); |
65115bb0 BS |
461 | struct nva3_pm_state *info = exec->priv; |
462 | struct nouveau_pm_level *perflvl = info->perflvl; | |
463 | int i; | |
464 | ||
465 | for (i = 0; i < 9; i++) | |
77145f1c | 466 | nv_wr32(device, 0x100220 + (i * 4), perflvl->timing.reg[i]); |
30e53390 | 467 | |
001a3990 BS |
468 | if (info->ramcfg) { |
469 | u32 data = (info->ramcfg[2] & 0x08) ? 0x00000000 : 0x00001000; | |
77145f1c | 470 | nv_mask(device, 0x100200, 0x00001000, data); |
001a3990 BS |
471 | } |
472 | ||
473 | if (info->ramcfg) { | |
77145f1c BS |
474 | u32 unk714 = nv_rd32(device, 0x100714) & ~0xf0000010; |
475 | u32 unk718 = nv_rd32(device, 0x100718) & ~0x00000100; | |
476 | u32 unk71c = nv_rd32(device, 0x10071c) & ~0x00000100; | |
001a3990 | 477 | if ( (info->ramcfg[2] & 0x20)) |
30e53390 | 478 | unk714 |= 0xf0000000; |
001a3990 | 479 | if (!(info->ramcfg[2] & 0x04)) |
30e53390 | 480 | unk714 |= 0x00000010; |
77145f1c | 481 | nv_wr32(device, 0x100714, unk714); |
30e53390 | 482 | |
001a3990 | 483 | if (info->ramcfg[2] & 0x01) |
30e53390 | 484 | unk71c |= 0x00000100; |
77145f1c | 485 | nv_wr32(device, 0x10071c, unk71c); |
30e53390 | 486 | |
001a3990 | 487 | if (info->ramcfg[2] & 0x02) |
30e53390 | 488 | unk718 |= 0x00000100; |
77145f1c | 489 | nv_wr32(device, 0x100718, unk718); |
2b20fd0a BS |
490 | |
491 | if (info->ramcfg[2] & 0x10) | |
77145f1c | 492 | nv_wr32(device, 0x111100, 0x48000000); /*XXX*/ |
30e53390 | 493 | } |
65115bb0 BS |
494 | } |
495 | ||
496 | static void | |
497 | prog_mem(struct drm_device *dev, struct nva3_pm_state *info) | |
498 | { | |
77145f1c | 499 | struct nouveau_device *device = nouveau_dev(dev); |
65115bb0 BS |
500 | struct nouveau_mem_exec_func exec = { |
501 | .dev = dev, | |
502 | .precharge = mclk_precharge, | |
503 | .refresh = mclk_refresh, | |
504 | .refresh_auto = mclk_refresh_auto, | |
505 | .refresh_self = mclk_refresh_self, | |
506 | .wait = mclk_wait, | |
507 | .mrg = mclk_mrg, | |
508 | .mrs = mclk_mrs, | |
509 | .clock_set = mclk_clock_set, | |
510 | .timing_set = mclk_timing_set, | |
511 | .priv = info | |
512 | }; | |
4719b55b BS |
513 | u32 ctrl; |
514 | ||
19a1e477 BS |
515 | /* XXX: where the fuck does 750MHz come from? */ |
516 | if (info->perflvl->memory <= 750000) { | |
517 | info->r004018 = 0x10000000; | |
518 | info->r100760 = 0x22222222; | |
519 | } | |
520 | ||
77145f1c | 521 | ctrl = nv_rd32(device, 0x004000); |
4719b55b BS |
522 | if (ctrl & 0x00000008) { |
523 | if (info->mclk.pll) { | |
77145f1c BS |
524 | nv_mask(device, 0x004128, 0x00000101, 0x00000101); |
525 | nv_wr32(device, 0x004004, info->mclk.pll); | |
526 | nv_wr32(device, 0x004000, (ctrl |= 0x00000001)); | |
527 | nv_wr32(device, 0x004000, (ctrl &= 0xffffffef)); | |
528 | nv_wait(device, 0x004000, 0x00020000, 0x00020000); | |
529 | nv_wr32(device, 0x004000, (ctrl |= 0x00000010)); | |
530 | nv_wr32(device, 0x004018, 0x00005000 | info->r004018); | |
531 | nv_wr32(device, 0x004000, (ctrl |= 0x00000004)); | |
4719b55b BS |
532 | } |
533 | } else { | |
5f54d29e BS |
534 | u32 ssel = 0x00000101; |
535 | if (info->mclk.clk) | |
536 | ssel |= info->mclk.clk; | |
537 | else | |
538 | ssel |= 0x00080000; /* 324MHz, shouldn't matter... */ | |
77145f1c | 539 | nv_mask(device, 0x004168, 0x003f3141, ctrl); |
4719b55b | 540 | } |
65115bb0 | 541 | |
2b20fd0a BS |
542 | if (info->ramcfg) { |
543 | if (info->ramcfg[2] & 0x10) { | |
77145f1c | 544 | nv_mask(device, 0x111104, 0x00000600, 0x00000000); |
2b20fd0a | 545 | } else { |
77145f1c BS |
546 | nv_mask(device, 0x111100, 0x40000000, 0x40000000); |
547 | nv_mask(device, 0x111104, 0x00000180, 0x00000000); | |
2b20fd0a BS |
548 | } |
549 | } | |
001a3990 | 550 | if (info->rammap && !(info->rammap[4] & 0x02)) |
77145f1c BS |
551 | nv_mask(device, 0x100200, 0x00000800, 0x00000000); |
552 | nv_wr32(device, 0x611200, 0x00003300); | |
2b20fd0a | 553 | if (!(info->ramcfg[2] & 0x10)) |
77145f1c | 554 | nv_wr32(device, 0x111100, 0x4c020000); /*XXX*/ |
001a3990 | 555 | |
65115bb0 | 556 | nouveau_mem_exec(&exec, info->perflvl); |
001a3990 | 557 | |
77145f1c | 558 | nv_wr32(device, 0x611200, 0x00003330); |
001a3990 | 559 | if (info->rammap && (info->rammap[4] & 0x02)) |
77145f1c | 560 | nv_mask(device, 0x100200, 0x00000800, 0x00000800); |
2b20fd0a BS |
561 | if (info->ramcfg) { |
562 | if (info->ramcfg[2] & 0x10) { | |
77145f1c BS |
563 | nv_mask(device, 0x111104, 0x00000180, 0x00000180); |
564 | nv_mask(device, 0x111100, 0x40000000, 0x00000000); | |
2b20fd0a | 565 | } else { |
77145f1c | 566 | nv_mask(device, 0x111104, 0x00000600, 0x00000600); |
2b20fd0a BS |
567 | } |
568 | } | |
4719b55b BS |
569 | |
570 | if (info->mclk.pll) { | |
77145f1c BS |
571 | nv_mask(device, 0x004168, 0x00000001, 0x00000000); |
572 | nv_mask(device, 0x004168, 0x00000100, 0x00000000); | |
4719b55b | 573 | } else { |
77145f1c BS |
574 | nv_mask(device, 0x004000, 0x00000001, 0x00000000); |
575 | nv_mask(device, 0x004128, 0x00000001, 0x00000000); | |
576 | nv_mask(device, 0x004128, 0x00000100, 0x00000000); | |
4719b55b | 577 | } |
65115bb0 BS |
578 | } |
579 | ||
dd1da8de | 580 | int |
ca94a71f | 581 | nva3_pm_clocks_set(struct drm_device *dev, void *pre_state) |
fade7ad5 | 582 | { |
77145f1c BS |
583 | struct nouveau_device *device = nouveau_dev(dev); |
584 | struct nouveau_drm *drm = nouveau_drm(dev); | |
ca94a71f | 585 | struct nva3_pm_state *info = pre_state; |
dd1da8de | 586 | int ret = -EAGAIN; |
d0f67a48 BS |
587 | |
588 | /* prevent any new grctx switches from starting */ | |
77145f1c BS |
589 | nv_wr32(device, 0x400324, 0x00000000); |
590 | nv_wr32(device, 0x400328, 0x0050001c); /* wait flag 0x1c */ | |
d0f67a48 | 591 | /* wait for any pending grctx switches to complete */ |
77145f1c BS |
592 | if (!nv_wait_cb(device, nva3_pm_grcp_idle, dev)) { |
593 | NV_ERROR(drm, "pm: ctxprog didn't go idle\n"); | |
d0f67a48 BS |
594 | goto cleanup; |
595 | } | |
596 | /* freeze PFIFO */ | |
77145f1c BS |
597 | nv_mask(device, 0x002504, 0x00000001, 0x00000001); |
598 | if (!nv_wait(device, 0x002504, 0x00000010, 0x00000010)) { | |
599 | NV_ERROR(drm, "pm: fifo didn't go idle\n"); | |
d0f67a48 BS |
600 | goto cleanup; |
601 | } | |
ca94a71f | 602 | |
cec2a270 BS |
603 | prog_pll(dev, 0x00, 0x004200, &info->nclk); |
604 | prog_pll(dev, 0x01, 0x004220, &info->sclk); | |
4fd2847e BS |
605 | prog_clk(dev, 0x20, &info->unka0); |
606 | prog_clk(dev, 0x21, &info->vdec); | |
ca94a71f | 607 | |
65115bb0 BS |
608 | if (info->mclk.clk || info->mclk.pll) |
609 | prog_mem(dev, info); | |
ca94a71f | 610 | |
dd1da8de MP |
611 | ret = 0; |
612 | ||
d0f67a48 BS |
613 | cleanup: |
614 | /* unfreeze PFIFO */ | |
77145f1c | 615 | nv_mask(device, 0x002504, 0x00000001, 0x00000000); |
d0f67a48 | 616 | /* restore ctxprog to normal */ |
77145f1c BS |
617 | nv_wr32(device, 0x400324, 0x00000000); |
618 | nv_wr32(device, 0x400328, 0x0070009c); /* set flag 0x1c */ | |
d0f67a48 | 619 | /* unblock it if necessary */ |
77145f1c BS |
620 | if (nv_rd32(device, 0x400308) == 0x0050001c) |
621 | nv_mask(device, 0x400824, 0x10000000, 0x10000000); | |
ca94a71f | 622 | kfree(info); |
dd1da8de | 623 | return ret; |
fade7ad5 | 624 | } |