[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nv84_fifo.c

/*
 * Copyright (C) 2012 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <drm/drmP.h>
#include "nouveau_drv.h"
#include "nouveau_fifo.h"
#include "nouveau_ramht.h"
#include "nouveau_vm.h"

struct nv84_fifo_priv {
	struct nouveau_fifo_priv base;
	struct nouveau_gpuobj *playlist[2];
	int cur_playlist;
};

struct nv84_fifo_chan {
	struct nouveau_fifo_chan base;
	struct nouveau_gpuobj *ramfc;
	struct nouveau_gpuobj *cache;
};

static int
nv84_fifo_context_new(struct nouveau_channel *chan, int engine)
{
	struct nv84_fifo_priv *priv = nv_engine(chan->dev, engine);
	struct nv84_fifo_chan *fctx;
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
        u64 ib_offset = chan->pushbuf_base + chan->dma.ib_base * 4;
	u64 instance;
	unsigned long flags;
	int ret;

	fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
	if (!fctx)
		return -ENOMEM;
	atomic_inc(&chan->vm->engref[engine]);

	chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
			     NV50_USER(chan->id), PAGE_SIZE);
	if (!chan->user) {
		ret = -ENOMEM;
		goto error;
	}

	ret = nouveau_gpuobj_new(dev, chan, 256, 256, NVOBJ_FLAG_ZERO_ALLOC |
				 NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
	if (ret)
		goto error;

	instance = fctx->ramfc->vinst >> 8;

	ret = nouveau_gpuobj_new(dev, chan, 4096, 1024, 0, &fctx->cache);
	if (ret)
		goto error;

	nv_wo32(fctx->ramfc, 0x3c, 0x403f6078);
	nv_wo32(fctx->ramfc, 0x40, 0x00000000);
	nv_wo32(fctx->ramfc, 0x44, 0x01003fff);
	nv_wo32(fctx->ramfc, 0x48, chan->pushbuf->cinst >> 4);
	nv_wo32(fctx->ramfc, 0x50, lower_32_bits(ib_offset));
	nv_wo32(fctx->ramfc, 0x54, upper_32_bits(ib_offset) |
				   drm_order(chan->dma.ib_max + 1) << 16);
	nv_wo32(fctx->ramfc, 0x60, 0x7fffffff);
	nv_wo32(fctx->ramfc, 0x78, 0x00000000);
	nv_wo32(fctx->ramfc, 0x7c, 0x30000001);
	nv_wo32(fctx->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
				   (4 << 24) /* SEARCH_FULL */ |
				   (chan->ramht->gpuobj->cinst >> 4));
	nv_wo32(fctx->ramfc, 0x88, fctx->cache->vinst >> 10);
	nv_wo32(fctx->ramfc, 0x98, chan->ramin->vinst >> 12);

	nv_wo32(chan->ramin, 0x00, chan->id);
	nv_wo32(chan->ramin, 0x04, fctx->ramfc->vinst >> 8);

	dev_priv->engine.instmem.flush(dev);

	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	nv_wr32(dev, 0x002600 + (chan->id * 4), 0x80000000 | instance);
	nv50_fifo_playlist_update(dev);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

error:
	if (ret)
		priv->base.base.context_del(chan, engine);
	return ret;
}

static void
nv84_fifo_context_del(struct nouveau_channel *chan, int engine)
{
	struct nv84_fifo_chan *fctx = chan->engctx[engine];
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	unsigned long flags;
	u32 save;

	/* remove channel from playlist, will context switch if active */
	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000);
	nv50_fifo_playlist_update(dev);

	save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);

	/* tell any engines on this channel to unload their contexts */
	nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
	if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff))
		NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);

	nv_wr32(dev, 0x002520, save);

	nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	/* clean up */
	if (chan->user) {
		iounmap(chan->user);
		chan->user = NULL;
	}

	nouveau_gpuobj_ref(NULL, &fctx->ramfc);
	nouveau_gpuobj_ref(NULL, &fctx->cache);

	atomic_dec(&chan->vm->engref[engine]);
	chan->engctx[engine] = NULL;
	kfree(fctx);
}

static int
nv84_fifo_init(struct drm_device *dev, int engine)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv84_fifo_chan *fctx;
	u32 instance;
	int i;

	nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
	nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
	nv_wr32(dev, 0x00250c, 0x6f3cfc34);
	nv_wr32(dev, 0x002044, 0x01003fff);

	nv_wr32(dev, 0x002100, 0xffffffff);
	nv_wr32(dev, 0x002140, 0xffffffff);

	for (i = 0; i < 128; i++) {
		struct nouveau_channel *chan = dev_priv->channels.ptr[i];
		if (chan && (fctx = chan->engctx[engine]))
			instance = 0x80000000 | fctx->ramfc->vinst >> 8;
		else
			instance = 0x00000000;
		nv_wr32(dev, 0x002600 + (i * 4), instance);
	}

	nv50_fifo_playlist_update(dev);

	nv_wr32(dev, 0x003200, 1);
	nv_wr32(dev, 0x003250, 1);
	nv_wr32(dev, 0x002500, 1);
	return 0;
}

static int
nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv84_fifo_priv *priv = nv_engine(dev, engine);
	int i;
	u32 save;

	/* set playlist length to zero, fifo will unload context */
	nv_wr32(dev, 0x0032ec, 0);

	save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);

	/* tell all connected engines to unload their contexts */
	for (i = 0; i < priv->base.channels; i++) {
		struct nouveau_channel *chan = dev_priv->channels.ptr[i];
		if (chan)
			nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
		if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff)) {
			NV_INFO(dev, "PFIFO: channel %d unload timeout\n", i);
			return -EBUSY;
		}
	}

	nv_wr32(dev, 0x002520, save);
	nv_wr32(dev, 0x002140, 0);
	return 0;
}

int
nv84_fifo_create(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv84_fifo_priv *priv;
	int ret;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base.base.destroy = nv50_fifo_destroy;
	priv->base.base.init = nv84_fifo_init;
	priv->base.base.fini = nv84_fifo_fini;
	priv->base.base.context_new = nv84_fifo_context_new;
	priv->base.base.context_del = nv84_fifo_context_del;
	priv->base.base.tlb_flush = nv50_fifo_tlb_flush;
	priv->base.channels = 127;
	dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;

	ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000,
				 NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[0]);
	if (ret)
		goto error;

	ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000,
				 NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[1]);
	if (ret)
		goto error;

	nouveau_irq_register(dev, 8, nv04_fifo_isr);
error:
	if (ret)
		priv->base.base.destroy(dev, NVOBJ_ENGINE_FIFO);
	return ret;
}
Commit	Line	Data
c420b2dc BS	1	/*
	2	* Copyright (C) 2012 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
760285e7	27	#include <drm/drmP.h>
c420b2dc BS	28	#include "nouveau_drv.h"
	29	#include "nouveau_fifo.h"
	30	#include "nouveau_ramht.h"
	31	#include "nouveau_vm.h"
	32
	33	struct nv84_fifo_priv {
	34	struct nouveau_fifo_priv base;
	35	struct nouveau_gpuobj *playlist[2];
	36	int cur_playlist;
	37	};
	38
	39	struct nv84_fifo_chan {
	40	struct nouveau_fifo_chan base;
	41	struct nouveau_gpuobj *ramfc;
	42	struct nouveau_gpuobj *cache;
	43	};
	44
	45	static int
	46	nv84_fifo_context_new(struct nouveau_channel *chan, int engine)
	47	{
	48	struct nv84_fifo_priv *priv = nv_engine(chan->dev, engine);
	49	struct nv84_fifo_chan *fctx;
	50	struct drm_device *dev = chan->dev;
	51	struct drm_nouveau_private *dev_priv = dev->dev_private;
	52	u64 ib_offset = chan->pushbuf_base + chan->dma.ib_base * 4;
	53	u64 instance;
	54	unsigned long flags;
	55	int ret;
	56
	57	fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
	58	if (!fctx)
	59	return -ENOMEM;
	60	atomic_inc(&chan->vm->engref[engine]);
	61
	62	chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
	63	NV50_USER(chan->id), PAGE_SIZE);
	64	if (!chan->user) {
	65	ret = -ENOMEM;
	66	goto error;
	67	}
	68
	69	ret = nouveau_gpuobj_new(dev, chan, 256, 256, NVOBJ_FLAG_ZERO_ALLOC \|
	70	NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc);
	71	if (ret)
	72	goto error;
	73
	74	instance = fctx->ramfc->vinst >> 8;
	75
	76	ret = nouveau_gpuobj_new(dev, chan, 4096, 1024, 0, &fctx->cache);
	77	if (ret)
	78	goto error;
	79
	80	nv_wo32(fctx->ramfc, 0x3c, 0x403f6078);
	81	nv_wo32(fctx->ramfc, 0x40, 0x00000000);
	82	nv_wo32(fctx->ramfc, 0x44, 0x01003fff);
	83	nv_wo32(fctx->ramfc, 0x48, chan->pushbuf->cinst >> 4);
	84	nv_wo32(fctx->ramfc, 0x50, lower_32_bits(ib_offset));
	85	nv_wo32(fctx->ramfc, 0x54, upper_32_bits(ib_offset) \|
	86	drm_order(chan->dma.ib_max + 1) << 16);
	87	nv_wo32(fctx->ramfc, 0x60, 0x7fffffff);
	88	nv_wo32(fctx->ramfc, 0x78, 0x00000000);
	89	nv_wo32(fctx->ramfc, 0x7c, 0x30000001);
	90	nv_wo32(fctx->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) \|
	91	(4 << 24) /* SEARCH_FULL */ \|
92	(chan->ramht->gpuobj->cinst >> 4));
93	nv_wo32(fctx->ramfc, 0x88, fctx->cache->vinst >> 10);
94	nv_wo32(fctx->ramfc, 0x98, chan->ramin->vinst >> 12);
95
96	nv_wo32(chan->ramin, 0x00, chan->id);
97	nv_wo32(chan->ramin, 0x04, fctx->ramfc->vinst >> 8);
98
99	dev_priv->engine.instmem.flush(dev);
100
101	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
102	nv_wr32(dev, 0x002600 + (chan->id * 4), 0x80000000 \| instance);
103	nv50_fifo_playlist_update(dev);
104	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
105
106	error:
107	if (ret)
108	priv->base.base.context_del(chan, engine);
109	return ret;
110	}
111
112	static void
113	nv84_fifo_context_del(struct nouveau_channel *chan, int engine)
114	{
115	struct nv84_fifo_chan *fctx = chan->engctx[engine];
116	struct drm_device *dev = chan->dev;
117	struct drm_nouveau_private *dev_priv = dev->dev_private;
118	unsigned long flags;
2064db72	119	u32 save;
c420b2dc BS	120
	121	/* remove channel from playlist, will context switch if active */
	122	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	123	nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000);
	124	nv50_fifo_playlist_update(dev);
	125
2064db72 ML	126	save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
2064db72 ML	127
c420b2dc BS	128	/* tell any engines on this channel to unload their contexts */
	129	nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
	130	if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff))
	131	NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);
	132
2064db72 ML	133	nv_wr32(dev, 0x002520, save);
2064db72 ML	134
c420b2dc BS	135	nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000);
	136	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	137
	138	/* clean up */
	139	if (chan->user) {
	140	iounmap(chan->user);
	141	chan->user = NULL;
	142	}
	143
	144	nouveau_gpuobj_ref(NULL, &fctx->ramfc);
	145	nouveau_gpuobj_ref(NULL, &fctx->cache);
	146
	147	atomic_dec(&chan->vm->engref[engine]);
	148	chan->engctx[engine] = NULL;
	149	kfree(fctx);
	150	}
	151
	152	static int
	153	nv84_fifo_init(struct drm_device *dev, int engine)
	154	{
	155	struct drm_nouveau_private *dev_priv = dev->dev_private;
	156	struct nv84_fifo_chan *fctx;
	157	u32 instance;
	158	int i;
	159
	160	nv_mask(dev, 0x000200, 0x00000100, 0x00000000);
	161	nv_mask(dev, 0x000200, 0x00000100, 0x00000100);
	162	nv_wr32(dev, 0x00250c, 0x6f3cfc34);
	163	nv_wr32(dev, 0x002044, 0x01003fff);
	164
	165	nv_wr32(dev, 0x002100, 0xffffffff);
	166	nv_wr32(dev, 0x002140, 0xffffffff);
	167
	168	for (i = 0; i < 128; i++) {
	169	struct nouveau_channel *chan = dev_priv->channels.ptr[i];
	170	if (chan && (fctx = chan->engctx[engine]))
	171	instance = 0x80000000 \| fctx->ramfc->vinst >> 8;
	172	else
	173	instance = 0x00000000;
	174	nv_wr32(dev, 0x002600 + (i * 4), instance);
	175	}
	176
	177	nv50_fifo_playlist_update(dev);
	178
	179	nv_wr32(dev, 0x003200, 1);
	180	nv_wr32(dev, 0x003250, 1);
	181	nv_wr32(dev, 0x002500, 1);
	182	return 0;
	183	}
	184
	185	static int
	186	nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend)
	187	{
	188	struct drm_nouveau_private *dev_priv = dev->dev_private;
	189	struct nv84_fifo_priv *priv = nv_engine(dev, engine);
	190	int i;
2064db72	191	u32 save;
c420b2dc BS	192
	193	/* set playlist length to zero, fifo will unload context */
	194	nv_wr32(dev, 0x0032ec, 0);
	195
2064db72 ML	196	save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
2064db72 ML	197
c420b2dc BS	198	/* tell all connected engines to unload their contexts */
	199	for (i = 0; i < priv->base.channels; i++) {
	200	struct nouveau_channel *chan = dev_priv->channels.ptr[i];
	201	if (chan)
	202	nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
	203	if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff)) {
	204	NV_INFO(dev, "PFIFO: channel %d unload timeout\n", i);
	205	return -EBUSY;
	206	}
	207	}
	208
2064db72	209	nv_wr32(dev, 0x002520, save);
c420b2dc BS	210	nv_wr32(dev, 0x002140, 0);
	211	return 0;
	212	}
	213
	214	int
	215	nv84_fifo_create(struct drm_device *dev)
	216	{
	217	struct drm_nouveau_private *dev_priv = dev->dev_private;
	218	struct nv84_fifo_priv *priv;
	219	int ret;
	220
	221	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	222	if (!priv)
	223	return -ENOMEM;
	224
	225	priv->base.base.destroy = nv50_fifo_destroy;
	226	priv->base.base.init = nv84_fifo_init;
	227	priv->base.base.fini = nv84_fifo_fini;
	228	priv->base.base.context_new = nv84_fifo_context_new;
	229	priv->base.base.context_del = nv84_fifo_context_del;
	230	priv->base.base.tlb_flush = nv50_fifo_tlb_flush;
	231	priv->base.channels = 127;
	232	dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base;
	233
	234	ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000,
	235	NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[0]);
	236	if (ret)
	237	goto error;
	238
	239	ret = nouveau_gpuobj_new(dev, NULL, priv->base.channels * 4, 0x1000,
	240	NVOBJ_FLAG_ZERO_ALLOC, &priv->playlist[1]);
	241	if (ret)
	242	goto error;
	243
	244	nouveau_irq_register(dev, 8, nv04_fifo_isr);
	245	error:
	246	if (ret)
	247	priv->base.base.destroy(dev, NVOBJ_ENGINE_FIFO);
	248	return ret;
	249	}