[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nv50_pm.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"
#include "nouveau_drv.h"
#include "nouveau_bios.h"
#include "nouveau_hw.h"
#include "nouveau_pm.h"

enum clk_src {
	clk_src_crystal,
	clk_src_href,
	clk_src_hclk,
	clk_src_hclkm3,
	clk_src_hclkm3d2,
	clk_src_host,
	clk_src_nvclk,
	clk_src_sclk,
	clk_src_mclk,
	clk_src_vdec,
	clk_src_dom6
};

static u32 read_clk(struct drm_device *, enum clk_src);

static u32
read_div(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	switch (dev_priv->chipset) {
	case 0x50: /* it exists, but only has bit 31, not the dividers.. */
	case 0x84:
	case 0x86:
	case 0x98:
	case 0xa0:
		return nv_rd32(dev, 0x004700);
	case 0x92:
	case 0x94:
	case 0x96:
		return nv_rd32(dev, 0x004800);
	default:
		return 0x00000000;
	}
}

static u32
read_pll_src(struct drm_device *dev, u32 base)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	u32 coef, ref = read_clk(dev, clk_src_crystal);
	u32 rsel = nv_rd32(dev, 0x00e18c);
	int P, N, M, id;

	switch (dev_priv->chipset) {
	case 0x50:
	case 0xa0:
		switch (base) {
		case 0x4020:
		case 0x4028: id = !!(rsel & 0x00000004); break;
		case 0x4008: id = !!(rsel & 0x00000008); break;
		case 0x4030: id = 0; break;
		default:
			NV_ERROR(dev, "ref: bad pll 0x%06x\n", base);
			return 0;
		}

		coef = nv_rd32(dev, 0x00e81c + (id * 0x0c));
		ref *=  (coef & 0x01000000) ? 2 : 4;
		P    =  (coef & 0x00070000) >> 16;
		N    = ((coef & 0x0000ff00) >> 8) + 1;
		M    = ((coef & 0x000000ff) >> 0) + 1;
		break;
	case 0x84:
	case 0x86:
	case 0x92:
		coef = nv_rd32(dev, 0x00e81c);
		P    = (coef & 0x00070000) >> 16;
		N    = (coef & 0x0000ff00) >> 8;
		M    = (coef & 0x000000ff) >> 0;
		break;
	case 0x94:
	case 0x96:
	case 0x98:
		rsel = nv_rd32(dev, 0x00c050);
		switch (base) {
		case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
		case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
		case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
		case 0x4030: rsel = 3; break;
		default:
			NV_ERROR(dev, "ref: bad pll 0x%06x\n", base);
			return 0;
		}

		switch (rsel) {
		case 0: id = 1; break;
		case 1: return read_clk(dev, clk_src_crystal);
		case 2: return read_clk(dev, clk_src_href);
		case 3: id = 0; break;
		}

		coef =  nv_rd32(dev, 0x00e81c + (id * 0x28));
		P    = (nv_rd32(dev, 0x00e824 + (id * 0x28)) >> 16) & 7;
		P   += (coef & 0x00070000) >> 16;
		N    = (coef & 0x0000ff00) >> 8;
		M    = (coef & 0x000000ff) >> 0;
		break;
	default:
		BUG_ON(1);
	}

	if (M)
		return (ref * N / M) >> P;
	return 0;
}

static u32
read_pll_ref(struct drm_device *dev, u32 base)
{
	u32 src, mast = nv_rd32(dev, 0x00c040);

	switch (base) {
	case 0x004028:
		src = !!(mast & 0x00200000);
		break;
	case 0x004020:
		src = !!(mast & 0x00400000);
		break;
	case 0x004008:
		src = !!(mast & 0x00010000);
		break;
	case 0x004030:
		src = !!(mast & 0x02000000);
		break;
	case 0x00e810:
		return read_clk(dev, clk_src_crystal);
	default:
		NV_ERROR(dev, "bad pll 0x%06x\n", base);
		return 0;
	}

	if (src)
		return read_clk(dev, clk_src_href);
	return read_pll_src(dev, base);
}

static u32
read_pll(struct drm_device *dev, u32 base)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	u32 mast = nv_rd32(dev, 0x00c040);
	u32 ctrl = nv_rd32(dev, base + 0);
	u32 coef = nv_rd32(dev, base + 4);
	u32 ref = read_pll_ref(dev, base);
	u32 clk = 0;
	int N1, N2, M1, M2;

	if (base == 0x004028 && (mast & 0x00100000)) {
		/* wtf, appears to only disable post-divider on nva0 */
		if (dev_priv->chipset != 0xa0)
			return read_clk(dev, clk_src_dom6);
	}

	N2 = (coef & 0xff000000) >> 24;
	M2 = (coef & 0x00ff0000) >> 16;
	N1 = (coef & 0x0000ff00) >> 8;
	M1 = (coef & 0x000000ff);
	if ((ctrl & 0x80000000) && M1) {
		clk = ref * N1 / M1;
		if ((ctrl & 0x40000100) == 0x40000000) {
			if (M2)
				clk = clk * N2 / M2;
			else
				clk = 0;
		}
	}

	return clk;
}

static u32
read_clk(struct drm_device *dev, enum clk_src src)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	u32 mast = nv_rd32(dev, 0x00c040);
	u32 P = 0;

	switch (src) {
	case clk_src_crystal:
		return dev_priv->crystal;
	case clk_src_href:
		return 100000; /* PCIE reference clock */
	case clk_src_hclk:
		return read_clk(dev, clk_src_href) * 27778 / 10000;
	case clk_src_hclkm3:
		return read_clk(dev, clk_src_hclk) * 3;
	case clk_src_hclkm3d2:
		return read_clk(dev, clk_src_hclk) * 3 / 2;
	case clk_src_host:
		switch (mast & 0x30000000) {
		case 0x00000000: return read_clk(dev, clk_src_href);
		case 0x10000000: break;
		case 0x20000000: /* !0x50 */
		case 0x30000000: return read_clk(dev, clk_src_hclk);
		}
		break;
	case clk_src_nvclk:
		if (!(mast & 0x00100000))
			P = (nv_rd32(dev, 0x004028) & 0x00070000) >> 16;
		switch (mast & 0x00000003) {
		case 0x00000000: return read_clk(dev, clk_src_crystal) >> P;
		case 0x00000001: return read_clk(dev, clk_src_dom6);
		case 0x00000002: return read_pll(dev, 0x004020) >> P;
		case 0x00000003: return read_pll(dev, 0x004028) >> P;
		}
		break;
	case clk_src_sclk:
		P = (nv_rd32(dev, 0x004020) & 0x00070000) >> 16;
		switch (mast & 0x00000030) {
		case 0x00000000:
			if (mast & 0x00000080)
				return read_clk(dev, clk_src_host) >> P;
			return read_clk(dev, clk_src_crystal) >> P;
		case 0x00000010: break;
		case 0x00000020: return read_pll(dev, 0x004028) >> P;
		case 0x00000030: return read_pll(dev, 0x004020) >> P;
		}
		break;
	case clk_src_mclk:
		P = (nv_rd32(dev, 0x004008) & 0x00070000) >> 16;
		if (nv_rd32(dev, 0x004008) & 0x00000200) {
			switch (mast & 0x0000c000) {
			case 0x00000000:
				return read_clk(dev, clk_src_crystal) >> P;
			case 0x00008000:
			case 0x0000c000:
				return read_clk(dev, clk_src_href) >> P;
			}
		} else {
			return read_pll(dev, 0x004008) >> P;
		}
		break;
	case clk_src_vdec:
		P = (read_div(dev) & 0x00000700) >> 8;
		switch (dev_priv->chipset) {
		case 0x84:
		case 0x86:
		case 0x92:
		case 0x94:
		case 0x96:
		case 0xa0:
			switch (mast & 0x00000c00) {
			case 0x00000000:
				if (dev_priv->chipset == 0xa0) /* wtf?? */
					return read_clk(dev, clk_src_nvclk) >> P;
				return read_clk(dev, clk_src_crystal) >> P;
			case 0x00000400:
				return 0;
			case 0x00000800:
				if (mast & 0x01000000)
					return read_pll(dev, 0x004028) >> P;
				return read_pll(dev, 0x004030) >> P;
			case 0x00000c00:
				return read_clk(dev, clk_src_nvclk) >> P;
			}
			break;
		case 0x98:
			switch (mast & 0x00000c00) {
			case 0x00000000:
				return read_clk(dev, clk_src_nvclk) >> P;
			case 0x00000400:
				return 0;
			case 0x00000800:
				return read_clk(dev, clk_src_hclkm3d2) >> P;
			case 0x00000c00:
				return read_clk(dev, clk_src_mclk) >> P;
			}
			break;
		}
		break;
	case clk_src_dom6:
		switch (dev_priv->chipset) {
		case 0x50:
		case 0xa0:
			return read_pll(dev, 0x00e810) >> 2;
		case 0x84:
		case 0x86:
		case 0x92:
		case 0x94:
		case 0x96:
		case 0x98:
			P = (read_div(dev) & 0x00000007) >> 0;
			switch (mast & 0x0c000000) {
			case 0x00000000: return read_clk(dev, clk_src_href);
			case 0x04000000: break;
			case 0x08000000: return read_clk(dev, clk_src_hclk);
			case 0x0c000000:
				return read_clk(dev, clk_src_hclkm3) >> P;
			}
			break;
		default:
			break;
		}
	default:
		break;
	}

	NV_DEBUG(dev, "unknown clock source %d 0x%08x\n", src, mast);
	return 0;
}

int
nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	if (dev_priv->chipset == 0xaa ||
	    dev_priv->chipset == 0xac)
		return 0;

	perflvl->core   = read_clk(dev, clk_src_nvclk);
	perflvl->shader = read_clk(dev, clk_src_sclk);
	perflvl->memory = read_clk(dev, clk_src_mclk);
	if (dev_priv->chipset != 0x50) {
		perflvl->vdec = read_clk(dev, clk_src_vdec);
		perflvl->dom6 = read_clk(dev, clk_src_dom6);
	}

	return 0;
}

struct nv50_pm_state {
	u32 emast;
	u32 nctrl;
	u32 ncoef;
	u32 sctrl;
	u32 scoef;

	u32 amast;
	u32 pdivs;

	u32 mscript;
	u32 mctrl;
	u32 mcoef;
};

static u32
calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll,
	 u32 clk, int *N1, int *M1, int *log2P)
{
	struct nouveau_pll_vals coef;
	int ret;

	ret = get_pll_limits(dev, reg, pll);
	if (ret)
		return 0;

	pll->vco2.maxfreq = 0;
	pll->refclk = read_pll_ref(dev, reg);
	if (!pll->refclk)
		return 0;

	ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef);
	if (ret == 0)
		return 0;

	*N1 = coef.N1;
	*M1 = coef.M1;
	*log2P = coef.log2P;
	return ret;
}

static inline u32
calc_div(u32 src, u32 target, int *div)
{
	u32 clk0 = src, clk1 = src;
	for (*div = 0; *div <= 7; (*div)++) {
		if (clk0 <= target) {
			clk1 = clk0 << (*div ? 1 : 0);
			break;
		}
		clk0 >>= 1;
	}

	if (target - clk0 <= clk1 - target)
		return clk0;
	(*div)--;
	return clk1;
}

static inline u32
clk_same(u32 a, u32 b)
{
	return ((a / 1000) == (b / 1000));
}

void *
nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv50_pm_state *info;
	struct pll_lims pll;
	int ret = -EINVAL;
	int N, M, P1, P2;
	u32 clk, out;

	if (dev_priv->chipset == 0xaa ||
	    dev_priv->chipset == 0xac)
		return ERR_PTR(-ENODEV);

	info = kmalloc(sizeof(*info), GFP_KERNEL);
	if (!info)
		return ERR_PTR(-ENOMEM);

	/* core: for the moment at least, always use nvpll */
	clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1);
	if (clk == 0)
		goto error;

	info->emast = 0x00000003;
	info->nctrl = 0x80000000 | (P1 << 19) | (P1 << 16);
	info->ncoef = (N << 8) | M;

	/* shader: tie to nvclk if possible, otherwise use spll.  have to be
	 * very careful that the shader clock is at least twice the core, or
	 * some chipsets will be very unhappy.  i expect most or all of these
	 * cases will be handled by tying to nvclk, but it's possible there's
	 * corners
	 */
	if (P1-- && perflvl->shader == (perflvl->core << 1)) {
		info->emast |= 0x00000020;
		info->sctrl  = 0x00000000 | (P1 << 19) | (P1 << 16);
		info->scoef  = nv_rd32(dev, 0x004024);
	} else {
		clk = calc_pll(dev, 0x4020, &pll, perflvl->shader, &N, &M, &P1);
		if (clk == 0)
			goto error;

		info->emast |= 0x00000030;
		info->sctrl  = 0x80000000 | (P1 << 19) | (P1 << 16);
		info->scoef  = (N << 8) | M;
	}

	/* memory: use pcie refclock if possible, otherwise use mpll */
	info->mscript = perflvl->memscript;
	if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) {
		info->mctrl = 0x00000200 | (pll.log2p_bias << 19);
		info->mcoef = nv_rd32(dev, 0x400c);
	} else
	if (perflvl->memory) {
		clk = calc_pll(dev, 0x4008, &pll, perflvl->memory,
			       &N, &M, &P1);
		if (clk == 0)
			goto error;

		info->mctrl  = 0x80000000 | (P1 << 22) | (P1 << 16);
		info->mctrl |= pll.log2p_bias << 19;
		info->mcoef  = (N << 8) | M;
	} else {
		info->mctrl = 0x00000000;
	}

	/* vdec: avoid modifying xpll until we know exactly how the other
	 * clock domains work, i suspect at least some of them can also be
	 * tied to xpll...
	 */
	info->amast = nv_rd32(dev, 0x00c040);
	info->pdivs = read_div(dev);
	if (perflvl->vdec) {
		/* see how close we can get using nvclk as a source */
		clk = calc_div(perflvl->core, perflvl->vdec, &P1);

		/* see how close we can get using xpll/hclk as a source */
		if (dev_priv->chipset != 0x98)
			out = read_pll(dev, 0x004030);
		else
			out = read_clk(dev, clk_src_hclkm3d2);
		out = calc_div(out, perflvl->vdec, &P2);

		/* select whichever gets us closest */
		info->amast &= ~0x00000c00;
		info->pdivs &= ~0x00000700;
		if (abs((int)perflvl->vdec - clk) <=
		    abs((int)perflvl->vdec - out)) {
			if (dev_priv->chipset != 0x98)
				info->amast |= 0x00000c00;
			info->pdivs |= P1 << 8;
		} else {
			info->amast |= 0x00000800;
			info->pdivs |= P2 << 8;
		}
	}

	/* dom6: nfi what this is, but we're limited to various combinations
	 * of the host clock frequency
	 */
	if (perflvl->dom6) {
		info->amast &= ~0x0c000000;
		if (clk_same(perflvl->dom6, read_clk(dev, clk_src_href))) {
			info->amast |= 0x00000000;
		} else
		if (clk_same(perflvl->dom6, read_clk(dev, clk_src_hclk))) {
			info->amast |= 0x08000000;
		} else {
			clk = read_clk(dev, clk_src_hclk) * 3;
			clk = calc_div(clk, perflvl->dom6, &P1);

			info->amast |= 0x0c000000;
			info->pdivs  = (info->pdivs & ~0x00000007) | P1;
		}
	}

	return info;
error:
	kfree(info);
	return ERR_PTR(ret);
}

int
nv50_pm_clocks_set(struct drm_device *dev, void *data)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv50_pm_state *info = data;
	struct bit_entry M;
	int ret = 0;

	/* halt and idle execution engines */
	nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
	if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010))
		goto error;

	/* reclock vdec/dom6 */
	nv_mask(dev, 0x00c040, 0x00000c00, 0x00000000);
	switch (dev_priv->chipset) {
	case 0x92:
	case 0x94:
	case 0x96:
		nv_mask(dev, 0x004800, 0x00000707, info->pdivs);
		break;
	default:
		nv_mask(dev, 0x004700, 0x00000707, info->pdivs);
		break;
	}
	nv_mask(dev, 0x00c040, 0x0c000c00, info->amast);

	/* core/shader: make sure sclk/nvclk are disconnected from their
	 * plls (nvclk to dom6, sclk to hclk), modify the plls, and
	 * reconnect sclk/nvclk to their new clock source
	 */
	if (dev_priv->chipset < 0x92)
		nv_mask(dev, 0x00c040, 0x001000b0, 0x00100080); /* grrr! */
	else
		nv_mask(dev, 0x00c040, 0x000000b3, 0x00000081);
	nv_mask(dev, 0x004020, 0xc03f0100, info->sctrl);
	nv_wr32(dev, 0x004024, info->scoef);
	nv_mask(dev, 0x004028, 0xc03f0100, info->nctrl);
	nv_wr32(dev, 0x00402c, info->ncoef);
	nv_mask(dev, 0x00c040, 0x00100033, info->emast);

	/* memory */
	if (!info->mctrl)
		goto resume;

	/* execute some scripts that do ??? from the vbios.. */
	if (!bit_table(dev, 'M', &M) && M.version == 1) {
		if (M.length >= 6)
			nouveau_bios_init_exec(dev, ROM16(M.data[5]));
		if (M.length >= 8)
			nouveau_bios_init_exec(dev, ROM16(M.data[7]));
		if (M.length >= 10)
			nouveau_bios_init_exec(dev, ROM16(M.data[9]));
		nouveau_bios_init_exec(dev, info->mscript);
	}

	/* disable display */
	if (dev_priv->chipset >= 0x92) {
		nv_wr32(dev, 0x611200, 0x00003300);
		udelay(100);
	}

	/* prepare ram for reclocking */
	nv_wr32(dev, 0x1002d4, 0x00000001); /* precharge */
	nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
	nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
	nv_mask(dev, 0x100210, 0x80000000, 0x00000000); /* no auto-refresh */
	nv_wr32(dev, 0x1002dc, 0x00000001); /* enable self-refresh */

	/* modify mpll */
	nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000);
	nv_mask(dev, 0x004008, 0x01ff0200, 0x00000200 | info->mctrl);
	nv_wr32(dev, 0x00400c, info->mcoef);
	udelay(100);
	nv_mask(dev, 0x004008, 0x81ff0200, info->mctrl);

	/* re-enable normal operation of memory controller */
	nv_wr32(dev, 0x1002dc, 0x00000000);
	nv_mask(dev, 0x100210, 0x80000000, 0x80000000);
	udelay(100);

	/* re-enable display */
	if (dev_priv->chipset >= 0x92)
		nv_wr32(dev, 0x611200, 0x00003330);

	goto resume;
error:
	ret = -EBUSY;
resume:
	nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
	kfree(info);
	return ret;
}

static int
pwm_info(struct drm_device *dev, struct dcb_gpio_entry *gpio,
	 int *ctrl, int *line, int *indx)
{
	if (gpio->line == 0x04) {
		*ctrl = 0x00e100;
		*line = 4;
		*indx = 0;
	} else
	if (gpio->line == 0x09) {
		*ctrl = 0x00e100;
		*line = 9;
		*indx = 1;
	} else
	if (gpio->line == 0x10) {
		*ctrl = 0x00e28c;
		*line = 0;
		*indx = 0;
	} else {
		NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", gpio->line);
		return -ENODEV;
	}

	return 0;
}

int
nv50_pm_pwm_get(struct drm_device *dev, struct dcb_gpio_entry *gpio,
		u32 *divs, u32 *duty)
{
	int ctrl, line, id, ret = pwm_info(dev, gpio, &ctrl, &line, &id);
	if (ret)
		return ret;

	if (nv_rd32(dev, ctrl) & (1 << line)) {
		*divs = nv_rd32(dev, 0x00e114 + (id * 8));
		*duty = nv_rd32(dev, 0x00e118 + (id * 8));
		return 0;
	}

	return -EINVAL;
}

int
nv50_pm_pwm_set(struct drm_device *dev, struct dcb_gpio_entry *gpio,
		u32 divs, u32 duty)
{
	int ctrl, line, id, ret = pwm_info(dev, gpio, &ctrl, &line, &id);
	if (ret)
		return ret;

	nv_mask(dev, ctrl, 0x00010001 << line, 0x00000001 << line);
	nv_wr32(dev, 0x00e114 + (id * 8), divs);
	nv_wr32(dev, 0x00e118 + (id * 8), duty | 0x80000000);
	return 0;
}
Commit	Line	Data
02c30ca0 BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
	26	#include "nouveau_drv.h"
aee582de	27	#include "nouveau_bios.h"
f3fbaf34	28	#include "nouveau_hw.h"
02c30ca0 BS	29	#include "nouveau_pm.h"
02c30ca0 BS	30
f3fbaf34 BS	31	enum clk_src {
	32	clk_src_crystal,
	33	clk_src_href,
	34	clk_src_hclk,
	35	clk_src_hclkm3,
	36	clk_src_hclkm3d2,
	37	clk_src_host,
	38	clk_src_nvclk,
	39	clk_src_sclk,
	40	clk_src_mclk,
	41	clk_src_vdec,
	42	clk_src_dom6
02c30ca0 BS	43	};
02c30ca0 BS	44
f3fbaf34 BS	45	static u32 read_clk(struct drm_device *, enum clk_src);
	46
	47	static u32
	48	read_div(struct drm_device *dev)
	49	{
	50	struct drm_nouveau_private *dev_priv = dev->dev_private;
	51
	52	switch (dev_priv->chipset) {
	53	case 0x50: /* it exists, but only has bit 31, not the dividers.. */
	54	case 0x84:
	55	case 0x86:
	56	case 0x98:
	57	case 0xa0:
	58	return nv_rd32(dev, 0x004700);
	59	case 0x92:
	60	case 0x94:
	61	case 0x96:
	62	return nv_rd32(dev, 0x004800);
	63	default:
	64	return 0x00000000;
	65	}
	66	}
	67
	68	static u32
463464eb	69	read_pll_src(struct drm_device *dev, u32 base)
f3fbaf34 BS	70	{
	71	struct drm_nouveau_private *dev_priv = dev->dev_private;
	72	u32 coef, ref = read_clk(dev, clk_src_crystal);
	73	u32 rsel = nv_rd32(dev, 0x00e18c);
	74	int P, N, M, id;
	75
	76	switch (dev_priv->chipset) {
	77	case 0x50:
	78	case 0xa0:
	79	switch (base) {
	80	case 0x4020:
	81	case 0x4028: id = !!(rsel & 0x00000004); break;
	82	case 0x4008: id = !!(rsel & 0x00000008); break;
	83	case 0x4030: id = 0; break;
	84	default:
	85	NV_ERROR(dev, "ref: bad pll 0x%06x\n", base);
	86	return 0;
	87	}
	88
	89	coef = nv_rd32(dev, 0x00e81c + (id * 0x0c));
	90	ref *= (coef & 0x01000000) ? 2 : 4;
	91	P = (coef & 0x00070000) >> 16;
	92	N = ((coef & 0x0000ff00) >> 8) + 1;
	93	M = ((coef & 0x000000ff) >> 0) + 1;
	94	break;
	95	case 0x84:
	96	case 0x86:
	97	case 0x92:
	98	coef = nv_rd32(dev, 0x00e81c);
	99	P = (coef & 0x00070000) >> 16;
	100	N = (coef & 0x0000ff00) >> 8;
	101	M = (coef & 0x000000ff) >> 0;
	102	break;
	103	case 0x94:
	104	case 0x96:
	105	case 0x98:
	106	rsel = nv_rd32(dev, 0x00c050);
	107	switch (base) {
	108	case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
	109	case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
	110	case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
	111	case 0x4030: rsel = 3; break;
	112	default:
	113	NV_ERROR(dev, "ref: bad pll 0x%06x\n", base);
	114	return 0;
	115	}
	116
	117	switch (rsel) {
	118	case 0: id = 1; break;
	119	case 1: return read_clk(dev, clk_src_crystal);
	120	case 2: return read_clk(dev, clk_src_href);
	121	case 3: id = 0; break;
	122	}
	123
	124	coef = nv_rd32(dev, 0x00e81c + (id * 0x28));
	125	P = (nv_rd32(dev, 0x00e824 + (id * 0x28)) >> 16) & 7;
	126	P += (coef & 0x00070000) >> 16;
	127	N = (coef & 0x0000ff00) >> 8;
	128	M = (coef & 0x000000ff) >> 0;
	129	break;
	130	default:
	131	BUG_ON(1);
	132	}
	133
134	if (M)
135	return (ref * N / M) >> P;
136	return 0;
137	}
138
139	static u32
463464eb	140	read_pll_ref(struct drm_device *dev, u32 base)
f3fbaf34	141	{
463464eb	142	u32 src, mast = nv_rd32(dev, 0x00c040);
f3fbaf34 BS	143
	144	switch (base) {
	145	case 0x004028:
f3fbaf34 BS	146	src = !!(mast & 0x00200000);
	147	break;
	148	case 0x004020:
	149	src = !!(mast & 0x00400000);
	150	break;
	151	case 0x004008:
	152	src = !!(mast & 0x00010000);
	153	break;
	154	case 0x004030:
	155	src = !!(mast & 0x02000000);
	156	break;
	157	case 0x00e810:
463464eb	158	return read_clk(dev, clk_src_crystal);
f3fbaf34 BS	159	default:
	160	NV_ERROR(dev, "bad pll 0x%06x\n", base);
	161	return 0;
	162	}
	163
463464eb BS	164	if (src)
	165	return read_clk(dev, clk_src_href);
	166	return read_pll_src(dev, base);
	167	}
f3fbaf34	168
463464eb BS	169	static u32
	170	read_pll(struct drm_device *dev, u32 base)
	171	{
	172	struct drm_nouveau_private *dev_priv = dev->dev_private;
	173	u32 mast = nv_rd32(dev, 0x00c040);
	174	u32 ctrl = nv_rd32(dev, base + 0);
	175	u32 coef = nv_rd32(dev, base + 4);
	176	u32 ref = read_pll_ref(dev, base);
	177	u32 clk = 0;
	178	int N1, N2, M1, M2;
	179
	180	if (base == 0x004028 && (mast & 0x00100000)) {
	181	/* wtf, appears to only disable post-divider on nva0 */
	182	if (dev_priv->chipset != 0xa0)
	183	return read_clk(dev, clk_src_dom6);
	184	}
f3fbaf34 BS	185
	186	N2 = (coef & 0xff000000) >> 24;
	187	M2 = (coef & 0x00ff0000) >> 16;
	188	N1 = (coef & 0x0000ff00) >> 8;
	189	M1 = (coef & 0x000000ff);
	190	if ((ctrl & 0x80000000) && M1) {
	191	clk = ref * N1 / M1;
	192	if ((ctrl & 0x40000100) == 0x40000000) {
	193	if (M2)
	194	clk = clk * N2 / M2;
	195	else
	196	clk = 0;
	197	}
	198	}
	199
	200	return clk;
	201	}
	202
	203	static u32
	204	read_clk(struct drm_device *dev, enum clk_src src)
	205	{
	206	struct drm_nouveau_private *dev_priv = dev->dev_private;
	207	u32 mast = nv_rd32(dev, 0x00c040);
	208	u32 P = 0;
	209
	210	switch (src) {
	211	case clk_src_crystal:
	212	return dev_priv->crystal;
	213	case clk_src_href:
	214	return 100000; /* PCIE reference clock */
	215	case clk_src_hclk:
	216	return read_clk(dev, clk_src_href) * 27778 / 10000;
	217	case clk_src_hclkm3:
	218	return read_clk(dev, clk_src_hclk) * 3;
	219	case clk_src_hclkm3d2:
	220	return read_clk(dev, clk_src_hclk) * 3 / 2;
	221	case clk_src_host:
	222	switch (mast & 0x30000000) {
	223	case 0x00000000: return read_clk(dev, clk_src_href);
	224	case 0x10000000: break;
	225	case 0x20000000: /* !0x50 */
	226	case 0x30000000: return read_clk(dev, clk_src_hclk);
	227	}
	228	break;
	229	case clk_src_nvclk:
	230	if (!(mast & 0x00100000))
	231	P = (nv_rd32(dev, 0x004028) & 0x00070000) >> 16;
	232	switch (mast & 0x00000003) {
	233	case 0x00000000: return read_clk(dev, clk_src_crystal) >> P;
	234	case 0x00000001: return read_clk(dev, clk_src_dom6);
	235	case 0x00000002: return read_pll(dev, 0x004020) >> P;
	236	case 0x00000003: return read_pll(dev, 0x004028) >> P;
	237	}
	238	break;
	239	case clk_src_sclk:
	240	P = (nv_rd32(dev, 0x004020) & 0x00070000) >> 16;
	241	switch (mast & 0x00000030) {
	242	case 0x00000000:
	243	if (mast & 0x00000080)
	244	return read_clk(dev, clk_src_host) >> P;
	245	return read_clk(dev, clk_src_crystal) >> P;
	246	case 0x00000010: break;
	247	case 0x00000020: return read_pll(dev, 0x004028) >> P;
	248	case 0x00000030: return read_pll(dev, 0x004020) >> P;
249	}
250	break;
251	case clk_src_mclk:
252	P = (nv_rd32(dev, 0x004008) & 0x00070000) >> 16;
253	if (nv_rd32(dev, 0x004008) & 0x00000200) {
254	switch (mast & 0x0000c000) {
255	case 0x00000000:
256	return read_clk(dev, clk_src_crystal) >> P;
257	case 0x00008000:
258	case 0x0000c000:
259	return read_clk(dev, clk_src_href) >> P;
260	}
261	} else {
262	return read_pll(dev, 0x004008) >> P;
263	}
264	break;
265	case clk_src_vdec:
266	P = (read_div(dev) & 0x00000700) >> 8;
267	switch (dev_priv->chipset) {
268	case 0x84:
269	case 0x86:
270	case 0x92:
271	case 0x94:
272	case 0x96:
273	case 0xa0:
274	switch (mast & 0x00000c00) {
275	case 0x00000000:
276	if (dev_priv->chipset == 0xa0) /* wtf?? */
277	return read_clk(dev, clk_src_nvclk) >> P;
278	return read_clk(dev, clk_src_crystal) >> P;
279	case 0x00000400:
280	return 0;
281	case 0x00000800:
282	if (mast & 0x01000000)
283	return read_pll(dev, 0x004028) >> P;
284	return read_pll(dev, 0x004030) >> P;
285	case 0x00000c00:
286	return read_clk(dev, clk_src_nvclk) >> P;
287	}
288	break;
289	case 0x98:
290	switch (mast & 0x00000c00) {
291	case 0x00000000:
292	return read_clk(dev, clk_src_nvclk) >> P;
293	case 0x00000400:
294	return 0;
295	case 0x00000800:
296	return read_clk(dev, clk_src_hclkm3d2) >> P;
297	case 0x00000c00:
d4676461	298	return read_clk(dev, clk_src_mclk) >> P;
f3fbaf34 BS	299	}
	300	break;
	301	}
	302	break;
	303	case clk_src_dom6:
	304	switch (dev_priv->chipset) {
	305	case 0x50:
	306	case 0xa0:
	307	return read_pll(dev, 0x00e810) >> 2;
	308	case 0x84:
	309	case 0x86:
	310	case 0x92:
	311	case 0x94:
	312	case 0x96:
	313	case 0x98:
	314	P = (read_div(dev) & 0x00000007) >> 0;
	315	switch (mast & 0x0c000000) {
	316	case 0x00000000: return read_clk(dev, clk_src_href);
	317	case 0x04000000: break;
	318	case 0x08000000: return read_clk(dev, clk_src_hclk);
	319	case 0x0c000000:
	320	return read_clk(dev, clk_src_hclkm3) >> P;
	321	}
	322	break;
	323	default:
	324	break;
	325	}
	326	default:
	327	break;
	328	}
	329
	330	NV_DEBUG(dev, "unknown clock source %d 0x%08x\n", src, mast);
	331	return 0;
	332	}
	333
02c30ca0	334	int
f3fbaf34	335	nv50_pm_clocks_get(struct drm_device dev, struct nouveau_pm_level perflvl)
02c30ca0	336	{
f3fbaf34 BS	337	struct drm_nouveau_private *dev_priv = dev->dev_private;
	338	if (dev_priv->chipset == 0xaa \|\|
	339	dev_priv->chipset == 0xac)
	340	return 0;
	341
	342	perflvl->core = read_clk(dev, clk_src_nvclk);
	343	perflvl->shader = read_clk(dev, clk_src_sclk);
	344	perflvl->memory = read_clk(dev, clk_src_mclk);
	345	if (dev_priv->chipset != 0x50) {
	346	perflvl->vdec = read_clk(dev, clk_src_vdec);
	347	perflvl->dom6 = read_clk(dev, clk_src_dom6);
	348	}
	349
	350	return 0;
	351	}
	352
	353	struct nv50_pm_state {
	354	u32 emast;
	355	u32 nctrl;
	356	u32 ncoef;
	357	u32 sctrl;
	358	u32 scoef;
	359
	360	u32 amast;
	361	u32 pdivs;
	362
	363	u32 mscript;
	364	u32 mctrl;
	365	u32 mcoef;
	366	};
	367
	368	static u32
	369	calc_pll(struct drm_device dev, u32 reg, struct pll_lims pll,
	370	u32 clk, int N1, int M1, int *log2P)
	371	{
	372	struct nouveau_pll_vals coef;
	373	int ret;
02c30ca0	374
f3fbaf34	375	ret = get_pll_limits(dev, reg, pll);
02c30ca0	376	if (ret)
f3fbaf34 BS	377	return 0;
	378
	379	pll->vco2.maxfreq = 0;
	380	pll->refclk = read_pll_ref(dev, reg);
	381	if (!pll->refclk)
	382	return 0;
	383
	384	ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef);
	385	if (ret == 0)
	386	return 0;
	387
	388	*N1 = coef.N1;
	389	*M1 = coef.M1;
	390	*log2P = coef.log2P;
	391	return ret;
	392	}
	393
	394	static inline u32
	395	calc_div(u32 src, u32 target, int *div)
	396	{
	397	u32 clk0 = src, clk1 = src;
	398	for (div = 0; div <= 7; (*div)++) {
	399	if (clk0 <= target) {
	400	clk1 = clk0 << (*div ? 1 : 0);
	401	break;
619d4f7e	402	}
f3fbaf34	403	clk0 >>= 1;
619d4f7e EV	404	}
619d4f7e EV	405
f3fbaf34 BS	406	if (target - clk0 <= clk1 - target)
	407	return clk0;
	408	(*div)--;
	409	return clk1;
	410	}
02c30ca0	411
f3fbaf34 BS	412	static inline u32
	413	clk_same(u32 a, u32 b)
	414	{
	415	return ((a / 1000) == (b / 1000));
02c30ca0 BS	416	}
	417
	418	void *
f3fbaf34	419	nv50_pm_clocks_pre(struct drm_device dev, struct nouveau_pm_level perflvl)
02c30ca0	420	{
f3fbaf34 BS	421	struct drm_nouveau_private *dev_priv = dev->dev_private;
	422	struct nv50_pm_state *info;
	423	struct pll_lims pll;
	424	int ret = -EINVAL;
	425	int N, M, P1, P2;
	426	u32 clk, out;
	427
	428	if (dev_priv->chipset == 0xaa \|\|
	429	dev_priv->chipset == 0xac)
	430	return ERR_PTR(-ENODEV);
02c30ca0	431
f3fbaf34 BS	432	info = kmalloc(sizeof(*info), GFP_KERNEL);
f3fbaf34 BS	433	if (!info)
02c30ca0	434	return ERR_PTR(-ENOMEM);
02c30ca0	435
f3fbaf34 BS	436	/* core: for the moment at least, always use nvpll */
	437	clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1);
	438	if (clk == 0)
	439	goto error;
	440
	441	info->emast = 0x00000003;
	442	info->nctrl = 0x80000000 \| (P1 << 19) \| (P1 << 16);
	443	info->ncoef = (N << 8) \| M;
	444
	445	/* shader: tie to nvclk if possible, otherwise use spll. have to be
	446	* very careful that the shader clock is at least twice the core, or
	447	* some chipsets will be very unhappy. i expect most or all of these
	448	* cases will be handled by tying to nvclk, but it's possible there's
	449	* corners
	450	*/
	451	if (P1-- && perflvl->shader == (perflvl->core << 1)) {
	452	info->emast \|= 0x00000020;
	453	info->sctrl = 0x00000000 \| (P1 << 19) \| (P1 << 16);
	454	info->scoef = nv_rd32(dev, 0x004024);
	455	} else {
	456	clk = calc_pll(dev, 0x4020, &pll, perflvl->shader, &N, &M, &P1);
	457	if (clk == 0)
	458	goto error;
	459
	460	info->emast \|= 0x00000030;
	461	info->sctrl = 0x80000000 \| (P1 << 19) \| (P1 << 16);
	462	info->scoef = (N << 8) \| M;
	463	}
	464
	465	/* memory: use pcie refclock if possible, otherwise use mpll */
	466	info->mscript = perflvl->memscript;
	467	if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) {
8b5f4d0d	468	info->mctrl = 0x00000200 \| (pll.log2p_bias << 19);
f3fbaf34 BS	469	info->mcoef = nv_rd32(dev, 0x400c);
	470	} else
	471	if (perflvl->memory) {
	472	clk = calc_pll(dev, 0x4008, &pll, perflvl->memory,
	473	&N, &M, &P1);
	474	if (clk == 0)
	475	goto error;
	476
	477	info->mctrl = 0x80000000 \| (P1 << 22) \| (P1 << 16);
	478	info->mctrl \|= pll.log2p_bias << 19;
	479	info->mcoef = (N << 8) \| M;
	480	} else {
	481	info->mctrl = 0x00000000;
	482	}
	483
	484	/* vdec: avoid modifying xpll until we know exactly how the other
	485	* clock domains work, i suspect at least some of them can also be
	486	* tied to xpll...
	487	*/
973e8616 BS	488	info->amast = nv_rd32(dev, 0x00c040);
973e8616 BS	489	info->pdivs = read_div(dev);
f3fbaf34 BS	490	if (perflvl->vdec) {
	491	/* see how close we can get using nvclk as a source */
	492	clk = calc_div(perflvl->core, perflvl->vdec, &P1);
	493
	494	/* see how close we can get using xpll/hclk as a source */
	495	if (dev_priv->chipset != 0x98)
	496	out = read_pll(dev, 0x004030);
	497	else
	498	out = read_clk(dev, clk_src_hclkm3d2);
	499	out = calc_div(out, perflvl->vdec, &P2);
	500
	501	/* select whichever gets us closest */
973e8616 BS	502	info->amast &= ~0x00000c00;
973e8616 BS	503	info->pdivs &= ~0x00000700;
f3fbaf34 BS	504	if (abs((int)perflvl->vdec - clk) <=
	505	abs((int)perflvl->vdec - out)) {
	506	if (dev_priv->chipset != 0x98)
	507	info->amast \|= 0x00000c00;
f3fbaf34 BS	508	info->pdivs \|= P1 << 8;
	509	} else {
	510	info->amast \|= 0x00000800;
	511	info->pdivs \|= P2 << 8;
	512	}
02c30ca0 BS	513	}
02c30ca0 BS	514
f3fbaf34 BS	515	/* dom6: nfi what this is, but we're limited to various combinations
	516	* of the host clock frequency
	517	*/
f3fbaf34	518	if (perflvl->dom6) {
973e8616 BS	519	info->amast &= ~0x0c000000;
	520	if (clk_same(perflvl->dom6, read_clk(dev, clk_src_href))) {
	521	info->amast \|= 0x00000000;
	522	} else
	523	if (clk_same(perflvl->dom6, read_clk(dev, clk_src_hclk))) {
	524	info->amast \|= 0x08000000;
	525	} else {
	526	clk = read_clk(dev, clk_src_hclk) * 3;
	527	clk = calc_div(clk, perflvl->dom6, &P1);
f3fbaf34	528
973e8616 BS	529	info->amast \|= 0x0c000000;
	530	info->pdivs = (info->pdivs & ~0x00000007) \| P1;
	531	}
02c30ca0 BS	532	}
02c30ca0 BS	533
f3fbaf34 BS	534	return info;
	535	error:
	536	kfree(info);
	537	return ERR_PTR(ret);
02c30ca0 BS	538	}
02c30ca0 BS	539
f3fbaf34 BS	540	int
f3fbaf34 BS	541	nv50_pm_clocks_set(struct drm_device dev, void data)
02c30ca0	542	{
f3fbaf34 BS	543	struct drm_nouveau_private *dev_priv = dev->dev_private;
	544	struct nv50_pm_state *info = data;
	545	struct bit_entry M;
	546	int ret = 0;
	547
	548	/* halt and idle execution engines */
	549	nv_mask(dev, 0x002504, 0x00000001, 0x00000001);
	550	if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010))
	551	goto error;
aee582de	552
f3fbaf34 BS	553	/* reclock vdec/dom6 */
	554	nv_mask(dev, 0x00c040, 0x00000c00, 0x00000000);
	555	switch (dev_priv->chipset) {
	556	case 0x92:
	557	case 0x94:
	558	case 0x96:
	559	nv_mask(dev, 0x004800, 0x00000707, info->pdivs);
	560	break;
	561	default:
	562	nv_mask(dev, 0x004700, 0x00000707, info->pdivs);
	563	break;
fade7ad5	564	}
f3fbaf34 BS	565	nv_mask(dev, 0x00c040, 0x0c000c00, info->amast);
f3fbaf34 BS	566
6805979f BS	567	/* core/shader: make sure sclk/nvclk are disconnected from their
	568	* plls (nvclk to dom6, sclk to hclk), modify the plls, and
	569	* reconnect sclk/nvclk to their new clock source
	570	*/
	571	if (dev_priv->chipset < 0x92)
f3fbaf34 BS	572	nv_mask(dev, 0x00c040, 0x001000b0, 0x00100080); /* grrr! */
	573	else
	574	nv_mask(dev, 0x00c040, 0x000000b3, 0x00000081);
	575	nv_mask(dev, 0x004020, 0xc03f0100, info->sctrl);
	576	nv_wr32(dev, 0x004024, info->scoef);
	577	nv_mask(dev, 0x004028, 0xc03f0100, info->nctrl);
	578	nv_wr32(dev, 0x00402c, info->ncoef);
	579	nv_mask(dev, 0x00c040, 0x00100033, info->emast);
fade7ad5	580
f3fbaf34 BS	581	/* memory */
	582	if (!info->mctrl)
	583	goto resume;
fade7ad5	584
f3fbaf34 BS	585	/* execute some scripts that do ??? from the vbios.. */
	586	if (!bit_table(dev, 'M', &M) && M.version == 1) {
	587	if (M.length >= 6)
	588	nouveau_bios_init_exec(dev, ROM16(M.data[5]));
	589	if (M.length >= 8)
	590	nouveau_bios_init_exec(dev, ROM16(M.data[7]));
	591	if (M.length >= 10)
	592	nouveau_bios_init_exec(dev, ROM16(M.data[9]));
	593	nouveau_bios_init_exec(dev, info->mscript);
02c30ca0 BS	594	}
02c30ca0 BS	595
f3fbaf34	596	/* disable display */
d2491567 BS	597	if (dev_priv->chipset >= 0x92) {
	598	nv_wr32(dev, 0x611200, 0x00003300);
	599	udelay(100);
	600	}
f3fbaf34 BS	601
	602	/* prepare ram for reclocking */
	603	nv_wr32(dev, 0x1002d4, 0x00000001); /* precharge */
	604	nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
	605	nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */
	606	nv_mask(dev, 0x100210, 0x80000000, 0x00000000); /* no auto-refresh */
	607	nv_wr32(dev, 0x1002dc, 0x00000001); /* enable self-refresh */
	608
	609	/* modify mpll */
	610	nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000);
8b5f4d0d	611	nv_mask(dev, 0x004008, 0x01ff0200, 0x00000200 \| info->mctrl);
f3fbaf34 BS	612	nv_wr32(dev, 0x00400c, info->mcoef);
	613	udelay(100);
	614	nv_mask(dev, 0x004008, 0x81ff0200, info->mctrl);
	615
	616	/* re-enable normal operation of memory controller */
	617	nv_wr32(dev, 0x1002dc, 0x00000000);
	618	nv_mask(dev, 0x100210, 0x80000000, 0x80000000);
	619	udelay(100);
	620
	621	/* re-enable display */
d2491567 BS	622	if (dev_priv->chipset >= 0x92)
d2491567 BS	623	nv_wr32(dev, 0x611200, 0x00003330);
f3fbaf34 BS	624
	625	goto resume;
	626	error:
	627	ret = -EBUSY;
	628	resume:
	629	nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
19fa224f	630	kfree(info);
f3fbaf34	631	return ret;
02c30ca0 BS	632	}
02c30ca0 BS	633
cb9fa626	634	static int
5a4267ab BS	635	pwm_info(struct drm_device dev, struct dcb_gpio_entry gpio,
5a4267ab BS	636	int ctrl, int line, int *indx)
cb9fa626	637	{
5a4267ab BS	638	if (gpio->line == 0x04) {
	639	*ctrl = 0x00e100;
	640	*line = 4;
	641	*indx = 0;
	642	} else
	643	if (gpio->line == 0x09) {
	644	*ctrl = 0x00e100;
	645	*line = 9;
	646	*indx = 1;
	647	} else
	648	if (gpio->line == 0x10) {
	649	*ctrl = 0x00e28c;
	650	*line = 0;
	651	*indx = 0;
	652	} else {
	653	NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", gpio->line);
	654	return -ENODEV;
cb9fa626 BS	655	}
cb9fa626 BS	656
5a4267ab	657	return 0;
cb9fa626 BS	658	}
	659
	660	int
5a4267ab BS	661	nv50_pm_pwm_get(struct drm_device dev, struct dcb_gpio_entry gpio,
5a4267ab BS	662	u32 divs, u32 duty)
cb9fa626	663	{
5a4267ab	664	int ctrl, line, id, ret = pwm_info(dev, gpio, &ctrl, &line, &id);
cb9fa626 BS	665	if (ret)
	666	return ret;
	667
5a4267ab BS	668	if (nv_rd32(dev, ctrl) & (1 << line)) {
	669	divs = nv_rd32(dev, 0x00e114 + (id 8));
	670	duty = nv_rd32(dev, 0x00e118 + (id 8));
cb9fa626 BS	671	return 0;
	672	}
	673
5a4267ab	674	return -EINVAL;
cb9fa626 BS	675	}
	676
	677	int
5a4267ab BS	678	nv50_pm_pwm_set(struct drm_device dev, struct dcb_gpio_entry gpio,
5a4267ab BS	679	u32 divs, u32 duty)
cb9fa626	680	{
5a4267ab	681	int ctrl, line, id, ret = pwm_info(dev, gpio, &ctrl, &line, &id);
cb9fa626 BS	682	if (ret)
	683	return ret;
	684
5a4267ab BS	685	nv_mask(dev, ctrl, 0x00010001 << line, 0x00000001 << line);
	686	nv_wr32(dev, 0x00e114 + (id * 8), divs);
	687	nv_wr32(dev, 0x00e118 + (id * 8), duty \| 0x80000000);
cb9fa626 BS	688	return 0;
cb9fa626 BS	689	}