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02c30ca0 BS |
1 | /* |
2 | * Copyright 2010 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include "drmP.h" | |
26 | #include "nouveau_drv.h" | |
aee582de | 27 | #include "nouveau_bios.h" |
f3fbaf34 | 28 | #include "nouveau_hw.h" |
02c30ca0 | 29 | #include "nouveau_pm.h" |
eeb7a50b | 30 | #include "nouveau_hwsq.h" |
02c30ca0 | 31 | |
f3fbaf34 BS |
32 | enum clk_src { |
33 | clk_src_crystal, | |
34 | clk_src_href, | |
35 | clk_src_hclk, | |
36 | clk_src_hclkm3, | |
37 | clk_src_hclkm3d2, | |
38 | clk_src_host, | |
39 | clk_src_nvclk, | |
40 | clk_src_sclk, | |
41 | clk_src_mclk, | |
42 | clk_src_vdec, | |
43 | clk_src_dom6 | |
02c30ca0 BS |
44 | }; |
45 | ||
f3fbaf34 BS |
46 | static u32 read_clk(struct drm_device *, enum clk_src); |
47 | ||
48 | static u32 | |
49 | read_div(struct drm_device *dev) | |
50 | { | |
51 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
52 | ||
53 | switch (dev_priv->chipset) { | |
54 | case 0x50: /* it exists, but only has bit 31, not the dividers.. */ | |
55 | case 0x84: | |
56 | case 0x86: | |
57 | case 0x98: | |
58 | case 0xa0: | |
59 | return nv_rd32(dev, 0x004700); | |
60 | case 0x92: | |
61 | case 0x94: | |
62 | case 0x96: | |
63 | return nv_rd32(dev, 0x004800); | |
64 | default: | |
65 | return 0x00000000; | |
66 | } | |
67 | } | |
68 | ||
69 | static u32 | |
463464eb | 70 | read_pll_src(struct drm_device *dev, u32 base) |
f3fbaf34 BS |
71 | { |
72 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
73 | u32 coef, ref = read_clk(dev, clk_src_crystal); | |
74 | u32 rsel = nv_rd32(dev, 0x00e18c); | |
75 | int P, N, M, id; | |
76 | ||
77 | switch (dev_priv->chipset) { | |
78 | case 0x50: | |
79 | case 0xa0: | |
80 | switch (base) { | |
81 | case 0x4020: | |
82 | case 0x4028: id = !!(rsel & 0x00000004); break; | |
83 | case 0x4008: id = !!(rsel & 0x00000008); break; | |
84 | case 0x4030: id = 0; break; | |
85 | default: | |
86 | NV_ERROR(dev, "ref: bad pll 0x%06x\n", base); | |
87 | return 0; | |
88 | } | |
89 | ||
90 | coef = nv_rd32(dev, 0x00e81c + (id * 0x0c)); | |
91 | ref *= (coef & 0x01000000) ? 2 : 4; | |
92 | P = (coef & 0x00070000) >> 16; | |
93 | N = ((coef & 0x0000ff00) >> 8) + 1; | |
94 | M = ((coef & 0x000000ff) >> 0) + 1; | |
95 | break; | |
96 | case 0x84: | |
97 | case 0x86: | |
98 | case 0x92: | |
99 | coef = nv_rd32(dev, 0x00e81c); | |
100 | P = (coef & 0x00070000) >> 16; | |
101 | N = (coef & 0x0000ff00) >> 8; | |
102 | M = (coef & 0x000000ff) >> 0; | |
103 | break; | |
104 | case 0x94: | |
105 | case 0x96: | |
106 | case 0x98: | |
107 | rsel = nv_rd32(dev, 0x00c050); | |
108 | switch (base) { | |
109 | case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; | |
110 | case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; | |
111 | case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; | |
112 | case 0x4030: rsel = 3; break; | |
113 | default: | |
114 | NV_ERROR(dev, "ref: bad pll 0x%06x\n", base); | |
115 | return 0; | |
116 | } | |
117 | ||
118 | switch (rsel) { | |
119 | case 0: id = 1; break; | |
120 | case 1: return read_clk(dev, clk_src_crystal); | |
121 | case 2: return read_clk(dev, clk_src_href); | |
122 | case 3: id = 0; break; | |
123 | } | |
124 | ||
125 | coef = nv_rd32(dev, 0x00e81c + (id * 0x28)); | |
126 | P = (nv_rd32(dev, 0x00e824 + (id * 0x28)) >> 16) & 7; | |
127 | P += (coef & 0x00070000) >> 16; | |
128 | N = (coef & 0x0000ff00) >> 8; | |
129 | M = (coef & 0x000000ff) >> 0; | |
130 | break; | |
131 | default: | |
132 | BUG_ON(1); | |
133 | } | |
134 | ||
135 | if (M) | |
136 | return (ref * N / M) >> P; | |
137 | return 0; | |
138 | } | |
139 | ||
140 | static u32 | |
463464eb | 141 | read_pll_ref(struct drm_device *dev, u32 base) |
f3fbaf34 | 142 | { |
463464eb | 143 | u32 src, mast = nv_rd32(dev, 0x00c040); |
f3fbaf34 BS |
144 | |
145 | switch (base) { | |
146 | case 0x004028: | |
f3fbaf34 BS |
147 | src = !!(mast & 0x00200000); |
148 | break; | |
149 | case 0x004020: | |
150 | src = !!(mast & 0x00400000); | |
151 | break; | |
152 | case 0x004008: | |
153 | src = !!(mast & 0x00010000); | |
154 | break; | |
155 | case 0x004030: | |
156 | src = !!(mast & 0x02000000); | |
157 | break; | |
158 | case 0x00e810: | |
463464eb | 159 | return read_clk(dev, clk_src_crystal); |
f3fbaf34 BS |
160 | default: |
161 | NV_ERROR(dev, "bad pll 0x%06x\n", base); | |
162 | return 0; | |
163 | } | |
164 | ||
463464eb BS |
165 | if (src) |
166 | return read_clk(dev, clk_src_href); | |
167 | return read_pll_src(dev, base); | |
168 | } | |
f3fbaf34 | 169 | |
463464eb BS |
170 | static u32 |
171 | read_pll(struct drm_device *dev, u32 base) | |
172 | { | |
173 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
174 | u32 mast = nv_rd32(dev, 0x00c040); | |
175 | u32 ctrl = nv_rd32(dev, base + 0); | |
176 | u32 coef = nv_rd32(dev, base + 4); | |
177 | u32 ref = read_pll_ref(dev, base); | |
178 | u32 clk = 0; | |
179 | int N1, N2, M1, M2; | |
180 | ||
181 | if (base == 0x004028 && (mast & 0x00100000)) { | |
182 | /* wtf, appears to only disable post-divider on nva0 */ | |
183 | if (dev_priv->chipset != 0xa0) | |
184 | return read_clk(dev, clk_src_dom6); | |
185 | } | |
f3fbaf34 BS |
186 | |
187 | N2 = (coef & 0xff000000) >> 24; | |
188 | M2 = (coef & 0x00ff0000) >> 16; | |
189 | N1 = (coef & 0x0000ff00) >> 8; | |
190 | M1 = (coef & 0x000000ff); | |
191 | if ((ctrl & 0x80000000) && M1) { | |
192 | clk = ref * N1 / M1; | |
193 | if ((ctrl & 0x40000100) == 0x40000000) { | |
194 | if (M2) | |
195 | clk = clk * N2 / M2; | |
196 | else | |
197 | clk = 0; | |
198 | } | |
199 | } | |
200 | ||
201 | return clk; | |
202 | } | |
203 | ||
204 | static u32 | |
205 | read_clk(struct drm_device *dev, enum clk_src src) | |
206 | { | |
207 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
208 | u32 mast = nv_rd32(dev, 0x00c040); | |
209 | u32 P = 0; | |
210 | ||
211 | switch (src) { | |
212 | case clk_src_crystal: | |
213 | return dev_priv->crystal; | |
214 | case clk_src_href: | |
215 | return 100000; /* PCIE reference clock */ | |
216 | case clk_src_hclk: | |
217 | return read_clk(dev, clk_src_href) * 27778 / 10000; | |
218 | case clk_src_hclkm3: | |
219 | return read_clk(dev, clk_src_hclk) * 3; | |
220 | case clk_src_hclkm3d2: | |
221 | return read_clk(dev, clk_src_hclk) * 3 / 2; | |
222 | case clk_src_host: | |
223 | switch (mast & 0x30000000) { | |
224 | case 0x00000000: return read_clk(dev, clk_src_href); | |
225 | case 0x10000000: break; | |
226 | case 0x20000000: /* !0x50 */ | |
227 | case 0x30000000: return read_clk(dev, clk_src_hclk); | |
228 | } | |
229 | break; | |
230 | case clk_src_nvclk: | |
231 | if (!(mast & 0x00100000)) | |
232 | P = (nv_rd32(dev, 0x004028) & 0x00070000) >> 16; | |
233 | switch (mast & 0x00000003) { | |
234 | case 0x00000000: return read_clk(dev, clk_src_crystal) >> P; | |
235 | case 0x00000001: return read_clk(dev, clk_src_dom6); | |
236 | case 0x00000002: return read_pll(dev, 0x004020) >> P; | |
237 | case 0x00000003: return read_pll(dev, 0x004028) >> P; | |
238 | } | |
239 | break; | |
240 | case clk_src_sclk: | |
241 | P = (nv_rd32(dev, 0x004020) & 0x00070000) >> 16; | |
242 | switch (mast & 0x00000030) { | |
243 | case 0x00000000: | |
244 | if (mast & 0x00000080) | |
245 | return read_clk(dev, clk_src_host) >> P; | |
246 | return read_clk(dev, clk_src_crystal) >> P; | |
247 | case 0x00000010: break; | |
248 | case 0x00000020: return read_pll(dev, 0x004028) >> P; | |
249 | case 0x00000030: return read_pll(dev, 0x004020) >> P; | |
250 | } | |
251 | break; | |
252 | case clk_src_mclk: | |
253 | P = (nv_rd32(dev, 0x004008) & 0x00070000) >> 16; | |
254 | if (nv_rd32(dev, 0x004008) & 0x00000200) { | |
255 | switch (mast & 0x0000c000) { | |
256 | case 0x00000000: | |
257 | return read_clk(dev, clk_src_crystal) >> P; | |
258 | case 0x00008000: | |
259 | case 0x0000c000: | |
260 | return read_clk(dev, clk_src_href) >> P; | |
261 | } | |
262 | } else { | |
263 | return read_pll(dev, 0x004008) >> P; | |
264 | } | |
265 | break; | |
266 | case clk_src_vdec: | |
267 | P = (read_div(dev) & 0x00000700) >> 8; | |
268 | switch (dev_priv->chipset) { | |
269 | case 0x84: | |
270 | case 0x86: | |
271 | case 0x92: | |
272 | case 0x94: | |
273 | case 0x96: | |
274 | case 0xa0: | |
275 | switch (mast & 0x00000c00) { | |
276 | case 0x00000000: | |
277 | if (dev_priv->chipset == 0xa0) /* wtf?? */ | |
278 | return read_clk(dev, clk_src_nvclk) >> P; | |
279 | return read_clk(dev, clk_src_crystal) >> P; | |
280 | case 0x00000400: | |
281 | return 0; | |
282 | case 0x00000800: | |
283 | if (mast & 0x01000000) | |
284 | return read_pll(dev, 0x004028) >> P; | |
285 | return read_pll(dev, 0x004030) >> P; | |
286 | case 0x00000c00: | |
287 | return read_clk(dev, clk_src_nvclk) >> P; | |
288 | } | |
289 | break; | |
290 | case 0x98: | |
291 | switch (mast & 0x00000c00) { | |
292 | case 0x00000000: | |
293 | return read_clk(dev, clk_src_nvclk) >> P; | |
294 | case 0x00000400: | |
295 | return 0; | |
296 | case 0x00000800: | |
297 | return read_clk(dev, clk_src_hclkm3d2) >> P; | |
298 | case 0x00000c00: | |
d4676461 | 299 | return read_clk(dev, clk_src_mclk) >> P; |
f3fbaf34 BS |
300 | } |
301 | break; | |
302 | } | |
303 | break; | |
304 | case clk_src_dom6: | |
305 | switch (dev_priv->chipset) { | |
306 | case 0x50: | |
307 | case 0xa0: | |
308 | return read_pll(dev, 0x00e810) >> 2; | |
309 | case 0x84: | |
310 | case 0x86: | |
311 | case 0x92: | |
312 | case 0x94: | |
313 | case 0x96: | |
314 | case 0x98: | |
315 | P = (read_div(dev) & 0x00000007) >> 0; | |
316 | switch (mast & 0x0c000000) { | |
317 | case 0x00000000: return read_clk(dev, clk_src_href); | |
318 | case 0x04000000: break; | |
319 | case 0x08000000: return read_clk(dev, clk_src_hclk); | |
320 | case 0x0c000000: | |
321 | return read_clk(dev, clk_src_hclkm3) >> P; | |
322 | } | |
323 | break; | |
324 | default: | |
325 | break; | |
326 | } | |
327 | default: | |
328 | break; | |
329 | } | |
330 | ||
331 | NV_DEBUG(dev, "unknown clock source %d 0x%08x\n", src, mast); | |
332 | return 0; | |
333 | } | |
334 | ||
02c30ca0 | 335 | int |
f3fbaf34 | 336 | nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) |
02c30ca0 | 337 | { |
f3fbaf34 BS |
338 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
339 | if (dev_priv->chipset == 0xaa || | |
340 | dev_priv->chipset == 0xac) | |
341 | return 0; | |
342 | ||
343 | perflvl->core = read_clk(dev, clk_src_nvclk); | |
344 | perflvl->shader = read_clk(dev, clk_src_sclk); | |
345 | perflvl->memory = read_clk(dev, clk_src_mclk); | |
346 | if (dev_priv->chipset != 0x50) { | |
347 | perflvl->vdec = read_clk(dev, clk_src_vdec); | |
348 | perflvl->dom6 = read_clk(dev, clk_src_dom6); | |
349 | } | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | struct nv50_pm_state { | |
eeb7a50b MP |
355 | struct hwsq_ucode mclk_hwsq; |
356 | u32 mscript; | |
357 | ||
f3fbaf34 BS |
358 | u32 emast; |
359 | u32 nctrl; | |
360 | u32 ncoef; | |
361 | u32 sctrl; | |
362 | u32 scoef; | |
363 | ||
364 | u32 amast; | |
365 | u32 pdivs; | |
f3fbaf34 BS |
366 | }; |
367 | ||
368 | static u32 | |
369 | calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll, | |
370 | u32 clk, int *N1, int *M1, int *log2P) | |
371 | { | |
372 | struct nouveau_pll_vals coef; | |
373 | int ret; | |
02c30ca0 | 374 | |
f3fbaf34 | 375 | ret = get_pll_limits(dev, reg, pll); |
02c30ca0 | 376 | if (ret) |
f3fbaf34 BS |
377 | return 0; |
378 | ||
379 | pll->vco2.maxfreq = 0; | |
380 | pll->refclk = read_pll_ref(dev, reg); | |
381 | if (!pll->refclk) | |
382 | return 0; | |
383 | ||
384 | ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef); | |
385 | if (ret == 0) | |
386 | return 0; | |
387 | ||
388 | *N1 = coef.N1; | |
389 | *M1 = coef.M1; | |
390 | *log2P = coef.log2P; | |
391 | return ret; | |
392 | } | |
393 | ||
394 | static inline u32 | |
395 | calc_div(u32 src, u32 target, int *div) | |
396 | { | |
397 | u32 clk0 = src, clk1 = src; | |
398 | for (*div = 0; *div <= 7; (*div)++) { | |
399 | if (clk0 <= target) { | |
400 | clk1 = clk0 << (*div ? 1 : 0); | |
401 | break; | |
619d4f7e | 402 | } |
f3fbaf34 | 403 | clk0 >>= 1; |
619d4f7e EV |
404 | } |
405 | ||
f3fbaf34 BS |
406 | if (target - clk0 <= clk1 - target) |
407 | return clk0; | |
408 | (*div)--; | |
409 | return clk1; | |
410 | } | |
02c30ca0 | 411 | |
f3fbaf34 BS |
412 | static inline u32 |
413 | clk_same(u32 a, u32 b) | |
414 | { | |
415 | return ((a / 1000) == (b / 1000)); | |
02c30ca0 BS |
416 | } |
417 | ||
eeb7a50b MP |
418 | static int |
419 | calc_mclk(struct drm_device *dev, u32 freq, struct hwsq_ucode *hwsq) | |
420 | { | |
421 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
422 | struct pll_lims pll; | |
423 | u32 mast = nv_rd32(dev, 0x00c040); | |
424 | u32 ctrl = nv_rd32(dev, 0x004008); | |
425 | u32 coef = nv_rd32(dev, 0x00400c); | |
426 | u32 orig = ctrl; | |
427 | u32 crtc_mask = 0; | |
428 | int N, M, P; | |
429 | int ret, i; | |
430 | ||
431 | /* use pcie refclock if possible, otherwise use mpll */ | |
432 | ctrl &= ~0x81ff0200; | |
433 | if (clk_same(freq, read_clk(dev, clk_src_href))) { | |
434 | ctrl |= 0x00000200 | (pll.log2p_bias << 19); | |
435 | } else { | |
436 | ret = calc_pll(dev, 0x4008, &pll, freq, &N, &M, &P); | |
437 | if (ret == 0) | |
438 | return -EINVAL; | |
439 | ||
440 | ctrl |= 0x80000000 | (P << 22) | (P << 16); | |
441 | ctrl |= pll.log2p_bias << 19; | |
442 | coef = (N << 8) | M; | |
443 | } | |
444 | ||
445 | mast &= ~0xc0000000; /* get MCLK_2 from HREF */ | |
446 | mast |= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */ | |
447 | ||
448 | /* determine active crtcs */ | |
449 | for (i = 0; i < 2; i++) { | |
450 | if (nv_rd32(dev, NV50_PDISPLAY_CRTC_C(i, CLOCK))) | |
451 | crtc_mask |= (1 << i); | |
452 | } | |
453 | ||
454 | /* build the ucode which will reclock the memory for us */ | |
455 | hwsq_init(hwsq); | |
456 | if (crtc_mask) { | |
457 | hwsq_op5f(hwsq, crtc_mask, 0x00); /* wait for scanout */ | |
458 | hwsq_op5f(hwsq, crtc_mask, 0x01); /* wait for vblank */ | |
459 | } | |
460 | if (dev_priv->chipset >= 0x92) | |
461 | hwsq_wr32(hwsq, 0x611200, 0x00003300); /* disable scanout */ | |
c8b9641a | 462 | hwsq_setf(hwsq, 0x10, 0); /* disable bus access */ |
eeb7a50b MP |
463 | hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */ |
464 | ||
465 | /* prepare memory controller */ | |
466 | hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */ | |
467 | hwsq_wr32(hwsq, 0x1002d0, 0x00000001); /* force refresh */ | |
468 | hwsq_wr32(hwsq, 0x100210, 0x00000000); /* stop the automatic refresh */ | |
469 | hwsq_wr32(hwsq, 0x1002dc, 0x00000001); /* start self refresh mode */ | |
470 | ||
471 | /* reclock memory */ | |
472 | hwsq_wr32(hwsq, 0xc040, mast); | |
473 | hwsq_wr32(hwsq, 0x4008, orig | 0x00000200); /* bypass MPLL */ | |
474 | hwsq_wr32(hwsq, 0x400c, coef); | |
475 | hwsq_wr32(hwsq, 0x4008, ctrl); | |
476 | ||
477 | /* restart memory controller */ | |
478 | hwsq_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge banks and idle */ | |
479 | hwsq_wr32(hwsq, 0x1002dc, 0x00000000); /* stop self refresh mode */ | |
480 | hwsq_wr32(hwsq, 0x100210, 0x80000000); /* restart automatic refresh */ | |
c8b9641a | 481 | hwsq_usec(hwsq, 12); /* wait for the PLL to stabilize */ |
eeb7a50b | 482 | |
c8b9641a BS |
483 | hwsq_usec(hwsq, 48); /* may be unnecessary: causes flickering */ |
484 | hwsq_setf(hwsq, 0x10, 1); /* enable bus access */ | |
eeb7a50b MP |
485 | hwsq_op5f(hwsq, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */ |
486 | if (dev_priv->chipset >= 0x92) | |
487 | hwsq_wr32(hwsq, 0x611200, 0x00003330); /* enable scanout */ | |
488 | hwsq_fini(hwsq); | |
489 | return 0; | |
490 | } | |
491 | ||
02c30ca0 | 492 | void * |
f3fbaf34 | 493 | nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) |
02c30ca0 | 494 | { |
f3fbaf34 BS |
495 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
496 | struct nv50_pm_state *info; | |
497 | struct pll_lims pll; | |
498 | int ret = -EINVAL; | |
499 | int N, M, P1, P2; | |
500 | u32 clk, out; | |
501 | ||
502 | if (dev_priv->chipset == 0xaa || | |
503 | dev_priv->chipset == 0xac) | |
504 | return ERR_PTR(-ENODEV); | |
02c30ca0 | 505 | |
f3fbaf34 BS |
506 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
507 | if (!info) | |
02c30ca0 | 508 | return ERR_PTR(-ENOMEM); |
02c30ca0 | 509 | |
f3fbaf34 BS |
510 | /* core: for the moment at least, always use nvpll */ |
511 | clk = calc_pll(dev, 0x4028, &pll, perflvl->core, &N, &M, &P1); | |
512 | if (clk == 0) | |
513 | goto error; | |
514 | ||
515 | info->emast = 0x00000003; | |
516 | info->nctrl = 0x80000000 | (P1 << 19) | (P1 << 16); | |
517 | info->ncoef = (N << 8) | M; | |
518 | ||
519 | /* shader: tie to nvclk if possible, otherwise use spll. have to be | |
520 | * very careful that the shader clock is at least twice the core, or | |
521 | * some chipsets will be very unhappy. i expect most or all of these | |
522 | * cases will be handled by tying to nvclk, but it's possible there's | |
523 | * corners | |
524 | */ | |
525 | if (P1-- && perflvl->shader == (perflvl->core << 1)) { | |
526 | info->emast |= 0x00000020; | |
527 | info->sctrl = 0x00000000 | (P1 << 19) | (P1 << 16); | |
528 | info->scoef = nv_rd32(dev, 0x004024); | |
529 | } else { | |
530 | clk = calc_pll(dev, 0x4020, &pll, perflvl->shader, &N, &M, &P1); | |
531 | if (clk == 0) | |
532 | goto error; | |
533 | ||
534 | info->emast |= 0x00000030; | |
535 | info->sctrl = 0x80000000 | (P1 << 19) | (P1 << 16); | |
536 | info->scoef = (N << 8) | M; | |
537 | } | |
538 | ||
eeb7a50b MP |
539 | /* memory: build hwsq ucode which we'll use to reclock memory */ |
540 | info->mclk_hwsq.len = 0; | |
f3fbaf34 | 541 | if (perflvl->memory) { |
eeb7a50b MP |
542 | clk = calc_mclk(dev, perflvl->memory, &info->mclk_hwsq); |
543 | if (clk < 0) { | |
544 | ret = clk; | |
f3fbaf34 | 545 | goto error; |
eeb7a50b | 546 | } |
f3fbaf34 | 547 | |
eeb7a50b | 548 | info->mscript = perflvl->memscript; |
f3fbaf34 BS |
549 | } |
550 | ||
551 | /* vdec: avoid modifying xpll until we know exactly how the other | |
552 | * clock domains work, i suspect at least some of them can also be | |
553 | * tied to xpll... | |
554 | */ | |
973e8616 BS |
555 | info->amast = nv_rd32(dev, 0x00c040); |
556 | info->pdivs = read_div(dev); | |
f3fbaf34 BS |
557 | if (perflvl->vdec) { |
558 | /* see how close we can get using nvclk as a source */ | |
559 | clk = calc_div(perflvl->core, perflvl->vdec, &P1); | |
560 | ||
561 | /* see how close we can get using xpll/hclk as a source */ | |
562 | if (dev_priv->chipset != 0x98) | |
563 | out = read_pll(dev, 0x004030); | |
564 | else | |
565 | out = read_clk(dev, clk_src_hclkm3d2); | |
566 | out = calc_div(out, perflvl->vdec, &P2); | |
567 | ||
568 | /* select whichever gets us closest */ | |
973e8616 BS |
569 | info->amast &= ~0x00000c00; |
570 | info->pdivs &= ~0x00000700; | |
f3fbaf34 BS |
571 | if (abs((int)perflvl->vdec - clk) <= |
572 | abs((int)perflvl->vdec - out)) { | |
573 | if (dev_priv->chipset != 0x98) | |
574 | info->amast |= 0x00000c00; | |
f3fbaf34 BS |
575 | info->pdivs |= P1 << 8; |
576 | } else { | |
577 | info->amast |= 0x00000800; | |
578 | info->pdivs |= P2 << 8; | |
579 | } | |
02c30ca0 BS |
580 | } |
581 | ||
f3fbaf34 BS |
582 | /* dom6: nfi what this is, but we're limited to various combinations |
583 | * of the host clock frequency | |
584 | */ | |
f3fbaf34 | 585 | if (perflvl->dom6) { |
973e8616 BS |
586 | info->amast &= ~0x0c000000; |
587 | if (clk_same(perflvl->dom6, read_clk(dev, clk_src_href))) { | |
588 | info->amast |= 0x00000000; | |
589 | } else | |
590 | if (clk_same(perflvl->dom6, read_clk(dev, clk_src_hclk))) { | |
591 | info->amast |= 0x08000000; | |
592 | } else { | |
593 | clk = read_clk(dev, clk_src_hclk) * 3; | |
594 | clk = calc_div(clk, perflvl->dom6, &P1); | |
f3fbaf34 | 595 | |
973e8616 BS |
596 | info->amast |= 0x0c000000; |
597 | info->pdivs = (info->pdivs & ~0x00000007) | P1; | |
598 | } | |
02c30ca0 BS |
599 | } |
600 | ||
f3fbaf34 BS |
601 | return info; |
602 | error: | |
603 | kfree(info); | |
604 | return ERR_PTR(ret); | |
02c30ca0 BS |
605 | } |
606 | ||
eeb7a50b MP |
607 | static int |
608 | prog_mclk(struct drm_device *dev, struct hwsq_ucode *hwsq) | |
609 | { | |
610 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
611 | u32 hwsq_data, hwsq_kick; | |
612 | int i; | |
613 | ||
614 | if (dev_priv->chipset < 0x90) { | |
615 | hwsq_data = 0x001400; | |
616 | hwsq_kick = 0x00000003; | |
617 | } else { | |
618 | hwsq_data = 0x080000; | |
619 | hwsq_kick = 0x00000001; | |
620 | } | |
621 | ||
622 | /* upload hwsq ucode */ | |
623 | nv_mask(dev, 0x001098, 0x00000008, 0x00000000); | |
624 | nv_wr32(dev, 0x001304, 0x00000000); | |
625 | for (i = 0; i < hwsq->len / 4; i++) | |
626 | nv_wr32(dev, hwsq_data + (i * 4), hwsq->ptr.u32[i]); | |
627 | nv_mask(dev, 0x001098, 0x00000018, 0x00000018); | |
628 | ||
629 | /* launch, and wait for completion */ | |
630 | nv_wr32(dev, 0x00130c, hwsq_kick); | |
631 | if (!nv_wait(dev, 0x001308, 0x00000100, 0x00000000)) { | |
632 | NV_ERROR(dev, "hwsq ucode exec timed out\n"); | |
633 | NV_ERROR(dev, "0x001308: 0x%08x\n", nv_rd32(dev, 0x001308)); | |
634 | for (i = 0; i < hwsq->len / 4; i++) { | |
635 | NV_ERROR(dev, "0x%06x: 0x%08x\n", 0x1400 + (i * 4), | |
636 | nv_rd32(dev, 0x001400 + (i * 4))); | |
637 | } | |
638 | ||
639 | return -EIO; | |
640 | } | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
f3fbaf34 BS |
645 | int |
646 | nv50_pm_clocks_set(struct drm_device *dev, void *data) | |
02c30ca0 | 647 | { |
f3fbaf34 BS |
648 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
649 | struct nv50_pm_state *info = data; | |
650 | struct bit_entry M; | |
651 | int ret = 0; | |
652 | ||
653 | /* halt and idle execution engines */ | |
654 | nv_mask(dev, 0x002504, 0x00000001, 0x00000001); | |
655 | if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) | |
656 | goto error; | |
aee582de | 657 | |
eeb7a50b MP |
658 | /* memory: it is *very* important we change this first, the ucode |
659 | * we build in pre() now has hardcoded 0xc040 values, which can't | |
660 | * change before we execute it or the engine clocks may end up | |
661 | * messed up. | |
662 | */ | |
663 | if (info->mclk_hwsq.len) { | |
664 | /* execute some scripts that do ??? from the vbios.. */ | |
665 | if (!bit_table(dev, 'M', &M) && M.version == 1) { | |
666 | if (M.length >= 6) | |
667 | nouveau_bios_init_exec(dev, ROM16(M.data[5])); | |
668 | if (M.length >= 8) | |
669 | nouveau_bios_init_exec(dev, ROM16(M.data[7])); | |
670 | if (M.length >= 10) | |
671 | nouveau_bios_init_exec(dev, ROM16(M.data[9])); | |
672 | nouveau_bios_init_exec(dev, info->mscript); | |
673 | } | |
674 | ||
675 | ret = prog_mclk(dev, &info->mclk_hwsq); | |
676 | if (ret) | |
677 | goto resume; | |
678 | } | |
679 | ||
f3fbaf34 BS |
680 | /* reclock vdec/dom6 */ |
681 | nv_mask(dev, 0x00c040, 0x00000c00, 0x00000000); | |
682 | switch (dev_priv->chipset) { | |
683 | case 0x92: | |
684 | case 0x94: | |
685 | case 0x96: | |
686 | nv_mask(dev, 0x004800, 0x00000707, info->pdivs); | |
687 | break; | |
688 | default: | |
689 | nv_mask(dev, 0x004700, 0x00000707, info->pdivs); | |
690 | break; | |
fade7ad5 | 691 | } |
f3fbaf34 BS |
692 | nv_mask(dev, 0x00c040, 0x0c000c00, info->amast); |
693 | ||
6805979f BS |
694 | /* core/shader: make sure sclk/nvclk are disconnected from their |
695 | * plls (nvclk to dom6, sclk to hclk), modify the plls, and | |
696 | * reconnect sclk/nvclk to their new clock source | |
697 | */ | |
698 | if (dev_priv->chipset < 0x92) | |
f3fbaf34 BS |
699 | nv_mask(dev, 0x00c040, 0x001000b0, 0x00100080); /* grrr! */ |
700 | else | |
701 | nv_mask(dev, 0x00c040, 0x000000b3, 0x00000081); | |
702 | nv_mask(dev, 0x004020, 0xc03f0100, info->sctrl); | |
703 | nv_wr32(dev, 0x004024, info->scoef); | |
704 | nv_mask(dev, 0x004028, 0xc03f0100, info->nctrl); | |
705 | nv_wr32(dev, 0x00402c, info->ncoef); | |
706 | nv_mask(dev, 0x00c040, 0x00100033, info->emast); | |
fade7ad5 | 707 | |
f3fbaf34 BS |
708 | goto resume; |
709 | error: | |
710 | ret = -EBUSY; | |
711 | resume: | |
712 | nv_mask(dev, 0x002504, 0x00000001, 0x00000000); | |
19fa224f | 713 | kfree(info); |
f3fbaf34 | 714 | return ret; |
02c30ca0 BS |
715 | } |
716 | ||
cb9fa626 | 717 | static int |
675aac03 | 718 | pwm_info(struct drm_device *dev, int *line, int *ctrl, int *indx) |
cb9fa626 | 719 | { |
675aac03 | 720 | if (*line == 0x04) { |
5a4267ab BS |
721 | *ctrl = 0x00e100; |
722 | *line = 4; | |
723 | *indx = 0; | |
724 | } else | |
675aac03 | 725 | if (*line == 0x09) { |
5a4267ab BS |
726 | *ctrl = 0x00e100; |
727 | *line = 9; | |
728 | *indx = 1; | |
729 | } else | |
675aac03 | 730 | if (*line == 0x10) { |
5a4267ab BS |
731 | *ctrl = 0x00e28c; |
732 | *line = 0; | |
733 | *indx = 0; | |
734 | } else { | |
675aac03 | 735 | NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", *line); |
5a4267ab | 736 | return -ENODEV; |
cb9fa626 BS |
737 | } |
738 | ||
5a4267ab | 739 | return 0; |
cb9fa626 BS |
740 | } |
741 | ||
742 | int | |
675aac03 | 743 | nv50_pm_pwm_get(struct drm_device *dev, int line, u32 *divs, u32 *duty) |
cb9fa626 | 744 | { |
675aac03 | 745 | int ctrl, id, ret = pwm_info(dev, &line, &ctrl, &id); |
cb9fa626 BS |
746 | if (ret) |
747 | return ret; | |
748 | ||
5a4267ab BS |
749 | if (nv_rd32(dev, ctrl) & (1 << line)) { |
750 | *divs = nv_rd32(dev, 0x00e114 + (id * 8)); | |
751 | *duty = nv_rd32(dev, 0x00e118 + (id * 8)); | |
cb9fa626 BS |
752 | return 0; |
753 | } | |
754 | ||
5a4267ab | 755 | return -EINVAL; |
cb9fa626 BS |
756 | } |
757 | ||
758 | int | |
675aac03 | 759 | nv50_pm_pwm_set(struct drm_device *dev, int line, u32 divs, u32 duty) |
cb9fa626 | 760 | { |
675aac03 | 761 | int ctrl, id, ret = pwm_info(dev, &line, &ctrl, &id); |
cb9fa626 BS |
762 | if (ret) |
763 | return ret; | |
764 | ||
5a4267ab BS |
765 | nv_mask(dev, ctrl, 0x00010001 << line, 0x00000001 << line); |
766 | nv_wr32(dev, 0x00e114 + (id * 8), divs); | |
767 | nv_wr32(dev, 0x00e118 + (id * 8), duty | 0x80000000); | |
cb9fa626 BS |
768 | return 0; |
769 | } |