UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nv50_gpio.c
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45284162
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1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
6c06d608 25#include <linux/dmi.h>
760285e7 26#include <drm/drmP.h>
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27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
a0b25635 29#include "nouveau_gpio.h"
45284162 30
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31#include "nv50_display.h"
32
45284162 33static int
a0b25635 34nv50_gpio_location(int line, u32 *reg, u32 *shift)
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35{
36 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
37
a0b25635 38 if (line >= 32)
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39 return -EINVAL;
40
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41 *reg = nv50_gpio_reg[line >> 3];
42 *shift = (line & 7) << 2;
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43 return 0;
44}
45
46int
a0b25635 47nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out)
45284162 48{
a0b25635 49 u32 reg, shift;
45284162 50
a0b25635 51 if (nv50_gpio_location(line, &reg, &shift))
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52 return -EINVAL;
53
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54 nv_mask(dev, reg, 7 << shift, (((dir ^ 1) << 1) | out) << shift);
55 return 0;
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56}
57
58int
a0b25635 59nv50_gpio_sense(struct drm_device *dev, int line)
45284162 60{
a0b25635 61 u32 reg, shift;
45284162 62
a0b25635 63 if (nv50_gpio_location(line, &reg, &shift))
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64 return -EINVAL;
65
a0b25635 66 return !!(nv_rd32(dev, reg) & (4 << shift));
45284162 67}
d0875edd 68
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69void
70nv50_gpio_irq_enable(struct drm_device *dev, int line, bool on)
d7f8172c 71{
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72 u32 reg = line < 16 ? 0xe050 : 0xe070;
73 u32 mask = 0x00010001 << (line & 0xf);
d7f8172c 74
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75 nv_wr32(dev, reg + 4, mask);
76 nv_mask(dev, reg + 0, mask, on ? mask : 0);
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77}
78
79int
a0b25635 80nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out)
d7f8172c 81{
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82 u32 data = ((dir ^ 1) << 13) | (out << 12);
83 nv_mask(dev, 0x00d610 + (line * 4), 0x00003000, data);
84 nv_mask(dev, 0x00d604, 0x00000001, 0x00000001); /* update? */
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85 return 0;
86}
87
fce2bad0 88int
a0b25635 89nvd0_gpio_sense(struct drm_device *dev, int line)
fce2bad0 90{
a0b25635 91 return !!(nv_rd32(dev, 0x00d610 + (line * 4)) & 0x00004000);
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92}
93
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94static void
95nv50_gpio_isr(struct drm_device *dev)
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96{
97 struct drm_nouveau_private *dev_priv = dev->dev_private;
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98 u32 intr0, intr1 = 0;
99 u32 hi, lo;
fce2bad0 100
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101 intr0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
102 if (dev_priv->chipset >= 0x90)
103 intr1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
fce2bad0 104
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105 hi = (intr0 & 0x0000ffff) | (intr1 << 16);
106 lo = (intr0 >> 16) | (intr1 & 0xffff0000);
107 nouveau_gpio_isr(dev, 0, hi | lo);
fce2bad0 108
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109 nv_wr32(dev, 0xe054, intr0);
110 if (dev_priv->chipset >= 0x90)
111 nv_wr32(dev, 0xe074, intr1);
d0875edd 112}
ee2e0131 113
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114static struct dmi_system_id gpio_reset_ids[] = {
115 {
116 .ident = "Apple Macbook 10,1",
117 .matches = {
118 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
119 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro10,1"),
120 }
121 },
122 { }
123};
124
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125int
126nv50_gpio_init(struct drm_device *dev)
127{
128 struct drm_nouveau_private *dev_priv = dev->dev_private;
129
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130 /* initialise gpios and routing to vbios defaults */
131 if (dmi_check_system(gpio_reset_ids))
132 nouveau_gpio_reset(dev);
133
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134 /* disable, and ack any pending gpio interrupts */
135 nv_wr32(dev, 0xe050, 0x00000000);
136 nv_wr32(dev, 0xe054, 0xffffffff);
137 if (dev_priv->chipset >= 0x90) {
138 nv_wr32(dev, 0xe070, 0x00000000);
139 nv_wr32(dev, 0xe074, 0xffffffff);
140 }
141
2cbd4c81 142 nouveau_irq_register(dev, 21, nv50_gpio_isr);
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143 return 0;
144}
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145
146void
147nv50_gpio_fini(struct drm_device *dev)
148{
149 struct drm_nouveau_private *dev_priv = dev->dev_private;
150
151 nv_wr32(dev, 0xe050, 0x00000000);
152 if (dev_priv->chipset >= 0x90)
153 nv_wr32(dev, 0xe070, 0x00000000);
154 nouveau_irq_unregister(dev, 21);
2cbd4c81 155}