[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nv50_evo.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"

#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_ramht.h"

static void
nv50_evo_channel_del(struct nouveau_channel **pevo)
{
	struct drm_nouveau_private *dev_priv;
	struct nouveau_channel *evo = *pevo;

	if (!evo)
		return;
	*pevo = NULL;

	dev_priv = evo->dev->dev_private;
	dev_priv->evo_alloc &= ~(1 << evo->id);

	nouveau_gpuobj_channel_takedown(evo);
	nouveau_bo_unmap(evo->pushbuf_bo);
	nouveau_bo_ref(NULL, &evo->pushbuf_bo);

	if (evo->user)
		iounmap(evo->user);

	kfree(evo);
}

int
nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
		    u32 tile_flags, u32 magic_flags, u32 offset, u32 limit)
{
	struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
	struct drm_device *dev = evo->dev;
	struct nouveau_gpuobj *obj = NULL;
	int ret;

	ret = nouveau_gpuobj_new(dev, dev_priv->evo, 6*4, 32, 0, &obj);
	if (ret)
		return ret;
	obj->engine = NVOBJ_ENGINE_DISPLAY;

	nv_wo32(obj,  0, (tile_flags << 22) | (magic_flags << 16) | class);
	nv_wo32(obj,  4, limit);
	nv_wo32(obj,  8, offset);
	nv_wo32(obj, 12, 0x00000000);
	nv_wo32(obj, 16, 0x00000000);
	if (dev_priv->card_type < NV_C0)
		nv_wo32(obj, 20, 0x00010000);
	else
		nv_wo32(obj, 20, 0x00020000);
	dev_priv->engine.instmem.flush(dev);

	ret = nouveau_ramht_insert(evo, name, obj);
	nouveau_gpuobj_ref(NULL, &obj);
	if (ret) {
		return ret;
	}

	return 0;
}

static int
nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_channel *evo;
	int ret;

	evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
	if (!evo)
		return -ENOMEM;
	*pevo = evo;

	for (evo->id = 0; evo->id < 5; evo->id++) {
		if (dev_priv->evo_alloc & (1 << evo->id))
			continue;

		dev_priv->evo_alloc |= (1 << evo->id);
		break;
	}

	if (evo->id == 5) {
		kfree(evo);
		return -ENODEV;
	}

	evo->dev = dev;
	evo->user_get = 4;
	evo->user_put = 0;

	ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
			     false, true, &evo->pushbuf_bo);
	if (ret == 0)
		ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
	if (ret) {
		NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
		nv50_evo_channel_del(pevo);
		return ret;
	}

	ret = nouveau_bo_map(evo->pushbuf_bo);
	if (ret) {
		NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
		nv50_evo_channel_del(pevo);
		return ret;
	}

	evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
			    NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
	if (!evo->user) {
		NV_ERROR(dev, "Error mapping EVO control regs.\n");
		nv50_evo_channel_del(pevo);
		return -ENOMEM;
	}

	/* bind primary evo channel's ramht to the channel */
	if (dev_priv->evo && evo != dev_priv->evo)
		nouveau_ramht_ref(dev_priv->evo->ramht, &evo->ramht, NULL);

	return 0;
}

static int
nv50_evo_channel_init(struct nouveau_channel *evo)
{
	struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
	struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
	struct drm_device *dev = evo->dev;
	int id = evo->id, ret, i;
	u64 start;
	u32 tmp;

	/* taken from nv bug #12637, attempts to un-wedge the hw if it's
	 * stuck in some unspecified state
	 */
	start = ptimer->read(dev);
	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x2b00);
	while ((tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))) & 0x1e0000) {
		if ((tmp & 0x9f0000) == 0x20000)
			nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x800000);

		if ((tmp & 0x3f0000) == 0x30000)
			nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x200000);

		if (ptimer->read(dev) - start > 1000000000ULL) {
			NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
			NV_ERROR(dev, "0x610200 = 0x%08x\n", tmp);
			return -EBUSY;
		}
	}

	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x1000b03);
	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id),
		     0x40000000, 0x40000000)) {
		NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
		NV_ERROR(dev, "0x610200 = 0x%08x\n",
			  nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
		return -EBUSY;
	}

	/* initialise fifo */
	nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id),
		((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) |
		NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
		NV50_PDISPLAY_EVO_DMA_CB_VALID);
	nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
	nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
		NV_ERROR(dev, "0x610200 = 0x%08x\n",
			 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
		return -EBUSY;
	}
	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id),
		(nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)) & ~0x00000003) |
		 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
	nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0);
	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
		     NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);

	/* enable error reporting on the channel */
	nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);

	evo->dma.max = (4096/4) - 2;
	evo->dma.put = 0;
	evo->dma.cur = evo->dma.put;
	evo->dma.free = evo->dma.max - evo->dma.cur;

	ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
	if (ret)
		return ret;

	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
		OUT_RING(evo, 0);

	return 0;
}

static void
nv50_evo_channel_fini(struct nouveau_channel *evo)
{
	struct drm_device *dev = evo->dev;

	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0);
	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0x1e0000, 0)) {
		NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
		NV_ERROR(dev, "0x610200 = 0x%08x\n",
			  nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id)));
	}
}

static int
nv50_evo_create(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *ramht = NULL;
	struct nouveau_channel *evo;
	int ret;

	/* create primary evo channel, the one we use for modesetting
	 * purporses
	 */
	ret = nv50_evo_channel_new(dev, &dev_priv->evo);
	if (ret)
		return ret;
	evo = dev_priv->evo;

	/* setup object management on it, any other evo channel will
	 * use this also as there's no per-channel support on the
	 * hardware
	 */
	ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
				 NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
	if (ret) {
		NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
		nv50_evo_channel_del(&dev_priv->evo);
		return ret;
	}

	ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
	if (ret) {
		NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
		nv50_evo_channel_del(&dev_priv->evo);
		return ret;
	}

	ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
	if (ret) {
		NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
		nv50_evo_channel_del(&dev_priv->evo);
		return ret;
	}

	ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
	nouveau_gpuobj_ref(NULL, &ramht);
	if (ret) {
		nv50_evo_channel_del(&dev_priv->evo);
		return ret;
	}

	/* create some default objects for the scanout memtypes we support */
	if (dev_priv->chipset != 0x50) {
		ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
					  0, 0xffffffff);
		if (ret) {
			nv50_evo_channel_del(&dev_priv->evo);
			return ret;
		}


		ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
					  0, 0xffffffff);
		if (ret) {
			nv50_evo_channel_del(&dev_priv->evo);
			return ret;
		}
	}

	ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
				  0, dev_priv->vram_size);
	if (ret) {
		nv50_evo_channel_del(&dev_priv->evo);
		return ret;
	}

	return 0;
}

int
nv50_evo_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int ret;

	if (!dev_priv->evo) {
		ret = nv50_evo_create(dev);
		if (ret)
			return ret;
	}

	return nv50_evo_channel_init(dev_priv->evo);
}

void
nv50_evo_fini(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (dev_priv->evo) {
		nv50_evo_channel_fini(dev_priv->evo);
		nv50_evo_channel_del(&dev_priv->evo);
	}
}
Commit	Line	Data
b7bc613a BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
	26
	27	#include "nouveau_drv.h"
	28	#include "nouveau_dma.h"
	29	#include "nouveau_ramht.h"
	30
	31	static void
1e96268a	32	nv50_evo_channel_del(struct nouveau_channel **pevo)
b7bc613a	33	{
1e96268a BS	34	struct drm_nouveau_private *dev_priv;
1e96268a BS	35	struct nouveau_channel evo = pevo;
b7bc613a	36
1e96268a	37	if (!evo)
b7bc613a	38	return;
1e96268a	39	*pevo = NULL;
b7bc613a	40
1e96268a BS	41	dev_priv = evo->dev->dev_private;
1e96268a BS	42	dev_priv->evo_alloc &= ~(1 << evo->id);
b7bc613a	43
1e96268a BS	44	nouveau_gpuobj_channel_takedown(evo);
	45	nouveau_bo_unmap(evo->pushbuf_bo);
	46	nouveau_bo_ref(NULL, &evo->pushbuf_bo);
b7bc613a	47
1e96268a BS	48	if (evo->user)
	49	iounmap(evo->user);
	50
	51	kfree(evo);
b7bc613a BS	52	}
	53
	54	int
	55	nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
	56	u32 tile_flags, u32 magic_flags, u32 offset, u32 limit)
	57	{
	58	struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
	59	struct drm_device *dev = evo->dev;
	60	struct nouveau_gpuobj *obj = NULL;
	61	int ret;
	62
1e96268a	63	ret = nouveau_gpuobj_new(dev, dev_priv->evo, 6*4, 32, 0, &obj);
b7bc613a BS	64	if (ret)
	65	return ret;
	66	obj->engine = NVOBJ_ENGINE_DISPLAY;
	67
	68	nv_wo32(obj, 0, (tile_flags << 22) \| (magic_flags << 16) \| class);
	69	nv_wo32(obj, 4, limit);
	70	nv_wo32(obj, 8, offset);
	71	nv_wo32(obj, 12, 0x00000000);
	72	nv_wo32(obj, 16, 0x00000000);
	73	if (dev_priv->card_type < NV_C0)
	74	nv_wo32(obj, 20, 0x00010000);
	75	else
	76	nv_wo32(obj, 20, 0x00020000);
	77	dev_priv->engine.instmem.flush(dev);
	78
	79	ret = nouveau_ramht_insert(evo, name, obj);
	80	nouveau_gpuobj_ref(NULL, &obj);
	81	if (ret) {
	82	return ret;
	83	}
	84
	85	return 0;
	86	}
	87
	88	static int
1e96268a	89	nv50_evo_channel_new(struct drm_device dev, struct nouveau_channel *pevo)
b7bc613a BS	90	{
b7bc613a BS	91	struct drm_nouveau_private *dev_priv = dev->dev_private;
1e96268a	92	struct nouveau_channel *evo;
b7bc613a BS	93	int ret;
b7bc613a BS	94
1e96268a BS	95	evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
1e96268a BS	96	if (!evo)
b7bc613a	97	return -ENOMEM;
1e96268a	98	*pevo = evo;
b7bc613a	99
1e96268a BS	100	for (evo->id = 0; evo->id < 5; evo->id++) {
	101	if (dev_priv->evo_alloc & (1 << evo->id))
	102	continue;
b7bc613a	103
1e96268a BS	104	dev_priv->evo_alloc \|= (1 << evo->id);
1e96268a BS	105	break;
b7bc613a BS	106	}
b7bc613a BS	107
1e96268a BS	108	if (evo->id == 5) {
	109	kfree(evo);
	110	return -ENODEV;
b7bc613a BS	111	}
b7bc613a BS	112
1e96268a BS	113	evo->dev = dev;
	114	evo->user_get = 4;
	115	evo->user_put = 0;
b7bc613a BS	116
b7bc613a BS	117	ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
1e96268a	118	false, true, &evo->pushbuf_bo);
b7bc613a	119	if (ret == 0)
1e96268a	120	ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
b7bc613a BS	121	if (ret) {
b7bc613a BS	122	NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
1e96268a	123	nv50_evo_channel_del(pevo);
b7bc613a BS	124	return ret;
	125	}
	126
1e96268a	127	ret = nouveau_bo_map(evo->pushbuf_bo);
b7bc613a BS	128	if (ret) {
b7bc613a BS	129	NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
1e96268a	130	nv50_evo_channel_del(pevo);
b7bc613a BS	131	return ret;
	132	}
	133
1e96268a BS	134	evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
	135	NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
	136	if (!evo->user) {
b7bc613a	137	NV_ERROR(dev, "Error mapping EVO control regs.\n");
1e96268a	138	nv50_evo_channel_del(pevo);
b7bc613a BS	139	return -ENOMEM;
	140	}
	141
1e96268a BS	142	/* bind primary evo channel's ramht to the channel */
	143	if (dev_priv->evo && evo != dev_priv->evo)
	144	nouveau_ramht_ref(dev_priv->evo->ramht, &evo->ramht, NULL);
	145
b7bc613a BS	146	return 0;
	147	}
	148
	149	static int
	150	nv50_evo_channel_init(struct nouveau_channel *evo)
	151	{
	152	struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
	153	struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
	154	struct drm_device *dev = evo->dev;
1e96268a	155	int id = evo->id, ret, i;
b7bc613a BS	156	u64 start;
	157	u32 tmp;
	158
	159	/* taken from nv bug #12637, attempts to un-wedge the hw if it's
	160	* stuck in some unspecified state
	161	*/
	162	start = ptimer->read(dev);
1e96268a BS	163	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x2b00);
1e96268a BS	164	while ((tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))) & 0x1e0000) {
b7bc613a	165	if ((tmp & 0x9f0000) == 0x20000)
1e96268a	166	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp \| 0x800000);
b7bc613a BS	167
b7bc613a BS	168	if ((tmp & 0x3f0000) == 0x30000)
1e96268a	169	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp \| 0x200000);
b7bc613a BS	170
	171	if (ptimer->read(dev) - start > 1000000000ULL) {
	172	NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
	173	NV_ERROR(dev, "0x610200 = 0x%08x\n", tmp);
	174	return -EBUSY;
	175	}
	176	}
	177
1e96268a BS	178	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x1000b03);
1e96268a BS	179	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id),
b7bc613a BS	180	0x40000000, 0x40000000)) {
	181	NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
	182	NV_ERROR(dev, "0x610200 = 0x%08x\n",
1e96268a	183	nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
b7bc613a BS	184	return -EBUSY;
	185	}
	186
	187	/* initialise fifo */
1e96268a	188	nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id),
b7bc613a BS	189	((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) \|
	190	NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM \|
	191	NV50_PDISPLAY_EVO_DMA_CB_VALID);
1e96268a BS	192	nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
	193	nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
	194	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
b7bc613a	195	NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
1e96268a BS	196	NV_ERROR(dev, "0x610200 = 0x%08x\n",
1e96268a BS	197	nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
b7bc613a BS	198	return -EBUSY;
b7bc613a BS	199	}
1e96268a BS	200	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id),
1e96268a BS	201	(nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)) & ~0x00000003) \|
b7bc613a	202	NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
1e96268a BS	203	nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0);
	204	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 \|
	205	NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
b7bc613a BS	206
b7bc613a BS	207	/* enable error reporting on the channel */
1e96268a	208	nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
b7bc613a BS	209
	210	evo->dma.max = (4096/4) - 2;
	211	evo->dma.put = 0;
	212	evo->dma.cur = evo->dma.put;
	213	evo->dma.free = evo->dma.max - evo->dma.cur;
	214
	215	ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
	216	if (ret)
	217	return ret;
	218
	219	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
	220	OUT_RING(evo, 0);
	221
	222	return 0;
	223	}
	224
	225	static void
	226	nv50_evo_channel_fini(struct nouveau_channel *evo)
	227	{
	228	struct drm_device *dev = evo->dev;
	229
1e96268a BS	230	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0);
1e96268a BS	231	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(evo->id), 0x1e0000, 0)) {
b7bc613a BS	232	NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
b7bc613a BS	233	NV_ERROR(dev, "0x610200 = 0x%08x\n",
1e96268a BS	234	nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(evo->id)));
	235	}
	236	}
	237
	238	static int
	239	nv50_evo_create(struct drm_device *dev)
	240	{
	241	struct drm_nouveau_private *dev_priv = dev->dev_private;
	242	struct nouveau_gpuobj *ramht = NULL;
	243	struct nouveau_channel *evo;
	244	int ret;
	245
	246	/* create primary evo channel, the one we use for modesetting
	247	* purporses
	248	*/
	249	ret = nv50_evo_channel_new(dev, &dev_priv->evo);
	250	if (ret)
	251	return ret;
	252	evo = dev_priv->evo;
	253
	254	/* setup object management on it, any other evo channel will
	255	* use this also as there's no per-channel support on the
	256	* hardware
	257	*/
	258	ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
	259	NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
	260	if (ret) {
	261	NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
	262	nv50_evo_channel_del(&dev_priv->evo);
	263	return ret;
	264	}
	265
	266	ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
	267	if (ret) {
	268	NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
	269	nv50_evo_channel_del(&dev_priv->evo);
	270	return ret;
	271	}
	272
	273	ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
	274	if (ret) {
	275	NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
	276	nv50_evo_channel_del(&dev_priv->evo);
	277	return ret;
	278	}
	279
	280	ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
	281	nouveau_gpuobj_ref(NULL, &ramht);
	282	if (ret) {
	283	nv50_evo_channel_del(&dev_priv->evo);
	284	return ret;
	285	}
	286
	287	/* create some default objects for the scanout memtypes we support */
	288	if (dev_priv->chipset != 0x50) {
	289	ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
	290	0, 0xffffffff);
	291	if (ret) {
	292	nv50_evo_channel_del(&dev_priv->evo);
	293	return ret;
	294	}
	295
	296
	297	ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
298	0, 0xffffffff);
299	if (ret) {
300	nv50_evo_channel_del(&dev_priv->evo);
301	return ret;
302	}
303	}
304
305	ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
306	0, dev_priv->vram_size);
307	if (ret) {
308	nv50_evo_channel_del(&dev_priv->evo);
309	return ret;
b7bc613a	310	}
1e96268a BS	311
1e96268a BS	312	return 0;
b7bc613a BS	313	}
	314
	315	int
	316	nv50_evo_init(struct drm_device *dev)
	317	{
	318	struct drm_nouveau_private *dev_priv = dev->dev_private;
	319	int ret;
	320
	321	if (!dev_priv->evo) {
1e96268a	322	ret = nv50_evo_create(dev);
b7bc613a BS	323	if (ret)
	324	return ret;
	325	}
	326
	327	return nv50_evo_channel_init(dev_priv->evo);
	328	}
	329
	330	void
	331	nv50_evo_fini(struct drm_device *dev)
	332	{
	333	struct drm_nouveau_private *dev_priv = dev->dev_private;
	334
	335	if (dev_priv->evo) {
	336	nv50_evo_channel_fini(dev_priv->evo);
	337	nv50_evo_channel_del(&dev_priv->evo);
	338	}
	339	}