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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2008 Maarten Maathuis. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include "drmP.h" | |
28 | #include "drm_mode.h" | |
29 | #include "drm_crtc_helper.h" | |
30 | ||
31 | #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) | |
32 | #include "nouveau_reg.h" | |
33 | #include "nouveau_drv.h" | |
34 | #include "nouveau_hw.h" | |
35 | #include "nouveau_encoder.h" | |
36 | #include "nouveau_crtc.h" | |
37 | #include "nouveau_fb.h" | |
38 | #include "nouveau_connector.h" | |
39 | #include "nv50_display.h" | |
40 | ||
41 | static void | |
42 | nv50_crtc_lut_load(struct drm_crtc *crtc) | |
43 | { | |
44 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
45 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
46 | int i; | |
47 | ||
ef2bb506 | 48 | NV_DEBUG_KMS(crtc->dev, "\n"); |
6ee73861 BS |
49 | |
50 | for (i = 0; i < 256; i++) { | |
51 | writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0); | |
52 | writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2); | |
53 | writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4); | |
54 | } | |
55 | ||
56 | if (nv_crtc->lut.depth == 30) { | |
57 | writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0); | |
58 | writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2); | |
59 | writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4); | |
60 | } | |
61 | } | |
62 | ||
63 | int | |
64 | nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked) | |
65 | { | |
66 | struct drm_device *dev = nv_crtc->base.dev; | |
67 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
59c0f578 | 68 | struct nouveau_channel *evo = nv50_display(dev)->master; |
6ee73861 BS |
69 | int index = nv_crtc->index, ret; |
70 | ||
ef2bb506 MM |
71 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
72 | NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked"); | |
6ee73861 BS |
73 | |
74 | if (blanked) { | |
75 | nv_crtc->cursor.hide(nv_crtc, false); | |
76 | ||
77 | ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5); | |
78 | if (ret) { | |
79 | NV_ERROR(dev, "no space while blanking crtc\n"); | |
80 | return ret; | |
81 | } | |
82 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); | |
83 | OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK); | |
84 | OUT_RING(evo, 0); | |
85 | if (dev_priv->chipset != 0x50) { | |
86 | BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); | |
87 | OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE); | |
88 | } | |
89 | ||
90 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); | |
91 | OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE); | |
92 | } else { | |
93 | if (nv_crtc->cursor.visible) | |
94 | nv_crtc->cursor.show(nv_crtc, false); | |
95 | else | |
96 | nv_crtc->cursor.hide(nv_crtc, false); | |
97 | ||
98 | ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8); | |
99 | if (ret) { | |
100 | NV_ERROR(dev, "no space while unblanking crtc\n"); | |
101 | return ret; | |
102 | } | |
103 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); | |
104 | OUT_RING(evo, nv_crtc->lut.depth == 8 ? | |
105 | NV50_EVO_CRTC_CLUT_MODE_OFF : | |
106 | NV50_EVO_CRTC_CLUT_MODE_ON); | |
180cc306 | 107 | OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8); |
6ee73861 BS |
108 | if (dev_priv->chipset != 0x50) { |
109 | BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); | |
110 | OUT_RING(evo, NvEvoVRAM); | |
111 | } | |
112 | ||
113 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2); | |
114 | OUT_RING(evo, nv_crtc->fb.offset >> 8); | |
115 | OUT_RING(evo, 0); | |
116 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); | |
117 | if (dev_priv->chipset != 0x50) | |
6d86951a BS |
118 | if (nv_crtc->fb.tile_flags == 0x7a00 || |
119 | nv_crtc->fb.tile_flags == 0xfe00) | |
6ee73861 BS |
120 | OUT_RING(evo, NvEvoFB32); |
121 | else | |
122 | if (nv_crtc->fb.tile_flags == 0x7000) | |
123 | OUT_RING(evo, NvEvoFB16); | |
124 | else | |
6d86951a | 125 | OUT_RING(evo, NvEvoVRAM_LP); |
6ee73861 | 126 | else |
6d86951a | 127 | OUT_RING(evo, NvEvoVRAM_LP); |
6ee73861 BS |
128 | } |
129 | ||
130 | nv_crtc->fb.blanked = blanked; | |
131 | return 0; | |
132 | } | |
133 | ||
134 | static int | |
488ff207 | 135 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
6ee73861 | 136 | { |
de691855 BS |
137 | struct nouveau_channel *evo = nv50_display(nv_crtc->base.dev)->master; |
138 | struct nouveau_connector *nv_connector; | |
139 | struct drm_connector *connector; | |
140 | int head = nv_crtc->index, ret; | |
141 | u32 mode = 0x00; | |
142 | ||
143 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
144 | connector = &nv_connector->base; | |
145 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { | |
146 | if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3) | |
147 | mode = DITHERING_MODE_DYNAMIC2X2; | |
148 | } else { | |
149 | mode = nv_connector->dithering_mode; | |
6ee73861 BS |
150 | } |
151 | ||
de691855 BS |
152 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { |
153 | if (connector->display_info.bpc >= 8) | |
154 | mode |= DITHERING_DEPTH_8BPC; | |
155 | } else { | |
156 | mode |= nv_connector->dithering_depth; | |
157 | } | |
6ee73861 | 158 | |
de691855 BS |
159 | ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); |
160 | if (ret == 0) { | |
161 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(head, DITHER_CTRL), 1); | |
162 | OUT_RING (evo, mode); | |
163 | if (update) { | |
164 | BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); | |
165 | OUT_RING (evo, 0); | |
166 | FIRE_RING (evo); | |
167 | } | |
6ee73861 BS |
168 | } |
169 | ||
de691855 | 170 | return ret; |
6ee73861 BS |
171 | } |
172 | ||
173 | struct nouveau_connector * | |
174 | nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc) | |
175 | { | |
176 | struct drm_device *dev = nv_crtc->base.dev; | |
177 | struct drm_connector *connector; | |
178 | struct drm_crtc *crtc = to_drm_crtc(nv_crtc); | |
179 | ||
180 | /* The safest approach is to find an encoder with the right crtc, that | |
181 | * is also linked to a connector. */ | |
182 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
183 | if (connector->encoder) | |
184 | if (connector->encoder->crtc == crtc) | |
185 | return nouveau_connector(connector); | |
186 | } | |
187 | ||
188 | return NULL; | |
189 | } | |
190 | ||
191 | static int | |
488ff207 | 192 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
6ee73861 | 193 | { |
b29caa58 | 194 | struct nouveau_connector *nv_connector; |
549cd872 BS |
195 | struct drm_crtc *crtc = &nv_crtc->base; |
196 | struct drm_device *dev = crtc->dev; | |
59c0f578 | 197 | struct nouveau_channel *evo = nv50_display(dev)->master; |
549cd872 | 198 | struct drm_display_mode *mode = &crtc->mode; |
488ff207 | 199 | int scaling_mode, ret; |
b29caa58 | 200 | u32 ctrl = 0, oX, oY; |
6ee73861 | 201 | |
ef2bb506 | 202 | NV_DEBUG_KMS(dev, "\n"); |
6ee73861 | 203 | |
b29caa58 BS |
204 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
205 | if (!nv_connector || !nv_connector->native_mode) { | |
206 | NV_ERROR(dev, "no native mode, forcing panel scaling\n"); | |
207 | scaling_mode = DRM_MODE_SCALE_NONE; | |
488ff207 BS |
208 | } else { |
209 | scaling_mode = nv_connector->scaling_mode; | |
b29caa58 BS |
210 | } |
211 | ||
212 | /* start off at the resolution we programmed the crtc for, this | |
213 | * effectively handles NONE/FULL scaling | |
214 | */ | |
215 | if (scaling_mode != DRM_MODE_SCALE_NONE) { | |
216 | oX = nv_connector->native_mode->hdisplay; | |
217 | oY = nv_connector->native_mode->vdisplay; | |
218 | } else { | |
219 | oX = mode->hdisplay; | |
220 | oY = mode->vdisplay; | |
221 | } | |
222 | ||
223 | /* add overscan compensation if necessary, will keep the aspect | |
224 | * ratio the same as the backend mode unless overridden by the | |
225 | * user setting both hborder and vborder properties. | |
226 | */ | |
227 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || | |
228 | (nv_connector->underscan == UNDERSCAN_AUTO && | |
229 | nv_connector->edid && | |
230 | drm_detect_hdmi_monitor(nv_connector->edid)))) { | |
231 | u32 bX = nv_connector->underscan_hborder; | |
232 | u32 bY = nv_connector->underscan_vborder; | |
233 | u32 aspect = (oY << 19) / oX; | |
234 | ||
235 | if (bX) { | |
236 | oX -= (bX * 2); | |
237 | if (bY) oY -= (bY * 2); | |
238 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
6ee73861 | 239 | } else { |
b29caa58 BS |
240 | oX -= (oX >> 4) + 32; |
241 | if (bY) oY -= (bY * 2); | |
242 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
6ee73861 | 243 | } |
6ee73861 BS |
244 | } |
245 | ||
b29caa58 BS |
246 | /* handle CENTER/ASPECT scaling, taking into account the areas |
247 | * removed already for overscan compensation | |
248 | */ | |
6ee73861 | 249 | switch (scaling_mode) { |
b29caa58 BS |
250 | case DRM_MODE_SCALE_CENTER: |
251 | oX = min((u32)mode->hdisplay, oX); | |
252 | oY = min((u32)mode->vdisplay, oY); | |
253 | /* fall-through */ | |
6ee73861 | 254 | case DRM_MODE_SCALE_ASPECT: |
b29caa58 BS |
255 | if (oY < oX) { |
256 | u32 aspect = (mode->hdisplay << 19) / mode->vdisplay; | |
257 | oX = ((oY * aspect) + (aspect / 2)) >> 19; | |
6ee73861 | 258 | } else { |
b29caa58 BS |
259 | u32 aspect = (mode->vdisplay << 19) / mode->hdisplay; |
260 | oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
6ee73861 BS |
261 | } |
262 | break; | |
6ee73861 | 263 | default: |
6ee73861 BS |
264 | break; |
265 | } | |
266 | ||
b29caa58 BS |
267 | if (mode->hdisplay != oX || mode->vdisplay != oY || |
268 | mode->flags & DRM_MODE_FLAG_INTERLACE || | |
269 | mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
270 | ctrl |= NV50_EVO_CRTC_SCALE_CTRL_ACTIVE; | |
271 | ||
549cd872 | 272 | ret = RING_SPACE(evo, 5); |
6ee73861 BS |
273 | if (ret) |
274 | return ret; | |
275 | ||
6ee73861 | 276 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1); |
b29caa58 | 277 | OUT_RING (evo, ctrl); |
6ee73861 | 278 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2); |
b29caa58 BS |
279 | OUT_RING (evo, oY << 16 | oX); |
280 | OUT_RING (evo, oY << 16 | oX); | |
6ee73861 BS |
281 | |
282 | if (update) { | |
549cd872 | 283 | nv50_display_flip_stop(crtc); |
e6e039d1 | 284 | nv50_display_sync(dev); |
549cd872 | 285 | nv50_display_flip_next(crtc, crtc->fb, NULL); |
6ee73861 BS |
286 | } |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | int | |
292 | nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) | |
293 | { | |
1ac7b528 | 294 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
e9ebb68b | 295 | struct pll_lims pll; |
5b32165b | 296 | uint32_t reg1, reg2; |
e9ebb68b | 297 | int ret, N1, M1, N2, M2, P; |
6ee73861 | 298 | |
5b32165b | 299 | ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll); |
6ee73861 BS |
300 | if (ret) |
301 | return ret; | |
302 | ||
e9ebb68b BS |
303 | if (pll.vco2.maxfreq) { |
304 | ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P); | |
305 | if (ret <= 0) | |
306 | return 0; | |
6ee73861 | 307 | |
17b96cc3 | 308 | NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n", |
e9ebb68b BS |
309 | pclk, ret, N1, M1, N2, M2, P); |
310 | ||
5b32165b BS |
311 | reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00; |
312 | reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00; | |
313 | nv_wr32(dev, pll.reg + 0, 0x10000611); | |
314 | nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1); | |
315 | nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2); | |
1ac7b528 BS |
316 | } else |
317 | if (dev_priv->chipset < NV_C0) { | |
52eba8dd | 318 | ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P); |
e9ebb68b BS |
319 | if (ret <= 0) |
320 | return 0; | |
321 | ||
322 | NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n", | |
323 | pclk, ret, N1, N2, M1, P); | |
17b96cc3 | 324 | |
5b32165b BS |
325 | reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000; |
326 | nv_wr32(dev, pll.reg + 0, 0x50000610); | |
327 | nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1); | |
328 | nv_wr32(dev, pll.reg + 8, N2); | |
1ac7b528 | 329 | } else { |
52eba8dd | 330 | ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P); |
1ac7b528 BS |
331 | if (ret <= 0) |
332 | return 0; | |
333 | ||
334 | NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n", | |
335 | pclk, ret, N1, N2, M1, P); | |
336 | ||
5b32165b BS |
337 | nv_mask(dev, pll.reg + 0x0c, 0x00000000, 0x00000100); |
338 | nv_wr32(dev, pll.reg + 0x04, (P << 16) | (N1 << 8) | M1); | |
339 | nv_wr32(dev, pll.reg + 0x10, N2 << 16); | |
6ee73861 BS |
340 | } |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
345 | static void | |
346 | nv50_crtc_destroy(struct drm_crtc *crtc) | |
347 | { | |
dd19e44b MS |
348 | struct drm_device *dev; |
349 | struct nouveau_crtc *nv_crtc; | |
6ee73861 BS |
350 | |
351 | if (!crtc) | |
352 | return; | |
353 | ||
dd19e44b MS |
354 | dev = crtc->dev; |
355 | nv_crtc = nouveau_crtc(crtc); | |
356 | ||
357 | NV_DEBUG_KMS(dev, "\n"); | |
358 | ||
6ee73861 BS |
359 | drm_crtc_cleanup(&nv_crtc->base); |
360 | ||
9d59e8a1 | 361 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
6ee73861 | 362 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
9d59e8a1 | 363 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
6ee73861 | 364 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
6ee73861 BS |
365 | kfree(nv_crtc); |
366 | } | |
367 | ||
368 | int | |
369 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, | |
370 | uint32_t buffer_handle, uint32_t width, uint32_t height) | |
371 | { | |
372 | struct drm_device *dev = crtc->dev; | |
6ee73861 BS |
373 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
374 | struct nouveau_bo *cursor = NULL; | |
375 | struct drm_gem_object *gem; | |
376 | int ret = 0, i; | |
377 | ||
6ee73861 BS |
378 | if (!buffer_handle) { |
379 | nv_crtc->cursor.hide(nv_crtc, true); | |
380 | return 0; | |
381 | } | |
382 | ||
b4fa9d0f MS |
383 | if (width != 64 || height != 64) |
384 | return -EINVAL; | |
385 | ||
6ee73861 BS |
386 | gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); |
387 | if (!gem) | |
bf79cb91 | 388 | return -ENOENT; |
6ee73861 BS |
389 | cursor = nouveau_gem_object(gem); |
390 | ||
391 | ret = nouveau_bo_map(cursor); | |
392 | if (ret) | |
393 | goto out; | |
394 | ||
395 | /* The simple will do for now. */ | |
396 | for (i = 0; i < 64 * 64; i++) | |
397 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i)); | |
398 | ||
399 | nouveau_bo_unmap(cursor); | |
400 | ||
180cc306 | 401 | nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset); |
6ee73861 BS |
402 | nv_crtc->cursor.show(nv_crtc, true); |
403 | ||
404 | out: | |
bc9025bd | 405 | drm_gem_object_unreference_unlocked(gem); |
6ee73861 BS |
406 | return ret; |
407 | } | |
408 | ||
409 | int | |
410 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
411 | { | |
412 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
413 | ||
414 | nv_crtc->cursor.set_pos(nv_crtc, x, y); | |
415 | return 0; | |
416 | } | |
417 | ||
418 | static void | |
419 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, | |
7203425a | 420 | uint32_t start, uint32_t size) |
6ee73861 | 421 | { |
7203425a | 422 | int end = (start + size > 256) ? 256 : start + size, i; |
6ee73861 | 423 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
6ee73861 | 424 | |
7203425a | 425 | for (i = start; i < end; i++) { |
6ee73861 BS |
426 | nv_crtc->lut.r[i] = r[i]; |
427 | nv_crtc->lut.g[i] = g[i]; | |
428 | nv_crtc->lut.b[i] = b[i]; | |
429 | } | |
430 | ||
431 | /* We need to know the depth before we upload, but it's possible to | |
432 | * get called before a framebuffer is bound. If this is the case, | |
433 | * mark the lut values as dirty by setting depth==0, and it'll be | |
434 | * uploaded on the first mode_set_base() | |
435 | */ | |
436 | if (!nv_crtc->base.fb) { | |
437 | nv_crtc->lut.depth = 0; | |
438 | return; | |
439 | } | |
440 | ||
441 | nv50_crtc_lut_load(crtc); | |
442 | } | |
443 | ||
444 | static void | |
445 | nv50_crtc_save(struct drm_crtc *crtc) | |
446 | { | |
447 | NV_ERROR(crtc->dev, "!!\n"); | |
448 | } | |
449 | ||
450 | static void | |
451 | nv50_crtc_restore(struct drm_crtc *crtc) | |
452 | { | |
453 | NV_ERROR(crtc->dev, "!!\n"); | |
454 | } | |
455 | ||
456 | static const struct drm_crtc_funcs nv50_crtc_funcs = { | |
457 | .save = nv50_crtc_save, | |
458 | .restore = nv50_crtc_restore, | |
459 | .cursor_set = nv50_crtc_cursor_set, | |
460 | .cursor_move = nv50_crtc_cursor_move, | |
461 | .gamma_set = nv50_crtc_gamma_set, | |
462 | .set_config = drm_crtc_helper_set_config, | |
332b242f | 463 | .page_flip = nouveau_crtc_page_flip, |
6ee73861 BS |
464 | .destroy = nv50_crtc_destroy, |
465 | }; | |
466 | ||
467 | static void | |
468 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) | |
469 | { | |
470 | } | |
471 | ||
472 | static void | |
473 | nv50_crtc_prepare(struct drm_crtc *crtc) | |
474 | { | |
475 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
476 | struct drm_device *dev = crtc->dev; | |
6ee73861 | 477 | |
ef2bb506 | 478 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 | 479 | |
1d3fac0c | 480 | nv50_display_flip_stop(crtc); |
1c180fa5 | 481 | drm_vblank_pre_modeset(dev, nv_crtc->index); |
6ee73861 BS |
482 | nv50_crtc_blank(nv_crtc, true); |
483 | } | |
484 | ||
485 | static void | |
486 | nv50_crtc_commit(struct drm_crtc *crtc) | |
487 | { | |
6ee73861 | 488 | struct drm_device *dev = crtc->dev; |
6ee73861 | 489 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
6ee73861 | 490 | |
ef2bb506 | 491 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 BS |
492 | |
493 | nv50_crtc_blank(nv_crtc, false); | |
1c180fa5 | 494 | drm_vblank_post_modeset(dev, nv_crtc->index); |
e6e039d1 | 495 | nv50_display_sync(dev); |
1d3fac0c | 496 | nv50_display_flip_next(crtc, crtc->fb, NULL); |
6ee73861 BS |
497 | } |
498 | ||
499 | static bool | |
500 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
501 | struct drm_display_mode *adjusted_mode) | |
502 | { | |
503 | return true; | |
504 | } | |
505 | ||
506 | static int | |
be64c2bb CB |
507 | nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, |
508 | struct drm_framebuffer *passed_fb, | |
60f60bf1 | 509 | int x, int y, bool atomic) |
6ee73861 BS |
510 | { |
511 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
512 | struct drm_device *dev = nv_crtc->base.dev; | |
513 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
59c0f578 | 514 | struct nouveau_channel *evo = nv50_display(dev)->master; |
ffbc559b EV |
515 | struct drm_framebuffer *drm_fb; |
516 | struct nouveau_framebuffer *fb; | |
45c4e0aa | 517 | int ret; |
6ee73861 | 518 | |
ef2bb506 | 519 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 | 520 | |
ffbc559b EV |
521 | /* no fb bound */ |
522 | if (!atomic && !crtc->fb) { | |
523 | NV_DEBUG_KMS(dev, "No FB bound\n"); | |
524 | return 0; | |
525 | } | |
526 | ||
be64c2bb CB |
527 | /* If atomic, we want to switch to the fb we were passed, so |
528 | * now we update pointers to do that. (We don't pin; just | |
529 | * assume we're already pinned and update the base address.) | |
530 | */ | |
531 | if (atomic) { | |
532 | drm_fb = passed_fb; | |
533 | fb = nouveau_framebuffer(passed_fb); | |
f9ec8f6c | 534 | } else { |
ffbc559b EV |
535 | drm_fb = crtc->fb; |
536 | fb = nouveau_framebuffer(crtc->fb); | |
be64c2bb CB |
537 | /* If not atomic, we can go ahead and pin, and unpin the |
538 | * old fb we were passed. | |
539 | */ | |
540 | ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM); | |
541 | if (ret) | |
542 | return ret; | |
543 | ||
544 | if (passed_fb) { | |
545 | struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb); | |
546 | nouveau_bo_unpin(ofb->nvbo); | |
547 | } | |
548 | } | |
549 | ||
180cc306 | 550 | nv_crtc->fb.offset = fb->nvbo->bo.offset; |
f13b3263 | 551 | nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo); |
6ee73861 BS |
552 | nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8; |
553 | if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) { | |
554 | ret = RING_SPACE(evo, 2); | |
555 | if (ret) | |
556 | return ret; | |
557 | ||
558 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1); | |
45c4e0aa | 559 | OUT_RING (evo, fb->r_dma); |
6ee73861 BS |
560 | } |
561 | ||
562 | ret = RING_SPACE(evo, 12); | |
563 | if (ret) | |
564 | return ret; | |
565 | ||
566 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5); | |
45c4e0aa BS |
567 | OUT_RING (evo, nv_crtc->fb.offset >> 8); |
568 | OUT_RING (evo, 0); | |
569 | OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width); | |
570 | OUT_RING (evo, fb->r_pitch); | |
571 | OUT_RING (evo, fb->r_format); | |
6ee73861 BS |
572 | |
573 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1); | |
45c4e0aa BS |
574 | OUT_RING (evo, fb->base.depth == 8 ? |
575 | NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON); | |
6ee73861 BS |
576 | |
577 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1); | |
45c4e0aa | 578 | OUT_RING (evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR); |
6ee73861 | 579 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1); |
45c4e0aa | 580 | OUT_RING (evo, (y << 16) | x); |
6ee73861 BS |
581 | |
582 | if (nv_crtc->lut.depth != fb->base.depth) { | |
583 | nv_crtc->lut.depth = fb->base.depth; | |
584 | nv50_crtc_lut_load(crtc); | |
585 | } | |
586 | ||
6ee73861 BS |
587 | return 0; |
588 | } | |
589 | ||
590 | static int | |
591 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
592 | struct drm_display_mode *adjusted_mode, int x, int y, | |
593 | struct drm_framebuffer *old_fb) | |
594 | { | |
595 | struct drm_device *dev = crtc->dev; | |
59c0f578 | 596 | struct nouveau_channel *evo = nv50_display(dev)->master; |
6ee73861 BS |
597 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
598 | struct nouveau_connector *nv_connector = NULL; | |
599 | uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end; | |
600 | uint32_t hunk1, vunk1, vunk2a, vunk2b; | |
601 | int ret; | |
602 | ||
603 | /* Find the connector attached to this CRTC */ | |
604 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
605 | ||
ef2bb506 | 606 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 BS |
607 | |
608 | hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start; | |
609 | vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
610 | hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
611 | vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
612 | /* I can't give this a proper name, anyone else can? */ | |
613 | hunk1 = adjusted_mode->htotal - | |
614 | adjusted_mode->hsync_start + adjusted_mode->hdisplay; | |
615 | vunk1 = adjusted_mode->vtotal - | |
616 | adjusted_mode->vsync_start + adjusted_mode->vdisplay; | |
617 | /* Another strange value, this time only for interlaced adjusted_modes. */ | |
618 | vunk2a = 2 * adjusted_mode->vtotal - | |
619 | adjusted_mode->vsync_start + adjusted_mode->vdisplay; | |
620 | vunk2b = adjusted_mode->vtotal - | |
621 | adjusted_mode->vsync_start + adjusted_mode->vtotal; | |
622 | ||
623 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
624 | vsync_dur /= 2; | |
625 | vsync_start_to_end /= 2; | |
626 | vunk1 /= 2; | |
627 | vunk2a /= 2; | |
628 | vunk2b /= 2; | |
629 | /* magic */ | |
630 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
631 | vsync_start_to_end -= 1; | |
632 | vunk1 -= 1; | |
633 | vunk2a -= 1; | |
634 | vunk2b -= 1; | |
635 | } | |
636 | } | |
637 | ||
b98e3f5c | 638 | ret = RING_SPACE(evo, 19); |
6ee73861 BS |
639 | if (ret) |
640 | return ret; | |
641 | ||
642 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2); | |
643 | OUT_RING(evo, adjusted_mode->clock | 0x800000); | |
644 | OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0); | |
645 | ||
646 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5); | |
647 | OUT_RING(evo, 0); | |
648 | OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal); | |
649 | OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1)); | |
650 | OUT_RING(evo, (vsync_start_to_end - 1) << 16 | | |
651 | (hsync_start_to_end - 1)); | |
652 | OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1)); | |
653 | ||
654 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
655 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1); | |
656 | OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1)); | |
657 | } else { | |
658 | OUT_RING(evo, 0); | |
659 | OUT_RING(evo, 0); | |
660 | } | |
661 | ||
662 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1); | |
b98e3f5c BS |
663 | OUT_RING (evo, 0); |
664 | /* required to make display sync channel not hate life */ | |
665 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK900), 1); | |
666 | OUT_RING (evo, 0x00000311); | |
6ee73861 BS |
667 | |
668 | /* This is the actual resolution of the mode. */ | |
669 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1); | |
670 | OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay); | |
671 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1); | |
672 | OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0)); | |
673 | ||
488ff207 BS |
674 | nv_crtc->set_dither(nv_crtc, false); |
675 | nv_crtc->set_scale(nv_crtc, false); | |
6ee73861 | 676 | |
60f60bf1 | 677 | return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false); |
6ee73861 BS |
678 | } |
679 | ||
680 | static int | |
681 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
682 | struct drm_framebuffer *old_fb) | |
683 | { | |
60f60bf1 BS |
684 | int ret; |
685 | ||
1d3fac0c | 686 | nv50_display_flip_stop(crtc); |
60f60bf1 BS |
687 | ret = nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false); |
688 | if (ret) | |
689 | return ret; | |
690 | ||
e6e039d1 | 691 | ret = nv50_display_sync(crtc->dev); |
1d3fac0c BS |
692 | if (ret) |
693 | return ret; | |
694 | ||
695 | return nv50_display_flip_next(crtc, crtc->fb, NULL); | |
be64c2bb CB |
696 | } |
697 | ||
698 | static int | |
699 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, | |
700 | struct drm_framebuffer *fb, | |
21c74a8e | 701 | int x, int y, enum mode_set_atomic state) |
be64c2bb | 702 | { |
60f60bf1 BS |
703 | int ret; |
704 | ||
1d3fac0c | 705 | nv50_display_flip_stop(crtc); |
60f60bf1 BS |
706 | ret = nv50_crtc_do_mode_set_base(crtc, fb, x, y, true); |
707 | if (ret) | |
708 | return ret; | |
709 | ||
e6e039d1 | 710 | return nv50_display_sync(crtc->dev); |
6ee73861 BS |
711 | } |
712 | ||
713 | static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = { | |
714 | .dpms = nv50_crtc_dpms, | |
715 | .prepare = nv50_crtc_prepare, | |
716 | .commit = nv50_crtc_commit, | |
717 | .mode_fixup = nv50_crtc_mode_fixup, | |
718 | .mode_set = nv50_crtc_mode_set, | |
719 | .mode_set_base = nv50_crtc_mode_set_base, | |
be64c2bb | 720 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, |
6ee73861 BS |
721 | .load_lut = nv50_crtc_lut_load, |
722 | }; | |
723 | ||
724 | int | |
725 | nv50_crtc_create(struct drm_device *dev, int index) | |
726 | { | |
727 | struct nouveau_crtc *nv_crtc = NULL; | |
728 | int ret, i; | |
729 | ||
ef2bb506 | 730 | NV_DEBUG_KMS(dev, "\n"); |
6ee73861 BS |
731 | |
732 | nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); | |
733 | if (!nv_crtc) | |
734 | return -ENOMEM; | |
735 | ||
6ee73861 BS |
736 | /* Default CLUT parameters, will be activated on the hw upon |
737 | * first mode set. | |
738 | */ | |
739 | for (i = 0; i < 256; i++) { | |
740 | nv_crtc->lut.r[i] = i << 8; | |
741 | nv_crtc->lut.g[i] = i << 8; | |
742 | nv_crtc->lut.b[i] = i << 8; | |
743 | } | |
744 | nv_crtc->lut.depth = 0; | |
745 | ||
7375c95b | 746 | ret = nouveau_bo_new(dev, 4096, 0x100, TTM_PL_FLAG_VRAM, |
d550c41e | 747 | 0, 0x0000, &nv_crtc->lut.nvbo); |
6ee73861 BS |
748 | if (!ret) { |
749 | ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM); | |
750 | if (!ret) | |
751 | ret = nouveau_bo_map(nv_crtc->lut.nvbo); | |
752 | if (ret) | |
753 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); | |
754 | } | |
755 | ||
756 | if (ret) { | |
6ee73861 BS |
757 | kfree(nv_crtc); |
758 | return ret; | |
759 | } | |
760 | ||
761 | nv_crtc->index = index; | |
762 | ||
763 | /* set function pointers */ | |
764 | nv_crtc->set_dither = nv50_crtc_set_dither; | |
765 | nv_crtc->set_scale = nv50_crtc_set_scale; | |
766 | ||
767 | drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs); | |
768 | drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs); | |
769 | drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); | |
770 | ||
7375c95b | 771 | ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, |
d550c41e | 772 | 0, 0x0000, &nv_crtc->cursor.nvbo); |
6ee73861 BS |
773 | if (!ret) { |
774 | ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); | |
775 | if (!ret) | |
776 | ret = nouveau_bo_map(nv_crtc->cursor.nvbo); | |
777 | if (ret) | |
778 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); | |
779 | } | |
780 | ||
781 | nv50_cursor_init(nv_crtc); | |
782 | return 0; | |
783 | } |