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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2008 Maarten Maathuis. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include "drmP.h" | |
28 | #include "drm_mode.h" | |
29 | #include "drm_crtc_helper.h" | |
30 | ||
31 | #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) | |
32 | #include "nouveau_reg.h" | |
33 | #include "nouveau_drv.h" | |
34 | #include "nouveau_hw.h" | |
35 | #include "nouveau_encoder.h" | |
36 | #include "nouveau_crtc.h" | |
37 | #include "nouveau_fb.h" | |
38 | #include "nouveau_connector.h" | |
39 | #include "nv50_display.h" | |
40 | ||
41 | static void | |
42 | nv50_crtc_lut_load(struct drm_crtc *crtc) | |
43 | { | |
44 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
45 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
46 | int i; | |
47 | ||
ef2bb506 | 48 | NV_DEBUG_KMS(crtc->dev, "\n"); |
6ee73861 BS |
49 | |
50 | for (i = 0; i < 256; i++) { | |
51 | writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0); | |
52 | writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2); | |
53 | writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4); | |
54 | } | |
55 | ||
56 | if (nv_crtc->lut.depth == 30) { | |
57 | writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0); | |
58 | writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2); | |
59 | writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4); | |
60 | } | |
61 | } | |
62 | ||
63 | int | |
64 | nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked) | |
65 | { | |
66 | struct drm_device *dev = nv_crtc->base.dev; | |
67 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
59c0f578 | 68 | struct nouveau_channel *evo = nv50_display(dev)->master; |
6ee73861 BS |
69 | int index = nv_crtc->index, ret; |
70 | ||
ef2bb506 MM |
71 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
72 | NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked"); | |
6ee73861 BS |
73 | |
74 | if (blanked) { | |
75 | nv_crtc->cursor.hide(nv_crtc, false); | |
76 | ||
77 | ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5); | |
78 | if (ret) { | |
79 | NV_ERROR(dev, "no space while blanking crtc\n"); | |
80 | return ret; | |
81 | } | |
82 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); | |
83 | OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK); | |
84 | OUT_RING(evo, 0); | |
85 | if (dev_priv->chipset != 0x50) { | |
86 | BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); | |
87 | OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE); | |
88 | } | |
89 | ||
90 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); | |
91 | OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE); | |
92 | } else { | |
93 | if (nv_crtc->cursor.visible) | |
94 | nv_crtc->cursor.show(nv_crtc, false); | |
95 | else | |
96 | nv_crtc->cursor.hide(nv_crtc, false); | |
97 | ||
98 | ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8); | |
99 | if (ret) { | |
100 | NV_ERROR(dev, "no space while unblanking crtc\n"); | |
101 | return ret; | |
102 | } | |
103 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); | |
104 | OUT_RING(evo, nv_crtc->lut.depth == 8 ? | |
105 | NV50_EVO_CRTC_CLUT_MODE_OFF : | |
106 | NV50_EVO_CRTC_CLUT_MODE_ON); | |
180cc306 | 107 | OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8); |
6ee73861 BS |
108 | if (dev_priv->chipset != 0x50) { |
109 | BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); | |
110 | OUT_RING(evo, NvEvoVRAM); | |
111 | } | |
112 | ||
113 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2); | |
114 | OUT_RING(evo, nv_crtc->fb.offset >> 8); | |
115 | OUT_RING(evo, 0); | |
116 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); | |
117 | if (dev_priv->chipset != 0x50) | |
6d86951a BS |
118 | if (nv_crtc->fb.tile_flags == 0x7a00 || |
119 | nv_crtc->fb.tile_flags == 0xfe00) | |
6ee73861 BS |
120 | OUT_RING(evo, NvEvoFB32); |
121 | else | |
122 | if (nv_crtc->fb.tile_flags == 0x7000) | |
123 | OUT_RING(evo, NvEvoFB16); | |
124 | else | |
6d86951a | 125 | OUT_RING(evo, NvEvoVRAM_LP); |
6ee73861 | 126 | else |
6d86951a | 127 | OUT_RING(evo, NvEvoVRAM_LP); |
6ee73861 BS |
128 | } |
129 | ||
130 | nv_crtc->fb.blanked = blanked; | |
131 | return 0; | |
132 | } | |
133 | ||
134 | static int | |
135 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update) | |
136 | { | |
137 | struct drm_device *dev = nv_crtc->base.dev; | |
59c0f578 | 138 | struct nouveau_channel *evo = nv50_display(dev)->master; |
6ee73861 BS |
139 | int ret; |
140 | ||
ef2bb506 | 141 | NV_DEBUG_KMS(dev, "\n"); |
6ee73861 BS |
142 | |
143 | ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); | |
144 | if (ret) { | |
145 | NV_ERROR(dev, "no space while setting dither\n"); | |
146 | return ret; | |
147 | } | |
148 | ||
149 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1); | |
150 | if (on) | |
151 | OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_ON); | |
152 | else | |
153 | OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_OFF); | |
154 | ||
155 | if (update) { | |
156 | BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); | |
157 | OUT_RING(evo, 0); | |
158 | FIRE_RING(evo); | |
159 | } | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
164 | struct nouveau_connector * | |
165 | nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc) | |
166 | { | |
167 | struct drm_device *dev = nv_crtc->base.dev; | |
168 | struct drm_connector *connector; | |
169 | struct drm_crtc *crtc = to_drm_crtc(nv_crtc); | |
170 | ||
171 | /* The safest approach is to find an encoder with the right crtc, that | |
172 | * is also linked to a connector. */ | |
173 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
174 | if (connector->encoder) | |
175 | if (connector->encoder->crtc == crtc) | |
176 | return nouveau_connector(connector); | |
177 | } | |
178 | ||
179 | return NULL; | |
180 | } | |
181 | ||
182 | static int | |
183 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update) | |
184 | { | |
b29caa58 | 185 | struct nouveau_connector *nv_connector; |
549cd872 BS |
186 | struct drm_crtc *crtc = &nv_crtc->base; |
187 | struct drm_device *dev = crtc->dev; | |
59c0f578 | 188 | struct nouveau_channel *evo = nv50_display(dev)->master; |
549cd872 | 189 | struct drm_display_mode *mode = &crtc->mode; |
b29caa58 | 190 | u32 ctrl = 0, oX, oY; |
6ee73861 BS |
191 | int ret; |
192 | ||
ef2bb506 | 193 | NV_DEBUG_KMS(dev, "\n"); |
6ee73861 | 194 | |
b29caa58 BS |
195 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
196 | if (!nv_connector || !nv_connector->native_mode) { | |
197 | NV_ERROR(dev, "no native mode, forcing panel scaling\n"); | |
198 | scaling_mode = DRM_MODE_SCALE_NONE; | |
199 | } | |
200 | ||
201 | /* start off at the resolution we programmed the crtc for, this | |
202 | * effectively handles NONE/FULL scaling | |
203 | */ | |
204 | if (scaling_mode != DRM_MODE_SCALE_NONE) { | |
205 | oX = nv_connector->native_mode->hdisplay; | |
206 | oY = nv_connector->native_mode->vdisplay; | |
207 | } else { | |
208 | oX = mode->hdisplay; | |
209 | oY = mode->vdisplay; | |
210 | } | |
211 | ||
212 | /* add overscan compensation if necessary, will keep the aspect | |
213 | * ratio the same as the backend mode unless overridden by the | |
214 | * user setting both hborder and vborder properties. | |
215 | */ | |
216 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || | |
217 | (nv_connector->underscan == UNDERSCAN_AUTO && | |
218 | nv_connector->edid && | |
219 | drm_detect_hdmi_monitor(nv_connector->edid)))) { | |
220 | u32 bX = nv_connector->underscan_hborder; | |
221 | u32 bY = nv_connector->underscan_vborder; | |
222 | u32 aspect = (oY << 19) / oX; | |
223 | ||
224 | if (bX) { | |
225 | oX -= (bX * 2); | |
226 | if (bY) oY -= (bY * 2); | |
227 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
6ee73861 | 228 | } else { |
b29caa58 BS |
229 | oX -= (oX >> 4) + 32; |
230 | if (bY) oY -= (bY * 2); | |
231 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
6ee73861 | 232 | } |
6ee73861 BS |
233 | } |
234 | ||
b29caa58 BS |
235 | /* handle CENTER/ASPECT scaling, taking into account the areas |
236 | * removed already for overscan compensation | |
237 | */ | |
6ee73861 | 238 | switch (scaling_mode) { |
b29caa58 BS |
239 | case DRM_MODE_SCALE_CENTER: |
240 | oX = min((u32)mode->hdisplay, oX); | |
241 | oY = min((u32)mode->vdisplay, oY); | |
242 | /* fall-through */ | |
6ee73861 | 243 | case DRM_MODE_SCALE_ASPECT: |
b29caa58 BS |
244 | if (oY < oX) { |
245 | u32 aspect = (mode->hdisplay << 19) / mode->vdisplay; | |
246 | oX = ((oY * aspect) + (aspect / 2)) >> 19; | |
6ee73861 | 247 | } else { |
b29caa58 BS |
248 | u32 aspect = (mode->vdisplay << 19) / mode->hdisplay; |
249 | oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
6ee73861 BS |
250 | } |
251 | break; | |
6ee73861 | 252 | default: |
6ee73861 BS |
253 | break; |
254 | } | |
255 | ||
b29caa58 BS |
256 | if (mode->hdisplay != oX || mode->vdisplay != oY || |
257 | mode->flags & DRM_MODE_FLAG_INTERLACE || | |
258 | mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
259 | ctrl |= NV50_EVO_CRTC_SCALE_CTRL_ACTIVE; | |
260 | ||
549cd872 | 261 | ret = RING_SPACE(evo, 5); |
6ee73861 BS |
262 | if (ret) |
263 | return ret; | |
264 | ||
6ee73861 | 265 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1); |
b29caa58 | 266 | OUT_RING (evo, ctrl); |
6ee73861 | 267 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2); |
b29caa58 BS |
268 | OUT_RING (evo, oY << 16 | oX); |
269 | OUT_RING (evo, oY << 16 | oX); | |
6ee73861 BS |
270 | |
271 | if (update) { | |
549cd872 | 272 | nv50_display_flip_stop(crtc); |
e6e039d1 | 273 | nv50_display_sync(dev); |
549cd872 | 274 | nv50_display_flip_next(crtc, crtc->fb, NULL); |
6ee73861 BS |
275 | } |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | int | |
281 | nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) | |
282 | { | |
1ac7b528 | 283 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
e9ebb68b | 284 | struct pll_lims pll; |
5b32165b | 285 | uint32_t reg1, reg2; |
e9ebb68b | 286 | int ret, N1, M1, N2, M2, P; |
6ee73861 | 287 | |
5b32165b | 288 | ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll); |
6ee73861 BS |
289 | if (ret) |
290 | return ret; | |
291 | ||
e9ebb68b BS |
292 | if (pll.vco2.maxfreq) { |
293 | ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P); | |
294 | if (ret <= 0) | |
295 | return 0; | |
6ee73861 | 296 | |
17b96cc3 | 297 | NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n", |
e9ebb68b BS |
298 | pclk, ret, N1, M1, N2, M2, P); |
299 | ||
5b32165b BS |
300 | reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00; |
301 | reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00; | |
302 | nv_wr32(dev, pll.reg + 0, 0x10000611); | |
303 | nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1); | |
304 | nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2); | |
1ac7b528 BS |
305 | } else |
306 | if (dev_priv->chipset < NV_C0) { | |
52eba8dd | 307 | ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P); |
e9ebb68b BS |
308 | if (ret <= 0) |
309 | return 0; | |
310 | ||
311 | NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n", | |
312 | pclk, ret, N1, N2, M1, P); | |
17b96cc3 | 313 | |
5b32165b BS |
314 | reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000; |
315 | nv_wr32(dev, pll.reg + 0, 0x50000610); | |
316 | nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1); | |
317 | nv_wr32(dev, pll.reg + 8, N2); | |
1ac7b528 | 318 | } else { |
52eba8dd | 319 | ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P); |
1ac7b528 BS |
320 | if (ret <= 0) |
321 | return 0; | |
322 | ||
323 | NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n", | |
324 | pclk, ret, N1, N2, M1, P); | |
325 | ||
5b32165b BS |
326 | nv_mask(dev, pll.reg + 0x0c, 0x00000000, 0x00000100); |
327 | nv_wr32(dev, pll.reg + 0x04, (P << 16) | (N1 << 8) | M1); | |
328 | nv_wr32(dev, pll.reg + 0x10, N2 << 16); | |
6ee73861 BS |
329 | } |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | static void | |
335 | nv50_crtc_destroy(struct drm_crtc *crtc) | |
336 | { | |
dd19e44b MS |
337 | struct drm_device *dev; |
338 | struct nouveau_crtc *nv_crtc; | |
6ee73861 BS |
339 | |
340 | if (!crtc) | |
341 | return; | |
342 | ||
dd19e44b MS |
343 | dev = crtc->dev; |
344 | nv_crtc = nouveau_crtc(crtc); | |
345 | ||
346 | NV_DEBUG_KMS(dev, "\n"); | |
347 | ||
6ee73861 BS |
348 | drm_crtc_cleanup(&nv_crtc->base); |
349 | ||
9d59e8a1 | 350 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
6ee73861 | 351 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
9d59e8a1 | 352 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
6ee73861 BS |
353 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
354 | kfree(nv_crtc->mode); | |
355 | kfree(nv_crtc); | |
356 | } | |
357 | ||
358 | int | |
359 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, | |
360 | uint32_t buffer_handle, uint32_t width, uint32_t height) | |
361 | { | |
362 | struct drm_device *dev = crtc->dev; | |
6ee73861 BS |
363 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
364 | struct nouveau_bo *cursor = NULL; | |
365 | struct drm_gem_object *gem; | |
366 | int ret = 0, i; | |
367 | ||
6ee73861 BS |
368 | if (!buffer_handle) { |
369 | nv_crtc->cursor.hide(nv_crtc, true); | |
370 | return 0; | |
371 | } | |
372 | ||
b4fa9d0f MS |
373 | if (width != 64 || height != 64) |
374 | return -EINVAL; | |
375 | ||
6ee73861 BS |
376 | gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); |
377 | if (!gem) | |
bf79cb91 | 378 | return -ENOENT; |
6ee73861 BS |
379 | cursor = nouveau_gem_object(gem); |
380 | ||
381 | ret = nouveau_bo_map(cursor); | |
382 | if (ret) | |
383 | goto out; | |
384 | ||
385 | /* The simple will do for now. */ | |
386 | for (i = 0; i < 64 * 64; i++) | |
387 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i)); | |
388 | ||
389 | nouveau_bo_unmap(cursor); | |
390 | ||
180cc306 | 391 | nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset); |
6ee73861 BS |
392 | nv_crtc->cursor.show(nv_crtc, true); |
393 | ||
394 | out: | |
bc9025bd | 395 | drm_gem_object_unreference_unlocked(gem); |
6ee73861 BS |
396 | return ret; |
397 | } | |
398 | ||
399 | int | |
400 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
401 | { | |
402 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
403 | ||
404 | nv_crtc->cursor.set_pos(nv_crtc, x, y); | |
405 | return 0; | |
406 | } | |
407 | ||
408 | static void | |
409 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, | |
7203425a | 410 | uint32_t start, uint32_t size) |
6ee73861 | 411 | { |
7203425a | 412 | int end = (start + size > 256) ? 256 : start + size, i; |
6ee73861 | 413 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
6ee73861 | 414 | |
7203425a | 415 | for (i = start; i < end; i++) { |
6ee73861 BS |
416 | nv_crtc->lut.r[i] = r[i]; |
417 | nv_crtc->lut.g[i] = g[i]; | |
418 | nv_crtc->lut.b[i] = b[i]; | |
419 | } | |
420 | ||
421 | /* We need to know the depth before we upload, but it's possible to | |
422 | * get called before a framebuffer is bound. If this is the case, | |
423 | * mark the lut values as dirty by setting depth==0, and it'll be | |
424 | * uploaded on the first mode_set_base() | |
425 | */ | |
426 | if (!nv_crtc->base.fb) { | |
427 | nv_crtc->lut.depth = 0; | |
428 | return; | |
429 | } | |
430 | ||
431 | nv50_crtc_lut_load(crtc); | |
432 | } | |
433 | ||
434 | static void | |
435 | nv50_crtc_save(struct drm_crtc *crtc) | |
436 | { | |
437 | NV_ERROR(crtc->dev, "!!\n"); | |
438 | } | |
439 | ||
440 | static void | |
441 | nv50_crtc_restore(struct drm_crtc *crtc) | |
442 | { | |
443 | NV_ERROR(crtc->dev, "!!\n"); | |
444 | } | |
445 | ||
446 | static const struct drm_crtc_funcs nv50_crtc_funcs = { | |
447 | .save = nv50_crtc_save, | |
448 | .restore = nv50_crtc_restore, | |
449 | .cursor_set = nv50_crtc_cursor_set, | |
450 | .cursor_move = nv50_crtc_cursor_move, | |
451 | .gamma_set = nv50_crtc_gamma_set, | |
452 | .set_config = drm_crtc_helper_set_config, | |
332b242f | 453 | .page_flip = nouveau_crtc_page_flip, |
6ee73861 BS |
454 | .destroy = nv50_crtc_destroy, |
455 | }; | |
456 | ||
457 | static void | |
458 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) | |
459 | { | |
460 | } | |
461 | ||
462 | static void | |
463 | nv50_crtc_prepare(struct drm_crtc *crtc) | |
464 | { | |
465 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
466 | struct drm_device *dev = crtc->dev; | |
6ee73861 | 467 | |
ef2bb506 | 468 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 | 469 | |
1d3fac0c | 470 | nv50_display_flip_stop(crtc); |
1c180fa5 | 471 | drm_vblank_pre_modeset(dev, nv_crtc->index); |
6ee73861 BS |
472 | nv50_crtc_blank(nv_crtc, true); |
473 | } | |
474 | ||
475 | static void | |
476 | nv50_crtc_commit(struct drm_crtc *crtc) | |
477 | { | |
6ee73861 | 478 | struct drm_device *dev = crtc->dev; |
6ee73861 | 479 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
6ee73861 | 480 | |
ef2bb506 | 481 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 BS |
482 | |
483 | nv50_crtc_blank(nv_crtc, false); | |
1c180fa5 | 484 | drm_vblank_post_modeset(dev, nv_crtc->index); |
e6e039d1 | 485 | nv50_display_sync(dev); |
1d3fac0c | 486 | nv50_display_flip_next(crtc, crtc->fb, NULL); |
6ee73861 BS |
487 | } |
488 | ||
489 | static bool | |
490 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
491 | struct drm_display_mode *adjusted_mode) | |
492 | { | |
493 | return true; | |
494 | } | |
495 | ||
496 | static int | |
be64c2bb CB |
497 | nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, |
498 | struct drm_framebuffer *passed_fb, | |
60f60bf1 | 499 | int x, int y, bool atomic) |
6ee73861 BS |
500 | { |
501 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
502 | struct drm_device *dev = nv_crtc->base.dev; | |
503 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
59c0f578 | 504 | struct nouveau_channel *evo = nv50_display(dev)->master; |
ffbc559b EV |
505 | struct drm_framebuffer *drm_fb; |
506 | struct nouveau_framebuffer *fb; | |
45c4e0aa | 507 | int ret; |
6ee73861 | 508 | |
ef2bb506 | 509 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 | 510 | |
ffbc559b EV |
511 | /* no fb bound */ |
512 | if (!atomic && !crtc->fb) { | |
513 | NV_DEBUG_KMS(dev, "No FB bound\n"); | |
514 | return 0; | |
515 | } | |
516 | ||
be64c2bb CB |
517 | /* If atomic, we want to switch to the fb we were passed, so |
518 | * now we update pointers to do that. (We don't pin; just | |
519 | * assume we're already pinned and update the base address.) | |
520 | */ | |
521 | if (atomic) { | |
522 | drm_fb = passed_fb; | |
523 | fb = nouveau_framebuffer(passed_fb); | |
f9ec8f6c | 524 | } else { |
ffbc559b EV |
525 | drm_fb = crtc->fb; |
526 | fb = nouveau_framebuffer(crtc->fb); | |
be64c2bb CB |
527 | /* If not atomic, we can go ahead and pin, and unpin the |
528 | * old fb we were passed. | |
529 | */ | |
530 | ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM); | |
531 | if (ret) | |
532 | return ret; | |
533 | ||
534 | if (passed_fb) { | |
535 | struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb); | |
536 | nouveau_bo_unpin(ofb->nvbo); | |
537 | } | |
538 | } | |
539 | ||
180cc306 | 540 | nv_crtc->fb.offset = fb->nvbo->bo.offset; |
f13b3263 | 541 | nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo); |
6ee73861 BS |
542 | nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8; |
543 | if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) { | |
544 | ret = RING_SPACE(evo, 2); | |
545 | if (ret) | |
546 | return ret; | |
547 | ||
548 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1); | |
45c4e0aa | 549 | OUT_RING (evo, fb->r_dma); |
6ee73861 BS |
550 | } |
551 | ||
552 | ret = RING_SPACE(evo, 12); | |
553 | if (ret) | |
554 | return ret; | |
555 | ||
556 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5); | |
45c4e0aa BS |
557 | OUT_RING (evo, nv_crtc->fb.offset >> 8); |
558 | OUT_RING (evo, 0); | |
559 | OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width); | |
560 | OUT_RING (evo, fb->r_pitch); | |
561 | OUT_RING (evo, fb->r_format); | |
6ee73861 BS |
562 | |
563 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1); | |
45c4e0aa BS |
564 | OUT_RING (evo, fb->base.depth == 8 ? |
565 | NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON); | |
6ee73861 BS |
566 | |
567 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1); | |
45c4e0aa | 568 | OUT_RING (evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR); |
6ee73861 | 569 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1); |
45c4e0aa | 570 | OUT_RING (evo, (y << 16) | x); |
6ee73861 BS |
571 | |
572 | if (nv_crtc->lut.depth != fb->base.depth) { | |
573 | nv_crtc->lut.depth = fb->base.depth; | |
574 | nv50_crtc_lut_load(crtc); | |
575 | } | |
576 | ||
6ee73861 BS |
577 | return 0; |
578 | } | |
579 | ||
580 | static int | |
581 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
582 | struct drm_display_mode *adjusted_mode, int x, int y, | |
583 | struct drm_framebuffer *old_fb) | |
584 | { | |
585 | struct drm_device *dev = crtc->dev; | |
59c0f578 | 586 | struct nouveau_channel *evo = nv50_display(dev)->master; |
6ee73861 BS |
587 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
588 | struct nouveau_connector *nv_connector = NULL; | |
589 | uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end; | |
590 | uint32_t hunk1, vunk1, vunk2a, vunk2b; | |
591 | int ret; | |
592 | ||
593 | /* Find the connector attached to this CRTC */ | |
594 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
595 | ||
596 | *nv_crtc->mode = *adjusted_mode; | |
597 | ||
ef2bb506 | 598 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 BS |
599 | |
600 | hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start; | |
601 | vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start; | |
602 | hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start; | |
603 | vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start; | |
604 | /* I can't give this a proper name, anyone else can? */ | |
605 | hunk1 = adjusted_mode->htotal - | |
606 | adjusted_mode->hsync_start + adjusted_mode->hdisplay; | |
607 | vunk1 = adjusted_mode->vtotal - | |
608 | adjusted_mode->vsync_start + adjusted_mode->vdisplay; | |
609 | /* Another strange value, this time only for interlaced adjusted_modes. */ | |
610 | vunk2a = 2 * adjusted_mode->vtotal - | |
611 | adjusted_mode->vsync_start + adjusted_mode->vdisplay; | |
612 | vunk2b = adjusted_mode->vtotal - | |
613 | adjusted_mode->vsync_start + adjusted_mode->vtotal; | |
614 | ||
615 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
616 | vsync_dur /= 2; | |
617 | vsync_start_to_end /= 2; | |
618 | vunk1 /= 2; | |
619 | vunk2a /= 2; | |
620 | vunk2b /= 2; | |
621 | /* magic */ | |
622 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
623 | vsync_start_to_end -= 1; | |
624 | vunk1 -= 1; | |
625 | vunk2a -= 1; | |
626 | vunk2b -= 1; | |
627 | } | |
628 | } | |
629 | ||
b98e3f5c | 630 | ret = RING_SPACE(evo, 19); |
6ee73861 BS |
631 | if (ret) |
632 | return ret; | |
633 | ||
634 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2); | |
635 | OUT_RING(evo, adjusted_mode->clock | 0x800000); | |
636 | OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0); | |
637 | ||
638 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5); | |
639 | OUT_RING(evo, 0); | |
640 | OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal); | |
641 | OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1)); | |
642 | OUT_RING(evo, (vsync_start_to_end - 1) << 16 | | |
643 | (hsync_start_to_end - 1)); | |
644 | OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1)); | |
645 | ||
646 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
647 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1); | |
648 | OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1)); | |
649 | } else { | |
650 | OUT_RING(evo, 0); | |
651 | OUT_RING(evo, 0); | |
652 | } | |
653 | ||
654 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1); | |
b98e3f5c BS |
655 | OUT_RING (evo, 0); |
656 | /* required to make display sync channel not hate life */ | |
657 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK900), 1); | |
658 | OUT_RING (evo, 0x00000311); | |
6ee73861 BS |
659 | |
660 | /* This is the actual resolution of the mode. */ | |
661 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1); | |
662 | OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay); | |
663 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1); | |
664 | OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0)); | |
665 | ||
666 | nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false); | |
667 | nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false); | |
668 | ||
60f60bf1 | 669 | return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false); |
6ee73861 BS |
670 | } |
671 | ||
672 | static int | |
673 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
674 | struct drm_framebuffer *old_fb) | |
675 | { | |
60f60bf1 BS |
676 | int ret; |
677 | ||
1d3fac0c | 678 | nv50_display_flip_stop(crtc); |
60f60bf1 BS |
679 | ret = nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false); |
680 | if (ret) | |
681 | return ret; | |
682 | ||
e6e039d1 | 683 | ret = nv50_display_sync(crtc->dev); |
1d3fac0c BS |
684 | if (ret) |
685 | return ret; | |
686 | ||
687 | return nv50_display_flip_next(crtc, crtc->fb, NULL); | |
be64c2bb CB |
688 | } |
689 | ||
690 | static int | |
691 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, | |
692 | struct drm_framebuffer *fb, | |
21c74a8e | 693 | int x, int y, enum mode_set_atomic state) |
be64c2bb | 694 | { |
60f60bf1 BS |
695 | int ret; |
696 | ||
1d3fac0c | 697 | nv50_display_flip_stop(crtc); |
60f60bf1 BS |
698 | ret = nv50_crtc_do_mode_set_base(crtc, fb, x, y, true); |
699 | if (ret) | |
700 | return ret; | |
701 | ||
e6e039d1 | 702 | return nv50_display_sync(crtc->dev); |
6ee73861 BS |
703 | } |
704 | ||
705 | static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = { | |
706 | .dpms = nv50_crtc_dpms, | |
707 | .prepare = nv50_crtc_prepare, | |
708 | .commit = nv50_crtc_commit, | |
709 | .mode_fixup = nv50_crtc_mode_fixup, | |
710 | .mode_set = nv50_crtc_mode_set, | |
711 | .mode_set_base = nv50_crtc_mode_set_base, | |
be64c2bb | 712 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, |
6ee73861 BS |
713 | .load_lut = nv50_crtc_lut_load, |
714 | }; | |
715 | ||
716 | int | |
717 | nv50_crtc_create(struct drm_device *dev, int index) | |
718 | { | |
719 | struct nouveau_crtc *nv_crtc = NULL; | |
720 | int ret, i; | |
721 | ||
ef2bb506 | 722 | NV_DEBUG_KMS(dev, "\n"); |
6ee73861 BS |
723 | |
724 | nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); | |
725 | if (!nv_crtc) | |
726 | return -ENOMEM; | |
727 | ||
728 | nv_crtc->mode = kzalloc(sizeof(*nv_crtc->mode), GFP_KERNEL); | |
729 | if (!nv_crtc->mode) { | |
730 | kfree(nv_crtc); | |
731 | return -ENOMEM; | |
732 | } | |
733 | ||
734 | /* Default CLUT parameters, will be activated on the hw upon | |
735 | * first mode set. | |
736 | */ | |
737 | for (i = 0; i < 256; i++) { | |
738 | nv_crtc->lut.r[i] = i << 8; | |
739 | nv_crtc->lut.g[i] = i << 8; | |
740 | nv_crtc->lut.b[i] = i << 8; | |
741 | } | |
742 | nv_crtc->lut.depth = 0; | |
743 | ||
7375c95b | 744 | ret = nouveau_bo_new(dev, 4096, 0x100, TTM_PL_FLAG_VRAM, |
d550c41e | 745 | 0, 0x0000, &nv_crtc->lut.nvbo); |
6ee73861 BS |
746 | if (!ret) { |
747 | ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM); | |
748 | if (!ret) | |
749 | ret = nouveau_bo_map(nv_crtc->lut.nvbo); | |
750 | if (ret) | |
751 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); | |
752 | } | |
753 | ||
754 | if (ret) { | |
755 | kfree(nv_crtc->mode); | |
756 | kfree(nv_crtc); | |
757 | return ret; | |
758 | } | |
759 | ||
760 | nv_crtc->index = index; | |
761 | ||
762 | /* set function pointers */ | |
763 | nv_crtc->set_dither = nv50_crtc_set_dither; | |
764 | nv_crtc->set_scale = nv50_crtc_set_scale; | |
765 | ||
766 | drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs); | |
767 | drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs); | |
768 | drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); | |
769 | ||
7375c95b | 770 | ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, |
d550c41e | 771 | 0, 0x0000, &nv_crtc->cursor.nvbo); |
6ee73861 BS |
772 | if (!ret) { |
773 | ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); | |
774 | if (!ret) | |
775 | ret = nouveau_bo_map(nv_crtc->cursor.nvbo); | |
776 | if (ret) | |
777 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); | |
778 | } | |
779 | ||
780 | nv50_cursor_init(nv_crtc); | |
781 | return 0; | |
782 | } |