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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2008 Maarten Maathuis. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include "drmP.h" | |
28 | #include "drm_mode.h" | |
29 | #include "drm_crtc_helper.h" | |
30 | ||
31 | #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) | |
32 | #include "nouveau_reg.h" | |
33 | #include "nouveau_drv.h" | |
34 | #include "nouveau_hw.h" | |
35 | #include "nouveau_encoder.h" | |
36 | #include "nouveau_crtc.h" | |
37 | #include "nouveau_fb.h" | |
38 | #include "nouveau_connector.h" | |
39 | #include "nv50_display.h" | |
40 | ||
41 | static void | |
42 | nv50_crtc_lut_load(struct drm_crtc *crtc) | |
43 | { | |
44 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
45 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
46 | int i; | |
47 | ||
ef2bb506 | 48 | NV_DEBUG_KMS(crtc->dev, "\n"); |
6ee73861 BS |
49 | |
50 | for (i = 0; i < 256; i++) { | |
51 | writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0); | |
52 | writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2); | |
53 | writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4); | |
54 | } | |
55 | ||
56 | if (nv_crtc->lut.depth == 30) { | |
57 | writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0); | |
58 | writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2); | |
59 | writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4); | |
60 | } | |
61 | } | |
62 | ||
63 | int | |
64 | nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked) | |
65 | { | |
66 | struct drm_device *dev = nv_crtc->base.dev; | |
67 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
59c0f578 | 68 | struct nouveau_channel *evo = nv50_display(dev)->master; |
6ee73861 BS |
69 | int index = nv_crtc->index, ret; |
70 | ||
ef2bb506 MM |
71 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
72 | NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked"); | |
6ee73861 BS |
73 | |
74 | if (blanked) { | |
75 | nv_crtc->cursor.hide(nv_crtc, false); | |
76 | ||
77 | ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5); | |
78 | if (ret) { | |
79 | NV_ERROR(dev, "no space while blanking crtc\n"); | |
80 | return ret; | |
81 | } | |
6d597027 | 82 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); |
6ee73861 BS |
83 | OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK); |
84 | OUT_RING(evo, 0); | |
85 | if (dev_priv->chipset != 0x50) { | |
6d597027 | 86 | BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); |
6ee73861 BS |
87 | OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE); |
88 | } | |
89 | ||
6d597027 | 90 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); |
6ee73861 BS |
91 | OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE); |
92 | } else { | |
93 | if (nv_crtc->cursor.visible) | |
94 | nv_crtc->cursor.show(nv_crtc, false); | |
95 | else | |
96 | nv_crtc->cursor.hide(nv_crtc, false); | |
97 | ||
98 | ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8); | |
99 | if (ret) { | |
100 | NV_ERROR(dev, "no space while unblanking crtc\n"); | |
101 | return ret; | |
102 | } | |
6d597027 | 103 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); |
6ee73861 BS |
104 | OUT_RING(evo, nv_crtc->lut.depth == 8 ? |
105 | NV50_EVO_CRTC_CLUT_MODE_OFF : | |
106 | NV50_EVO_CRTC_CLUT_MODE_ON); | |
180cc306 | 107 | OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8); |
6ee73861 | 108 | if (dev_priv->chipset != 0x50) { |
6d597027 | 109 | BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); |
6ee73861 BS |
110 | OUT_RING(evo, NvEvoVRAM); |
111 | } | |
112 | ||
6d597027 | 113 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2); |
6ee73861 BS |
114 | OUT_RING(evo, nv_crtc->fb.offset >> 8); |
115 | OUT_RING(evo, 0); | |
6d597027 | 116 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); |
6ee73861 | 117 | if (dev_priv->chipset != 0x50) |
6d86951a BS |
118 | if (nv_crtc->fb.tile_flags == 0x7a00 || |
119 | nv_crtc->fb.tile_flags == 0xfe00) | |
6ee73861 BS |
120 | OUT_RING(evo, NvEvoFB32); |
121 | else | |
122 | if (nv_crtc->fb.tile_flags == 0x7000) | |
123 | OUT_RING(evo, NvEvoFB16); | |
124 | else | |
6d86951a | 125 | OUT_RING(evo, NvEvoVRAM_LP); |
6ee73861 | 126 | else |
6d86951a | 127 | OUT_RING(evo, NvEvoVRAM_LP); |
6ee73861 BS |
128 | } |
129 | ||
130 | nv_crtc->fb.blanked = blanked; | |
131 | return 0; | |
132 | } | |
133 | ||
134 | static int | |
488ff207 | 135 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
6ee73861 | 136 | { |
de691855 BS |
137 | struct nouveau_channel *evo = nv50_display(nv_crtc->base.dev)->master; |
138 | struct nouveau_connector *nv_connector; | |
139 | struct drm_connector *connector; | |
140 | int head = nv_crtc->index, ret; | |
141 | u32 mode = 0x00; | |
142 | ||
143 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
144 | connector = &nv_connector->base; | |
145 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { | |
146 | if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3) | |
147 | mode = DITHERING_MODE_DYNAMIC2X2; | |
148 | } else { | |
149 | mode = nv_connector->dithering_mode; | |
6ee73861 BS |
150 | } |
151 | ||
de691855 BS |
152 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { |
153 | if (connector->display_info.bpc >= 8) | |
154 | mode |= DITHERING_DEPTH_8BPC; | |
155 | } else { | |
156 | mode |= nv_connector->dithering_depth; | |
157 | } | |
6ee73861 | 158 | |
de691855 BS |
159 | ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); |
160 | if (ret == 0) { | |
6d597027 | 161 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(head, DITHER_CTRL), 1); |
de691855 BS |
162 | OUT_RING (evo, mode); |
163 | if (update) { | |
6d597027 | 164 | BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); |
de691855 BS |
165 | OUT_RING (evo, 0); |
166 | FIRE_RING (evo); | |
167 | } | |
6ee73861 BS |
168 | } |
169 | ||
de691855 | 170 | return ret; |
6ee73861 BS |
171 | } |
172 | ||
df26bc9c CB |
173 | static int |
174 | nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) | |
175 | { | |
176 | struct drm_device *dev = nv_crtc->base.dev; | |
177 | struct nouveau_channel *evo = nv50_display(dev)->master; | |
178 | int ret; | |
179 | int adj; | |
180 | u32 hue, vib; | |
181 | ||
182 | NV_DEBUG_KMS(dev, "vibrance = %i, hue = %i\n", | |
183 | nv_crtc->color_vibrance, nv_crtc->vibrant_hue); | |
184 | ||
185 | ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); | |
186 | if (ret) { | |
187 | NV_ERROR(dev, "no space while setting color vibrance\n"); | |
188 | return ret; | |
189 | } | |
190 | ||
191 | adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; | |
192 | vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; | |
193 | ||
194 | hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; | |
195 | ||
6d597027 | 196 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1); |
df26bc9c CB |
197 | OUT_RING (evo, (hue << 20) | (vib << 8)); |
198 | ||
199 | if (update) { | |
6d597027 | 200 | BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); |
df26bc9c CB |
201 | OUT_RING (evo, 0); |
202 | FIRE_RING (evo); | |
203 | } | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
6ee73861 BS |
208 | struct nouveau_connector * |
209 | nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc) | |
210 | { | |
211 | struct drm_device *dev = nv_crtc->base.dev; | |
212 | struct drm_connector *connector; | |
213 | struct drm_crtc *crtc = to_drm_crtc(nv_crtc); | |
214 | ||
215 | /* The safest approach is to find an encoder with the right crtc, that | |
216 | * is also linked to a connector. */ | |
217 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
218 | if (connector->encoder) | |
219 | if (connector->encoder->crtc == crtc) | |
220 | return nouveau_connector(connector); | |
221 | } | |
222 | ||
223 | return NULL; | |
224 | } | |
225 | ||
226 | static int | |
488ff207 | 227 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
6ee73861 | 228 | { |
b29caa58 | 229 | struct nouveau_connector *nv_connector; |
549cd872 BS |
230 | struct drm_crtc *crtc = &nv_crtc->base; |
231 | struct drm_device *dev = crtc->dev; | |
59c0f578 | 232 | struct nouveau_channel *evo = nv50_display(dev)->master; |
1cb9469e BS |
233 | struct drm_display_mode *umode = &crtc->mode; |
234 | struct drm_display_mode *omode; | |
488ff207 | 235 | int scaling_mode, ret; |
b29caa58 | 236 | u32 ctrl = 0, oX, oY; |
6ee73861 | 237 | |
ef2bb506 | 238 | NV_DEBUG_KMS(dev, "\n"); |
6ee73861 | 239 | |
b29caa58 BS |
240 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
241 | if (!nv_connector || !nv_connector->native_mode) { | |
242 | NV_ERROR(dev, "no native mode, forcing panel scaling\n"); | |
243 | scaling_mode = DRM_MODE_SCALE_NONE; | |
488ff207 BS |
244 | } else { |
245 | scaling_mode = nv_connector->scaling_mode; | |
b29caa58 BS |
246 | } |
247 | ||
248 | /* start off at the resolution we programmed the crtc for, this | |
249 | * effectively handles NONE/FULL scaling | |
250 | */ | |
1cb9469e BS |
251 | if (scaling_mode != DRM_MODE_SCALE_NONE) |
252 | omode = nv_connector->native_mode; | |
253 | else | |
254 | omode = umode; | |
255 | ||
256 | oX = omode->hdisplay; | |
257 | oY = omode->vdisplay; | |
258 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) | |
259 | oY *= 2; | |
b29caa58 BS |
260 | |
261 | /* add overscan compensation if necessary, will keep the aspect | |
262 | * ratio the same as the backend mode unless overridden by the | |
263 | * user setting both hborder and vborder properties. | |
264 | */ | |
265 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || | |
266 | (nv_connector->underscan == UNDERSCAN_AUTO && | |
267 | nv_connector->edid && | |
268 | drm_detect_hdmi_monitor(nv_connector->edid)))) { | |
269 | u32 bX = nv_connector->underscan_hborder; | |
270 | u32 bY = nv_connector->underscan_vborder; | |
271 | u32 aspect = (oY << 19) / oX; | |
272 | ||
273 | if (bX) { | |
274 | oX -= (bX * 2); | |
275 | if (bY) oY -= (bY * 2); | |
276 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
6ee73861 | 277 | } else { |
b29caa58 BS |
278 | oX -= (oX >> 4) + 32; |
279 | if (bY) oY -= (bY * 2); | |
280 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
6ee73861 | 281 | } |
6ee73861 BS |
282 | } |
283 | ||
b29caa58 BS |
284 | /* handle CENTER/ASPECT scaling, taking into account the areas |
285 | * removed already for overscan compensation | |
286 | */ | |
6ee73861 | 287 | switch (scaling_mode) { |
b29caa58 | 288 | case DRM_MODE_SCALE_CENTER: |
1cb9469e BS |
289 | oX = min((u32)umode->hdisplay, oX); |
290 | oY = min((u32)umode->vdisplay, oY); | |
b29caa58 | 291 | /* fall-through */ |
6ee73861 | 292 | case DRM_MODE_SCALE_ASPECT: |
b29caa58 | 293 | if (oY < oX) { |
1cb9469e | 294 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; |
b29caa58 | 295 | oX = ((oY * aspect) + (aspect / 2)) >> 19; |
6ee73861 | 296 | } else { |
1cb9469e | 297 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; |
b29caa58 | 298 | oY = ((oX * aspect) + (aspect / 2)) >> 19; |
6ee73861 BS |
299 | } |
300 | break; | |
6ee73861 | 301 | default: |
6ee73861 BS |
302 | break; |
303 | } | |
304 | ||
1cb9469e BS |
305 | if (umode->hdisplay != oX || umode->vdisplay != oY || |
306 | umode->flags & DRM_MODE_FLAG_INTERLACE || | |
307 | umode->flags & DRM_MODE_FLAG_DBLSCAN) | |
b29caa58 BS |
308 | ctrl |= NV50_EVO_CRTC_SCALE_CTRL_ACTIVE; |
309 | ||
549cd872 | 310 | ret = RING_SPACE(evo, 5); |
6ee73861 BS |
311 | if (ret) |
312 | return ret; | |
313 | ||
6d597027 | 314 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1); |
b29caa58 | 315 | OUT_RING (evo, ctrl); |
6d597027 | 316 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2); |
b29caa58 BS |
317 | OUT_RING (evo, oY << 16 | oX); |
318 | OUT_RING (evo, oY << 16 | oX); | |
6ee73861 BS |
319 | |
320 | if (update) { | |
549cd872 | 321 | nv50_display_flip_stop(crtc); |
e6e039d1 | 322 | nv50_display_sync(dev); |
549cd872 | 323 | nv50_display_flip_next(crtc, crtc->fb, NULL); |
6ee73861 BS |
324 | } |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
329 | int | |
330 | nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) | |
331 | { | |
1ac7b528 | 332 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
e9ebb68b | 333 | struct pll_lims pll; |
5b32165b | 334 | uint32_t reg1, reg2; |
e9ebb68b | 335 | int ret, N1, M1, N2, M2, P; |
6ee73861 | 336 | |
5b32165b | 337 | ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll); |
6ee73861 BS |
338 | if (ret) |
339 | return ret; | |
340 | ||
e9ebb68b BS |
341 | if (pll.vco2.maxfreq) { |
342 | ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P); | |
343 | if (ret <= 0) | |
344 | return 0; | |
6ee73861 | 345 | |
17b96cc3 | 346 | NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n", |
e9ebb68b BS |
347 | pclk, ret, N1, M1, N2, M2, P); |
348 | ||
5b32165b BS |
349 | reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00; |
350 | reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00; | |
351 | nv_wr32(dev, pll.reg + 0, 0x10000611); | |
352 | nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1); | |
353 | nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2); | |
1ac7b528 BS |
354 | } else |
355 | if (dev_priv->chipset < NV_C0) { | |
52eba8dd | 356 | ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P); |
e9ebb68b BS |
357 | if (ret <= 0) |
358 | return 0; | |
359 | ||
360 | NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n", | |
361 | pclk, ret, N1, N2, M1, P); | |
17b96cc3 | 362 | |
5b32165b BS |
363 | reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000; |
364 | nv_wr32(dev, pll.reg + 0, 0x50000610); | |
365 | nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1); | |
366 | nv_wr32(dev, pll.reg + 8, N2); | |
1ac7b528 | 367 | } else { |
52eba8dd | 368 | ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P); |
1ac7b528 BS |
369 | if (ret <= 0) |
370 | return 0; | |
371 | ||
372 | NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n", | |
373 | pclk, ret, N1, N2, M1, P); | |
374 | ||
5b32165b BS |
375 | nv_mask(dev, pll.reg + 0x0c, 0x00000000, 0x00000100); |
376 | nv_wr32(dev, pll.reg + 0x04, (P << 16) | (N1 << 8) | M1); | |
377 | nv_wr32(dev, pll.reg + 0x10, N2 << 16); | |
6ee73861 BS |
378 | } |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static void | |
384 | nv50_crtc_destroy(struct drm_crtc *crtc) | |
385 | { | |
a8f81837 | 386 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
dd19e44b | 387 | |
a8f81837 | 388 | NV_DEBUG_KMS(crtc->dev, "\n"); |
6ee73861 | 389 | |
9d59e8a1 | 390 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
6ee73861 | 391 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
9d59e8a1 | 392 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
6ee73861 | 393 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
a8f81837 | 394 | drm_crtc_cleanup(&nv_crtc->base); |
6ee73861 BS |
395 | kfree(nv_crtc); |
396 | } | |
397 | ||
398 | int | |
399 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, | |
400 | uint32_t buffer_handle, uint32_t width, uint32_t height) | |
401 | { | |
402 | struct drm_device *dev = crtc->dev; | |
6ee73861 BS |
403 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
404 | struct nouveau_bo *cursor = NULL; | |
405 | struct drm_gem_object *gem; | |
406 | int ret = 0, i; | |
407 | ||
6ee73861 BS |
408 | if (!buffer_handle) { |
409 | nv_crtc->cursor.hide(nv_crtc, true); | |
410 | return 0; | |
411 | } | |
412 | ||
b4fa9d0f MS |
413 | if (width != 64 || height != 64) |
414 | return -EINVAL; | |
415 | ||
6ee73861 BS |
416 | gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); |
417 | if (!gem) | |
bf79cb91 | 418 | return -ENOENT; |
6ee73861 BS |
419 | cursor = nouveau_gem_object(gem); |
420 | ||
421 | ret = nouveau_bo_map(cursor); | |
422 | if (ret) | |
423 | goto out; | |
424 | ||
425 | /* The simple will do for now. */ | |
426 | for (i = 0; i < 64 * 64; i++) | |
427 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i)); | |
428 | ||
429 | nouveau_bo_unmap(cursor); | |
430 | ||
180cc306 | 431 | nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset); |
6ee73861 BS |
432 | nv_crtc->cursor.show(nv_crtc, true); |
433 | ||
434 | out: | |
bc9025bd | 435 | drm_gem_object_unreference_unlocked(gem); |
6ee73861 BS |
436 | return ret; |
437 | } | |
438 | ||
439 | int | |
440 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
441 | { | |
442 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
443 | ||
444 | nv_crtc->cursor.set_pos(nv_crtc, x, y); | |
445 | return 0; | |
446 | } | |
447 | ||
448 | static void | |
449 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, | |
7203425a | 450 | uint32_t start, uint32_t size) |
6ee73861 | 451 | { |
7203425a | 452 | int end = (start + size > 256) ? 256 : start + size, i; |
6ee73861 | 453 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
6ee73861 | 454 | |
7203425a | 455 | for (i = start; i < end; i++) { |
6ee73861 BS |
456 | nv_crtc->lut.r[i] = r[i]; |
457 | nv_crtc->lut.g[i] = g[i]; | |
458 | nv_crtc->lut.b[i] = b[i]; | |
459 | } | |
460 | ||
461 | /* We need to know the depth before we upload, but it's possible to | |
462 | * get called before a framebuffer is bound. If this is the case, | |
463 | * mark the lut values as dirty by setting depth==0, and it'll be | |
464 | * uploaded on the first mode_set_base() | |
465 | */ | |
466 | if (!nv_crtc->base.fb) { | |
467 | nv_crtc->lut.depth = 0; | |
468 | return; | |
469 | } | |
470 | ||
471 | nv50_crtc_lut_load(crtc); | |
472 | } | |
473 | ||
474 | static void | |
475 | nv50_crtc_save(struct drm_crtc *crtc) | |
476 | { | |
477 | NV_ERROR(crtc->dev, "!!\n"); | |
478 | } | |
479 | ||
480 | static void | |
481 | nv50_crtc_restore(struct drm_crtc *crtc) | |
482 | { | |
483 | NV_ERROR(crtc->dev, "!!\n"); | |
484 | } | |
485 | ||
486 | static const struct drm_crtc_funcs nv50_crtc_funcs = { | |
487 | .save = nv50_crtc_save, | |
488 | .restore = nv50_crtc_restore, | |
489 | .cursor_set = nv50_crtc_cursor_set, | |
490 | .cursor_move = nv50_crtc_cursor_move, | |
491 | .gamma_set = nv50_crtc_gamma_set, | |
492 | .set_config = drm_crtc_helper_set_config, | |
332b242f | 493 | .page_flip = nouveau_crtc_page_flip, |
6ee73861 BS |
494 | .destroy = nv50_crtc_destroy, |
495 | }; | |
496 | ||
497 | static void | |
498 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) | |
499 | { | |
500 | } | |
501 | ||
502 | static void | |
503 | nv50_crtc_prepare(struct drm_crtc *crtc) | |
504 | { | |
505 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
506 | struct drm_device *dev = crtc->dev; | |
6ee73861 | 507 | |
ef2bb506 | 508 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 | 509 | |
1d3fac0c | 510 | nv50_display_flip_stop(crtc); |
1c180fa5 | 511 | drm_vblank_pre_modeset(dev, nv_crtc->index); |
6ee73861 BS |
512 | nv50_crtc_blank(nv_crtc, true); |
513 | } | |
514 | ||
515 | static void | |
516 | nv50_crtc_commit(struct drm_crtc *crtc) | |
517 | { | |
6ee73861 | 518 | struct drm_device *dev = crtc->dev; |
6ee73861 | 519 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
6ee73861 | 520 | |
ef2bb506 | 521 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 BS |
522 | |
523 | nv50_crtc_blank(nv_crtc, false); | |
1c180fa5 | 524 | drm_vblank_post_modeset(dev, nv_crtc->index); |
e6e039d1 | 525 | nv50_display_sync(dev); |
1d3fac0c | 526 | nv50_display_flip_next(crtc, crtc->fb, NULL); |
6ee73861 BS |
527 | } |
528 | ||
529 | static bool | |
530 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
531 | struct drm_display_mode *adjusted_mode) | |
532 | { | |
533 | return true; | |
534 | } | |
535 | ||
536 | static int | |
be64c2bb CB |
537 | nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, |
538 | struct drm_framebuffer *passed_fb, | |
60f60bf1 | 539 | int x, int y, bool atomic) |
6ee73861 BS |
540 | { |
541 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
542 | struct drm_device *dev = nv_crtc->base.dev; | |
543 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
59c0f578 | 544 | struct nouveau_channel *evo = nv50_display(dev)->master; |
ffbc559b EV |
545 | struct drm_framebuffer *drm_fb; |
546 | struct nouveau_framebuffer *fb; | |
45c4e0aa | 547 | int ret; |
6ee73861 | 548 | |
ef2bb506 | 549 | NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); |
6ee73861 | 550 | |
ffbc559b EV |
551 | /* no fb bound */ |
552 | if (!atomic && !crtc->fb) { | |
553 | NV_DEBUG_KMS(dev, "No FB bound\n"); | |
554 | return 0; | |
555 | } | |
556 | ||
be64c2bb CB |
557 | /* If atomic, we want to switch to the fb we were passed, so |
558 | * now we update pointers to do that. (We don't pin; just | |
559 | * assume we're already pinned and update the base address.) | |
560 | */ | |
561 | if (atomic) { | |
562 | drm_fb = passed_fb; | |
563 | fb = nouveau_framebuffer(passed_fb); | |
f9ec8f6c | 564 | } else { |
ffbc559b EV |
565 | drm_fb = crtc->fb; |
566 | fb = nouveau_framebuffer(crtc->fb); | |
be64c2bb CB |
567 | /* If not atomic, we can go ahead and pin, and unpin the |
568 | * old fb we were passed. | |
569 | */ | |
570 | ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM); | |
571 | if (ret) | |
572 | return ret; | |
573 | ||
574 | if (passed_fb) { | |
575 | struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb); | |
576 | nouveau_bo_unpin(ofb->nvbo); | |
577 | } | |
578 | } | |
579 | ||
180cc306 | 580 | nv_crtc->fb.offset = fb->nvbo->bo.offset; |
f13b3263 | 581 | nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo); |
6ee73861 BS |
582 | nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8; |
583 | if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) { | |
584 | ret = RING_SPACE(evo, 2); | |
585 | if (ret) | |
586 | return ret; | |
587 | ||
6d597027 | 588 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1); |
45c4e0aa | 589 | OUT_RING (evo, fb->r_dma); |
6ee73861 BS |
590 | } |
591 | ||
592 | ret = RING_SPACE(evo, 12); | |
593 | if (ret) | |
594 | return ret; | |
595 | ||
6d597027 | 596 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5); |
45c4e0aa BS |
597 | OUT_RING (evo, nv_crtc->fb.offset >> 8); |
598 | OUT_RING (evo, 0); | |
599 | OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width); | |
600 | OUT_RING (evo, fb->r_pitch); | |
601 | OUT_RING (evo, fb->r_format); | |
6ee73861 | 602 | |
6d597027 | 603 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1); |
45c4e0aa BS |
604 | OUT_RING (evo, fb->base.depth == 8 ? |
605 | NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON); | |
6ee73861 | 606 | |
6d597027 | 607 | BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1); |
45c4e0aa | 608 | OUT_RING (evo, (y << 16) | x); |
6ee73861 BS |
609 | |
610 | if (nv_crtc->lut.depth != fb->base.depth) { | |
611 | nv_crtc->lut.depth = fb->base.depth; | |
612 | nv50_crtc_lut_load(crtc); | |
613 | } | |
614 | ||
6ee73861 BS |
615 | return 0; |
616 | } | |
617 | ||
618 | static int | |
616a5f57 BS |
619 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, |
620 | struct drm_display_mode *mode, int x, int y, | |
6ee73861 BS |
621 | struct drm_framebuffer *old_fb) |
622 | { | |
623 | struct drm_device *dev = crtc->dev; | |
59c0f578 | 624 | struct nouveau_channel *evo = nv50_display(dev)->master; |
6ee73861 | 625 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
616a5f57 BS |
626 | u32 head = nv_crtc->index * 0x400; |
627 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; | |
628 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; | |
629 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; | |
630 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; | |
631 | u32 vblan2e = 0, vblan2s = 1; | |
6ee73861 BS |
632 | int ret; |
633 | ||
616a5f57 BS |
634 | /* hw timing description looks like this: |
635 | * | |
636 | * <sync> <back porch> <---------display---------> <front porch> | |
637 | * ______ | |
638 | * |____________|---------------------------|____________| | |
639 | * | |
640 | * ^ synce ^ blanke ^ blanks ^ active | |
641 | * | |
642 | * interlaced modes also have 2 additional values pointing at the end | |
643 | * and start of the next field's blanking period. | |
644 | */ | |
6ee73861 | 645 | |
616a5f57 BS |
646 | hactive = mode->htotal; |
647 | hsynce = mode->hsync_end - mode->hsync_start - 1; | |
648 | hbackp = mode->htotal - mode->hsync_end; | |
649 | hblanke = hsynce + hbackp; | |
650 | hfrontp = mode->hsync_start - mode->hdisplay; | |
651 | hblanks = mode->htotal - hfrontp - 1; | |
652 | ||
653 | vactive = mode->vtotal * vscan / ilace; | |
654 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; | |
655 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; | |
656 | vblanke = vsynce + vbackp; | |
657 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; | |
658 | vblanks = vactive - vfrontp - 1; | |
659 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
660 | vblan2e = vactive + vsynce + vbackp; | |
661 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); | |
662 | vactive = (vactive * 2) + 1; | |
6ee73861 BS |
663 | } |
664 | ||
616a5f57 BS |
665 | ret = RING_SPACE(evo, 18); |
666 | if (ret == 0) { | |
6d597027 | 667 | BEGIN_NV04(evo, 0, 0x0804 + head, 2); |
616a5f57 BS |
668 | OUT_RING (evo, 0x00800000 | mode->clock); |
669 | OUT_RING (evo, (ilace == 2) ? 2 : 0); | |
6d597027 | 670 | BEGIN_NV04(evo, 0, 0x0810 + head, 6); |
616a5f57 BS |
671 | OUT_RING (evo, 0x00000000); /* border colour */ |
672 | OUT_RING (evo, (vactive << 16) | hactive); | |
673 | OUT_RING (evo, ( vsynce << 16) | hsynce); | |
674 | OUT_RING (evo, (vblanke << 16) | hblanke); | |
675 | OUT_RING (evo, (vblanks << 16) | hblanks); | |
676 | OUT_RING (evo, (vblan2e << 16) | vblan2s); | |
6d597027 | 677 | BEGIN_NV04(evo, 0, 0x082c + head, 1); |
616a5f57 | 678 | OUT_RING (evo, 0x00000000); |
6d597027 | 679 | BEGIN_NV04(evo, 0, 0x0900 + head, 1); |
616a5f57 | 680 | OUT_RING (evo, 0x00000311); /* makes sync channel work */ |
6d597027 | 681 | BEGIN_NV04(evo, 0, 0x08c8 + head, 1); |
616a5f57 | 682 | OUT_RING (evo, (umode->vdisplay << 16) | umode->hdisplay); |
6d597027 | 683 | BEGIN_NV04(evo, 0, 0x08d4 + head, 1); |
616a5f57 | 684 | OUT_RING (evo, 0x00000000); /* screen position */ |
6ee73861 BS |
685 | } |
686 | ||
488ff207 BS |
687 | nv_crtc->set_dither(nv_crtc, false); |
688 | nv_crtc->set_scale(nv_crtc, false); | |
df26bc9c | 689 | nv_crtc->set_color_vibrance(nv_crtc, false); |
6ee73861 | 690 | |
60f60bf1 | 691 | return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false); |
6ee73861 BS |
692 | } |
693 | ||
694 | static int | |
695 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
696 | struct drm_framebuffer *old_fb) | |
697 | { | |
60f60bf1 BS |
698 | int ret; |
699 | ||
1d3fac0c | 700 | nv50_display_flip_stop(crtc); |
60f60bf1 BS |
701 | ret = nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false); |
702 | if (ret) | |
703 | return ret; | |
704 | ||
e6e039d1 | 705 | ret = nv50_display_sync(crtc->dev); |
1d3fac0c BS |
706 | if (ret) |
707 | return ret; | |
708 | ||
709 | return nv50_display_flip_next(crtc, crtc->fb, NULL); | |
be64c2bb CB |
710 | } |
711 | ||
712 | static int | |
713 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, | |
714 | struct drm_framebuffer *fb, | |
21c74a8e | 715 | int x, int y, enum mode_set_atomic state) |
be64c2bb | 716 | { |
60f60bf1 BS |
717 | int ret; |
718 | ||
1d3fac0c | 719 | nv50_display_flip_stop(crtc); |
60f60bf1 BS |
720 | ret = nv50_crtc_do_mode_set_base(crtc, fb, x, y, true); |
721 | if (ret) | |
722 | return ret; | |
723 | ||
e6e039d1 | 724 | return nv50_display_sync(crtc->dev); |
6ee73861 BS |
725 | } |
726 | ||
727 | static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = { | |
728 | .dpms = nv50_crtc_dpms, | |
729 | .prepare = nv50_crtc_prepare, | |
730 | .commit = nv50_crtc_commit, | |
731 | .mode_fixup = nv50_crtc_mode_fixup, | |
732 | .mode_set = nv50_crtc_mode_set, | |
733 | .mode_set_base = nv50_crtc_mode_set_base, | |
be64c2bb | 734 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, |
6ee73861 BS |
735 | .load_lut = nv50_crtc_lut_load, |
736 | }; | |
737 | ||
738 | int | |
739 | nv50_crtc_create(struct drm_device *dev, int index) | |
740 | { | |
741 | struct nouveau_crtc *nv_crtc = NULL; | |
742 | int ret, i; | |
743 | ||
ef2bb506 | 744 | NV_DEBUG_KMS(dev, "\n"); |
6ee73861 BS |
745 | |
746 | nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); | |
747 | if (!nv_crtc) | |
748 | return -ENOMEM; | |
749 | ||
a8f81837 BS |
750 | nv_crtc->index = index; |
751 | nv_crtc->set_dither = nv50_crtc_set_dither; | |
752 | nv_crtc->set_scale = nv50_crtc_set_scale; | |
753 | nv_crtc->set_color_vibrance = nv50_crtc_set_color_vibrance; | |
df26bc9c CB |
754 | nv_crtc->color_vibrance = 50; |
755 | nv_crtc->vibrant_hue = 0; | |
a8f81837 | 756 | nv_crtc->lut.depth = 0; |
6ee73861 BS |
757 | for (i = 0; i < 256; i++) { |
758 | nv_crtc->lut.r[i] = i << 8; | |
759 | nv_crtc->lut.g[i] = i << 8; | |
760 | nv_crtc->lut.b[i] = i << 8; | |
761 | } | |
a8f81837 BS |
762 | |
763 | drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs); | |
764 | drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs); | |
765 | drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); | |
6ee73861 | 766 | |
7375c95b | 767 | ret = nouveau_bo_new(dev, 4096, 0x100, TTM_PL_FLAG_VRAM, |
22b33e8e | 768 | 0, 0x0000, NULL, &nv_crtc->lut.nvbo); |
6ee73861 BS |
769 | if (!ret) { |
770 | ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM); | |
771 | if (!ret) | |
772 | ret = nouveau_bo_map(nv_crtc->lut.nvbo); | |
773 | if (ret) | |
774 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); | |
775 | } | |
776 | ||
a8f81837 BS |
777 | if (ret) |
778 | goto out; | |
6ee73861 | 779 | |
6ee73861 | 780 | |
7375c95b | 781 | ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, |
22b33e8e | 782 | 0, 0x0000, NULL, &nv_crtc->cursor.nvbo); |
6ee73861 BS |
783 | if (!ret) { |
784 | ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); | |
785 | if (!ret) | |
786 | ret = nouveau_bo_map(nv_crtc->cursor.nvbo); | |
787 | if (ret) | |
788 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); | |
789 | } | |
790 | ||
a8f81837 BS |
791 | if (ret) |
792 | goto out; | |
793 | ||
6ee73861 | 794 | nv50_cursor_init(nv_crtc); |
a8f81837 BS |
795 | out: |
796 | if (ret) | |
797 | nv50_crtc_destroy(&nv_crtc->base); | |
798 | return ret; | |
6ee73861 | 799 | } |