[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nv40_graph.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <drm/drmP.h>
#include "nouveau_drv.h"
#include "nouveau_fifo.h"
#include "nouveau_ramht.h"

struct nv40_graph_engine {
	struct nouveau_exec_engine base;
	u32 grctx_size;
};

static int
nv40_graph_context_new(struct nouveau_channel *chan, int engine)
{
	struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *grctx = NULL;
	unsigned long flags;
	int ret;

	ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
				 NVOBJ_FLAG_ZERO_ALLOC, &grctx);
	if (ret)
		return ret;

	/* Initialise default context values */
	nv40_grctx_fill(dev, grctx);
	nv_wo32(grctx, 0, grctx->vinst);

	/* init grctx pointer in ramfc, and on PFIFO if channel is
	 * already active there
	 */
	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
	if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
		nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
	nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	chan->engctx[engine] = grctx;
	return 0;
}

static void
nv40_graph_context_del(struct nouveau_channel *chan, int engine)
{
	struct nouveau_gpuobj *grctx = chan->engctx[engine];
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	u32 inst = 0x01000000 | (grctx->pinst >> 4);
	unsigned long flags;

	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	nv_mask(dev, 0x400720, 0x00000000, 0x00000001);
	if (nv_rd32(dev, 0x40032c) == inst)
		nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
	if (nv_rd32(dev, 0x400330) == inst)
		nv_mask(dev, 0x400330, 0x01000000, 0x00000000);
	nv_mask(dev, 0x400720, 0x00000001, 0x00000001);
	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	/* Free the context resources */
	nouveau_gpuobj_ref(NULL, &grctx);
	chan->engctx[engine] = NULL;
}

int
nv40_graph_object_new(struct nouveau_channel *chan, int engine,
		      u32 handle, u16 class)
{
	struct drm_device *dev = chan->dev;
	struct nouveau_gpuobj *obj = NULL;
	int ret;

	ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
	if (ret)
		return ret;
	obj->engine = 1;
	obj->class  = class;

	nv_wo32(obj, 0x00, class);
	nv_wo32(obj, 0x04, 0x00000000);
#ifndef __BIG_ENDIAN
	nv_wo32(obj, 0x08, 0x00000000);
#else
	nv_wo32(obj, 0x08, 0x01000000);
#endif
	nv_wo32(obj, 0x0c, 0x00000000);
	nv_wo32(obj, 0x10, 0x00000000);

	ret = nouveau_ramht_insert(chan, handle, obj);
	nouveau_gpuobj_ref(NULL, &obj);
	return ret;
}

static void
nv40_graph_set_tile_region(struct drm_device *dev, int i)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	switch (dev_priv->chipset) {
	case 0x40:
	case 0x41: /* guess */
	case 0x42:
	case 0x43:
	case 0x45: /* guess */
	case 0x4e:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
		break;
	case 0x44:
	case 0x4a:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
		break;
	case 0x46:
	case 0x47:
	case 0x49:
	case 0x4b:
	case 0x4c:
	case 0x67:
	default:
		nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
		nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
		nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
		break;
	}
}

/*
 * G70		0x47
 * G71		0x49
 * NV45		0x48
 * G72[M]	0x46
 * G73		0x4b
 * C51_G7X	0x4c
 * C51		0x4e
 */
int
nv40_graph_init(struct drm_device *dev, int engine)
{
	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	uint32_t vramsz;
	int i, j;

	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
			~NV_PMC_ENABLE_PGRAPH);
	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
			 NV_PMC_ENABLE_PGRAPH);

	/* generate and upload context program */
	nv40_grctx_init(dev, &pgraph->grctx_size);

	/* No context present currently */
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);

	nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);

	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	j = nv_rd32(dev, 0x1540) & 0xff;
	if (j) {
		for (i = 0; !(j & 1); j >>= 1, i++)
			;
		nv_wr32(dev, 0x405000, i);
	}

	if (dev_priv->chipset == 0x40) {
		nv_wr32(dev, 0x4009b0, 0x83280fff);
		nv_wr32(dev, 0x4009b4, 0x000000a0);
	} else {
		nv_wr32(dev, 0x400820, 0x83280eff);
		nv_wr32(dev, 0x400824, 0x000000a0);
	}

	switch (dev_priv->chipset) {
	case 0x40:
	case 0x45:
		nv_wr32(dev, 0x4009b8, 0x0078e366);
		nv_wr32(dev, 0x4009bc, 0x0000014c);
		break;
	case 0x41:
	case 0x42: /* pciid also 0x00Cx */
	/* case 0x0120: XXX (pciid) */
		nv_wr32(dev, 0x400828, 0x007596ff);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x43:
		nv_wr32(dev, 0x400828, 0x0072cb77);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x44:
	case 0x46: /* G72 */
	case 0x4a:
	case 0x4c: /* G7x-based C51 */
	case 0x4e:
		nv_wr32(dev, 0x400860, 0);
		nv_wr32(dev, 0x400864, 0);
		break;
	case 0x47: /* G70 */
	case 0x49: /* G71 */
	case 0x4b: /* G73 */
		nv_wr32(dev, 0x400828, 0x07830610);
		nv_wr32(dev, 0x40082c, 0x0000016A);
		break;
	default:
		break;
	}

	nv_wr32(dev, 0x400b38, 0x2ffff800);
	nv_wr32(dev, 0x400b3c, 0x00006000);

	/* Tiling related stuff. */
	switch (dev_priv->chipset) {
	case 0x44:
	case 0x4a:
		nv_wr32(dev, 0x400bc4, 0x1003d888);
		nv_wr32(dev, 0x400bbc, 0xb7a7b500);
		break;
	case 0x46:
		nv_wr32(dev, 0x400bc4, 0x0000e024);
		nv_wr32(dev, 0x400bbc, 0xb7a7b520);
		break;
	case 0x4c:
	case 0x4e:
	case 0x67:
		nv_wr32(dev, 0x400bc4, 0x1003d888);
		nv_wr32(dev, 0x400bbc, 0xb7a7b540);
		break;
	default:
		break;
	}

	/* Turn all the tiling regions off. */
	for (i = 0; i < pfb->num_tiles; i++)
		nv40_graph_set_tile_region(dev, i);

	/* begin RAM config */
	vramsz = pci_resource_len(dev->pdev, 0) - 1;
	switch (dev_priv->chipset) {
	case 0x40:
		nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400820, 0);
		nv_wr32(dev, 0x400824, 0);
		nv_wr32(dev, 0x400864, vramsz);
		nv_wr32(dev, 0x400868, vramsz);
		break;
	default:
		switch (dev_priv->chipset) {
		case 0x41:
		case 0x42:
		case 0x43:
		case 0x45:
		case 0x4e:
		case 0x44:
		case 0x4a:
			nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		default:
			nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		}
		nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400840, 0);
		nv_wr32(dev, 0x400844, 0);
		nv_wr32(dev, 0x4008A0, vramsz);
		nv_wr32(dev, 0x4008A4, vramsz);
		break;
	}

	return 0;
}

static int
nv40_graph_fini(struct drm_device *dev, int engine, bool suspend)
{
	u32 inst = nv_rd32(dev, 0x40032c);
	if (inst & 0x01000000) {
		nv_wr32(dev, 0x400720, 0x00000000);
		nv_wr32(dev, 0x400784, inst);
		nv_mask(dev, 0x400310, 0x00000020, 0x00000020);
		nv_mask(dev, 0x400304, 0x00000001, 0x00000001);
		if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000)) {
			u32 insn = nv_rd32(dev, 0x400308);
			NV_ERROR(dev, "PGRAPH: ctxprog timeout 0x%08x\n", insn);
		}
		nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
	}
	return 0;
}

static int
nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
{
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *grctx;
	unsigned long flags;
	int i;

	spin_lock_irqsave(&dev_priv->channels.lock, flags);
	for (i = 0; i < pfifo->channels; i++) {
		if (!dev_priv->channels.ptr[i])
			continue;
		grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];

		if (grctx && grctx->pinst == inst)
			break;
	}
	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	return i;
}

static void
nv40_graph_isr(struct drm_device *dev)
{
	u32 stat;

	while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
		u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
		u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
		u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
		u32 chid = nv40_graph_isr_chid(dev, inst);
		u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
		u32 subc = (addr & 0x00070000) >> 16;
		u32 mthd = (addr & 0x00001ffc);
		u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
		u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
		u32 show = stat;

		if (stat & NV_PGRAPH_INTR_ERROR) {
			if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
				if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
					show &= ~NV_PGRAPH_INTR_ERROR;
			} else
			if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
				nv_mask(dev, 0x402000, 0, 0);
			}
		}

		nv_wr32(dev, NV03_PGRAPH_INTR, stat);
		nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);

		if (show && nouveau_ratelimit()) {
			NV_INFO(dev, "PGRAPH -");
			nouveau_bitfield_print(nv10_graph_intr, show);
			printk(" nsource:");
			nouveau_bitfield_print(nv04_graph_nsource, nsource);
			printk(" nstatus:");
			nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
			printk("\n");
			NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
				     "class 0x%04x mthd 0x%04x data 0x%08x\n",
				chid, inst, subc, class, mthd, data);
		}
	}
}

static void
nv40_graph_destroy(struct drm_device *dev, int engine)
{
	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);

	nouveau_irq_unregister(dev, 12);

	NVOBJ_ENGINE_DEL(dev, GR);
	kfree(pgraph);
}

int
nv40_graph_create(struct drm_device *dev)
{
	struct nv40_graph_engine *pgraph;

	pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
	if (!pgraph)
		return -ENOMEM;

	pgraph->base.destroy = nv40_graph_destroy;
	pgraph->base.init = nv40_graph_init;
	pgraph->base.fini = nv40_graph_fini;
	pgraph->base.context_new = nv40_graph_context_new;
	pgraph->base.context_del = nv40_graph_context_del;
	pgraph->base.object_new = nv40_graph_object_new;
	pgraph->base.set_tile_region = nv40_graph_set_tile_region;

	NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
	nouveau_irq_register(dev, 12, nv40_graph_isr);

	NVOBJ_CLASS(dev, 0x0030, GR); /* null */
	NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
	NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
	NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
	NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
	NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
	NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
	NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
	NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
	NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
	NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
	NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
	NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
	NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
	NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */

	/* curie */
	if (nv44_graph_class(dev))
		NVOBJ_CLASS(dev, 0x4497, GR);
	else
		NVOBJ_CLASS(dev, 0x4097, GR);

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
760285e7	27	#include <drm/drmP.h>
6ee73861	28	#include "nouveau_drv.h"
c420b2dc	29	#include "nouveau_fifo.h"
4ea52f89	30	#include "nouveau_ramht.h"
6ee73861	31
39c8d368 BS	32	struct nv40_graph_engine {
	33	struct nouveau_exec_engine base;
	34	u32 grctx_size;
	35	};
b8c157d3	36
39c8d368 BS	37	static int
	38	nv40_graph_context_new(struct nouveau_channel *chan, int engine)
	39	{
	40	struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
	41	struct drm_device *dev = chan->dev;
	42	struct drm_nouveau_private *dev_priv = dev->dev_private;
	43	struct nouveau_gpuobj *grctx = NULL;
39c8d368 BS	44	unsigned long flags;
	45	int ret;
	46
	47	ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
	48	NVOBJ_FLAG_ZERO_ALLOC, &grctx);
6ee73861 BS	49	if (ret)
	50	return ret;
	51
39c8d368	52	/* Initialise default context values */
d58086de	53	nv40_grctx_fill(dev, grctx);
39c8d368 BS	54	nv_wo32(grctx, 0, grctx->vinst);
	55
	56	/* init grctx pointer in ramfc, and on PFIFO if channel is
	57	* already active there
6ee73861	58	*/
39c8d368 BS	59	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
	60	nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
	61	nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
	62	if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
	63	nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
	64	nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
	65	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	66
	67	chan->engctx[engine] = grctx;
6ee73861 BS	68	return 0;
	69	}
	70
39c8d368 BS	71	static void
39c8d368 BS	72	nv40_graph_context_del(struct nouveau_channel *chan, int engine)
6ee73861	73	{
39c8d368 BS	74	struct nouveau_gpuobj *grctx = chan->engctx[engine];
	75	struct drm_device *dev = chan->dev;
	76	struct drm_nouveau_private *dev_priv = dev->dev_private;
12a30e26	77	u32 inst = 0x01000000 \| (grctx->pinst >> 4);
39c8d368	78	unsigned long flags;
6ee73861	79
39c8d368	80	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
12a30e26 BS	81	nv_mask(dev, 0x400720, 0x00000000, 0x00000001);
	82	if (nv_rd32(dev, 0x40032c) == inst)
	83	nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
	84	if (nv_rd32(dev, 0x400330) == inst)
	85	nv_mask(dev, 0x400330, 0x01000000, 0x00000000);
	86	nv_mask(dev, 0x400720, 0x00000001, 0x00000001);
39c8d368 BS	87	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
	88
	89	/* Free the context resources */
	90	nouveau_gpuobj_ref(NULL, &grctx);
	91	chan->engctx[engine] = NULL;
6ee73861 BS	92	}
6ee73861 BS	93
4ea52f89	94	int
39c8d368 BS	95	nv40_graph_object_new(struct nouveau_channel *chan, int engine,
39c8d368 BS	96	u32 handle, u16 class)
4ea52f89 BS	97	{
	98	struct drm_device *dev = chan->dev;
	99	struct nouveau_gpuobj *obj = NULL;
	100	int ret;
	101
	102	ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
	103	if (ret)
	104	return ret;
	105	obj->engine = 1;
	106	obj->class = class;
	107
	108	nv_wo32(obj, 0x00, class);
	109	nv_wo32(obj, 0x04, 0x00000000);
3acf67f6 BS	110	#ifndef __BIG_ENDIAN
	111	nv_wo32(obj, 0x08, 0x00000000);
	112	#else
4ea52f89 BS	113	nv_wo32(obj, 0x08, 0x01000000);
	114	#endif
	115	nv_wo32(obj, 0x0c, 0x00000000);
	116	nv_wo32(obj, 0x10, 0x00000000);
	117
	118	ret = nouveau_ramht_insert(chan, handle, obj);
	119	nouveau_gpuobj_ref(NULL, &obj);
	120	return ret;
	121	}
	122
96c50082	123	static void
a5cf68b0	124	nv40_graph_set_tile_region(struct drm_device *dev, int i)
0d87c100 FJ	125	{
0d87c100 FJ	126	struct drm_nouveau_private *dev_priv = dev->dev_private;
a5cf68b0	127	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
0d87c100 FJ	128
0d87c100 FJ	129	switch (dev_priv->chipset) {
1dc32671 BS	130	case 0x40:
	131	case 0x41: /* guess */
	132	case 0x42:
	133	case 0x43:
	134	case 0x45: /* guess */
	135	case 0x4e:
	136	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
	137	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
	138	nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
	139	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
	140	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
	141	nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
	142	break;
0d87c100 FJ	143	case 0x44:
0d87c100 FJ	144	case 0x4a:
a5cf68b0 FJ	145	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
	146	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
	147	nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
0d87c100	148	break;
0d87c100 FJ	149	case 0x46:
	150	case 0x47:
	151	case 0x49:
	152	case 0x4b:
1dc32671 BS	153	case 0x4c:
	154	case 0x67:
	155	default:
a5cf68b0 FJ	156	nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
	157	nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
	158	nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
	159	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
	160	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
	161	nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
0d87c100	162	break;
0d87c100 FJ	163	}
	164	}
	165
6ee73861 BS	166	/*
	167	* G70 0x47
	168	* G71 0x49
	169	* NV45 0x48
	170	* G72[M] 0x46
	171	* G73 0x4b
	172	* C51_G7X 0x4c
	173	* C51 0x4e
	174	*/
	175	int
39c8d368	176	nv40_graph_init(struct drm_device *dev, int engine)
6ee73861	177	{
39c8d368 BS	178	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
39c8d368 BS	179	struct drm_nouveau_private *dev_priv = dev->dev_private;
0d87c100	180	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
d58086de	181	uint32_t vramsz;
39c8d368	182	int i, j;
6ee73861 BS	183
	184	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
	185	~NV_PMC_ENABLE_PGRAPH);
	186	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \|
	187	NV_PMC_ENABLE_PGRAPH);
	188
d58086de BS	189	/* generate and upload context program */
d58086de BS	190	nv40_grctx_init(dev, &pgraph->grctx_size);
6ee73861 BS	191
	192	/* No context present currently */
	193	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
	194
	195	nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
	196	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
	197
	198	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	199	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	200	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	201	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	202	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	203	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
	204
	205	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	206	nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
	207
	208	j = nv_rd32(dev, 0x1540) & 0xff;
	209	if (j) {
	210	for (i = 0; !(j & 1); j >>= 1, i++)
	211	;
	212	nv_wr32(dev, 0x405000, i);
	213	}
	214
	215	if (dev_priv->chipset == 0x40) {
	216	nv_wr32(dev, 0x4009b0, 0x83280fff);
	217	nv_wr32(dev, 0x4009b4, 0x000000a0);
	218	} else {
	219	nv_wr32(dev, 0x400820, 0x83280eff);
	220	nv_wr32(dev, 0x400824, 0x000000a0);
	221	}
	222
	223	switch (dev_priv->chipset) {
	224	case 0x40:
	225	case 0x45:
	226	nv_wr32(dev, 0x4009b8, 0x0078e366);
	227	nv_wr32(dev, 0x4009bc, 0x0000014c);
	228	break;
	229	case 0x41:
	230	case 0x42: /* pciid also 0x00Cx */
	231	/* case 0x0120: XXX (pciid) */
	232	nv_wr32(dev, 0x400828, 0x007596ff);
	233	nv_wr32(dev, 0x40082c, 0x00000108);
	234	break;
	235	case 0x43:
	236	nv_wr32(dev, 0x400828, 0x0072cb77);
	237	nv_wr32(dev, 0x40082c, 0x00000108);
	238	break;
	239	case 0x44:
	240	case 0x46: /* G72 */
	241	case 0x4a:
	242	case 0x4c: /* G7x-based C51 */
	243	case 0x4e:
	244	nv_wr32(dev, 0x400860, 0);
	245	nv_wr32(dev, 0x400864, 0);
	246	break;
	247	case 0x47: /* G70 */
	248	case 0x49: /* G71 */
	249	case 0x4b: /* G73 */
	250	nv_wr32(dev, 0x400828, 0x07830610);
	251	nv_wr32(dev, 0x40082c, 0x0000016A);
	252	break;
	253	default:
	254	break;
255	}
256
257	nv_wr32(dev, 0x400b38, 0x2ffff800);
258	nv_wr32(dev, 0x400b3c, 0x00006000);
259
2295e17a FJ	260	/* Tiling related stuff. */
	261	switch (dev_priv->chipset) {
	262	case 0x44:
	263	case 0x4a:
	264	nv_wr32(dev, 0x400bc4, 0x1003d888);
	265	nv_wr32(dev, 0x400bbc, 0xb7a7b500);
	266	break;
	267	case 0x46:
	268	nv_wr32(dev, 0x400bc4, 0x0000e024);
	269	nv_wr32(dev, 0x400bbc, 0xb7a7b520);
	270	break;
	271	case 0x4c:
	272	case 0x4e:
	273	case 0x67:
	274	nv_wr32(dev, 0x400bc4, 0x1003d888);
	275	nv_wr32(dev, 0x400bbc, 0xb7a7b540);
	276	break;
	277	default:
	278	break;
	279	}
	280
0d87c100 FJ	281	/* Turn all the tiling regions off. */
0d87c100 FJ	282	for (i = 0; i < pfb->num_tiles; i++)
a5cf68b0	283	nv40_graph_set_tile_region(dev, i);
6ee73861 BS	284
6ee73861 BS	285	/* begin RAM config */
01d73a69	286	vramsz = pci_resource_len(dev->pdev, 0) - 1;
6ee73861 BS	287	switch (dev_priv->chipset) {
	288	case 0x40:
	289	nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
	290	nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
	291	nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
	292	nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
	293	nv_wr32(dev, 0x400820, 0);
	294	nv_wr32(dev, 0x400824, 0);
	295	nv_wr32(dev, 0x400864, vramsz);
	296	nv_wr32(dev, 0x400868, vramsz);
	297	break;
	298	default:
	299	switch (dev_priv->chipset) {
1dc32671 BS	300	case 0x41:
	301	case 0x42:
	302	case 0x43:
	303	case 0x45:
	304	case 0x4e:
	305	case 0x44:
	306	case 0x4a:
6ee73861 BS	307	nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
	308	nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
	309	break;
1dc32671 BS	310	default:
	311	nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
	312	nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
	313	break;
6ee73861 BS	314	}
	315	nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
	316	nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
	317	nv_wr32(dev, 0x400840, 0);
	318	nv_wr32(dev, 0x400844, 0);
	319	nv_wr32(dev, 0x4008A0, vramsz);
	320	nv_wr32(dev, 0x4008A4, vramsz);
	321	break;
	322	}
	323
	324	return 0;
	325	}
	326
b8c157d3	327	static int
6c320fef	328	nv40_graph_fini(struct drm_device *dev, int engine, bool suspend)
b8c157d3	329	{
12a30e26 BS	330	u32 inst = nv_rd32(dev, 0x40032c);
	331	if (inst & 0x01000000) {
	332	nv_wr32(dev, 0x400720, 0x00000000);
	333	nv_wr32(dev, 0x400784, inst);
	334	nv_mask(dev, 0x400310, 0x00000020, 0x00000020);
	335	nv_mask(dev, 0x400304, 0x00000001, 0x00000001);
	336	if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000)) {
	337	u32 insn = nv_rd32(dev, 0x400308);
	338	NV_ERROR(dev, "PGRAPH: ctxprog timeout 0x%08x\n", insn);
	339	}
	340	nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
	341	}
b8c157d3 BS	342	return 0;
b8c157d3 BS	343	}
274fec93 BS	344
	345	static int
	346	nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
	347	{
c420b2dc	348	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
274fec93	349	struct drm_nouveau_private *dev_priv = dev->dev_private;
39c8d368	350	struct nouveau_gpuobj *grctx;
274fec93 BS	351	unsigned long flags;
	352	int i;
	353
	354	spin_lock_irqsave(&dev_priv->channels.lock, flags);
c420b2dc	355	for (i = 0; i < pfifo->channels; i++) {
39c8d368	356	if (!dev_priv->channels.ptr[i])
274fec93	357	continue;
39c8d368	358	grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
274fec93	359
39c8d368	360	if (grctx && grctx->pinst == inst)
274fec93 BS	361	break;
	362	}
	363	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	364	return i;
	365	}
	366
	367	static void
	368	nv40_graph_isr(struct drm_device *dev)
	369	{
	370	u32 stat;
	371
	372	while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
	373	u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
	374	u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
	375	u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
	376	u32 chid = nv40_graph_isr_chid(dev, inst);
	377	u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
	378	u32 subc = (addr & 0x00070000) >> 16;
	379	u32 mthd = (addr & 0x00001ffc);
	380	u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
	381	u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
	382	u32 show = stat;
	383
	384	if (stat & NV_PGRAPH_INTR_ERROR) {
	385	if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
	386	if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
	387	show &= ~NV_PGRAPH_INTR_ERROR;
	388	} else
	389	if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
	390	nv_mask(dev, 0x402000, 0, 0);
	391	}
	392	}
	393
	394	nv_wr32(dev, NV03_PGRAPH_INTR, stat);
	395	nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
	396
	397	if (show && nouveau_ratelimit()) {
	398	NV_INFO(dev, "PGRAPH -");
	399	nouveau_bitfield_print(nv10_graph_intr, show);
	400	printk(" nsource:");
	401	nouveau_bitfield_print(nv04_graph_nsource, nsource);
	402	printk(" nstatus:");
	403	nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
	404	printk("\n");
	405	NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
	406	"class 0x%04x mthd 0x%04x data 0x%08x\n",
	407	chid, inst, subc, class, mthd, data);
	408	}
	409	}
	410	}
39c8d368 BS	411
	412	static void
	413	nv40_graph_destroy(struct drm_device *dev, int engine)
	414	{
	415	struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
	416
	417	nouveau_irq_unregister(dev, 12);
	418
	419	NVOBJ_ENGINE_DEL(dev, GR);
	420	kfree(pgraph);
	421	}
	422
	423	int
	424	nv40_graph_create(struct drm_device *dev)
	425	{
	426	struct nv40_graph_engine *pgraph;
	427
	428	pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
	429	if (!pgraph)
	430	return -ENOMEM;
	431
	432	pgraph->base.destroy = nv40_graph_destroy;
	433	pgraph->base.init = nv40_graph_init;
	434	pgraph->base.fini = nv40_graph_fini;
	435	pgraph->base.context_new = nv40_graph_context_new;
	436	pgraph->base.context_del = nv40_graph_context_del;
	437	pgraph->base.object_new = nv40_graph_object_new;
96c50082	438	pgraph->base.set_tile_region = nv40_graph_set_tile_region;
39c8d368 BS	439
	440	NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
	441	nouveau_irq_register(dev, 12, nv40_graph_isr);
	442
39c8d368 BS	443	NVOBJ_CLASS(dev, 0x0030, GR); /* null */
	444	NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
	445	NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
	446	NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
	447	NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
	448	NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
	449	NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
	450	NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
	451	NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
	452	NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
	453	NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
	454	NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
	455	NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
	456	NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
	457	NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
	458
	459	/* curie */
	460	if (nv44_graph_class(dev))
	461	NVOBJ_CLASS(dev, 0x4497, GR);
	462	else
	463	NVOBJ_CLASS(dev, 0x4097, GR);
	464
39c8d368 BS	465	return 0;
39c8d368 BS	466	}