[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nv10_fb.c

#include <drm/drmP.h>
#include "nouveau_drv.h"
#include <drm/nouveau_drm.h>

void
nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
			 uint32_t size, uint32_t pitch, uint32_t flags)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	tile->addr  = 0x80000000 | addr;
	tile->limit = max(1u, addr + size) - 1;
	tile->pitch = pitch;
}

void
nv10_fb_free_tile_region(struct drm_device *dev, int i)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	tile->addr = tile->limit = tile->pitch = tile->zcomp = 0;
}

void
nv10_fb_set_tile_region(struct drm_device *dev, int i)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
	nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
	nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
}

int
nv1a_fb_vram_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct pci_dev *bridge;
	uint32_t mem, mib;

	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	if (!bridge) {
		NV_ERROR(dev, "no bridge device\n");
		return 0;
	}

	if (dev_priv->chipset == 0x1a) {
		pci_read_config_dword(bridge, 0x7c, &mem);
		mib = ((mem >> 6) & 31) + 1;
	} else {
		pci_read_config_dword(bridge, 0x84, &mem);
		mib = ((mem >> 4) & 127) + 1;
	}

	dev_priv->vram_size = mib * 1024 * 1024;
	return 0;
}

int
nv10_fb_vram_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	u32 fifo_data = nv_rd32(dev, NV04_PFB_FIFO_DATA);
	u32 cfg0 = nv_rd32(dev, 0x100200);

	dev_priv->vram_size = fifo_data & NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;

	if (cfg0 & 0x00000001)
		dev_priv->vram_type = NV_MEM_TYPE_DDR1;
	else
		dev_priv->vram_type = NV_MEM_TYPE_SDRAM;

	return 0;
}

int
nv10_fb_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	int i;

	/* Turn all the tiling regions off. */
	pfb->num_tiles = NV10_PFB_TILE__SIZE;
	for (i = 0; i < pfb->num_tiles; i++)
		pfb->set_tile_region(dev, i);

	return 0;
}

void
nv10_fb_takedown(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	int i;

	for (i = 0; i < pfb->num_tiles; i++)
		pfb->free_tile_region(dev, i);
}
Commit	Line	Data
760285e7	1	#include <drm/drmP.h>
6ee73861	2	#include "nouveau_drv.h"
760285e7	3	#include <drm/nouveau_drm.h>
6ee73861	4
d81c19e3 BS	5	void
	6	nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
	7	uint32_t size, uint32_t pitch, uint32_t flags)
	8	{
	9	struct drm_nouveau_private *dev_priv = dev->dev_private;
	10	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
	11
	12	tile->addr = 0x80000000 \| addr;
	13	tile->limit = max(1u, addr + size) - 1;
	14	tile->pitch = pitch;
	15	}
	16
	17	void
	18	nv10_fb_free_tile_region(struct drm_device *dev, int i)
	19	{
	20	struct drm_nouveau_private *dev_priv = dev->dev_private;
	21	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
	22
	23	tile->addr = tile->limit = tile->pitch = tile->zcomp = 0;
	24	}
	25
	26	void
	27	nv10_fb_set_tile_region(struct drm_device *dev, int i)
	28	{
	29	struct drm_nouveau_private *dev_priv = dev->dev_private;
	30	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
	31
	32	nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
	33	nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
	34	nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
	35	}
	36
7ad2d31c BS	37	int
	38	nv1a_fb_vram_init(struct drm_device *dev)
	39	{
	40	struct drm_nouveau_private *dev_priv = dev->dev_private;
	41	struct pci_dev *bridge;
	42	uint32_t mem, mib;
	43
	44	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	45	if (!bridge) {
	46	NV_ERROR(dev, "no bridge device\n");
	47	return 0;
	48	}
	49
	50	if (dev_priv->chipset == 0x1a) {
	51	pci_read_config_dword(bridge, 0x7c, &mem);
	52	mib = ((mem >> 6) & 31) + 1;
	53	} else {
	54	pci_read_config_dword(bridge, 0x84, &mem);
	55	mib = ((mem >> 4) & 127) + 1;
	56	}
	57
	58	dev_priv->vram_size = mib * 1024 * 1024;
	59	return 0;
	60	}
	61
	62	int
	63	nv10_fb_vram_init(struct drm_device *dev)
	64	{
	65	struct drm_nouveau_private *dev_priv = dev->dev_private;
	66	u32 fifo_data = nv_rd32(dev, NV04_PFB_FIFO_DATA);
d81c19e3	67	u32 cfg0 = nv_rd32(dev, 0x100200);
7ad2d31c BS	68
7ad2d31c BS	69	dev_priv->vram_size = fifo_data & NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
87a326a3	70
d81c19e3 BS	71	if (cfg0 & 0x00000001)
	72	dev_priv->vram_type = NV_MEM_TYPE_DDR1;
	73	else
	74	dev_priv->vram_type = NV_MEM_TYPE_SDRAM;
87a326a3	75
d81c19e3	76	return 0;
0d87c100 FJ	77	}
0d87c100 FJ	78
6ee73861 BS	79	int
	80	nv10_fb_init(struct drm_device *dev)
	81	{
0d87c100 FJ	82	struct drm_nouveau_private *dev_priv = dev->dev_private;
0d87c100 FJ	83	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
6ee73861 BS	84	int i;
6ee73861 BS	85
0d87c100	86	/* Turn all the tiling regions off. */
d81c19e3	87	pfb->num_tiles = NV10_PFB_TILE__SIZE;
0d87c100	88	for (i = 0; i < pfb->num_tiles; i++)
a5cf68b0	89	pfb->set_tile_region(dev, i);
6ee73861 BS	90
	91	return 0;
	92	}
	93
	94	void
	95	nv10_fb_takedown(struct drm_device *dev)
	96	{
87a326a3 FJ	97	struct drm_nouveau_private *dev_priv = dev->dev_private;
	98	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	99	int i;
	100
	101	for (i = 0; i < pfb->num_tiles; i++)
	102	pfb->free_tile_region(dev, i);
6ee73861	103	}