[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nv04_fb.c

#include <drm/drmP.h>
#include "nouveau_drv.h"
#include <drm/nouveau_drm.h>

int
nv04_fb_vram_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	u32 boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);

	if (boot0 & 0x00000100) {
		dev_priv->vram_size  = ((boot0 >> 12) & 0xf) * 2 + 2;
		dev_priv->vram_size *= 1024 * 1024;
	} else {
		switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
		case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
			dev_priv->vram_size = 32 * 1024 * 1024;
			break;
		case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
			dev_priv->vram_size = 16 * 1024 * 1024;
			break;
		case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
			dev_priv->vram_size = 8 * 1024 * 1024;
			break;
		case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
			dev_priv->vram_size = 4 * 1024 * 1024;
			break;
		}
	}

	if ((boot0 & 0x00000038) <= 0x10)
		dev_priv->vram_type = NV_MEM_TYPE_SGRAM;
	else
		dev_priv->vram_type = NV_MEM_TYPE_SDRAM;

	return 0;
}

int
nv04_fb_init(struct drm_device *dev)
{
	/* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
	 * nvidia reading PFB_CFG_0, then writing back its original value.
	 * (which was 0x701114 in this case)
	 */

	nv_wr32(dev, NV04_PFB_CFG0, 0x1114);
	return 0;
}

void
nv04_fb_takedown(struct drm_device *dev)
{
}
Commit	Line	Data
760285e7	1	#include <drm/drmP.h>
6ee73861	2	#include "nouveau_drv.h"
760285e7	3	#include <drm/nouveau_drm.h>
6ee73861	4
7ad2d31c BS	5	int
	6	nv04_fb_vram_init(struct drm_device *dev)
	7	{
	8	struct drm_nouveau_private *dev_priv = dev->dev_private;
	9	u32 boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
	10
	11	if (boot0 & 0x00000100) {
	12	dev_priv->vram_size = ((boot0 >> 12) & 0xf) * 2 + 2;
	13	dev_priv->vram_size = 1024 1024;
	14	} else {
	15	switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
	16	case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
	17	dev_priv->vram_size = 32 * 1024 * 1024;
	18	break;
	19	case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
	20	dev_priv->vram_size = 16 * 1024 * 1024;
	21	break;
	22	case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
	23	dev_priv->vram_size = 8 * 1024 * 1024;
	24	break;
	25	case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
	26	dev_priv->vram_size = 4 * 1024 * 1024;
	27	break;
	28	}
	29	}
	30
ddfd2da4 BS	31	if ((boot0 & 0x00000038) <= 0x10)
	32	dev_priv->vram_type = NV_MEM_TYPE_SGRAM;
	33	else
	34	dev_priv->vram_type = NV_MEM_TYPE_SDRAM;
	35
7ad2d31c BS	36	return 0;
	37	}
	38
6ee73861 BS	39	int
	40	nv04_fb_init(struct drm_device *dev)
	41	{
	42	/* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
	43	* nvidia reading PFB_CFG_0, then writing back its original value.
	44	* (which was 0x701114 in this case)
	45	*/
	46
	47	nv_wr32(dev, NV04_PFB_CFG0, 0x1114);
	48	return 0;
	49	}
	50
	51	void
	52	nv04_fb_takedown(struct drm_device *dev)
	53	{
	54	}